diff options
Diffstat (limited to 'arch')
23 files changed, 294 insertions, 180 deletions
diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile index e5099975cba..f6323af1d06 100644 --- a/arch/arm/cpu/armv7/bcm281xx/Makefile +++ b/arch/arm/cpu/armv7/bcm281xx/Makefile @@ -7,5 +7,4 @@ obj-y += clk-core.o obj-y += clk-bcm281xx.o obj-y += clk-sdio.o obj-y += clk-bsc.o -obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o obj-y += clk-usb-otg.o diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c index b258fea45c8..39eb2ca01dc 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -307,27 +307,6 @@ static struct ccu_clock kps_ccu_clk = { .freq_tbl = slave_axi_freq_tbl, }; -#ifdef CONFIG_BCM_SF2_ETH -static struct ccu_clock esub_ccu_clk = { - .clk = { - .name = "esub_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = esub_freq_tbl, -}; -#endif - /* * Bus clocks */ @@ -562,9 +541,6 @@ struct clk_lookup arch_clk_tbl[] = { CLK_LK(bsc1_apb), CLK_LK(bsc2_apb), CLK_LK(bsc3_apb), -#ifdef CONFIG_BCM_SF2_ETH - CLK_LK(esub_ccu), -#endif }; /* public array size */ diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c deleted file mode 100644 index 5f7cc4a102d..00000000000 --- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include "clk-core.h" - -#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR -#define WR_ACCESS_PASSWORD 0xA5A500 - -#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00) - -#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58) -#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000 -#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001 - -#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38) -#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001 - -#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04) -#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300 -#define ESW_SYS_DIV_DIV_MASK 0x0000001C -#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100 -#define ESW_SYS_DIV_DIV_SELECT 0x4 -#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001 - -#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04) -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040 -#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0 -#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001 - -#define PLL_MAX_RETRY 100 - -/* Enable appropriate clocks for Ethernet */ -int clk_eth_enable(void) -{ - int rc = -1; - int retry_count = 0; - rc = clk_get_and_enable("esub_ccu_clk"); - - /* Enable Access to CCU registers */ - writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR); - - writel(readl(PLLE_POST_RESETB_ADDR) & - ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Take PLL out of reset and put into normal mode */ - writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, - PLLE_RESETB_ADDR); - - /* Wait for PLL lock */ - rc = -1; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - writel(readl(PLLE_POST_RESETB_ADDR) | - PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ - writel((readl(ESW_SYS_DIV_ADDR) & - ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) | - ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT, - ESW_SYS_DIV_ADDR); - - writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, - ESW_SYS_DIV_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* switch Esub AXI clock to 208MHz */ - writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) | - ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* Disable Access to CCU registers */ - writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR); - - return rc; -} diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi b/arch/arm/dts/apq8016-sbc-u-boot.dtsi index c8a46ed1448..26d4506815e 100644 --- a/arch/arm/dts/apq8016-sbc-u-boot.dtsi +++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi @@ -15,6 +15,6 @@ * because SBL de-initialises them. Indicate that the UART pins should be configured * during all boot stages. */ -&blsp_uart2_default { +&blsp_uart2_console_default { bootph-all; }; diff --git a/arch/arm/dts/apq8016-schneider-hmibsc.dts b/arch/arm/dts/apq8016-schneider-hmibsc.dts index 75c6137e5a1..d8257fc077f 100644 --- a/arch/arm/dts/apq8016-schneider-hmibsc.dts +++ b/arch/arm/dts/apq8016-schneider-hmibsc.dts @@ -463,7 +463,7 @@ drive-strength = <16>; }; -&blsp_uart1_default { +&blsp_uart1_console_default { bootph-all; }; diff --git a/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi b/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi new file mode 100644 index 00000000000..343f10cdf9a --- /dev/null +++ b/arch/arm/dts/at91-sama7d65_curiosity-u-boot.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama7d65_curiosity-u-boot.dtsi - Device Tree Include file for + * SAMA7D65 CURIOSITY. + * + * Copyright (c) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Ryan Wanner <ryan.wanner@microchip.com> + */ + +/{ + aliases { + serial0 = &uart6; + }; + + chosen { + bootph-all; + }; + + clocks { + slow_rc_osc: slow_rc_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; + + cpus { + cpu@0 { + clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 26>, <&main_xtal>; + clock-names = "cpu", "master", "xtal"; + }; + }; + + soc { + bootph-all; + }; +}; + +&clk32k { + clocks = <&slow_rc_osc>, <&slow_xtal>; +}; + +&main_xtal { + bootph-all; +}; + +&pioa { + bootph-all; +}; + +&pinctrl_uart6_default { + bootph-all; +}; + +&pit64b0 { + bootph-all; +}; + +&pmc { + bootph-all; +}; + +&sdmmc1 { + assigned-clock-parents = <&pmc PMC_TYPE_CORE 27>; /* MCK1 div */ + microchip,sdcal-inverted; + no-1-8-v; +}; + +&slow_rc_osc { + bootph-all; +}; + +&slow_xtal { + bootph-all; +}; + +&uart6 { + bootph-all; +}; diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 874e71b5ca4..402f0bec173 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -668,6 +668,12 @@ bootph-all; }; }; + + pwrmgr: pwrmgr@10d14000 { + compatible = "altr,pmgr-agilex5"; + reg = <0x10d14000 0x100>; + bootph-all; + }; }; }; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 86322d7b0ce..9bc3864022b 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -388,6 +388,7 @@ reg-io-width = <4>; num-cs = <4>; clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + spi-max-frequency = <50000000>; status = "disabled"; }; @@ -402,6 +403,7 @@ reg-io-width = <4>; num-cs = <4>; clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + spi-max-frequency = <50000000>; status = "disabled"; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 8d7dc0945ab..938ddb04c04 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -67,7 +67,7 @@ chosen { stdout-path = "serial0:115200n8"; - u-boot,spl-boot-order = &mmc,&flash0,"/memory"; + u-boot,spl-boot-order = &mmc,&flash0,&nand,"/memory"; }; }; diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index f76fe63281b..699ba15d6ea 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -87,7 +87,7 @@ &pinctrl { bootph-all; i2c3_pins_a: i2c3-0 { - bootph-all; + bootph-all; pins { bootph-all; pinmux = <STM32_PINMUX('B', 8, AF5)>, /* I2C3_SCL */ diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi index 9e13c2aa891..b3a32534762 100644 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ b/arch/arm/dts/sun8i-v3s.dtsi @@ -646,7 +646,7 @@ reg = <0x01cb4000 0x3000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI>; clock-names = "bus", "mod", "ram"; resets = <&ccu RST_BUS_CSI>; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index d21534ce883..7d00f1650b4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -52,6 +52,11 @@ config SAMA7G5 select CPU_V7A select AT91RESET_EXTRST +config SAMA7D65 + bool + select CPU_V7A + select AT91RESET_EXTRST + config SAMA5D2 bool select CPU_V7A @@ -299,6 +304,13 @@ config TARGET_SAMA7G54_CURIOSITY 4Gbit SLC nand-flash, MCP16502 PMIC, 2 x Mikrobus connectors, 1 x SD-Card connector, 1 x M.2 slot, 3 x USB +config TARGET_SAMA7D65_CURIOSITY + bool "SAMA7D65 CURIOSITY board" + select SAMA7D65 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply OF_UPSTREAM + config TARGET_TAURUS bool "Support taurus" select AT91SAM9G20 @@ -365,6 +377,7 @@ source "board/atmel/sam9x60_curiosity/Kconfig" source "board/atmel/sam9x75_curiosity/Kconfig" source "board/atmel/sama7g5ek/Kconfig" source "board/atmel/sama7g54_curiosity/Kconfig" +source "board/atmel/sama7d65_curiosity/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 6da1cdffef6..4303a60e0e3 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o clock.o obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o clock.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o clock.o obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o +obj-$(CONFIG_SAMA7D65) += sama7d65_devices.o obj-y += cpu.o ifneq ($(CONFIG_ATMEL_TCB_TIMER),y) ifneq ($(CONFIG_ATMEL_PIT_TIMER),y) diff --git a/arch/arm/mach-at91/armv7/sama7d65_devices.c b/arch/arm/mach-at91/armv7/sama7d65_devices.c new file mode 100644 index 00000000000..6c6ae751b1a --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama7d65_devices.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Microchip Technology, Inc. + */ + +#include <asm/arch/sama7d65.h> + +char *get_cpu_name(void) +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama7d65()) + switch (extension_id) { + case ARCH_EXID_SAMA7D65: + return "SAMA7D65"; + case ARCH_EXID_SAMA7D65_DD2: + return "SAMA7D65 DDR2"; + case ARCH_EXID_SAMA7D65_D1G: + return "SAMA7D65 1Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_D2G: + return "SAMA7D65 2Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_D4G: + return "SAMA7D65 4Gb DDR3L SiP"; + case ARCH_EXID_SAMA7D65_TA: + return "SAMA7D65 TA1000 SiP"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type10"; +} diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index de89714b097..0b2ddbab3be 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -27,6 +27,8 @@ # include <asm/arch/sam9x7.h> #elif defined(CONFIG_SAMA7G5) # include <asm/arch/sama7g5.h> +#elif defined(CONFIG_SAMA7D65) +# include <asm/arch/sama7d65.h> #elif defined(CONFIG_SAMA5D2) # include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) diff --git a/arch/arm/mach-at91/include/mach/sama7d65.h b/arch/arm/mach-at91/include/mach/sama7d65.h new file mode 100644 index 00000000000..8adc5c9a733 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama7d65.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chip-specific header file for the SAMA7D65 SoC + * + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries + */ + +#ifndef __SAMA7D65_H__ +#define __SAMA7D65_H__ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FLEXCOM0 34 +#define ATMEL_ID_FLEXCOM1 35 +#define ATMEL_ID_FLEXCOM2 36 +#define ATMEL_ID_FLEXCOM3 37 +#define ATMEL_ID_FLEXCOM4 38 +#define ATMEL_ID_FLEXCOM5 39 +#define ATMEL_ID_FLEXCOM6 40 +#define ATMEL_ID_FLEXCOM7 41 +#define ATMEL_ID_FLEXCOM8 42 + +#define ATMEL_ID_SDMMC0 75 +#define ATMEL_ID_SDMMC1 76 +#define ATMEL_ID_SDMMC2 77 + +#define ATMEL_ID_PIT64B0 66 +#define ATMEL_ID_PIT64B ATMEL_ID_PIT64B0 + +#define ATMEL_CHIPID_CIDR 0xe0020000 +#define ATMEL_CHIPID_EXID 0xe0020004 +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_PIOA 0xe0014000 +#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) +#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) +#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) +#define ATMEL_BASE_PIOE (ATMEL_BASE_PIOD + 0x40) + +#define ATMEL_PIO_PORTS 5 + +#define CPU_HAS_PCR + +#define ATMEL_BASE_PMC 0xe0018000 + +#define ATMEL_BASE_WDT 0xe001c000 +#define ATMEL_BASE_RSTC 0xe001d100 +#define ATMEL_BASE_WDTS 0xe001d180 +#define ATMEL_BASE_SCKCR 0xe001d500 + +#define ATMEL_BASE_SDMMC0 0xe1204000 +#define ATMEL_BASE_SDMMC1 0xe1208000 + +#define ATMEL_BASE_PIT64B0 0xe1800000 + +#define ATMEL_BASE_FLEXCOM0 0xe1820000 +#define ATMEL_BASE_FLEXCOM1 0xe1824000 +#define ATMEL_BASE_FLEXCOM2 0xe1828000 +#define ATMEL_BASE_FLEXCOM3 0xe182c000 +#define ATMEL_BASE_FLEXCOM4 0xe2018000 +#define ATMEL_BASE_FLEXCOM5 0xe201C000 +#define ATMEL_BASE_FLEXCOM6 0xe2020000 +#define ATMEL_BASE_FLEXCOM7 0xe2024000 +#define ATMEL_BASE_FLEXCOM8 0xe281C000 + +#define ATMEL_BASE_TZC400 0xe3000000 + +#define ATMEL_BASE_UMCTL2 0xe3800000 +#define ATMEL_BASE_UMCTL2_MP 0xe38003f8 +#define ATMEL_BASE_PUBL 0xe3804000 + +#define ATMEL_NUM_FLEXCOM 11 +#define ATMEL_PIO_PORTS 5 + +#define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0 + +#define ARCH_ID_SAMA7D65 0x80262100 +#define ARCH_EXID_SAMA7D65 0x00000080 +#define ARCH_EXID_SAMA7D65_DD2 0x00000010 +#define ARCH_EXID_SAMA7D65_D1G 0x00000018 +#define ARCH_EXID_SAMA7D65_D2G 0x00000020 +#define ARCH_EXID_SAMA7D65_D4G 0x00000028 +#define ARCH_EXID_SAMA7D65_TA 0x00000040 + +#define cpu_is_sama7d65() (get_chip_id() == ARCH_ID_SAMA7D65) +#define cpu_is_sama7d65_S() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65)) +#define cpu_is_sama7d65_DD2() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_DD2)) +#define cpu_is_sama7d65_D1G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D1G)) +#define cpu_is_sama7d65_D2G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D2G)) +#define cpu_is_sama7d65_D4G() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_D4G)) +#define cpu_is_sama7d65_TA() (cpu_is_sama7d65() && \ + (get_extension_chip_id() == ARCH_EXID_SAMA7D65_TA)) + +#ifndef __ASSEMBLY__ +unsigned int get_chip_id(void); +unsigned int get_extension_chip_id(void); +char *get_cpu_name(void); +#endif + +#endif /* #ifndef __SAMA7D65_H__ */ diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index a76a9fb2a39..156cfbbcf3b 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -120,7 +120,6 @@ config TARGET_SOCFPGA_N5X select BINMAN if SPL_ATF select CLK select GICV2 - select FPGA_INTEL_SDM_MAILBOX select NCORE_CACHE select SPL_ALTERA_SDRAM select SPL_CLK if SPL diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index bda12324803..28554b7a109 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -134,7 +134,7 @@ u8 socfpga_get_board_id(void) if (jtag_usercode == DEFAULT_JTAG_USERCODE) { debug("JTAG Usercode is not set. Default Board ID to 0\n"); - } else if (jtag_usercode >= 0 && jtag_usercode <= 255) { + } else if (jtag_usercode <= 255) { board_id = jtag_usercode; debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id); } else { diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 763b077d8c1..04203cceb8a 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -68,6 +68,7 @@ #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) +#define SOC64_HANDOFF_PERI_LEN 1 #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) #define SOC64_HANDOFF_SDRAM_LEN 5 #endif diff --git a/arch/arm/mach-socfpga/include/mach/secure_vab.h b/arch/arm/mach-socfpga/include/mach/secure_vab.h index 42588588e87..1be0cb61e7a 100644 --- a/arch/arm/mach-socfpga/include/mach/secure_vab.h +++ b/arch/arm/mach-socfpga/include/mach/secure_vab.h @@ -1,7 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause * * Copyright (C) 2020 Intel Corporation <www.intel.com> - * + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _SECURE_VAB_H_ diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 4f080f4f0b3..5222b384434 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -22,6 +22,22 @@ DECLARE_GLOBAL_DATA_PTR; +/* Agilex5 Sub Device Jtag ID List */ +#define A3690_JTAG_ID 0x036090DD +#define A3694_JTAG_ID 0x436090DD +#define A36C0_JTAG_ID 0x0360C0DD +#define A36C4_JTAG_ID 0x4360C0DD +#define A36D0_JTAG_ID 0x0360D0DD +#define A36D4_JTAG_ID 0x4360D0DD +#define A36F0_JTAG_ID 0x0360F0DD +#define A36F4_JTAG_ID 0x4360F0DD +#define A3610_JTAG_ID 0x036010DD +#define A3614_JTAG_ID 0x436010DD +#define A3630_JTAG_ID 0x036030DD +#define A3634_JTAG_ID 0x436030DD + +#define JTAG_ID_MASK 0xCFF0FFFF + /* * FPGA programming support for SoC FPGA Stratix 10 */ @@ -42,6 +58,22 @@ static Altera_desc altera_fpga[] = { }, }; +u32 socfpga_get_jtag_id(void) +{ + u32 jtag_id; + + jtag_id = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD4); + + if (!jtag_id) { + debug("Failed to read JTAG ID. Default JTAG ID to A36F4_JTAG_ID.\n"); + jtag_id = A36F4_JTAG_ID; + } + + debug("%s: jtag_id: 0x%x\n", __func__, jtag_id); + + return jtag_id; +} + /* * The Agilex5 platform has enabled the bloblist feature, and the bloblist * address and size are initialized based on the defconfig settings. diff --git a/arch/arm/mach-socfpga/secure_vab.c b/arch/arm/mach-socfpga/secure_vab.c index e931f1043b3..d5ff47a142c 100644 --- a/arch/arm/mach-socfpga/secure_vab.c +++ b/arch/arm/mach-socfpga/secure_vab.c @@ -1,17 +1,18 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause /* * Copyright (C) 2020 Intel Corporation <www.intel.com> - * + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ +#include <log.h> +#include <malloc.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/secure_vab.h> #include <asm/arch/smc_api.h> #include <asm/unaligned.h> -#include <exports.h> +#include <linux/delay.h> #include <linux/errno.h> #include <linux/intel-smc.h> -#include <log.h> #define CHUNKSZ_PER_WD_RESET (256 * SZ_1K) diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index a9aad5350d2..2a13301802d 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -96,6 +96,12 @@ void board_init_f(ulong dummy) hang(); } + ret = uclass_get_device(UCLASS_POWER_DOMAIN, 0, &dev); + if (ret) { + debug("PSS SRAM power-off failed: %d\n", ret); + hang(); + } + if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) { ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { |