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Diffstat (limited to 'board/gateworks/venice/lpddr4_timing_imx8mm.c')
-rw-r--r--board/gateworks/venice/lpddr4_timing_imx8mm.c195
1 files changed, 51 insertions, 144 deletions
diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c
index 956071c5125..896a5c66eb6 100644
--- a/board/gateworks/venice/lpddr4_timing_imx8mm.c
+++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c
@@ -10,6 +10,8 @@
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
+#include "eeprom.h"
+
/* ddr phy trained csr */
static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
{ 0x200b2, 0x0 },
@@ -1890,6 +1892,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = {
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0xf070707 },
+ { 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x29001701 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
@@ -2161,56 +2164,26 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
- { 0x54007, 0x0 },
{ 0x54008, 0x131f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
{ 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
{ 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54034, 0x6600 },
@@ -2223,69 +2196,33 @@ static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
- { 0x54007, 0x0 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
{ 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
{ 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3100 },
{ 0x54034, 0x6600 },
@@ -2298,69 +2235,33 @@ static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
{ 0xd0000, 0x1 },
};
/* P2 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
- { 0x54007, 0x0 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
{ 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
{ 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3100 },
{ 0x54034, 0x6600 },
@@ -2373,69 +2274,35 @@ static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
{ 0xd0000, 0x1 },
};
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
- { 0x54007, 0x0 },
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
{ 0x5400d, 0x100 },
- { 0x5400e, 0x0 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
- { 0x54011, 0x0 },
{ 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
{ 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54034, 0x6600 },
@@ -2448,13 +2315,6 @@ static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
{ 0xd0000, 0x1 },
};
@@ -2549,6 +2409,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_4gb[] = {
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x29001701 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
@@ -3065,6 +2926,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_2gb[] = {
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x29001701 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
@@ -3558,9 +3420,36 @@ static struct dram_cfg_param ddr_ddrphy_cfg_alt_patch[] = {
{ 0x120a5, 0x2 },
};
-struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
+/* 4GB single Die patch (MT53E1G32D2FW-046 revC) */
+static struct dram_cfg_param ddr_ddrc_cfg_4gb_single_die_patch[] = {
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400064, 0x5b011d },
+ { 0x3d40011c, 0x402 },
+ { 0x3d400138, 0x123 },
+ { 0x3d4000f4, 0x699 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d402064, 0xc0026 },
+ { 0x3d40211c, 0x302 },
+ { 0x3d402138, 0x27 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403064, 0x3000a },
+ { 0x3d40311c, 0x302 },
+ { 0x3d403138, 0xa },
+ { 0x3d4030f4, 0x599 }
+};
+
+static struct dram_cfg_param fsp_msg_4gb_single_die_patch[] = {
+ { 0x00054012, 0x110 },
+ { 0x0005402c, 0x1 },
+};
+
+struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info,
+ char *dram_desc, size_t sz_desc)
{
struct dram_timing_info *dram_timing;
+ int sizemb = (16 << info->sdram_size);
+ int i;
switch (sizemb) {
case 512:
@@ -3574,6 +3463,21 @@ struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
break;
case 4096:
dram_timing = &dram_timing_4gb;
+ if (info->sdram_variant == 1) {
+ if (dram_desc)
+ strlcpy(dram_desc, "single-die", sz_desc);
+ apply_cfg_patch(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num,
+ ddr_ddrc_cfg_4gb_single_die_patch,
+ ARRAY_SIZE(ddr_ddrc_cfg_4gb_single_die_patch));
+ for (i = 0; i < 4; i++) {
+ apply_cfg_patch(dram_timing->fsp_msg[i].fsp_cfg,
+ dram_timing->fsp_msg[i].fsp_cfg_num,
+ fsp_msg_4gb_single_die_patch,
+ ARRAY_SIZE(fsp_msg_4gb_single_die_patch));
+ }
+ } else if (dram_desc) {
+ strlcpy(dram_desc, "dual-die", sz_desc);
+ }
break;
default:
printf("unsupported");
@@ -3593,5 +3497,8 @@ struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
ARRAY_SIZE(ddr_ddrphy_cfg_alt_patch));
}
+ if (ddr_init(dram_timing))
+ return NULL;
+
return dram_timing;
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-18 09:13:42 +0000