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-rw-r--r--board/gateworks/venice/eeprom.c6
-rw-r--r--board/gateworks/venice/eeprom.h5
-rw-r--r--board/gateworks/venice/lpddr4_timing.h3
-rw-r--r--board/gateworks/venice/lpddr4_timing_imx8mm.c195
-rw-r--r--board/gateworks/venice/lpddr4_timing_imx8mn.c14
-rw-r--r--board/gateworks/venice/lpddr4_timing_imx8mp.c13
-rw-r--r--board/gateworks/venice/spl.c91
7 files changed, 163 insertions, 164 deletions
diff --git a/board/gateworks/venice/eeprom.c b/board/gateworks/venice/eeprom.c
index d9a87193434..88bbc2e1af8 100644
--- a/board/gateworks/venice/eeprom.c
+++ b/board/gateworks/venice/eeprom.c
@@ -356,7 +356,7 @@ static int eeprom_info(bool verbose)
return 0;
}
-int venice_eeprom_init(int quiet)
+struct venice_board_info *venice_eeprom_init(int quiet)
{
char rev_pcb;
int rev_bom;
@@ -466,10 +466,10 @@ int venice_eeprom_init(int quiet)
if (!strncmp(venice_model, "GW7901-SP486", 12) &&
strcmp(venice_model, "GW7901-SP486-C")) {
- return 2048;
+ som_info.sdram_size++;
}
- return (16 << som_info.sdram_size);
+ return &som_info;
}
void board_gsc_info(void)
diff --git a/board/gateworks/venice/eeprom.h b/board/gateworks/venice/eeprom.h
index a0f449299aa..817277f6276 100644
--- a/board/gateworks/venice/eeprom.h
+++ b/board/gateworks/venice/eeprom.h
@@ -18,13 +18,14 @@ struct venice_board_info {
u8 sdram_size; /* 0x2B: (16 << n) MB */
u8 sdram_speed; /* 0x2C: (33.333 * n) MHz */
u8 sdram_width; /* 0x2D: (8 << n) bit */
- u8 res3[2]; /* 0x2E */
+ u8 sdram_variant; /* 0x2E */
+ u8 res3[1]; /* 0x2D */
char model[16]; /* 0x30: model string */
u8 config[14]; /* 0x40: model config */
u8 chksum[2]; /* 0x4E */
};
-int venice_eeprom_init(int quiet);
+struct venice_board_info *venice_eeprom_init(int quiet);
const char *eeprom_get_model(void);
const char *eeprom_get_som_model(void);
const char *eeprom_get_baseboard_model(void);
diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h
index 21997f6fb2a..e4aa8b6821c 100644
--- a/board/gateworks/venice/lpddr4_timing.h
+++ b/board/gateworks/venice/lpddr4_timing.h
@@ -6,6 +6,7 @@
#ifndef __LPDDR4_TIMING_H__
#define __LPDDR4_TIMING_H__
-extern struct dram_timing_info *spl_dram_init(const char *model, int sizemb);
+struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info,
+ char *dram_desc, size_t sz_desc);
#endif /* __LPDDR4_TIMING_H__ */
diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c
index 956071c5125..896a5c66eb6 100644
--- a/board/gateworks/venice/lpddr4_timing_imx8mm.c
+++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c
@@ -10,6 +10,8 @@
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
+#include "eeprom.h"
+
/* ddr phy trained csr */
static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
{ 0x200b2, 0x0 },
@@ -1890,6 +1892,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = {
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0xf070707 },
+ { 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x29001701 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
@@ -2161,56 +2164,26 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
/* P0 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
- { 0x54007, 0x0 },
{ 0x54008, 0x131f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
{ 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
{ 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54034, 0x6600 },
@@ -2223,69 +2196,33 @@ static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
- { 0x54007, 0x0 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
{ 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
{ 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3100 },
{ 0x54034, 0x6600 },
@@ -2298,69 +2235,33 @@ static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
{ 0xd0000, 0x1 },
};
/* P2 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
- { 0x54007, 0x0 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
- { 0x5400d, 0x0 },
- { 0x5400e, 0x0 },
- { 0x5400f, 0x0 },
- { 0x54010, 0x0 },
- { 0x54011, 0x0 },
{ 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
{ 0x54019, 0x84 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x84 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
{ 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
{ 0x54032, 0x8400 },
{ 0x54033, 0x3100 },
{ 0x54034, 0x6600 },
@@ -2373,69 +2274,35 @@ static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
{ 0xd0000, 0x1 },
};
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
{ 0xd0000, 0x0 },
- { 0x54000, 0x0 },
- { 0x54001, 0x0 },
- { 0x54002, 0x0 },
{ 0x54003, 0xbb8 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
{ 0x54006, 0x11 },
- { 0x54007, 0x0 },
{ 0x54008, 0x61 },
{ 0x54009, 0xc8 },
- { 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
- { 0x5400c, 0x0 },
{ 0x5400d, 0x100 },
- { 0x5400e, 0x0 },
{ 0x5400f, 0x100 },
{ 0x54010, 0x1f7f },
- { 0x54011, 0x0 },
{ 0x54012, 0x110 },
- { 0x54013, 0x0 },
- { 0x54014, 0x0 },
- { 0x54015, 0x0 },
- { 0x54016, 0x0 },
- { 0x54017, 0x0 },
- { 0x54018, 0x0 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, 0x31 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d00 },
- { 0x5401d, 0x0 },
{ 0x5401e, 0x16 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, 0x31 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d00 },
- { 0x54023, 0x0 },
{ 0x54024, 0x16 },
- { 0x54025, 0x0 },
- { 0x54026, 0x0 },
- { 0x54027, 0x0 },
- { 0x54028, 0x0 },
- { 0x54029, 0x0 },
- { 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x1 },
- { 0x5402d, 0x0 },
- { 0x5402e, 0x0 },
- { 0x5402f, 0x0 },
- { 0x54030, 0x0 },
- { 0x54031, 0x0 },
{ 0x54032, 0xd400 },
{ 0x54033, 0x312d },
{ 0x54034, 0x6600 },
@@ -2448,13 +2315,6 @@ static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
{ 0x5403b, 0x4d },
{ 0x5403c, 0x4d },
{ 0x5403d, 0x1600 },
- { 0x5403e, 0x0 },
- { 0x5403f, 0x0 },
- { 0x54040, 0x0 },
- { 0x54041, 0x0 },
- { 0x54042, 0x0 },
- { 0x54043, 0x0 },
- { 0x54044, 0x0 },
{ 0xd0000, 0x1 },
};
@@ -2549,6 +2409,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_4gb[] = {
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x29001701 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
@@ -3065,6 +2926,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg_2gb[] = {
{ 0x3d400204, 0x80808 },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0x7070707 },
+ { 0x3d40021c, 0xf0f },
{ 0x3d400250, 0x29001701 },
{ 0x3d400254, 0x2c },
{ 0x3d40025c, 0x4000030 },
@@ -3558,9 +3420,36 @@ static struct dram_cfg_param ddr_ddrphy_cfg_alt_patch[] = {
{ 0x120a5, 0x2 },
};
-struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
+/* 4GB single Die patch (MT53E1G32D2FW-046 revC) */
+static struct dram_cfg_param ddr_ddrc_cfg_4gb_single_die_patch[] = {
+ { 0x3d400000, 0xa1080020 },
+ { 0x3d400064, 0x5b011d },
+ { 0x3d40011c, 0x402 },
+ { 0x3d400138, 0x123 },
+ { 0x3d4000f4, 0x699 },
+ { 0x3d400200, 0x1f },
+ { 0x3d40021c, 0xf07 },
+ { 0x3d402064, 0xc0026 },
+ { 0x3d40211c, 0x302 },
+ { 0x3d402138, 0x27 },
+ { 0x3d4020f4, 0x599 },
+ { 0x3d403064, 0x3000a },
+ { 0x3d40311c, 0x302 },
+ { 0x3d403138, 0xa },
+ { 0x3d4030f4, 0x599 }
+};
+
+static struct dram_cfg_param fsp_msg_4gb_single_die_patch[] = {
+ { 0x00054012, 0x110 },
+ { 0x0005402c, 0x1 },
+};
+
+struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info,
+ char *dram_desc, size_t sz_desc)
{
struct dram_timing_info *dram_timing;
+ int sizemb = (16 << info->sdram_size);
+ int i;
switch (sizemb) {
case 512:
@@ -3574,6 +3463,21 @@ struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
break;
case 4096:
dram_timing = &dram_timing_4gb;
+ if (info->sdram_variant == 1) {
+ if (dram_desc)
+ strlcpy(dram_desc, "single-die", sz_desc);
+ apply_cfg_patch(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num,
+ ddr_ddrc_cfg_4gb_single_die_patch,
+ ARRAY_SIZE(ddr_ddrc_cfg_4gb_single_die_patch));
+ for (i = 0; i < 4; i++) {
+ apply_cfg_patch(dram_timing->fsp_msg[i].fsp_cfg,
+ dram_timing->fsp_msg[i].fsp_cfg_num,
+ fsp_msg_4gb_single_die_patch,
+ ARRAY_SIZE(fsp_msg_4gb_single_die_patch));
+ }
+ } else if (dram_desc) {
+ strlcpy(dram_desc, "dual-die", sz_desc);
+ }
break;
default:
printf("unsupported");
@@ -3593,5 +3497,8 @@ struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
ARRAY_SIZE(ddr_ddrphy_cfg_alt_patch));
}
+ if (ddr_init(dram_timing))
+ return NULL;
+
return dram_timing;
}
diff --git a/board/gateworks/venice/lpddr4_timing_imx8mn.c b/board/gateworks/venice/lpddr4_timing_imx8mn.c
index e7d04822c9c..cad4fc0d31c 100644
--- a/board/gateworks/venice/lpddr4_timing_imx8mn.c
+++ b/board/gateworks/venice/lpddr4_timing_imx8mn.c
@@ -4,6 +4,8 @@
#include <string.h>
#include <asm/arch/ddr.h>
+#include "eeprom.h"
+
/*
* Generated code from MX8M_DDR_tool v3.20 using RPAv15
*/
@@ -2369,26 +2371,36 @@ static struct dram_timing_info dram_timing_2gb_dual_die = {
.fsp_table = { 3200, 400, 100, },
};
-struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
+struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info,
+ char *dram_desc, size_t sz_desc)
{
struct dram_timing_info *dram_timing;
+ int sizemb = (16 << info->sdram_size);
switch (sizemb) {
case 1024:
dram_timing = &dram_timing_1gb_single_die;
+ if (dram_desc)
+ strlcpy(dram_desc, "single-die", sz_desc);
break;
case 2048:
if (!strcmp(model, "GW7902-SP466-A") ||
!strcmp(model, "GW7902-SP466-B")) {
dram_timing = &dram_timing_2gb_dual_die;
+ if (dram_desc)
+ strlcpy(dram_desc, "dual-die", sz_desc);
} else {
dram_timing = &dram_timing_2gb_single_die;
+ if (dram_desc)
+ strlcpy(dram_desc, "single-die", sz_desc);
}
break;
default:
printf("unsupported");
dram_timing = &dram_timing_2gb_dual_die;
}
+ if (ddr_init(dram_timing))
+ return NULL;
return dram_timing;
}
diff --git a/board/gateworks/venice/lpddr4_timing_imx8mp.c b/board/gateworks/venice/lpddr4_timing_imx8mp.c
index 36c4cb147e8..f2d5d9ce565 100644
--- a/board/gateworks/venice/lpddr4_timing_imx8mp.c
+++ b/board/gateworks/venice/lpddr4_timing_imx8mp.c
@@ -1,8 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
#include <linux/kernel.h>
+#include <string.h>
#include <asm/arch/ddr.h>
+#include "eeprom.h"
+
/*
* Generated code from MX8M_DDR_tool v3.30 using MX8M_Plus RPAv7
*/
@@ -2378,21 +2381,29 @@ static struct dram_timing_info dram_timing_4gb_dual_die = {
.fsp_table = { 4000, 400, 100, },
};
-struct dram_timing_info *spl_dram_init(const char *model, int sizemb)
+struct dram_timing_info *spl_dram_init(const char *model, struct venice_board_info *info,
+ char *dram_desc, size_t sz_desc)
{
struct dram_timing_info *dram_timing;
+ int sizemb = (16 << info->sdram_size);
switch (sizemb) {
case 1024:
dram_timing = &dram_timing_1gb_single_die;
+ if (dram_desc)
+ strlcpy(dram_desc, "single-die", sz_desc);
break;
case 4096:
dram_timing = &dram_timing_4gb_dual_die;
+ if (dram_desc)
+ strlcpy(dram_desc, "dual-die", sz_desc);
break;
default:
printf("unsupported");
dram_timing = &dram_timing_4gb_dual_die;
}
+ if (ddr_init(dram_timing))
+ return NULL;
return dram_timing;
}
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index e813f3e763e..2c303211d32 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -188,9 +188,10 @@ static int power_init_board(const char *model, struct udevice *gsc)
void board_init_f(ulong dummy)
{
struct dram_timing_info *dram_timing;
+ struct venice_board_info *eeprom;
struct udevice *bus, *dev;
const char *model;
- int dram_szmb;
+ char dram_desc[32];
int i, ret;
arch_cpu_init();
@@ -249,23 +250,89 @@ void board_init_f(ulong dummy)
break;
mdelay(1);
}
- dram_szmb = venice_eeprom_init(0);
+ eeprom = venice_eeprom_init(0);
model = eeprom_get_model();
/* PMIC */
power_init_board(model, dev);
/* DDR initialization */
- printf("DRAM : LPDDR4 ");
- if (dram_szmb > 512)
- printf("%d GiB", dram_szmb / 1024);
- else
- printf("%d MiB", dram_szmb);
- dram_timing = spl_dram_init(model, dram_szmb);
- printf(" %dMT/s %dMHz\n",
- dram_timing->fsp_msg[0].drate,
- dram_timing->fsp_msg[0].drate / 2);
- ddr_init(dram_timing);
+ dram_desc[0] = 0;
+ dram_timing = spl_dram_init(model, eeprom, dram_desc, sizeof(dram_desc));
+ if (dram_timing) {
+ int dram_szmb = (16 << eeprom->sdram_size);
+
+ printf("DRAM : LPDDR4 ");
+ if (dram_szmb > 512)
+ printf("%d GiB", dram_szmb / 1024);
+ else
+ printf("%d MiB", dram_szmb);
+ printf(" %dMT/s %dMHz %s",
+ dram_timing->fsp_msg[0].drate,
+ dram_timing->fsp_msg[0].drate / 2,
+ dram_desc[0] ? dram_desc : "");
+
+#ifdef DEBUG
+ u8 mr[9] = { 0 };
+ /* Read MR5-MR8 to obtain details about DRAM part (and verify DRAM working) */
+ for (i = 5; i < 9; i++)
+ mr[i] = lpddr4_mr_read(0xf, i) & 0xff;
+
+ printf(" (0x%02x%02x%02x%02x", mr[5], mr[6], mr[7], mr[8]);
+ /* MR5 MFG_ID */
+ switch (mr[5]) {
+ case 0xff:
+ printf(" Micron");
+ break;
+ default:
+ break;
+ }
+ /* MR8 OP[7:6] Width */
+ i = 0;
+ switch ((mr[8] >> 6) & 0x3) {
+ case 0:
+ i = 16;
+ break;
+ case 1:
+ i = 8;
+ break;
+ }
+ if (i)
+ printf(" x%d", i);
+ /* MR8 OP[5:2] Density */
+ i = 0;
+ switch ((mr[8] >> 2) & 0xf) {
+ case 0:
+ i = 4;
+ break;
+ case 1:
+ i = 6;
+ break;
+ case 2:
+ i = 8;
+ break;
+ case 3:
+ i = 12;
+ break;
+ case 4:
+ i = 16;
+ break;
+ case 5:
+ i = 24;
+ break;
+ case 6:
+ i = 32;
+ break;
+ default:
+ break;
+ }
+ if (i)
+ printf(" %dGb per die", i);
+#endif
+ puts(")\n");
+ } else {
+ hang();
+ }
board_init_r(NULL, 0);
}
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-24 15:15:31 +0000