17 files changed, 2127 insertions, 9 deletions
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig
index 65451a3b20d..a72f66ee3f5 100644
--- a/board/phytec/common/Kconfig
+++ b/board/phytec/common/Kconfig
@@ -42,7 +42,7 @@ config PHYTEC_AM62A_SOM_DETECTION
 	bool "Support SoM detection for AM62Ax PHYTEC platforms"
 	depends on (TARGET_PHYCORE_AM62AX_A53 || TARGET_PHYCORE_AM62AX_R5) && \
 		   PHYTEC_SOM_DETECTION
-	select SUPPORT_EXTENSION_SCAN
+	select PHYTEC_SOM_DETECTION_BLOCKS
 	depends on SPL_I2C && DM_I2C
 	default y
 	help
@@ -59,3 +59,9 @@ config PHYTEC_AM64_SOM_DETECTION
 	help
 	   Support of I2C EEPROM based SoM detection. Supported
 	   for PHYTEC AM64x boards.
+
+config PHYTEC_EEPROM_BUS
+	int "Board EEPROM's I2C bus number"
+	range 0 8
+	default 0
+	depends on PHYTEC_SOM_DETECTION
diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c
index 7f34d71d530..33a779be06b 100644
--- a/board/phytec/common/k3/board.c
+++ b/board/phytec/common/k3/board.c
@@ -176,13 +176,14 @@ static void boot_targets_setup(void)
 	env_set("boot_targets", boot_targets);
 }
 
+#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)
 static void setup_mac_from_eeprom(void)
 {
 	struct phytec_api3_element *block_element;
 	struct phytec_eeprom_data data;
 	int ret;
 
-	ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
+	ret = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
 	if (ret || !data.valid)
 		return;
 
@@ -197,13 +198,15 @@ static void setup_mac_from_eeprom(void)
 		}
 	}
 }
+#endif
 
 int board_late_init(void)
 {
 	boot_targets_setup();
 
-	if (IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS))
-		setup_mac_from_eeprom();
+#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION_BLOCKS)
+	setup_mac_from_eeprom();
+#endif
 
 #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
 	configure_capsule_updates();
@@ -245,7 +248,7 @@ static void fdt_apply_som_overlays(void *blob)
 
 	memcpy(fdt_copy, blob, fdt_size);
 
-	err = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
+	err = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
 	if (err)
 		goto fixup_error;
 
@@ -292,7 +295,7 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	fdt_apply_som_overlays(blob);
 	fdt_copy_fixed_partitions(blob);
 
-	ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
+	ret = phytec_eeprom_data_setup(&data, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
 	if (ret || !data.valid)
 		return 0;
 
diff --git a/board/phytec/imx8mp-libra-fpsc/Kconfig b/board/phytec/imx8mp-libra-fpsc/Kconfig
new file mode 100644
index 00000000000..4961611f7b2
--- /dev/null
+++ b/board/phytec/imx8mp-libra-fpsc/Kconfig
@@ -0,0 +1,16 @@
+if TARGET_IMX8MP_LIBRA_FPSC
+
+config SYS_BOARD
+	default "imx8mp-libra-fpsc"
+
+config SYS_VENDOR
+	default "phytec"
+
+config IMX_CONFIG
+	default "board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg"
+
+config SYS_CONFIG_NAME
+	default "imx8mp-libra-fpsc"
+
+source "board/phytec/common/Kconfig"
+endif
diff --git a/board/phytec/imx8mp-libra-fpsc/MAINTAINERS b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS
new file mode 100644
index 00000000000..1fd99888a2e
--- /dev/null
+++ b/board/phytec/imx8mp-libra-fpsc/MAINTAINERS
@@ -0,0 +1,9 @@
+Libra-i.MX 8M Plus
+M:	Teresa Remmet <t.remmet@phytec.de>
+W:	https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/
+S:	Maintained
+F:	arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi
+F:	board/phytec/imx8mp-libra-fpsc/
+F:	configs/imx8mp-libra-fpsc_defconfig
+F:	include/configs/imx8mp-libra-fpsc.h
+F:	doc/board/phytec/imx8mp-libra-fpsc.rst
diff --git a/board/phytec/imx8mp-libra-fpsc/Makefile b/board/phytec/imx8mp-libra-fpsc/Makefile
new file mode 100644
index 00000000000..21b35d9142f
--- /dev/null
+++ b/board/phytec/imx8mp-libra-fpsc/Makefile
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Copyright (C) 2025 PHYTEC Messtechnik GmbH
+
+obj-y += imx8mp-libra-fpsc.o
+
+ifdef CONFIG_XPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c
new file mode 100644
index 00000000000..ffa21da1b34
--- /dev/null
+++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <linux/io.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <dwc3-uboot.h>
+#include <env.h>
+#include <init.h>
+#include <fdt_support.h>
+#include <jffs2/load_kernel.h>
+#include <miiphy.h>
+#include <mtd_node.h>
+#include <usb.h>
+#include <i2c.h>
+
+#define EEPROM_ADDR		0x51
+
+#define TUSB_PORT_POL_CRTL_REG	0xB
+#define TUSB_CUSTOM_POL		BIT(7)
+#define TUSB_P0_POL		BIT(0)
+
+/*
+ * WORKAROUND for PCM-937-L 1618.0, 1618.1.
+ * USB HUB TUSB8042A has swapped upstream pin polarity.
+ * Set i2c registers to inform the hub that the lines
+ * are swapped.
+ */
+void tusb8042a_swap_lines(void)
+{
+	const u8 pol_swap_val = (TUSB_CUSTOM_POL | TUSB_P0_POL);
+	const int addr = 0x44;
+	struct udevice *dev = 0;
+	int ret = i2c_get_chip_for_busnum(2, addr, 1, &dev);
+
+	if (!ret)
+		dm_i2c_write(dev, TUSB_PORT_POL_CRTL_REG, &pol_swap_val, 1);
+	else
+		printf("TUSB8042A: Failed to fixup USB HUB.\n");
+}
+
+int board_init(void)
+{
+	tusb8042a_swap_lines();
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+	switch (get_boot_device()) {
+	case SD2_BOOT:
+		env_set_ulong("mmcdev", 1);
+		if (!strcmp(env_get("boot_targets"), env_get_default("boot_targets")))
+			env_set("boot_targets", "mmc1 mmc2 ethernet");
+		break;
+	case MMC3_BOOT:
+		env_set_ulong("mmcdev", 2);
+		break;
+	case USB_BOOT:
+		printf("Detect USB boot. Will enter fastboot mode!\n");
+		if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd")))
+			env_set("bootcmd", "fastboot 0; bootflow scan -lb;");
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+int board_phys_sdram_size(phys_size_t *size)
+{
+	if (!size)
+		return -EINVAL;
+
+	*size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE);
+
+	return 0;
+}
diff --git a/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env
new file mode 100644
index 00000000000..c744248ab7a
--- /dev/null
+++ b/board/phytec/imx8mp-libra-fpsc/imx8mp-libra-fpsc.env
@@ -0,0 +1,19 @@
+boot_script_dhcp=boot.scr.uimg
+console=ttymxc3,CONFIG_BAUDRATE
+emmc_dev=2  /* This is needed by built-in uuu flash scripts */
+fdtfile=CONFIG_DEFAULT_FDT_FILE
+fdt_addr_r=0x40480000
+fdt_overlay_addr_r=0x404a0000
+fit_fdtconf=conf-imx8mp-libra-rdk-fpsc.dtb
+kernel_addr_r=0x40a00000
+kernel_comp_addr_r=0x43a00000
+kernel_comp_size=0x1e00000
+mmcroot=2
+pxefile_addr_r=0x45800000
+ramdisk_addr_r=0x45802000
+scriptaddr=0x47600000
+script_offset_f=0x0
+script_size_f=0x2000
+sd_dev=1    /* This is needed by built-in uuu flash scripts */
+ip_dyn=yes
+nfsroot=/srv/nfs
diff --git a/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg
new file mode 100644
index 00000000000..6dedf1724ab
--- /dev/null
+++ b/board/phytec/imx8mp-libra-fpsc/imximage-8mp-sd.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+
+ROM_VERSION	v2
+BOOT_FROM	sd
+LOADER		u-boot-spl-ddr.bin	0x920000
diff --git a/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c
new file mode 100644
index 00000000000..1b501828726
--- /dev/null
+++ b/board/phytec/imx8mp-libra-fpsc/lpddr4_timing.c
@@ -0,0 +1,1813 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2025 NXP
+ *
+ * Code generated with DDR Tool v3.5.0_9-1ddf053d.
+ * DDR PHY FW2020.06
+ */
+
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+
+/* Initialize DDRC registers */
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+	{0x3d400304, 0x1},
+	{0x3d400030, 0x1},
+	{0x3d400000, 0xa1080020},
+	{0x3d400020, 0x1323},
+	{0x3d400024, 0x1e84800},
+	{0x3d400064, 0x7a0118},
+	{0x3d400070, 0x7027f90},
+	{0x3d400074, 0x790},
+	{0x3d4000d0, 0xc00307a3},
+	{0x3d4000d4, 0xc50000},
+	{0x3d4000dc, 0xf4003f},
+	{0x3d4000e0, 0xe30000},
+	{0x3d4000e8, 0x440048},
+	{0x3d4000ec, 0x140048},
+	{0x3d400100, 0x2028222a},
+	{0x3d400104, 0x8083f},
+	{0x3d40010c, 0xe0e000},
+	{0x3d400110, 0x12040a12},
+	{0x3d400114, 0x2050f0f},
+	{0x3d400118, 0x1010009},
+	{0x3d40011c, 0x502},
+	{0x3d400130, 0x20800},
+	{0x3d400134, 0xe100002},
+	{0x3d400138, 0x120},
+	{0x3d400144, 0xc80064},
+	{0x3d400180, 0x3e8001e},
+	{0x3d400184, 0x3207a12},
+	{0x3d400188, 0x0},
+	{0x3d400190, 0x4a3820e},
+	{0x3d400194, 0x80303},
+	{0x3d4001b4, 0x230e},
+	{0x3d4001a0, 0xe0400018},
+	{0x3d4001a4, 0xdf00e4},
+	{0x3d4001a8, 0x80000000},
+	{0x3d4001b0, 0x11},
+	{0x3d4001c0, 0x7},
+	{0x3d4001c4, 0x1},
+	{0x3d4000f4, 0x799},
+	{0x3d400108, 0x9141d1c},
+	{0x3d400200, 0x1f},
+	{0x3d400208, 0x0},
+	{0x3d40020c, 0x0},
+	{0x3d400210, 0x1f1f},
+	{0x3d400204, 0x80808},
+	{0x3d400214, 0x7070707},
+	{0x3d400218, 0x7070707},
+	{0x3d40021c, 0xf0f},
+	{0x3d400250, 0x1705},
+	{0x3d400254, 0x2c},
+	{0x3d40025c, 0x4000030},
+	{0x3d400264, 0x900093e7},
+	{0x3d40026c, 0x2005574},
+	{0x3d400400, 0x111},
+	{0x3d400404, 0x72ff},
+	{0x3d400408, 0x72ff},
+	{0x3d400494, 0x2100e07},
+	{0x3d400498, 0x620096},
+	{0x3d40049c, 0x1100e07},
+	{0x3d4004a0, 0xc8012c},
+	{0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+	{0x100a0, 0x0},
+	{0x100a1, 0x1},
+	{0x100a2, 0x2},
+	{0x100a3, 0x3},
+	{0x100a4, 0x4},
+	{0x100a5, 0x5},
+	{0x100a6, 0x6},
+	{0x100a7, 0x7},
+	{0x110a0, 0x0},
+	{0x110a1, 0x1},
+	{0x110a2, 0x3},
+	{0x110a3, 0x4},
+	{0x110a4, 0x5},
+	{0x110a5, 0x2},
+	{0x110a6, 0x7},
+	{0x110a7, 0x6},
+	{0x120a0, 0x0},
+	{0x120a1, 0x1},
+	{0x120a2, 0x3},
+	{0x120a3, 0x2},
+	{0x120a4, 0x5},
+	{0x120a5, 0x4},
+	{0x120a6, 0x7},
+	{0x120a7, 0x6},
+	{0x130a0, 0x0},
+	{0x130a1, 0x1},
+	{0x130a2, 0x2},
+	{0x130a3, 0x3},
+	{0x130a4, 0x4},
+	{0x130a5, 0x5},
+	{0x130a6, 0x6},
+	{0x130a7, 0x7},
+	{0x1005f, 0x1ff},
+	{0x1015f, 0x1ff},
+	{0x1105f, 0x1ff},
+	{0x1115f, 0x1ff},
+	{0x1205f, 0x1ff},
+	{0x1215f, 0x1ff},
+	{0x1305f, 0x1ff},
+	{0x1315f, 0x1ff},
+	{0x55, 0x1ff},
+	{0x1055, 0x1ff},
+	{0x2055, 0x1ff},
+	{0x3055, 0x1ff},
+	{0x4055, 0x1ff},
+	{0x5055, 0x1ff},
+	{0x6055, 0x1ff},
+	{0x7055, 0x1ff},
+	{0x8055, 0x1ff},
+	{0x9055, 0x1ff},
+	{0x200c5, 0x18},
+	{0x2002e, 0x2},
+	{0x90204, 0x0},
+	{0x20024, 0x1e3},
+	{0x2003a, 0x2},
+	{0x2007d, 0x212},
+	{0x2007c, 0x61},
+	{0x20056, 0x3},
+	{0x1004d, 0x600},
+	{0x1014d, 0x600},
+	{0x1104d, 0x600},
+	{0x1114d, 0x600},
+	{0x1204d, 0x600},
+	{0x1214d, 0x600},
+	{0x1304d, 0x600},
+	{0x1314d, 0x600},
+	{0x10049, 0x618},
+	{0x10149, 0x618},
+	{0x11049, 0x618},
+	{0x11149, 0x618},
+	{0x12049, 0x618},
+	{0x12149, 0x618},
+	{0x13049, 0x618},
+	{0x13149, 0x618},
+	{0x43, 0x21},
+	{0x1043, 0x21},
+	{0x2043, 0x21},
+	{0x3043, 0x21},
+	{0x4043, 0x21},
+	{0x5043, 0x21},
+	{0x6043, 0x21},
+	{0x7043, 0x21},
+	{0x8043, 0x21},
+	{0x9043, 0x21},
+	{0x20018, 0x3},
+	{0x20075, 0x4},
+	{0x20050, 0x0},
+	{0x20008, 0x3e8},
+	{0x20088, 0x9},
+	{0x200b2, 0xdc},
+	{0x10043, 0x5a1},
+	{0x10143, 0x5a1},
+	{0x11043, 0x5a1},
+	{0x11143, 0x5a1},
+	{0x12043, 0x5a1},
+	{0x12143, 0x5a1},
+	{0x13043, 0x5a1},
+	{0x13143, 0x5a1},
+	{0x200fa, 0x1},
+	{0x20019, 0x1},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x4444},
+	{0x200f3, 0x8888},
+	{0x200f4, 0x5555},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0xf000},
+	{0x20025, 0x0},
+	{0x2002d, 0x1},
+	{0x2002c, 0x0},
+};
+
+/* PHY trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+	{0x1005f, 0x0},
+	{0x1015f, 0x0},
+	{0x1105f, 0x0},
+	{0x1115f, 0x0},
+	{0x1205f, 0x0},
+	{0x1215f, 0x0},
+	{0x1305f, 0x0},
+	{0x1315f, 0x0},
+	{0x55, 0x0},
+	{0x1055, 0x0},
+	{0x2055, 0x0},
+	{0x3055, 0x0},
+	{0x4055, 0x0},
+	{0x5055, 0x0},
+	{0x6055, 0x0},
+	{0x7055, 0x0},
+	{0x8055, 0x0},
+	{0x9055, 0x0},
+	{0x200c5, 0x0},
+	{0x2002e, 0x0},
+	{0x90204, 0x0},
+	{0x20024, 0x0},
+	{0x2003a, 0x0},
+	{0x2007d, 0x0},
+	{0x2007c, 0x0},
+	{0x20056, 0x0},
+	{0x1004d, 0x0},
+	{0x1014d, 0x0},
+	{0x1104d, 0x0},
+	{0x1114d, 0x0},
+	{0x1204d, 0x0},
+	{0x1214d, 0x0},
+	{0x1304d, 0x0},
+	{0x1314d, 0x0},
+	{0x10049, 0x0},
+	{0x10149, 0x0},
+	{0x11049, 0x0},
+	{0x11149, 0x0},
+	{0x12049, 0x0},
+	{0x12149, 0x0},
+	{0x13049, 0x0},
+	{0x13149, 0x0},
+	{0x43, 0x0},
+	{0x1043, 0x0},
+	{0x2043, 0x0},
+	{0x3043, 0x0},
+	{0x4043, 0x0},
+	{0x5043, 0x0},
+	{0x6043, 0x0},
+	{0x7043, 0x0},
+	{0x8043, 0x0},
+	{0x9043, 0x0},
+	{0x20018, 0x0},
+	{0x20075, 0x0},
+	{0x20050, 0x0},
+	{0x20008, 0x0},
+	{0x20088, 0x0},
+	{0x200b2, 0x0},
+	{0x10043, 0x0},
+	{0x10143, 0x0},
+	{0x11043, 0x0},
+	{0x11143, 0x0},
+	{0x12043, 0x0},
+	{0x12143, 0x0},
+	{0x13043, 0x0},
+	{0x13143, 0x0},
+	{0x200fa, 0x0},
+	{0x20019, 0x0},
+	{0x200f0, 0x0},
+	{0x200f1, 0x0},
+	{0x200f2, 0x0},
+	{0x200f3, 0x0},
+	{0x200f4, 0x0},
+	{0x200f5, 0x0},
+	{0x200f6, 0x0},
+	{0x200f7, 0x0},
+	{0x20025, 0x0},
+	{0x2002d, 0x0},
+	{0x2002c, 0x0},
+	{0xd0000, 0x0},
+	{0x90000, 0x0},
+	{0x90001, 0x0},
+	{0x90002, 0x0},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x0},
+	{0x90029, 0x0},
+	{0x9002a, 0x0},
+	{0x9002b, 0x0},
+	{0x9002c, 0x0},
+	{0x9002d, 0x0},
+	{0x9002e, 0x0},
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+	{0x100aa, 0x0},
+	{0x10062, 0x0},
+	{0x10001, 0x0},
+	{0x100a0, 0x0},
+	{0x100a1, 0x0},
+	{0x100a2, 0x0},
+	{0x100a3, 0x0},
+	{0x100a4, 0x0},
+	{0x100a5, 0x0},
+	{0x100a6, 0x0},
+	{0x100a7, 0x0},
+	{0x11068, 0x0},
+	{0x11069, 0x0},
+	{0x11168, 0x0},
+	{0x11169, 0x0},
+	{0x11268, 0x0},
+	{0x11269, 0x0},
+	{0x11368, 0x0},
+	{0x11369, 0x0},
+	{0x11468, 0x0},
+	{0x11469, 0x0},
+	{0x11568, 0x0},
+	{0x11569, 0x0},
+	{0x11668, 0x0},
+	{0x11669, 0x0},
+	{0x11768, 0x0},
+	{0x11769, 0x0},
+	{0x11868, 0x0},
+	{0x11869, 0x0},
+	{0x110aa, 0x0},
+	{0x11062, 0x0},
+	{0x11001, 0x0},
+	{0x110a0, 0x0},
+	{0x110a1, 0x0},
+	{0x110a2, 0x0},
+	{0x110a3, 0x0},
+	{0x110a4, 0x0},
+	{0x110a5, 0x0},
+	{0x110a6, 0x0},
+	{0x110a7, 0x0},
+	{0x12068, 0x0},
+	{0x12069, 0x0},
+	{0x12168, 0x0},
+	{0x12169, 0x0},
+	{0x12268, 0x0},
+	{0x12269, 0x0},
+	{0x12368, 0x0},
+	{0x12369, 0x0},
+	{0x12468, 0x0},
+	{0x12469, 0x0},
+	{0x12568, 0x0},
+	{0x12569, 0x0},
+	{0x12668, 0x0},
+	{0x12669, 0x0},
+	{0x12768, 0x0},
+	{0x12769, 0x0},
+	{0x12868, 0x0},
+	{0x12869, 0x0},
+	{0x120aa, 0x0},
+	{0x12062, 0x0},
+	{0x12001, 0x0},
+	{0x120a0, 0x0},
+	{0x120a1, 0x0},
+	{0x120a2, 0x0},
+	{0x120a3, 0x0},
+	{0x120a4, 0x0},
+	{0x120a5, 0x0},
+	{0x120a6, 0x0},
+	{0x120a7, 0x0},
+	{0x13068, 0x0},
+	{0x13069, 0x0},
+	{0x13168, 0x0},
+	{0x13169, 0x0},
+	{0x13268, 0x0},
+	{0x13269, 0x0},
+	{0x13368, 0x0},
+	{0x13369, 0x0},
+	{0x13468, 0x0},
+	{0x13469, 0x0},
+	{0x13568, 0x0},
+	{0x13569, 0x0},
+	{0x13668, 0x0},
+	{0x13669, 0x0},
+	{0x13768, 0x0},
+	{0x13769, 0x0},
+	{0x13868, 0x0},
+	{0x13869, 0x0},
+	{0x130aa, 0x0},
+	{0x13062, 0x0},
+	{0x13001, 0x0},
+	{0x130a0, 0x0},
+	{0x130a1, 0x0},
+	{0x130a2, 0x0},
+	{0x130a3, 0x0},
+	{0x130a4, 0x0},
+	{0x130a5, 0x0},
+	{0x130a6, 0x0},
+	{0x130a7, 0x0},
+	{0x80, 0x0},
+	{0x1080, 0x0},
+	{0x2080, 0x0},
+	{0x3080, 0x0},
+	{0x4080, 0x0},
+	{0x5080, 0x0},
+	{0x6080, 0x0},
+	{0x7080, 0x0},
+	{0x8080, 0x0},
+	{0x9080, 0x0},
+	{0x10020, 0x0},
+	{0x10080, 0x0},
+	{0x10081, 0x0},
+	{0x100d0, 0x0},
+	{0x100d1, 0x0},
+	{0x1008c, 0x0},
+	{0x1008d, 0x0},
+	{0x10180, 0x0},
+	{0x10181, 0x0},
+	{0x101d0, 0x0},
+	{0x101d1, 0x0},
+	{0x1018c, 0x0},
+	{0x1018d, 0x0},
+	{0x100c0, 0x0},
+	{0x100c1, 0x0},
+	{0x101c0, 0x0},
+	{0x101c1, 0x0},
+	{0x102c0, 0x0},
+	{0x102c1, 0x0},
+	{0x103c0, 0x0},
+	{0x103c1, 0x0},
+	{0x104c0, 0x0},
+	{0x104c1, 0x0},
+	{0x105c0, 0x0},
+	{0x105c1, 0x0},
+	{0x106c0, 0x0},
+	{0x106c1, 0x0},
+	{0x107c0, 0x0},
+	{0x107c1, 0x0},
+	{0x108c0, 0x0},
+	{0x108c1, 0x0},
+	{0x100ae, 0x0},
+	{0x100af, 0x0},
+	{0x11020, 0x0},
+	{0x11080, 0x0},
+	{0x11081, 0x0},
+	{0x110d0, 0x0},
+	{0x110d1, 0x0},
+	{0x1108c, 0x0},
+	{0x1108d, 0x0},
+	{0x11180, 0x0},
+	{0x11181, 0x0},
+	{0x111d0, 0x0},
+	{0x111d1, 0x0},
+	{0x1118c, 0x0},
+	{0x1118d, 0x0},
+	{0x110c0, 0x0},
+	{0x110c1, 0x0},
+	{0x111c0, 0x0},
+	{0x111c1, 0x0},
+	{0x112c0, 0x0},
+	{0x112c1, 0x0},
+	{0x113c0, 0x0},
+	{0x113c1, 0x0},
+	{0x114c0, 0x0},
+	{0x114c1, 0x0},
+	{0x115c0, 0x0},
+	{0x115c1, 0x0},
+	{0x116c0, 0x0},
+	{0x116c1, 0x0},
+	{0x117c0, 0x0},
+	{0x117c1, 0x0},
+	{0x118c0, 0x0},
+	{0x118c1, 0x0},
+	{0x110ae, 0x0},
+	{0x110af, 0x0},
+	{0x12020, 0x0},
+	{0x12080, 0x0},
+	{0x12081, 0x0},
+	{0x120d0, 0x0},
+	{0x120d1, 0x0},
+	{0x1208c, 0x0},
+	{0x1208d, 0x0},
+	{0x12180, 0x0},
+	{0x12181, 0x0},
+	{0x121d0, 0x0},
+	{0x121d1, 0x0},
+	{0x1218c, 0x0},
+	{0x1218d, 0x0},
+	{0x120c0, 0x0},
+	{0x120c1, 0x0},
+	{0x121c0, 0x0},
+	{0x121c1, 0x0},
+	{0x122c0, 0x0},
+	{0x122c1, 0x0},
+	{0x123c0, 0x0},
+	{0x123c1, 0x0},
+	{0x124c0, 0x0},
+	{0x124c1, 0x0},
+	{0x125c0, 0x0},
+	{0x125c1, 0x0},
+	{0x126c0, 0x0},
+	{0x126c1, 0x0},
+	{0x127c0, 0x0},
+	{0x127c1, 0x0},
+	{0x128c0, 0x0},
+	{0x128c1, 0x0},
+	{0x120ae, 0x0},
+	{0x120af, 0x0},
+	{0x13020, 0x0},
+	{0x13080, 0x0},
+	{0x13081, 0x0},
+	{0x130d0, 0x0},
+	{0x130d1, 0x0},
+	{0x1308c, 0x0},
+	{0x1308d, 0x0},
+	{0x13180, 0x0},
+	{0x13181, 0x0},
+	{0x131d0, 0x0},
+	{0x131d1, 0x0},
+	{0x1318c, 0x0},
+	{0x1318d, 0x0},
+	{0x130c0, 0x0},
+	{0x130c1, 0x0},
+	{0x131c0, 0x0},
+	{0x131c1, 0x0},
+	{0x132c0, 0x0},
+	{0x132c1, 0x0},
+	{0x133c0, 0x0},
+	{0x133c1, 0x0},
+	{0x134c0, 0x0},
+	{0x134c1, 0x0},
+	{0x135c0, 0x0},
+	{0x135c1, 0x0},
+	{0x136c0, 0x0},
+	{0x136c1, 0x0},
+	{0x137c0, 0x0},
+	{0x137c1, 0x0},
+	{0x138c0, 0x0},
+	{0x138c1, 0x0},
+	{0x130ae, 0x0},
+	{0x130af, 0x0},
+	{0x90201, 0x0},
+	{0x90202, 0x0},
+	{0x90203, 0x0},
+	{0x90205, 0x0},
+	{0x90206, 0x0},
+	{0x90207, 0x0},
+	{0x90208, 0x0},
+	{0x20020, 0x0},
+	{0x20077, 0x0},
+	{0x20072, 0x0},
+	{0x20073, 0x0},
+	{0x400c0, 0x0},
+	{0x10040, 0x0},
+	{0x10140, 0x0},
+	{0x10240, 0x0},
+	{0x10340, 0x0},
+	{0x10440, 0x0},
+	{0x10540, 0x0},
+	{0x10640, 0x0},
+	{0x10740, 0x0},
+	{0x10840, 0x0},
+	{0x11040, 0x0},
+	{0x11140, 0x0},
+	{0x11240, 0x0},
+	{0x11340, 0x0},
+	{0x11440, 0x0},
+	{0x11540, 0x0},
+	{0x11640, 0x0},
+	{0x11740, 0x0},
+	{0x11840, 0x0},
+	{0x12040, 0x0},
+	{0x12140, 0x0},
+	{0x12240, 0x0},
+	{0x12340, 0x0},
+	{0x12440, 0x0},
+	{0x12540, 0x0},
+	{0x12640, 0x0},
+	{0x12740, 0x0},
+	{0x12840, 0x0},
+	{0x13040, 0x0},
+	{0x13140, 0x0},
+	{0x13240, 0x0},
+	{0x13340, 0x0},
+	{0x13440, 0x0},
+	{0x13540, 0x0},
+	{0x13640, 0x0},
+	{0x13740, 0x0},
+	{0x13840, 0x0},
+};
+
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xfa0},
+	{0x54004, 0x2},
+	{0x54005, 0x3c3c},
+	{0x54006, 0x11},
+	{0x54008, 0x131f},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54012, 0x110},
+	{0x54019, 0x3ff4},
+	{0x5401a, 0xe3},
+	{0x5401b, 0x4844},
+	{0x5401c, 0x4800},
+	{0x5401e, 0x14},
+	{0x5401f, 0x3ff4},
+	{0x54020, 0xe3},
+	{0x54021, 0x4844},
+	{0x54022, 0x4800},
+	{0x54024, 0x14},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xf400},
+	{0x54033, 0xe33f},
+	{0x54034, 0x4400},
+	{0x54035, 0x48},
+	{0x54036, 0x48},
+	{0x54037, 0x1400},
+	{0x54038, 0xf400},
+	{0x54039, 0xe33f},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x48},
+	{0x5403c, 0x48},
+	{0x5403d, 0x1400},
+	{0xd0000, 0x1}
+};
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+	{0xd0000, 0x0},
+	{0x54003, 0xfa0},
+	{0x54004, 0x2},
+	{0x54005, 0x3c3c},
+	{0x54006, 0x11},
+	{0x54008, 0x61},
+	{0x54009, 0xc8},
+	{0x5400b, 0x2},
+	{0x5400f, 0x100},
+	{0x54010, 0x1f7f},
+	{0x54012, 0x110},
+	{0x54019, 0x3ff4},
+	{0x5401a, 0xe3},
+	{0x5401b, 0x4844},
+	{0x5401c, 0x4800},
+	{0x5401e, 0x14},
+	{0x5401f, 0x3ff4},
+	{0x54020, 0xe3},
+	{0x54021, 0x4844},
+	{0x54022, 0x4800},
+	{0x54024, 0x14},
+	{0x5402b, 0x1000},
+	{0x5402c, 0x1},
+	{0x54032, 0xf400},
+	{0x54033, 0xe33f},
+	{0x54034, 0x4400},
+	{0x54035, 0x48},
+	{0x54036, 0x48},
+	{0x54037, 0x1400},
+	{0x54038, 0xf400},
+	{0x54039, 0xe33f},
+	{0x5403a, 0x4400},
+	{0x5403b, 0x48},
+	{0x5403c, 0x48},
+	{0x5403d, 0x1400},
+	{0xd0000, 0x1}
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+	{0xd0000, 0x0},
+	{0x90000, 0x10},
+	{0x90001, 0x400},
+	{0x90002, 0x10e},
+	{0x90003, 0x0},
+	{0x90004, 0x0},
+	{0x90005, 0x8},
+	{0x90029, 0xb},
+	{0x9002a, 0x480},
+	{0x9002b, 0x109},
+	{0x9002c, 0x8},
+	{0x9002d, 0x448},
+	{0x9002e, 0x139},
+	{0x9002f, 0x8},
+	{0x90030, 0x478},
+	{0x90031, 0x109},
+	{0x90032, 0x0},
+	{0x90033, 0xe8},
+	{0x90034, 0x109},
+	{0x90035, 0x2},
+	{0x90036, 0x10},
+	{0x90037, 0x139},
+	{0x90038, 0xb},
+	{0x90039, 0x7c0},
+	{0x9003a, 0x139},
+	{0x9003b, 0x44},
+	{0x9003c, 0x633},
+	{0x9003d, 0x159},
+	{0x9003e, 0x14f},
+	{0x9003f, 0x630},
+	{0x90040, 0x159},
+	{0x90041, 0x47},
+	{0x90042, 0x633},
+	{0x90043, 0x149},
+	{0x90044, 0x4f},
+	{0x90045, 0x633},
+	{0x90046, 0x179},
+	{0x90047, 0x8},
+	{0x90048, 0xe0},
+	{0x90049, 0x109},
+	{0x9004a, 0x0},
+	{0x9004b, 0x7c8},
+	{0x9004c, 0x109},
+	{0x9004d, 0x0},
+	{0x9004e, 0x1},
+	{0x9004f, 0x8},
+	{0x90050, 0x0},
+	{0x90051, 0x45a},
+	{0x90052, 0x9},
+	{0x90053, 0x0},
+	{0x90054, 0x448},
+	{0x90055, 0x109},
+	{0x90056, 0x40},
+	{0x90057, 0x633},
+	{0x90058, 0x179},
+	{0x90059, 0x1},
+	{0x9005a, 0x618},
+	{0x9005b, 0x109},
+	{0x9005c, 0x40c0},
+	{0x9005d, 0x633},
+	{0x9005e, 0x149},
+	{0x9005f, 0x8},
+	{0x90060, 0x4},
+	{0x90061, 0x48},
+	{0x90062, 0x4040},
+	{0x90063, 0x633},
+	{0x90064, 0x149},
+	{0x90065, 0x0},
+	{0x90066, 0x4},
+	{0x90067, 0x48},
+	{0x90068, 0x40},
+	{0x90069, 0x633},
+	{0x9006a, 0x149},
+	{0x9006b, 0x10},
+	{0x9006c, 0x4},
+	{0x9006d, 0x18},
+	{0x9006e, 0x0},
+	{0x9006f, 0x4},
+	{0x90070, 0x78},
+	{0x90071, 0x549},
+	{0x90072, 0x633},
+	{0x90073, 0x159},
+	{0x90074, 0xd49},
+	{0x90075, 0x633},
+	{0x90076, 0x159},
+	{0x90077, 0x94a},
+	{0x90078, 0x633},
+	{0x90079, 0x159},
+	{0x9007a, 0x441},
+	{0x9007b, 0x633},
+	{0x9007c, 0x149},
+	{0x9007d, 0x42},
+	{0x9007e, 0x633},
+	{0x9007f, 0x149},
+	{0x90080, 0x1},
+	{0x90081, 0x633},
+	{0x90082, 0x149},
+	{0x90083, 0x0},
+	{0x90084, 0xe0},
+	{0x90085, 0x109},
+	{0x90086, 0xa},
+	{0x90087, 0x10},
+	{0x90088, 0x109},
+	{0x90089, 0x9},
+	{0x9008a, 0x3c0},
+	{0x9008b, 0x149},
+	{0x9008c, 0x9},
+	{0x9008d, 0x3c0},
+	{0x9008e, 0x159},
+	{0x9008f, 0x18},
+	{0x90090, 0x10},
+	{0x90091, 0x109},
+	{0x90092, 0x0},
+	{0x90093, 0x3c0},
+	{0x90094, 0x109},
+	{0x90095, 0x18},
+	{0x90096, 0x4},
+	{0x90097, 0x48},
+	{0x90098, 0x18},
+	{0x90099, 0x4},
+	{0x9009a, 0x58},
+	{0x9009b, 0xb},
+	{0x9009c, 0x10},
+	{0x9009d, 0x109},
+	{0x9009e, 0x1},
+	{0x9009f, 0x10},
+	{0x900a0, 0x109},
+	{0x900a1, 0x5},
+	{0x900a2, 0x7c0},
+	{0x900a3, 0x109},
+	{0x40000, 0x811},
+	{0x40020, 0x880},
+	{0x40040, 0x0},
+	{0x40060, 0x0},
+	{0x40001, 0x4008},
+	{0x40021, 0x83},
+	{0x40041, 0x4f},
+	{0x40061, 0x0},
+	{0x40002, 0x4040},
+	{0x40022, 0x83},
+	{0x40042, 0x51},
+	{0x40062, 0x0},
+	{0x40003, 0x811},
+	{0x40023, 0x880},
+	{0x40043, 0x0},
+	{0x40063, 0x0},
+	{0x40004, 0x720},
+	{0x40024, 0xf},
+	{0x40044, 0x1740},
+	{0x40064, 0x0},
+	{0x40005, 0x16},
+	{0x40025, 0x83},
+	{0x40045, 0x4b},
+	{0x40065, 0x0},
+	{0x40006, 0x716},
+	{0x40026, 0xf},
+	{0x40046, 0x2001},
+	{0x40066, 0x0},
+	{0x40007, 0x716},
+	{0x40027, 0xf},
+	{0x40047, 0x2800},
+	{0x40067, 0x0},
+	{0x40008, 0x716},
+	{0x40028, 0xf},
+	{0x40048, 0xf00},
+	{0x40068, 0x0},
+	{0x40009, 0x720},
+	{0x40029, 0xf},
+	{0x40049, 0x1400},
+	{0x40069, 0x0},
+	{0x4000a, 0xe08},
+	{0x4002a, 0xc15},
+	{0x4004a, 0x0},
+	{0x4006a, 0x0},
+	{0x4000b, 0x625},
+	{0x4002b, 0x15},
+	{0x4004b, 0x0},
+	{0x4006b, 0x0},
+	{0x4000c, 0x4028},
+	{0x4002c, 0x80},
+	{0x4004c, 0x0},
+	{0x4006c, 0x0},
+	{0x4000d, 0xe08},
+	{0x4002d, 0xc1a},
+	{0x4004d, 0x0},
+	{0x4006d, 0x0},
+	{0x4000e, 0x625},
+	{0x4002e, 0x1a},
+	{0x4004e, 0x0},
+	{0x4006e, 0x0},
+	{0x4000f, 0x4040},
+	{0x4002f, 0x80},
+	{0x4004f, 0x0},
+	{0x4006f, 0x0},
+	{0x40010, 0x2604},
+	{0x40030, 0x15},
+	{0x40050, 0x0},
+	{0x40070, 0x0},
+	{0x40011, 0x708},
+	{0x40031, 0x5},
+	{0x40051, 0x0},
+	{0x40071, 0x2002},
+	{0x40012, 0x8},
+	{0x40032, 0x80},
+	{0x40052, 0x0},
+	{0x40072, 0x0},
+	{0x40013, 0x2604},
+	{0x40033, 0x1a},
+	{0x40053, 0x0},
+	{0x40073, 0x0},
+	{0x40014, 0x708},
+	{0x40034, 0xa},
+	{0x40054, 0x0},
+	{0x40074, 0x2002},
+	{0x40015, 0x4040},
+	{0x40035, 0x80},
+	{0x40055, 0x0},
+	{0x40075, 0x0},
+	{0x40016, 0x60a},
+	{0x40036, 0x15},
+	{0x40056, 0x1200},
+	{0x40076, 0x0},
+	{0x40017, 0x61a},
+	{0x40037, 0x15},
+	{0x40057, 0x1300},
+	{0x40077, 0x0},
+	{0x40018, 0x60a},
+	{0x40038, 0x1a},
+	{0x40058, 0x1200},
+	{0x40078, 0x0},
+	{0x40019, 0x642},
+	{0x40039, 0x1a},
+	{0x40059, 0x1300},
+	{0x40079, 0x0},
+	{0x4001a, 0x4808},
+	{0x4003a, 0x880},
+	{0x4005a, 0x0},
+	{0x4007a, 0x0},
+	{0x900a4, 0x0},
+	{0x900a5, 0x790},
+	{0x900a6, 0x11a},
+	{0x900a7, 0x8},
+	{0x900a8, 0x7aa},
+	{0x900a9, 0x2a},
+	{0x900aa, 0x10},
+	{0x900ab, 0x7b2},
+	{0x900ac, 0x2a},
+	{0x900ad, 0x0},
+	{0x900ae, 0x7c8},
+	{0x900af, 0x109},
+	{0x900b0, 0x10},
+	{0x900b1, 0x10},
+	{0x900b2, 0x109},
+	{0x900b3, 0x10},
+	{0x900b4, 0x2a8},
+	{0x900b5, 0x129},
+	{0x900b6, 0x8},
+	{0x900b7, 0x370},
+	{0x900b8, 0x129},
+	{0x900b9, 0xa},
+	{0x900ba, 0x3c8},
+	{0x900bb, 0x1a9},
+	{0x900bc, 0xc},
+	{0x900bd, 0x408},
+	{0x900be, 0x199},
+	{0x900bf, 0x14},
+	{0x900c0, 0x790},
+	{0x900c1, 0x11a},
+	{0x900c2, 0x8},
+	{0x900c3, 0x4},
+	{0x900c4, 0x18},
+	{0x900c5, 0xe},
+	{0x900c6, 0x408},
+	{0x900c7, 0x199},
+	{0x900c8, 0x8},
+	{0x900c9, 0x8568},
+	{0x900ca, 0x108},
+	{0x900cb, 0x18},
+	{0x900cc, 0x790},
+	{0x900cd, 0x16a},
+	{0x900ce, 0x8},
+	{0x900cf, 0x1d8},
+	{0x900d0, 0x169},
+	{0x900d1, 0x10},
+	{0x900d2, 0x8558},
+	{0x900d3, 0x168},
+	{0x900d4, 0x70},
+	{0x900d5, 0x788},
+	{0x900d6, 0x16a},
+	{0x900d7, 0x1ff8},
+	{0x900d8, 0x85a8},
+	{0x900d9, 0x1e8},
+	{0x900da, 0x50},
+	{0x900db, 0x798},
+	{0x900dc, 0x16a},
+	{0x900dd, 0x60},
+	{0x900de, 0x7a0},
+	{0x900df, 0x16a},
+	{0x900e0, 0x8},
+	{0x900e1, 0x8310},
+	{0x900e2, 0x168},
+	{0x900e3, 0x8},
+	{0x900e4, 0xa310},
+	{0x900e5, 0x168},
+	{0x900e6, 0xa},
+	{0x900e7, 0x408},
+	{0x900e8, 0x169},
+	{0x900e9, 0x6e},
+	{0x900ea, 0x0},
+	{0x900eb, 0x68},
+	{0x900ec, 0x0},
+	{0x900ed, 0x408},
+	{0x900ee, 0x169},
+	{0x900ef, 0x0},
+	{0x900f0, 0x8310},
+	{0x900f1, 0x168},
+	{0x900f2, 0x0},
+	{0x900f3, 0xa310},
+	{0x900f4, 0x168},
+	{0x900f5, 0x1ff8},
+	{0x900f6, 0x85a8},
+	{0x900f7, 0x1e8},
+	{0x900f8, 0x68},
+	{0x900f9, 0x798},
+	{0x900fa, 0x16a},
+	{0x900fb, 0x78},
+	{0x900fc, 0x7a0},
+	{0x900fd, 0x16a},
+	{0x900fe, 0x68},
+	{0x900ff, 0x790},
+	{0x90100, 0x16a},
+	{0x90101, 0x8},
+	{0x90102, 0x8b10},
+	{0x90103, 0x168},
+	{0x90104, 0x8},
+	{0x90105, 0xab10},
+	{0x90106, 0x168},
+	{0x90107, 0xa},
+	{0x90108, 0x408},
+	{0x90109, 0x169},
+	{0x9010a, 0x58},
+	{0x9010b, 0x0},
+	{0x9010c, 0x68},
+	{0x9010d, 0x0},
+	{0x9010e, 0x408},
+	{0x9010f, 0x169},
+	{0x90110, 0x0},
+	{0x90111, 0x8b10},
+	{0x90112, 0x168},
+	{0x90113, 0x1},
+	{0x90114, 0xab10},
+	{0x90115, 0x168},
+	{0x90116, 0x0},
+	{0x90117, 0x1d8},
+	{0x90118, 0x169},
+	{0x90119, 0x80},
+	{0x9011a, 0x790},
+	{0x9011b, 0x16a},
+	{0x9011c, 0x18},
+	{0x9011d, 0x7aa},
+	{0x9011e, 0x6a},
+	{0x9011f, 0xa},
+	{0x90120, 0x0},
+	{0x90121, 0x1e9},
+	{0x90122, 0x8},
+	{0x90123, 0x8080},
+	{0x90124, 0x108},
+	{0x90125, 0xf},
+	{0x90126, 0x408},
+	{0x90127, 0x169},
+	{0x90128, 0xc},
+	{0x90129, 0x0},
+	{0x9012a, 0x68},
+	{0x9012b, 0x9},
+	{0x9012c, 0x0},
+	{0x9012d, 0x1a9},
+	{0x9012e, 0x0},
+	{0x9012f, 0x408},
+	{0x90130, 0x169},
+	{0x90131, 0x0},
+	{0x90132, 0x8080},
+	{0x90133, 0x108},
+	{0x90134, 0x8},
+	{0x90135, 0x7aa},
+	{0x90136, 0x6a},
+	{0x90137, 0x0},
+	{0x90138, 0x8568},
+	{0x90139, 0x108},
+	{0x9013a, 0xb7},
+	{0x9013b, 0x790},
+	{0x9013c, 0x16a},
+	{0x9013d, 0x1f},
+	{0x9013e, 0x0},
+	{0x9013f, 0x68},
+	{0x90140, 0x8},
+	{0x90141, 0x8558},
+	{0x90142, 0x168},
+	{0x90143, 0xf},
+	{0x90144, 0x408},
+	{0x90145, 0x169},
+	{0x90146, 0xd},
+	{0x90147, 0x0},
+	{0x90148, 0x68},
+	{0x90149, 0x0},
+	{0x9014a, 0x408},
+	{0x9014b, 0x169},
+	{0x9014c, 0x0},
+	{0x9014d, 0x8558},
+	{0x9014e, 0x168},
+	{0x9014f, 0x8},
+	{0x90150, 0x3c8},
+	{0x90151, 0x1a9},
+	{0x90152, 0x3},
+	{0x90153, 0x370},
+	{0x90154, 0x129},
+	{0x90155, 0x20},
+	{0x90156, 0x2aa},
+	{0x90157, 0x9},
+	{0x90158, 0x8},
+	{0x90159, 0xe8},
+	{0x9015a, 0x109},
+	{0x9015b, 0x0},
+	{0x9015c, 0x8140},
+	{0x9015d, 0x10c},
+	{0x9015e, 0x10},
+	{0x9015f, 0x8138},
+	{0x90160, 0x104},
+	{0x90161, 0x8},
+	{0x90162, 0x448},
+	{0x90163, 0x109},
+	{0x90164, 0xf},
+	{0x90165, 0x7c0},
+	{0x90166, 0x109},
+	{0x90167, 0x0},
+	{0x90168, 0xe8},
+	{0x90169, 0x109},
+	{0x9016a, 0x47},
+	{0x9016b, 0x630},
+	{0x9016c, 0x109},
+	{0x9016d, 0x8},
+	{0x9016e, 0x618},
+	{0x9016f, 0x109},
+	{0x90170, 0x8},
+	{0x90171, 0xe0},
+	{0x90172, 0x109},
+	{0x90173, 0x0},
+	{0x90174, 0x7c8},
+	{0x90175, 0x109},
+	{0x90176, 0x8},
+	{0x90177, 0x8140},
+	{0x90178, 0x10c},
+	{0x90179, 0x0},
+	{0x9017a, 0x478},
+	{0x9017b, 0x109},
+	{0x9017c, 0x0},
+	{0x9017d, 0x1},
+	{0x9017e, 0x8},
+	{0x9017f, 0x8},
+	{0x90180, 0x4},
+	{0x90181, 0x0},
+	{0x90006, 0x8},
+	{0x90007, 0x7c8},
+	{0x90008, 0x109},
+	{0x90009, 0x0},
+	{0x9000a, 0x400},
+	{0x9000b, 0x106},
+	{0xd00e7, 0x400},
+	{0x90017, 0x0},
+	{0x9001f, 0x29},
+	{0x90026, 0x68},
+	{0x400d0, 0x0},
+	{0x400d1, 0x101},
+	{0x400d2, 0x105},
+	{0x400d3, 0x107},
+	{0x400d4, 0x10f},
+	{0x400d5, 0x202},
+	{0x400d6, 0x20a},
+	{0x400d7, 0x20b},
+	{0x2003a, 0x2},
+	{0x200be, 0x3},
+	{0x2000b, 0x7d},
+	{0x2000c, 0xfa},
+	{0x2000d, 0x9c4},
+	{0x2000e, 0x2c},
+	{0x9000c, 0x0},
+	{0x9000d, 0x173},
+	{0x9000e, 0x60},
+	{0x9000f, 0x6110},
+	{0x90010, 0x2152},
+	{0x90011, 0xdfbd},
+	{0x90012, 0x2060},
+	{0x90013, 0x6152},
+	{0x20010, 0x5a},
+	{0x20011, 0x3},
+	{0x40080, 0xe0},
+	{0x40081, 0x12},
+	{0x40082, 0xe0},
+	{0x40083, 0x12},
+	{0x40084, 0xe0},
+	{0x40085, 0x12},
+	{0x400fd, 0xf},
+	{0x10011, 0x1},
+	{0x10012, 0x1},
+	{0x10013, 0x180},
+	{0x10018, 0x1},
+	{0x10002, 0x6209},
+	{0x100b2, 0x1},
+	{0x101b4, 0x1},
+	{0x102b4, 0x1},
+	{0x103b4, 0x1},
+	{0x104b4, 0x1},
+	{0x105b4, 0x1},
+	{0x106b4, 0x1},
+	{0x107b4, 0x1},
+	{0x108b4, 0x1},
+	{0x11011, 0x1},
+	{0x11012, 0x1},
+	{0x11013, 0x180},
+	{0x11018, 0x1},
+	{0x11002, 0x6209},
+	{0x110b2, 0x1},
+	{0x111b4, 0x1},
+	{0x112b4, 0x1},
+	{0x113b4, 0x1},
+	{0x114b4, 0x1},
+	{0x115b4, 0x1},
+	{0x116b4, 0x1},
+	{0x117b4, 0x1},
+	{0x118b4, 0x1},
+	{0x12011, 0x1},
+	{0x12012, 0x1},
+	{0x12013, 0x180},
+	{0x12018, 0x1},
+	{0x12002, 0x6209},
+	{0x120b2, 0x1},
+	{0x121b4, 0x1},
+	{0x122b4, 0x1},
+	{0x123b4, 0x1},
+	{0x124b4, 0x1},
+	{0x125b4, 0x1},
+	{0x126b4, 0x1},
+	{0x127b4, 0x1},
+	{0x128b4, 0x1},
+	{0x13011, 0x1},
+	{0x13012, 0x1},
+	{0x13013, 0x180},
+	{0x13018, 0x1},
+	{0x13002, 0x6209},
+	{0x130b2, 0x1},
+	{0x131b4, 0x1},
+	{0x132b4, 0x1},
+	{0x133b4, 0x1},
+	{0x134b4, 0x1},
+	{0x135b4, 0x1},
+	{0x136b4, 0x1},
+	{0x137b4, 0x1},
+	{0x138b4, 0x1},
+	{0x20089, 0x1},
+	{0x20088, 0x19},
+	{0xc0080, 0x2},
+	{0xd0000, 0x1},
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+	{
+		/* P0 4000mts 1D */
+		.drate = 4000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = ddr_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+	},
+	{
+		/* P0 4000mts 2D */
+		.drate = 4000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = ddr_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = ddr_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+	.ddrphy_cfg = ddr_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+	.fsp_msg = ddr_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+	.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+	.ddrphy_pie = ddr_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+	.fsp_table = { 4000, },
+};
diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c
new file mode 100644
index 00000000000..d704d588579
--- /dev/null
+++ b/board/phytec/imx8mp-libra-fpsc/spl.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 PHYTEC Messtechnik GmbH
+ */
+
+#include <config.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
+#include <spl.h>
+
+#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
+#include "../common/imx8m_som_detection.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EEPROM_ADDR		0x51
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return BOOT_DEVICE_BOOTROM;
+}
+
+void spl_dram_init(void)
+{
+#if IS_ENABLED(CONFIG_PHYTEC_SOM_DETECTION)
+	int ret;
+
+	ret = phytec_eeprom_data_setup(NULL, 0, EEPROM_ADDR);
+	if (!ret) {
+		ret = phytec_imx8m_detect(NULL);
+		if (!ret)
+			phytec_print_som_info(NULL);
+	}
+#endif
+
+	ddr_init(&dram_timing);
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	ret = power_pca9450_init(0, 0x25);
+	if (ret)
+		printf("power init failed");
+	p = pmic_get("PCA9450");
+	pmic_probe(p);
+
+	/* BUCKxOUT_DVS0/1 control BUCK123 output */
+	pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
+
+	/* Increase VDD_SOC and VDD_ARM to OD voltage 0.95V */
+	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
+	pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
+
+	/* Set BUCK1 DVS1 to suspend controlled through PMIC_STBY_REQ */
+	pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
+	pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
+
+	/* Set WDOG_B_CFG to cold reset */
+	pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	arch_misc_init();
+
+	/* Set GIC clock to 500Mhz for OD VDD_SOC. */
+	clock_enable(CCGR_GIC, 0);
+	clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
+	clock_enable(CCGR_GIC, 1);
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	arch_cpu_init();
+
+	ret = spl_early_init();
+	if (ret) {
+		debug("spl_early_init() failed: %d\n", ret);
+		hang();
+	}
+
+	preloader_console_init();
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+}
diff --git a/board/phytec/phycore_am62ax/phycore_am62ax.env b/board/phytec/phycore_am62ax/phycore_am62ax.env
index 47e90f1b7c6..eeb7cd6899a 100644
--- a/board/phytec/phycore_am62ax/phycore_am62ax.env
+++ b/board/phytec/phycore_am62ax/phycore_am62ax.env
@@ -2,6 +2,7 @@
 #include <env/phytec/k3_mmc.env>
 #include <env/phytec/k3_net.env>
 #include <env/phytec/k3_spi.env>
+#include <env/phytec/watchdog.env>
 
 fdtaddr=0x88000000
 loadaddr=0x82000000
@@ -31,3 +32,5 @@ bootmeths=rauc script efi extlinux pxe
 bootmeths=script efi extlinux pxe
 #endif
 boot_targets=mmc1 mmc0 spi_flash dhcp
+
+watchdog=watchdog@e000000
diff --git a/board/phytec/phycore_am62x/phycore_am62x.env b/board/phytec/phycore_am62x/phycore_am62x.env
index 47e90f1b7c6..eeb7cd6899a 100644
--- a/board/phytec/phycore_am62x/phycore_am62x.env
+++ b/board/phytec/phycore_am62x/phycore_am62x.env
@@ -2,6 +2,7 @@
 #include <env/phytec/k3_mmc.env>
 #include <env/phytec/k3_net.env>
 #include <env/phytec/k3_spi.env>
+#include <env/phytec/watchdog.env>
 
 fdtaddr=0x88000000
 loadaddr=0x82000000
@@ -31,3 +32,5 @@ bootmeths=rauc script efi extlinux pxe
 bootmeths=script efi extlinux pxe
 #endif
 boot_targets=mmc1 mmc0 spi_flash dhcp
+
+watchdog=watchdog@e000000
diff --git a/board/phytec/phycore_am64x/phycore_am64x.env b/board/phytec/phycore_am64x/phycore_am64x.env
index f4136ed237d..67d2b87f144 100644
--- a/board/phytec/phycore_am64x/phycore_am64x.env
+++ b/board/phytec/phycore_am64x/phycore_am64x.env
@@ -1,6 +1,7 @@
 #include <env/phytec/k3_mmc.env>
 #include <env/phytec/k3_net.env>
 #include <env/phytec/k3_spi.env>
+#include <env/phytec/watchdog.env>
 
 fdtaddr=0x88000000
 loadaddr=0x82000000
@@ -30,3 +31,5 @@ bootmeths=rauc script efi extlinux pxe
 bootmeths=script efi extlinux pxe
 #endif
 boot_targets=mmc1 mmc0 spi_flash dhcp
+
+watchdog=watchdog@e000000
diff --git a/board/phytec/phycore_imx8mm/MAINTAINERS b/board/phytec/phycore_imx8mm/MAINTAINERS
index 7631e1cb331..58c5e2d0af9 100644
--- a/board/phytec/phycore_imx8mm/MAINTAINERS
+++ b/board/phytec/phycore_imx8mm/MAINTAINERS
@@ -9,6 +9,5 @@ F:	configs/imx8mm-phygate-tauri-l_defconfig
 F:      configs/phycore-imx8mm_defconfig
 F:	doc/board/phytec/imx8mm-phygate-tauri-l.rst
 F:	doc/board/phytec/index.rst
-F:	doc/board/phytec/imx8mm-optee-build.rsti
 F:	doc/board/phytec/phycore_imx8mm.rst
 F:      include/configs/phycore_imx8mm.h
diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
index 9a129a0a4bf..70044997adb 100644
--- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env
+++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env
@@ -3,7 +3,11 @@ bootcmd=
 		fastboot 0;
 	fi;
 	bootflow scan -lb;
+#ifdef CONFIG_BOOTMETH_RAUC
+bootmeths=rauc script efi
+#else
 bootmeths=script efi
+#endif
 boot_targets=mmc2 mmc1 usb ethernet
 bootenv_addr_r=0x49100000
 boot_script_dhcp=boot.scr.uimg
diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c
index fab66caf2a1..c6a4e923b07 100644
--- a/board/phytec/phycore_imx93/phycore-imx93.c
+++ b/board/phytec/phycore_imx93/phycore-imx93.c
@@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
 {
-	int ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
+	int ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
 
 	if (ret)
 		printf("%s: EEPROM data init failed\n", __func__);
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 9768b5257de..aa7d562911a 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -52,7 +52,7 @@ void spl_dram_init(void)
 	int ret;
 	enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID;
 
-	ret = phytec_eeprom_data_setup(NULL, 2, EEPROM_ADDR);
+	ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR);
 	if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX))
 		goto out;