summaryrefslogtreecommitdiff
path: root/drivers/clk/altera
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/clk/altera')
-rw-r--r--drivers/clk/altera/clk-agilex.c130
-rw-r--r--drivers/clk/altera/clk-agilex.h20
2 files changed, 144 insertions, 6 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index 242740a4b00..fdbf834bb2f 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -14,6 +14,7 @@
#include <dm/lists.h>
#include <dm/util.h>
#include <dt-bindings/clock/agilex-clock.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <asm/arch/clock_manager.h>
@@ -22,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR;
struct socfpga_clk_plat {
void __iomem *regs;
+ int pllgrp;
+ int bitmask;
};
/*
@@ -544,14 +547,11 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
/* Get EMAC clock source */
ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
if (emac_id == AGILEX_EMAC0_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK, ctl);
else if (emac_id == AGILEX_EMAC1_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK, ctl);
else if (emac_id == AGILEX_EMAC2_CLK)
- ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
- CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
+ ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK, ctl);
else
return 0;
@@ -643,8 +643,125 @@ static ulong socfpga_clk_get_rate(struct clk *clk)
}
}
+static int bitmask_from_clk_id(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+
+ switch (clk->id) {
+ case AGILEX_MPU_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK;
+ break;
+ case AGILEX_L4_MAIN_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;
+ break;
+ case AGILEX_L4_MP_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;
+ break;
+ case AGILEX_L4_SP_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK;
+ break;
+ case AGILEX_CS_AT_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_TRACE_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_PDBG_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;
+ break;
+ case AGILEX_CS_TIMER_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK;
+ break;
+ case AGILEX_S2F_USER0_CLK:
+ plat->pllgrp = CLKMGR_MAINPLL_EN;
+ plat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK;
+ break;
+ case AGILEX_EMAC0_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK;
+ break;
+ case AGILEX_EMAC1_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK;
+ break;
+ case AGILEX_EMAC2_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK;
+ break;
+ case AGILEX_EMAC_PTP_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK;
+ break;
+ case AGILEX_GPIO_DB_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK;
+ break;
+ case AGILEX_SDMMC_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK;
+ break;
+ case AGILEX_S2F_USER1_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK;
+ break;
+ case AGILEX_PSI_REF_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK;
+ break;
+ case AGILEX_USB_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK;
+ break;
+ case AGILEX_SPI_M_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK;
+ break;
+ case AGILEX_NAND_CLK:
+ plat->pllgrp = CLKMGR_PERPLL_EN;
+ plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
+ break;
+ default:
+ return -ENXIO;
+ }
+
+ return 0;
+}
+
static int socfpga_clk_enable(struct clk *clk)
{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+ int ret;
+
+ ret = bitmask_from_clk_id(clk);
+ if (ret)
+ return ret;
+
+ setbits_le32(base_addr + plat->pllgrp, plat->bitmask);
+
+ return 0;
+}
+
+static int socfpga_clk_disable(struct clk *clk)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
+ uintptr_t base_addr = (uintptr_t)plat->regs;
+ int ret;
+
+ ret = bitmask_from_clk_id(clk);
+ if (ret)
+ return ret;
+
+ clrbits_le32(base_addr + plat->pllgrp, plat->bitmask);
+
return 0;
}
@@ -672,6 +789,7 @@ static int socfpga_clk_of_to_plat(struct udevice *dev)
static struct clk_ops socfpga_clk_ops = {
.enable = socfpga_clk_enable,
+ .disable = socfpga_clk_disable,
.get_rate = socfpga_clk_get_rate,
};
diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h
index b3e8841a512..be639957940 100644
--- a/drivers/clk/altera/clk-agilex.h
+++ b/drivers/clk/altera/clk-agilex.h
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*/
#ifndef _CLK_AGILEX_
@@ -210,7 +211,26 @@ struct cm_config {
#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
+#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK BIT(0)
+#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK BIT(1)
+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK BIT(2)
+#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK BIT(3)
+#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK BIT(4)
+#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK BIT(5)
+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK BIT(6)
+
+#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK BIT(0)
+#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK BIT(1)
+#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK BIT(2)
+#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK BIT(3)
+#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK BIT(4)
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
+#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK BIT(6)
+#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK BIT(7)
+#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK BIT(8)
+#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK BIT(9)
+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK BIT(10)
+
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
generated by cgit v1.2.3 (git 2.0.4) at 2025-10-11 19:34:49 +0000