diff options
Diffstat (limited to 'include/dt-bindings/reset/mt8188-resets.h')
| -rw-r--r-- | include/dt-bindings/reset/mt8188-resets.h | 116 |
1 files changed, 0 insertions, 116 deletions
diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h deleted file mode 100644 index 5a58c54e7d2..00000000000 --- a/include/dt-bindings/reset/mt8188-resets.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Runyang Chen <runyang.chen@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8188 - -#define MT8188_TOPRGU_CONN_MCU_SW_RST 0 -#define MT8188_TOPRGU_INFRA_GRST_SW_RST 1 -#define MT8188_TOPRGU_IPU0_SW_RST 2 -#define MT8188_TOPRGU_IPU1_SW_RST 3 -#define MT8188_TOPRGU_IPU2_SW_RST 4 -#define MT8188_TOPRGU_AUD_ASRC_SW_RST 5 -#define MT8188_TOPRGU_INFRA_SW_RST 6 -#define MT8188_TOPRGU_MMSYS_SW_RST 7 -#define MT8188_TOPRGU_MFG_SW_RST 8 -#define MT8188_TOPRGU_VENC_SW_RST 9 -#define MT8188_TOPRGU_VDEC_SW_RST 10 -#define MT8188_TOPRGU_CAM_VCORE_SW_RST 11 -#define MT8188_TOPRGU_SCP_SW_RST 12 -#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13 -#define MT8188_TOPRGU_AUDIO_SW_RST 14 -#define MT8188_TOPRGU_CAMSYS_SW_RST 15 -#define MT8188_TOPRGU_MJC_SW_RST 16 -#define MT8188_TOPRGU_PERI_SW_RST 17 -#define MT8188_TOPRGU_PERI_AO_SW_RST 18 -#define MT8188_TOPRGU_PCIE_SW_RST 19 -#define MT8188_TOPRGU_ADSPSYS_SW_RST 21 -#define MT8188_TOPRGU_DPTX_SW_RST 22 -#define MT8188_TOPRGU_SPMI_MST_SW_RST 23 - -#define MT8188_TOPRGU_SW_RST_NUM 24 - -/* INFRA resets */ -#define MT8188_INFRA_RST1_THERMAL_MCU_RST 0 -#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 -#define MT8188_INFRA_RST3_PTP_CTRL_RST 2 - -#define MT8188_VDO0_RST_DISP_OVL0 0 -#define MT8188_VDO0_RST_FAKE_ENG0 1 -#define MT8188_VDO0_RST_DISP_CCORR0 2 -#define MT8188_VDO0_RST_DISP_MUTEX0 3 -#define MT8188_VDO0_RST_DISP_GAMMA0 4 -#define MT8188_VDO0_RST_DISP_DITHER0 5 -#define MT8188_VDO0_RST_DISP_WDMA0 6 -#define MT8188_VDO0_RST_DISP_RDMA0 7 -#define MT8188_VDO0_RST_DSI0 8 -#define MT8188_VDO0_RST_DSI1 9 -#define MT8188_VDO0_RST_DSC_WRAP0 10 -#define MT8188_VDO0_RST_VPP_MERGE0 11 -#define MT8188_VDO0_RST_DP_INTF0 12 -#define MT8188_VDO0_RST_DISP_AAL0 13 -#define MT8188_VDO0_RST_INLINEROT0 14 -#define MT8188_VDO0_RST_APB_BUS 15 -#define MT8188_VDO0_RST_DISP_COLOR0 16 -#define MT8188_VDO0_RST_MDP_WROT0 17 -#define MT8188_VDO0_RST_DISP_RSZ0 18 - -#define MT8188_VDO1_RST_SMI_LARB2 0 -#define MT8188_VDO1_RST_SMI_LARB3 1 -#define MT8188_VDO1_RST_GALS 2 -#define MT8188_VDO1_RST_FAKE_ENG0 3 -#define MT8188_VDO1_RST_FAKE_ENG1 4 -#define MT8188_VDO1_RST_MDP_RDMA0 5 -#define MT8188_VDO1_RST_MDP_RDMA1 6 -#define MT8188_VDO1_RST_MDP_RDMA2 7 -#define MT8188_VDO1_RST_MDP_RDMA3 8 -#define MT8188_VDO1_RST_VPP_MERGE0 9 -#define MT8188_VDO1_RST_VPP_MERGE1 10 -#define MT8188_VDO1_RST_VPP_MERGE2 11 -#define MT8188_VDO1_RST_VPP_MERGE3 12 -#define MT8188_VDO1_RST_VPP_MERGE4 13 -#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14 -#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15 -#define MT8188_VDO1_RST_DISP_MUTEX 16 -#define MT8188_VDO1_RST_MDP_RDMA4 17 -#define MT8188_VDO1_RST_MDP_RDMA5 18 -#define MT8188_VDO1_RST_MDP_RDMA6 19 -#define MT8188_VDO1_RST_MDP_RDMA7 20 -#define MT8188_VDO1_RST_DP_INTF1_MMCK 21 -#define MT8188_VDO1_RST_DPI0_MM_CK 22 -#define MT8188_VDO1_RST_DPI1_MM_CK 23 -#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24 -#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25 -#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26 -#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27 -#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28 -#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29 -#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30 -#define MT8188_VDO1_RST_PADDING0 31 -#define MT8188_VDO1_RST_PADDING1 32 -#define MT8188_VDO1_RST_PADDING2 33 -#define MT8188_VDO1_RST_PADDING3 34 -#define MT8188_VDO1_RST_PADDING4 35 -#define MT8188_VDO1_RST_PADDING5 36 -#define MT8188_VDO1_RST_PADDING6 37 -#define MT8188_VDO1_RST_PADDING7 38 -#define MT8188_VDO1_RST_DISP_RSZ0 39 -#define MT8188_VDO1_RST_DISP_RSZ1 40 -#define MT8188_VDO1_RST_DISP_RSZ2 41 -#define MT8188_VDO1_RST_DISP_RSZ3 42 -#define MT8188_VDO1_RST_HDR_VDO_FE0 43 -#define MT8188_VDO1_RST_HDR_GFX_FE0 44 -#define MT8188_VDO1_RST_HDR_VDO_BE 45 -#define MT8188_VDO1_RST_HDR_VDO_FE1 46 -#define MT8188_VDO1_RST_HDR_GFX_FE1 47 -#define MT8188_VDO1_RST_DISP_MIXER 48 -#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49 -#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50 -#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51 -#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 -#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ |