diff options
Diffstat (limited to 'include/dt-bindings/reset')
157 files changed, 773 insertions, 11651 deletions
diff --git a/include/dt-bindings/reset/actions,s500-reset.h b/include/dt-bindings/reset/actions,s500-reset.h deleted file mode 100644 index f5d94176d10..00000000000 --- a/include/dt-bindings/reset/actions,s500-reset.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Device Tree binding constants for Actions Semi S500 Reset Management Unit - * - * Copyright (c) 2014 Actions Semi Inc. - * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> - */ - -#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H -#define __DT_BINDINGS_ACTIONS_S500_RESET_H - -#define RESET_DMAC 0 -#define RESET_NORIF 1 -#define RESET_DDR 2 -#define RESET_NANDC 3 -#define RESET_SD0 4 -#define RESET_SD1 5 -#define RESET_PCM1 6 -#define RESET_DE 7 -#define RESET_LCD 8 -#define RESET_SD2 9 -#define RESET_DSI 10 -#define RESET_CSI 11 -#define RESET_BISP 12 -#define RESET_KEY 13 -#define RESET_GPIO 14 -#define RESET_AUDIO 15 -#define RESET_PCM0 16 -#define RESET_VDE 17 -#define RESET_VCE 18 -#define RESET_GPU3D 19 -#define RESET_NIC301 20 -#define RESET_LENS 21 -#define RESET_PERIPHRESET 22 -#define RESET_USB2_0 23 -#define RESET_TVOUT 24 -#define RESET_HDMI 25 -#define RESET_HDCP2TX 26 -#define RESET_UART6 27 -#define RESET_UART0 28 -#define RESET_UART1 29 -#define RESET_UART2 30 -#define RESET_SPI0 31 -#define RESET_SPI1 32 -#define RESET_SPI2 33 -#define RESET_SPI3 34 -#define RESET_I2C0 35 -#define RESET_I2C1 36 -#define RESET_USB3 37 -#define RESET_UART3 38 -#define RESET_UART4 39 -#define RESET_UART5 40 -#define RESET_I2C2 41 -#define RESET_I2C3 42 -#define RESET_ETHERNET 43 -#define RESET_CHIPID 44 -#define RESET_USB2_1 45 -#define RESET_WD0RESET 46 -#define RESET_WD1RESET 47 -#define RESET_WD2RESET 48 -#define RESET_WD3RESET 49 -#define RESET_DBG0RESET 50 -#define RESET_DBG1RESET 51 -#define RESET_DBG2RESET 52 -#define RESET_DBG3RESET 53 - -#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */ diff --git a/include/dt-bindings/reset/actions,s700-reset.h b/include/dt-bindings/reset/actions,s700-reset.h deleted file mode 100644 index 5e3b16b8ef5..00000000000 --- a/include/dt-bindings/reset/actions,s700-reset.h +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -// -// Device Tree binding constants for Actions Semi S700 Reset Management Unit -// -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H -#define __DT_BINDINGS_ACTIONS_S700_RESET_H - -#define RESET_AUDIO 0 -#define RESET_CSI 1 -#define RESET_DE 2 -#define RESET_DSI 3 -#define RESET_GPIO 4 -#define RESET_I2C0 5 -#define RESET_I2C1 6 -#define RESET_I2C2 7 -#define RESET_I2C3 8 -#define RESET_KEY 9 -#define RESET_LCD0 10 -#define RESET_SI 11 -#define RESET_SPI0 12 -#define RESET_SPI1 13 -#define RESET_SPI2 14 -#define RESET_SPI3 15 -#define RESET_UART0 16 -#define RESET_UART1 17 -#define RESET_UART2 18 -#define RESET_UART3 19 -#define RESET_UART4 20 -#define RESET_UART5 21 -#define RESET_UART6 22 - -#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */ diff --git a/include/dt-bindings/reset/actions,s900-reset.h b/include/dt-bindings/reset/actions,s900-reset.h deleted file mode 100644 index 42c19d02e43..00000000000 --- a/include/dt-bindings/reset/actions,s900-reset.h +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -// -// Device Tree binding constants for Actions Semi S900 Reset Management Unit -// -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H -#define __DT_BINDINGS_ACTIONS_S900_RESET_H - -#define RESET_CHIPID 0 -#define RESET_CPU_SCNT 1 -#define RESET_SRAMI 2 -#define RESET_DDR_CTL_PHY 3 -#define RESET_DMAC 4 -#define RESET_GPIO 5 -#define RESET_BISP_AXI 6 -#define RESET_CSI0 7 -#define RESET_CSI1 8 -#define RESET_DE 9 -#define RESET_DSI 10 -#define RESET_GPU3D_PA 11 -#define RESET_GPU3D_PB 12 -#define RESET_HDE 13 -#define RESET_I2C0 14 -#define RESET_I2C1 15 -#define RESET_I2C2 16 -#define RESET_I2C3 17 -#define RESET_I2C4 18 -#define RESET_I2C5 19 -#define RESET_IMX 20 -#define RESET_NANDC0 21 -#define RESET_NANDC1 22 -#define RESET_SD0 23 -#define RESET_SD1 24 -#define RESET_SD2 25 -#define RESET_SD3 26 -#define RESET_SPI0 27 -#define RESET_SPI1 28 -#define RESET_SPI2 29 -#define RESET_SPI3 30 -#define RESET_UART0 31 -#define RESET_UART1 32 -#define RESET_UART2 33 -#define RESET_UART3 34 -#define RESET_UART4 35 -#define RESET_UART5 36 -#define RESET_UART6 37 -#define RESET_HDMI 38 -#define RESET_LVDS 39 -#define RESET_EDP 40 -#define RESET_USB2HUB 41 -#define RESET_USB2HSIC 42 -#define RESET_USB3 43 -#define RESET_PCM1 44 -#define RESET_AUDIO 45 -#define RESET_PCM0 46 -#define RESET_SE 47 -#define RESET_GIC 48 -#define RESET_DDR_CTL_PHY_AXI 49 -#define RESET_CMU_DDR 50 -#define RESET_DMM 51 -#define RESET_HDCP2TX 52 -#define RESET_ETHERNET 53 - -#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-bindings/reset/airoha,en7581-reset.h deleted file mode 100644 index 6544a1790b8..00000000000 --- a/include/dt-bindings/reset/airoha,en7581-reset.h +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2024 AIROHA Inc - * Author: Lorenzo Bianconi <lorenzo@kernel.org> - */ - -#ifndef __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ -#define __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ - -/* RST_CTRL2 */ -#define EN7581_XPON_PHY_RST 0 -#define EN7581_CPU_TIMER2_RST 1 -#define EN7581_HSUART_RST 2 -#define EN7581_UART4_RST 3 -#define EN7581_UART5_RST 4 -#define EN7581_I2C2_RST 5 -#define EN7581_XSI_MAC_RST 6 -#define EN7581_XSI_PHY_RST 7 -#define EN7581_NPU_RST 8 -#define EN7581_I2S_RST 9 -#define EN7581_TRNG_RST 10 -#define EN7581_TRNG_MSTART_RST 11 -#define EN7581_DUAL_HSI0_RST 12 -#define EN7581_DUAL_HSI1_RST 13 -#define EN7581_HSI_RST 14 -#define EN7581_DUAL_HSI0_MAC_RST 15 -#define EN7581_DUAL_HSI1_MAC_RST 16 -#define EN7581_HSI_MAC_RST 17 -#define EN7581_WDMA_RST 18 -#define EN7581_WOE0_RST 19 -#define EN7581_WOE1_RST 20 -#define EN7581_HSDMA_RST 21 -#define EN7581_TDMA_RST 22 -#define EN7581_EMMC_RST 23 -#define EN7581_SOE_RST 24 -#define EN7581_PCIE2_RST 25 -#define EN7581_XFP_MAC_RST 26 -#define EN7581_USB_HOST_P1_RST 27 -#define EN7581_USB_HOST_P1_U3_PHY_RST 28 -/* RST_CTRL1 */ -#define EN7581_PCM1_ZSI_ISI_RST 29 -#define EN7581_FE_PDMA_RST 30 -#define EN7581_FE_QDMA_RST 31 -#define EN7581_PCM_SPIWP_RST 32 -#define EN7581_CRYPTO_RST 33 -#define EN7581_TIMER_RST 34 -#define EN7581_PCM1_RST 35 -#define EN7581_UART_RST 36 -#define EN7581_GPIO_RST 37 -#define EN7581_GDMA_RST 38 -#define EN7581_I2C_MASTER_RST 39 -#define EN7581_PCM2_ZSI_ISI_RST 40 -#define EN7581_SFC_RST 41 -#define EN7581_UART2_RST 42 -#define EN7581_GDMP_RST 43 -#define EN7581_FE_RST 44 -#define EN7581_USB_HOST_P0_RST 45 -#define EN7581_GSW_RST 46 -#define EN7581_SFC2_PCM_RST 47 -#define EN7581_PCIE0_RST 48 -#define EN7581_PCIE1_RST 49 -#define EN7581_CPU_TIMER_RST 50 -#define EN7581_PCIE_HB_RST 51 -#define EN7581_XPON_MAC_RST 52 - -#endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h deleted file mode 100644 index 5d8a494c98d..00000000000 --- a/include/dt-bindings/reset/altr,rst-mgr-a10.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 - -/* PER0MODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define EMAC2_RESET 34 -#define USB0_RESET 35 -#define USB1_RESET 36 -#define NAND_RESET 37 -#define QSPI_RESET 38 -#define SDMMC_RESET 39 -#define EMAC0_OCP_RESET 40 -#define EMAC1_OCP_RESET 41 -#define EMAC2_OCP_RESET 42 -#define USB0_OCP_RESET 43 -#define USB1_OCP_RESET 44 -#define NAND_OCP_RESET 45 -#define QSPI_OCP_RESET 46 -#define SDMMC_OCP_RESET 47 -#define DMA_RESET 48 -#define SPIM0_RESET 49 -#define SPIM1_RESET 50 -#define SPIS0_RESET 51 -#define SPIS1_RESET 52 -#define DMA_OCP_RESET 53 -#define EMAC_PTP_RESET 54 -/* 55 is empty*/ -#define DMAIF0_RESET 56 -#define DMAIF1_RESET 57 -#define DMAIF2_RESET 58 -#define DMAIF3_RESET 59 -#define DMAIF4_RESET 60 -#define DMAIF5_RESET 61 -#define DMAIF6_RESET 62 -#define DMAIF7_RESET 63 - -/* PER1MODRST */ -#define L4WD0_RESET 64 -#define L4WD1_RESET 65 -#define L4SYSTIMER0_RESET 66 -#define L4SYSTIMER1_RESET 67 -#define SPTIMER0_RESET 68 -#define SPTIMER1_RESET 69 -/* 70-71 is reserved */ -#define I2C0_RESET 72 -#define I2C1_RESET 73 -#define I2C2_RESET 74 -#define I2C3_RESET 75 -#define I2C4_RESET 76 -/* 77-79 is reserved */ -#define UART0_RESET 80 -#define UART1_RESET 81 -/* 82-87 is reserved */ -#define GPIO0_RESET 88 -#define GPIO1_RESET 89 -#define GPIO2_RESET 90 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 -#define F2SSDRAM0_RESET 99 -#define F2SSDRAM1_RESET 100 -#define F2SSDRAM2_RESET 101 -#define DDRSCH_RESET 102 - -/* SYSMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -/* 130 is reserved */ -#define FPGAMGR_RESET 131 -#define S2F_RESET 132 -#define SYSDBG_RESET 133 -#define OCRAM_OCP_RESET 134 - -/* COLDMODRST */ -#define CLKMGRCOLD_RESET 160 -/* 161-162 is reserved */ -#define S2FCOLD_RESET 163 -#define TIMESTAMPCOLD_RESET 164 -#define TAPCOLD_RESET 165 -#define HMCCOLD_RESET 166 -#define IOMGRCOLD_RESET 167 - -/* NRSTMODRST */ -#define NRSTPINOE_RESET 192 - -/* DBGMODRST */ -#define DBG_RESET 224 -#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10sr.h b/include/dt-bindings/reset/altr,rst-mgr-a10sr.h deleted file mode 100644 index 09a15ea5818..00000000000 --- a/include/dt-bindings/reset/altr,rst-mgr-a10sr.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright Intel Corporation (C) 2017. All Rights Reserved - * - * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip - * - * Adapted from altr,rst-mgr-a10.h - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H - -/* Peripheral PHY resets */ -#define A10SR_RESET_ENET_HPS 0 -#define A10SR_RESET_PCIE 1 -#define A10SR_RESET_FILE 2 -#define A10SR_RESET_BQSPI 3 -#define A10SR_RESET_USB 4 - -#define A10SR_RESET_NUM 5 - -#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr-agx5.h b/include/dt-bindings/reset/altr,rst-mgr-agx5.h new file mode 100644 index 00000000000..1dba270aed4 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-agx5.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 Intel Corporation. All rights reserved + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_AGX_EDGE_H + +/* PER0MODRST */ +#define EMAC0_RESET 0 +#define EMAC1_RESET 1 +#define EMAC2_RESET 2 +#define USB0_RESET 3 +#define USB1_RESET 4 +#define NAND_RESET 5 +#define COMBOPHY_RESET 6 +#define SDMMC_RESET 7 +#define EMAC0_OCP_RESET 8 +#define EMAC1_OCP_RESET 9 +#define EMAC2_OCP_RESET 10 +#define USB0_OCP_RESET 11 +#define USB1_OCP_RESET 12 +#define NAND_OCP_RESET 13 +/* 14 is empty */ +#define SDMMC_OCP_RESET 15 +#define DMA_RESET 16 +#define SPIM0_RESET 17 +#define SPIM1_RESET 18 +#define SPIS0_RESET 19 +#define SPIS1_RESET 20 +#define DMA_OCP_RESET 21 +#define EMAC_PTP_RESET 22 +/* 23 is empty*/ +#define DMAIF0_RESET 24 +#define DMAIF1_RESET 25 +#define DMAIF2_RESET 26 +#define DMAIF3_RESET 27 +#define DMAIF4_RESET 28 +#define DMAIF5_RESET 29 +#define DMAIF6_RESET 30 +#define DMAIF7_RESET 31 + +/* PER1MODRST */ +#define WATCHDOG0_RESET 32 +#define WATCHDOG1_RESET 33 +#define WATCHDOG2_RESET 34 +#define WATCHDOG3_RESET 35 +#define L4SYSTIMER0_RESET 36 +#define L4SYSTIMER1_RESET 37 +#define SPTIMER0_RESET 38 +#define SPTIMER1_RESET 39 +#define I2C0_RESET 40 +#define I2C1_RESET 41 +#define I2C2_RESET 42 +#define I2C3_RESET 43 +#define I2C4_RESET 44 +#define I3C0_RESET 45 +#define I3C1_RESET 46 +/* 47 is empty */ +#define UART0_RESET 48 +#define UART1_RESET 49 +/* 50-55 is empty */ +#define GPIO0_RESET 56 +#define GPIO1_RESET 57 +#define WATCHDOG4_RESET 58 +/* 59-63 is empty */ + +/* BRGMODRST */ +#define SOC2FPGA_RESET 64 +#define LWHPS2FPGA_RESET 65 +#define FPGA2SOC_RESET 66 +#define F2SSDRAM_RESET 67 +/* 68-69 is empty */ +#define DDRSCH_RESET 70 +/* 71-95 is empty */ + +/* DBGMODRST */ +#define DBG_RESET 192 + +#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h deleted file mode 100644 index 04c4d0c6fd3..00000000000 --- a/include/dt-bindings/reset/altr,rst-mgr-s10.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Intel Corporation. All rights reserved - * Copyright (C) 2016 Altera Corporation. All rights reserved - * - * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define CPU2_RESET 2 -#define CPU3_RESET 3 - -/* PER0MODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define EMAC2_RESET 34 -#define USB0_RESET 35 -#define USB1_RESET 36 -#define NAND_RESET 37 -/* 38 is empty */ -#define SDMMC_RESET 39 -#define EMAC0_OCP_RESET 40 -#define EMAC1_OCP_RESET 41 -#define EMAC2_OCP_RESET 42 -#define USB0_OCP_RESET 43 -#define USB1_OCP_RESET 44 -#define NAND_OCP_RESET 45 -/* 46 is empty */ -#define SDMMC_OCP_RESET 47 -#define DMA_RESET 48 -#define SPIM0_RESET 49 -#define SPIM1_RESET 50 -#define SPIS0_RESET 51 -#define SPIS1_RESET 52 -#define DMA_OCP_RESET 53 -#define EMAC_PTP_RESET 54 -/* 55 is empty*/ -#define DMAIF0_RESET 56 -#define DMAIF1_RESET 57 -#define DMAIF2_RESET 58 -#define DMAIF3_RESET 59 -#define DMAIF4_RESET 60 -#define DMAIF5_RESET 61 -#define DMAIF6_RESET 62 -#define DMAIF7_RESET 63 - -/* PER1MODRST */ -#define WATCHDOG0_RESET 64 -#define WATCHDOG1_RESET 65 -#define WATCHDOG2_RESET 66 -#define WATCHDOG3_RESET 67 -#define L4SYSTIMER0_RESET 68 -#define L4SYSTIMER1_RESET 69 -#define SPTIMER0_RESET 70 -#define SPTIMER1_RESET 71 -#define I2C0_RESET 72 -#define I2C1_RESET 73 -#define I2C2_RESET 74 -#define I2C3_RESET 75 -#define I2C4_RESET 76 -#define I3C0_RESET 77 -#define I3C1_RESET 78 -/* 79 is empty */ -#define UART0_RESET 80 -#define UART1_RESET 81 -/* 82-87 is empty */ -#define GPIO0_RESET 88 -#define GPIO1_RESET 89 -#define WATCHDOG4_RESET 90 - -/* BRGMODRST */ -#define SOC2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2SOC_RESET 98 -#define F2SSDRAM0_RESET 99 -#define F2SSDRAM1_RESET 100 -#define F2SSDRAM2_RESET 101 -#define DDRSCH_RESET 102 - -/* COLDMODRST */ -#define CPUPO0_RESET 160 -#define CPUPO1_RESET 161 -#define CPUPO2_RESET 162 -#define CPUPO3_RESET 163 -/* 164-167 is empty */ -#define L2_RESET 168 - -/* DBGMODRST */ -#define DBG_RESET 224 -#define CSDAP_RESET 225 - -/* TAPMODRST */ -#define TAP_RESET 256 - -#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h deleted file mode 100644 index 9b6ce14f62c..00000000000 --- a/include/dt-bindings/reset/altr,rst-mgr.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 -#define L2_RESET 4 - -/* PERMODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define USB0_RESET 34 -#define USB1_RESET 35 -#define NAND_RESET 36 -#define QSPI_RESET 37 -#define L4WD0_RESET 38 -#define L4WD1_RESET 39 -#define OSC1TIMER0_RESET 40 -#define OSC1TIMER1_RESET 41 -#define SPTIMER0_RESET 42 -#define SPTIMER1_RESET 43 -#define I2C0_RESET 44 -#define I2C1_RESET 45 -#define I2C2_RESET 46 -#define I2C3_RESET 47 -#define UART0_RESET 48 -#define UART1_RESET 49 -#define SPIM0_RESET 50 -#define SPIM1_RESET 51 -#define SPIS0_RESET 52 -#define SPIS1_RESET 53 -#define SDMMC_RESET 54 -#define CAN0_RESET 55 -#define CAN1_RESET 56 -#define GPIO0_RESET 57 -#define GPIO1_RESET 58 -#define GPIO2_RESET 59 -#define DMA_RESET 60 -#define SDR_RESET 61 - -/* PER2MODRST */ -#define DMAIF0_RESET 64 -#define DMAIF1_RESET 65 -#define DMAIF2_RESET 66 -#define DMAIF3_RESET 67 -#define DMAIF4_RESET 68 -#define DMAIF5_RESET 69 -#define DMAIF6_RESET 70 -#define DMAIF7_RESET 71 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 - -/* MISCMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -#define SYSMGR_RESET 130 -#define SYSMGRCOLD_RESET 131 -#define FPGAMGR_RESET 132 -#define ACPIDMAP_RESET 133 -#define S2F_RESET 134 -#define S2FCOLD_RESET 135 -#define NRSTPIN_RESET 136 -#define TIMESTAMPCOLD_RESET 137 -#define CLKMGRCOLD_RESET 138 -#define SCANMGR_RESET 139 -#define FRZCTRLCOLD_RESET 140 -#define SYSDBG_RESET 141 -#define DBG_RESET 142 -#define TAPCOLD_RESET 143 -#define SDRCOLD_RESET 144 - -#endif diff --git a/include/dt-bindings/reset/amlogic,c3-reset.h b/include/dt-bindings/reset/amlogic,c3-reset.h deleted file mode 100644 index d9127863f60..00000000000 --- a/include/dt-bindings/reset/amlogic,c3-reset.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Copyright (c) 2023 Amlogic, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_AMLOGIC_C3_RESET_H -#define _DT_BINDINGS_AMLOGIC_C3_RESET_H - -/* RESET0 */ -/* 0-3 */ -#define RESET_USBCTRL 4 -/* 5-7 */ -#define RESET_USBPHY20 8 -/* 9 */ -#define RESET_USB2DRD 10 -#define RESET_MIPI_DSI_HOST 11 -#define RESET_MIPI_DSI_PHY 12 -/* 13-20 */ -#define RESET_GE2D 21 -#define RESET_DWAP 22 -/* 23-31 */ - -/* RESET1 */ -#define RESET_AUDIO 32 -/* 33-34 */ -#define RESET_DDRAPB 35 -#define RESET_DDR 36 -#define RESET_DOS_CAPB3 37 -#define RESET_DOS 38 -/* 39-46 */ -#define RESET_NNA 47 -#define RESET_ETHERNET 48 -#define RESET_ISP 49 -#define RESET_VC9000E_APB 50 -#define RESET_VC9000E_A 51 -/* 52 */ -#define RESET_VC9000E_CORE 53 -/* 54-63 */ - -/* RESET2 */ -#define RESET_ABUS_ARB 64 -#define RESET_IRCTRL 65 -/* 66 */ -#define RESET_TEMP_PII 67 -/* 68-72 */ -#define RESET_SPICC_0 73 -#define RESET_SPICC_1 74 -#define RESET_RSA 75 - -/* 76-79 */ -#define RESET_MSR_CLK 80 -#define RESET_SPIFC 81 -#define RESET_SAR_ADC 82 -/* 83-87 */ -#define RESET_ACODEC 88 -/* 89-90 */ -#define RESET_WATCHDOG 91 -/* 92-95 */ - -/* RESET3 */ -#define RESET_ISP_NIC_GPV 96 -#define RESET_ISP_NIC_MAIN 97 -#define RESET_ISP_NIC_VCLK 98 -#define RESET_ISP_NIC_VOUT 99 -#define RESET_ISP_NIC_ALL 100 -#define RESET_VOUT 101 -#define RESET_VOUT_VENC 102 -/* 103 */ -#define RESET_CVE_NIC_GPV 104 -#define RESET_CVE_NIC_MAIN 105 -#define RESET_CVE_NIC_GE2D 106 -#define RESET_CVE_NIC_DW 106 -#define RESET_CVE_NIC_CVE 108 -#define RESET_CVE_NIC_ALL 109 -#define RESET_CVE 110 -/* 112-127 */ - -/* RESET4 */ -#define RESET_RTC 128 -#define RESET_PWM_AB 129 -#define RESET_PWM_CD 130 -#define RESET_PWM_EF 131 -#define RESET_PWM_GH 132 -#define RESET_PWM_IJ 133 -#define RESET_PWM_KL 134 -#define RESET_PWM_MN 135 -/* 136-137 */ -#define RESET_UART_A 138 -#define RESET_UART_B 139 -#define RESET_UART_C 140 -#define RESET_UART_D 141 -#define RESET_UART_E 142 -#define RESET_UART_F 143 -#define RESET_I2C_S_A 144 -#define RESET_I2C_M_A 145 -#define RESET_I2C_M_B 146 -#define RESET_I2C_M_C 147 -#define RESET_I2C_M_D 148 -/* 149-151 */ -#define RESET_SD_EMMC_A 152 -#define RESET_SD_EMMC_B 153 -#define RESET_SD_EMMC_C 154 - -/* RESET5 */ -/* 160-172 */ -#define RESET_BRG_NIC_NNA 173 -#define RESET_BRG_MUX_NIC_MAIN 174 -#define RESET_BRG_AO_NIC_ALL 175 -/* 176-183 */ -#define RESET_BRG_NIC_VAPB 184 -#define RESET_BRG_NIC_SDIO_B 185 -#define RESET_BRG_NIC_SDIO_A 186 -#define RESET_BRG_NIC_EMMC 187 -#define RESET_BRG_NIC_DSU 188 -#define RESET_BRG_NIC_SYSCLK 189 -#define RESET_BRG_NIC_MAIN 190 -#define RESET_BRG_NIC_ALL 191 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h deleted file mode 100644 index 7693552f150..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-a1-audio-reset.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2024, SaluteDevices. All Rights Reserved. - * - * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com> - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H - -#define AUD_RESET_DDRARB 0 -#define AUD_RESET_TDMIN_A 1 -#define AUD_RESET_TDMIN_B 2 -#define AUD_RESET_TDMIN_LB 3 -#define AUD_RESET_LOOPBACK 4 -#define AUD_RESET_TDMOUT_A 5 -#define AUD_RESET_TDMOUT_B 6 -#define AUD_RESET_FRDDR_A 7 -#define AUD_RESET_FRDDR_B 8 -#define AUD_RESET_TODDR_A 9 -#define AUD_RESET_TODDR_B 10 -#define AUD_RESET_SPDIFIN 11 -#define AUD_RESET_RESAMPLE 12 -#define AUD_RESET_EQDRC 13 -#define AUD_RESET_LOCKER 14 -#define AUD_RESET_TOACODEC 30 -#define AUD_RESET_CLKTREE 31 - -#define AUD_VAD_RESET_DDRARB 0 -#define AUD_VAD_RESET_PDM 1 -#define AUD_VAD_RESET_TDMIN_VAD 2 -#define AUD_VAD_RESET_TODDR_VAD 3 -#define AUD_VAD_RESET_TOVAD 4 -#define AUD_VAD_RESET_CLKTREE 5 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON_A1_AUDIO_RESET_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h deleted file mode 100644 index f1a3a797540..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-a1-reset.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (c) 2019 Amlogic, Inc. All rights reserved. - * Author: Xingyu Chen <xingyu.chen@amlogic.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H - -/* RESET0 */ -/* 0 */ -#define RESET_AM2AXI_VAD 1 -/* 2-3 */ -#define RESET_PSRAM 4 -#define RESET_PAD_CTRL 5 -/* 6 */ -#define RESET_TEMP_SENSOR 7 -#define RESET_AM2AXI_DEV 8 -/* 9 */ -#define RESET_SPICC_A 10 -#define RESET_MSR_CLK 11 -#define RESET_AUDIO 12 -#define RESET_ANALOG_CTRL 13 -#define RESET_SAR_ADC 14 -#define RESET_AUDIO_VAD 15 -#define RESET_CEC 16 -#define RESET_PWM_EF 17 -#define RESET_PWM_CD 18 -#define RESET_PWM_AB 19 -/* 20 */ -#define RESET_IR_CTRL 21 -#define RESET_I2C_S_A 22 -/* 23 */ -#define RESET_I2C_M_D 24 -#define RESET_I2C_M_C 25 -#define RESET_I2C_M_B 26 -#define RESET_I2C_M_A 27 -#define RESET_I2C_PROD_AHB 28 -#define RESET_I2C_PROD 29 -/* 30-31 */ - -/* RESET1 */ -#define RESET_ACODEC 32 -#define RESET_DMA 33 -#define RESET_SD_EMMC_A 34 -/* 35 */ -#define RESET_USBCTRL 36 -/* 37 */ -#define RESET_USBPHY 38 -/* 39-41 */ -#define RESET_RSA 42 -#define RESET_DMC 43 -/* 44 */ -#define RESET_IRQ_CTRL 45 -/* 46 */ -#define RESET_NIC_VAD 47 -#define RESET_NIC_AXI 48 -#define RESET_RAMA 49 -#define RESET_RAMB 50 -/* 51-52 */ -#define RESET_ROM 53 -#define RESET_SPIFC 54 -#define RESET_GIC 55 -#define RESET_UART_C 56 -#define RESET_UART_B 57 -#define RESET_UART_A 58 -#define RESET_OSC_RING 59 -/* 60-63 */ - -/* RESET2 */ -/* 64-95 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h deleted file mode 100644 index 1ef807856cb..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) - * - * Copyright (c) 2018 Baylibre SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H - -#define AXG_ARB_TODDR_A 0 -#define AXG_ARB_TODDR_B 1 -#define AXG_ARB_TODDR_C 2 -#define AXG_ARB_FRDDR_A 3 -#define AXG_ARB_FRDDR_B 4 -#define AXG_ARB_FRDDR_C 5 -#define AXG_ARB_TODDR_D 6 -#define AXG_ARB_FRDDR_D 7 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ diff --git a/include/dt-bindings/reset/amlogic,meson-axg-reset.h b/include/dt-bindings/reset/amlogic,meson-axg-reset.h deleted file mode 100644 index 0f2e0fe45ca..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-axg-reset.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * - * Copyright (c) 2017 Amlogic, inc. - * Author: Yixun Lan <yixun.lan@amlogic.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_AXG_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -#define RESET_PCIE_A 1 -#define RESET_PCIE_B 2 -#define RESET_DDR_TOP 3 -/* 4 */ -#define RESET_VIU 5 -#define RESET_PCIE_PHY 6 -#define RESET_PCIE_APB 7 -/* 8 */ -/* 9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -/* 12 */ -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18-21 */ -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -/* 28-31 */ -/* RESET1 */ -/* 32 */ -/* 33 */ -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -/* 37 */ -#define RESET_AHB_SRAM 38 -/* 39 */ -/* 40 */ -#define RESET_DMA 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -/* 44 */ -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -/* 61-63 */ -/* RESET2 */ -/* 64 */ -/* 65 */ -#define RESET_AUDIO 66 -/* 67 */ -#define RESET_MIPI_HOST 68 -#define RESET_AUDIO_LOCKER 69 -#define RESET_GE2D 70 -/* 71-76 */ -#define RESET_AO_CPU_RESET 77 -/* 78-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -/* 97-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -#define RESET_MIPI_PHY 130 -/* 131-140 */ -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -/* 194 */ -/* 195 */ -#define RESET_PERIPHS_I2C_MASTER_0 196 -/* 197-200 */ -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1 202 -/* 203-204 */ -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_I2C_MASTER_3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -#define RESET_DMC_VPU_PIPEL 233 -/* 234-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h deleted file mode 100644 index f805129ca7a..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H - -#define AUD_RESET_PDM 0 -#define AUD_RESET_TDMIN_A 1 -#define AUD_RESET_TDMIN_B 2 -#define AUD_RESET_TDMIN_C 3 -#define AUD_RESET_TDMIN_LB 4 -#define AUD_RESET_LOOPBACK 5 -#define AUD_RESET_TODDR_A 6 -#define AUD_RESET_TODDR_B 7 -#define AUD_RESET_TODDR_C 8 -#define AUD_RESET_FRDDR_A 9 -#define AUD_RESET_FRDDR_B 10 -#define AUD_RESET_FRDDR_C 11 -#define AUD_RESET_TDMOUT_A 12 -#define AUD_RESET_TDMOUT_B 13 -#define AUD_RESET_TDMOUT_C 14 -#define AUD_RESET_SPDIFOUT 15 -#define AUD_RESET_SPDIFOUT_B 16 -#define AUD_RESET_SPDIFIN 17 -#define AUD_RESET_EQDRC 18 -#define AUD_RESET_RESAMPLE 19 -#define AUD_RESET_DDRARB 20 -#define AUD_RESET_POWDET 21 -#define AUD_RESET_TORAM 22 -#define AUD_RESET_TOACODEC 23 -#define AUD_RESET_TOHDMITX 24 -#define AUD_RESET_CLKTREE 25 - -/* SM1 added resets */ -#define AUD_RESET_RESAMPLE_B 26 -#define AUD_RESET_TOVAD 27 -#define AUD_RESET_LOCKER 28 -#define AUD_RESET_SPDIFIN_LB 29 -#define AUD_RESET_FRATV 30 -#define AUD_RESET_FRHDMIRX 31 -#define AUD_RESET_FRDDR_D 32 -#define AUD_RESET_TODDR_D 33 -#define AUD_RESET_LOOPBACK_B 34 -#define AUD_RESET_EARCTX 35 -#define AUD_RESET_EARCRX 36 -#define AUD_RESET_FRDDR_E 37 -#define AUD_RESET_TODDR_E 38 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-reset.h deleted file mode 100644 index 45f6b8a951d..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-g12a-reset.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet <jbrunet@baylibre.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_G12A_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS 2 -/* 3-4 */ -#define RESET_VIU 5 -#define RESET_AFIFO 6 -#define RESET_VID_PLL_DIV 7 -/* 8-9 */ -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_PCIE_CTRL_A 12 -#define RESET_VCBUS 13 -#define RESET_PCIE_PHY 14 -#define RESET_PCIE_APB 15 -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -/* 18 */ -#define RESET_HDMITX_CAPB3 19 -#define RESET_DVALIN_CAPB3 20 -#define RESET_DOS_CAPB3 21 -/* 22 */ -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -/* 27-31 */ -/* RESET1 */ -/* 32 */ -#define RESET_DEMUX 33 -#define RESET_USB 34 -#define RESET_DDR 35 -/* 36 */ -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -/* 41 */ -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -/* 47 */ -#define RESET_USB_PHY20 48 -#define RESET_USB_PHY21 49 -/* 50-60 */ -#define RESET_AUDIO_CODEC 61 -/* 62-63 */ -/* RESET2 */ -/* 64 */ -#define RESET_AUDIO 65 -#define RESET_HDMITX_PHY 66 -/* 67 */ -#define RESET_MIPI_DSI_HOST 68 -#define RESET_ALOCKER 69 -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75 */ -#define RESET_NNA 76 -/* 77 */ -#define RESET_DVALIN 78 -#define RESET_HDMITX 79 -/* 80-95 */ -/* RESET3 */ -/* 96-95 */ -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES_PL 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_0 109 -#define RESET_DEMUX_1 110 -#define RESET_DEMUX_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128-129 */ -#define RESET_MIPI_DSI_PHY 130 -/* 131-132 */ -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -/* 138-139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_M1 142 -#define RESET_I2C_M2 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_GEN 192 -#define RESET_SPICC0 193 -#define RESET_SC 194 -#define RESET_SANA_3 195 -#define RESET_I2C_M0 196 -#define RESET_TS_PLL 197 -#define RESET_SPICC1 198 -#define RESET_STREAM 199 -#define RESET_TS_CPU 200 -#define RESET_UART0 201 -#define RESET_UART1_2 202 -#define RESET_ASYNC0 203 -#define RESET_ASYNC1 204 -#define RESET_SPIFC0 205 -#define RESET_I2C_M3 206 -/* 207-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -#define RESET_TS_GPU 228 -#define RESET_DEVICE_MMC_ARB 229 -#define RESET_DVALIN_DMC_PIPL 230 -#define RESET_VID_LOCK 231 -#define RESET_NIC_DMC_PIPL 232 -#define RESET_DMC_VPU_PIPL 233 -#define RESET_GE2D_DMC_PIPL 234 -#define RESET_HCODEC_DMC_PIPL 235 -#define RESET_WAVE420_DMC_PIPL 236 -#define RESET_HEVCF_DMC_PIPL 237 -/* 238-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h b/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h deleted file mode 100644 index 883bfd3bcba..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-gxbb-reset.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ -#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -/* 1 */ -#define RESET_DOS_RESET 2 -#define RESET_DDR_TOP 3 -#define RESET_DCU_RESET 4 -#define RESET_VIU 5 -#define RESET_AIU 6 -#define RESET_VID_PLL_DIV 7 -/* 8 */ -#define RESET_PMUX 9 -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_AFIFO2 12 -#define RESET_VCBUS 13 -/* 14 */ -/* 15 */ -#define RESET_GIC 16 -#define RESET_CAPB3_DECODE 17 -#define RESET_NAND_CAPB3 18 -#define RESET_HDMITX_CAPB3 19 -#define RESET_MALI_CAPB3 20 -#define RESET_DOS_CAPB3 21 -#define RESET_SYS_CPU_CAPB3 22 -#define RESET_CBUS_CAPB3 23 -#define RESET_AHB_CNTL 24 -#define RESET_AHB_DATA 25 -#define RESET_VCBUS_CLK81 26 -#define RESET_MMC 27 -#define RESET_MIPI_0 28 -#define RESET_MIPI_1 29 -#define RESET_MIPI_2 30 -#define RESET_MIPI_3 31 -/* RESET1 */ -#define RESET_CPPM 32 -#define RESET_DEMUX 33 -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_AO_RESET 36 -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -/* 39 */ -#define RESET_PARSER 40 -#define RESET_BLKMV 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_SD_EMMC_A 44 -#define RESET_SD_EMMC_B 45 -#define RESET_SD_EMMC_C 46 -#define RESET_ROM_BOOT 47 -#define RESET_SYS_CPU_0 48 -#define RESET_SYS_CPU_1 49 -#define RESET_SYS_CPU_2 50 -#define RESET_SYS_CPU_3 51 -#define RESET_SYS_CPU_CORE_0 52 -#define RESET_SYS_CPU_CORE_1 53 -#define RESET_SYS_CPU_CORE_2 54 -#define RESET_SYS_CPU_CORE_3 55 -#define RESET_SYS_PLL_DIV 56 -#define RESET_SYS_CPU_AXI 57 -#define RESET_SYS_CPU_L2 58 -#define RESET_SYS_CPU_P 59 -#define RESET_SYS_CPU_MBIST 60 -#define RESET_ACODEC 61 -/* 62 */ -/* 63 */ -/* RESET2 */ -#define RESET_VD_RMEM 64 -#define RESET_AUDIN 65 -#define RESET_HDMI_TX 66 -/* 67 */ -/* 68 */ -/* 69 */ -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_PARSER_CTL 73 -#define RESET_PARSER_TOP 74 -/* 75 */ -/* 76 */ -#define RESET_AO_CPU_RESET 77 -#define RESET_MALI 78 -#define RESET_HDMI_SYSTEM_RESET 79 -/* 80-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -#define RESET_SYS_CPU 97 -#define RESET_EFUSE 98 -#define RESET_SYS_CPU_BVCI 99 -#define RESET_AIFIFO 100 -#define RESET_TVFE 101 -#define RESET_AHB_BRIDGE_CNTL 102 -/* 103 */ -#define RESET_AUDIO_DAC 104 -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_RESET_0 109 -#define RESET_DEMUX_RESET_1 110 -#define RESET_DEMUX_RESET_2 111 -/* 112-127 */ -/* RESET4 */ -/* 128 */ -/* 129 */ -/* 130 */ -/* 131 */ -#define RESET_DVIN_RESET 132 -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -/* 136 */ -#define RESET_VDAC 137 -#define RESET_RTC 138 -/* 139 */ -#define RESET_VDI6 140 -#define RESET_VENCL 141 -#define RESET_I2C_MASTER_2 142 -#define RESET_I2C_MASTER_1 143 -/* 144-159 */ -/* RESET5 */ -/* 160-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_SPICC 193 -#define RESET_PERIPHS_SMART_CARD 194 -#define RESET_PERIPHS_SAR_ADC 195 -#define RESET_PERIPHS_I2C_MASTER_0 196 -#define RESET_SANA 197 -/* 198 */ -#define RESET_PERIPHS_STREAM_INTERFACE 199 -#define RESET_PERIPHS_SDIO 200 -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1_2 202 -#define RESET_PERIPHS_ASYNC_0 203 -#define RESET_PERIPHS_ASYNC_1 204 -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_SDHC 206 -#define RESET_UART_SLIP 207 -/* 208-223 */ -/* RESET7 */ -#define RESET_USB_DDR_0 224 -#define RESET_USB_DDR_1 225 -#define RESET_USB_DDR_2 226 -#define RESET_USB_DDR_3 227 -/* 228 */ -#define RESET_DEVICE_MMC_ARB 229 -/* 230 */ -#define RESET_VID_LOCK 231 -#define RESET_A9_DMC_PIPEL 232 -/* 233-255 */ - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson-s4-reset.h b/include/dt-bindings/reset/amlogic,meson-s4-reset.h deleted file mode 100644 index eab428eb8ad..00000000000 --- a/include/dt-bindings/reset/amlogic,meson-s4-reset.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2021 Amlogic, Inc. All rights reserved. - * Author: Zelong Dong <zelong.dong@amlogic.com> - * - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON_S4_RESET_H - -/* RESET0 */ -#define RESET_USB_DDR0 0 -#define RESET_USB_DDR1 1 -#define RESET_USB_DDR2 2 -#define RESET_USB_DDR3 3 -#define RESET_USBCTRL 4 -/* 5-7 */ -#define RESET_USBPHY20 8 -#define RESET_USBPHY21 9 -/* 10-15 */ -#define RESET_HDMITX_APB 16 -#define RESET_BRG_VCBUS_DEC 17 -#define RESET_VCBUS 18 -#define RESET_VID_PLL_DIV 19 -#define RESET_VDI6 20 -#define RESET_GE2D 21 -#define RESET_HDMITXPHY 22 -#define RESET_VID_LOCK 23 -#define RESET_VENCL 24 -#define RESET_VDAC 25 -#define RESET_VENCP 26 -#define RESET_VENCI 27 -#define RESET_RDMA 28 -#define RESET_HDMI_TX 29 -#define RESET_VIU 30 -#define RESET_VENC 31 - -/* RESET1 */ -#define RESET_AUDIO 32 -#define RESET_MALI_APB 33 -#define RESET_MALI 34 -#define RESET_DDR_APB 35 -#define RESET_DDR 36 -#define RESET_DOS_APB 37 -#define RESET_DOS 38 -/* 39-47 */ -#define RESET_ETH 48 -/* 49-51 */ -#define RESET_DEMOD 52 -/* 53-63 */ - -/* RESET2 */ -#define RESET_ABUS_ARB 64 -#define RESET_IR_CTRL 65 -#define RESET_TEMPSENSOR_DDR 66 -#define RESET_TEMPSENSOR_PLL 67 -/* 68-71 */ -#define RESET_SMART_CARD 72 -#define RESET_SPICC0 73 -/* 74 */ -#define RESET_RSA 75 -/* 76-79 */ -#define RESET_MSR_CLK 80 -#define RESET_SPIFC 81 -#define RESET_SARADC 82 -/* 83-87 */ -#define RESET_ACODEC 88 -#define RESET_CEC 89 -#define RESET_AFIFO 90 -#define RESET_WATCHDOG 91 -/* 92-95 */ - -/* RESET3 */ -/* 96-127 */ - -/* RESET4 */ -/* 128-131 */ -#define RESET_PWM_AB 132 -#define RESET_PWM_CD 133 -#define RESET_PWM_EF 134 -#define RESET_PWM_GH 135 -#define RESET_PWM_IJ 136 -/* 137 */ -#define RESET_UART_A 138 -#define RESET_UART_B 139 -#define RESET_UART_C 140 -#define RESET_UART_D 141 -#define RESET_UART_E 142 -/* 143 */ -#define RESET_I2C_S_A 144 -#define RESET_I2C_M_A 145 -#define RESET_I2C_M_B 146 -#define RESET_I2C_M_C 147 -#define RESET_I2C_M_D 148 -#define RESET_I2C_M_E 149 -/* 150-151 */ -#define RESET_SD_EMMC_A 152 -#define RESET_SD_EMMC_B 153 -#define RESET_NAND_EMMC 154 -/* 155-159 */ - -/* RESET5 */ -#define RESET_BRG_VDEC_PIPL0 160 -#define RESET_BRG_HEVCF_PIPL0 161 -/* 162 */ -#define RESET_BRG_HCODEC_PIPL0 163 -#define RESET_BRG_GE2D_PIPL0 164 -#define RESET_BRG_VPU_PIPL0 165 -#define RESET_BRG_CPU_PIPL0 166 -#define RESET_BRG_MALI_PIPL0 167 -/* 168 */ -#define RESET_BRG_MALI_PIPL1 169 -/* 170-171 */ -#define RESET_BRG_HEVCF_PIPL1 172 -#define RESET_BRG_HEVCB_PIPL1 173 -/* 174-183 */ -#define RESET_RAMA 184 -/* 185-186 */ -#define RESET_BRG_NIC_VAPB 187 -#define RESET_BRG_NIC_DSU 188 -#define RESET_BRG_NIC_SYSCLK 189 -#define RESET_BRG_NIC_MAIN 190 -#define RESET_BRG_NIC_ALL 191 - -#endif diff --git a/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h deleted file mode 100644 index 1f1b56e5734..00000000000 --- a/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>. - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H - -#define CLKC_RESET_L2_CACHE_SOFT_RESET 0 -#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1 -#define CLKC_RESET_SCU_SOFT_RESET 2 -#define CLKC_RESET_CPU0_SOFT_RESET 3 -#define CLKC_RESET_CPU1_SOFT_RESET 4 -#define CLKC_RESET_CPU2_SOFT_RESET 5 -#define CLKC_RESET_CPU3_SOFT_RESET 6 -#define CLKC_RESET_A5_GLOBAL_RESET 7 -#define CLKC_RESET_A5_AXI_SOFT_RESET 8 -#define CLKC_RESET_A5_ABP_SOFT_RESET 9 -#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10 -#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11 -#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12 -#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13 -#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14 -#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15 - -#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */ diff --git a/include/dt-bindings/reset/amlogic,meson8b-reset.h b/include/dt-bindings/reset/amlogic,meson8b-reset.h deleted file mode 100644 index fbc524a900d..00000000000 --- a/include/dt-bindings/reset/amlogic,meson8b-reset.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ -#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H -#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H - -/* RESET0 */ -#define RESET_HIU 0 -#define RESET_VLD 1 -#define RESET_IQIDCT 2 -#define RESET_MC 3 -/* 8 */ -#define RESET_VIU 5 -#define RESET_AIU 6 -#define RESET_MCPU 7 -#define RESET_CCPU 8 -#define RESET_PMUX 9 -#define RESET_VENC 10 -#define RESET_ASSIST 11 -#define RESET_AFIFO2 12 -#define RESET_MDEC 13 -#define RESET_VLD_PART 14 -#define RESET_VIFIFO 15 -/* 16-31 */ -/* RESET1 */ -/* 32 */ -#define RESET_DEMUX 33 -#define RESET_USB_OTG 34 -#define RESET_DDR 35 -#define RESET_VDAC_1 36 -#define RESET_BT656 37 -#define RESET_AHB_SRAM 38 -#define RESET_AHB_BRIDGE 39 -#define RESET_PARSER 40 -#define RESET_BLKMV 41 -#define RESET_ISA 42 -#define RESET_ETHERNET 43 -#define RESET_ABUF 44 -#define RESET_AHB_DATA 45 -#define RESET_AHB_CNTL 46 -#define RESET_ROM_BOOT 47 -/* 48-63 */ -/* RESET2 */ -#define RESET_VD_RMEM 64 -#define RESET_AUDIN 65 -#define RESET_DBLK 66 -#define RESET_PIC_DC 67 -#define RESET_PSC 68 -#define RESET_NAND 69 -#define RESET_GE2D 70 -#define RESET_PARSER_REG 71 -#define RESET_PARSER_FETCH 72 -#define RESET_PARSER_CTL 73 -#define RESET_PARSER_TOP 74 -#define RESET_HDMI_APB 75 -#define RESET_AUDIO_APB 76 -#define RESET_MEDIA_CPU 77 -#define RESET_MALI 78 -#define RESET_HDMI_SYSTEM_RESET 79 -/* 80-95 */ -/* RESET3 */ -#define RESET_RING_OSCILLATOR 96 -#define RESET_SYS_CPU_0 97 -#define RESET_EFUSE 98 -#define RESET_SYS_CPU_BVCI 99 -#define RESET_AIFIFO 100 -#define RESET_AUDIO_PLL_MODULATOR 101 -#define RESET_AHB_BRIDGE_CNTL 102 -#define RESET_SYS_CPU_1 103 -#define RESET_AUDIO_DAC 104 -#define RESET_DEMUX_TOP 105 -#define RESET_DEMUX_DES 106 -#define RESET_DEMUX_S2P_0 107 -#define RESET_DEMUX_S2P_1 108 -#define RESET_DEMUX_RESET_0 109 -#define RESET_DEMUX_RESET_1 110 -#define RESET_DEMUX_RESET_2 111 -/* 112-127 */ -/* RESET4 */ -#define RESET_PL310 128 -#define RESET_A5_APB 129 -#define RESET_A5_AXI 130 -#define RESET_A5 131 -#define RESET_DVIN 132 -#define RESET_RDMA 133 -#define RESET_VENCI 134 -#define RESET_VENCP 135 -#define RESET_VENCT 136 -#define RESET_VDAC_4 137 -#define RESET_RTC 138 -#define RESET_A5_DEBUG 139 -#define RESET_VDI6 140 -#define RESET_VENCL 141 -/* 142-159 */ -/* RESET5 */ -#define RESET_DDR_PLL 160 -#define RESET_MISC_PLL 161 -#define RESET_SYS_PLL 162 -#define RESET_HPLL_PLL 163 -#define RESET_AUDIO_PLL 164 -#define RESET_VID2_PLL 165 -/* 166-191 */ -/* RESET6 */ -#define RESET_PERIPHS_GENERAL 192 -#define RESET_PERIPHS_IR_REMOTE 193 -#define RESET_PERIPHS_SMART_CARD 194 -#define RESET_PERIPHS_SAR_ADC 195 -#define RESET_PERIPHS_I2C_MASTER_0 196 -#define RESET_PERIPHS_I2C_MASTER_1 197 -#define RESET_PERIPHS_I2C_SLAVE 198 -#define RESET_PERIPHS_STREAM_INTERFACE 199 -#define RESET_PERIPHS_SDIO 200 -#define RESET_PERIPHS_UART_0 201 -#define RESET_PERIPHS_UART_1 202 -#define RESET_PERIPHS_ASYNC_0 203 -#define RESET_PERIPHS_ASYNC_1 204 -#define RESET_PERIPHS_SPI_0 205 -#define RESET_PERIPHS_SPI_1 206 -#define RESET_PERIPHS_LED_PWM 207 -/* 208-223 */ -/* RESET7 */ -/* 224-255 */ - -#endif diff --git a/include/dt-bindings/reset/aspeed,ast2700-scu.h b/include/dt-bindings/reset/aspeed,ast2700-scu.h deleted file mode 100644 index d53c719b7a6..00000000000 --- a/include/dt-bindings/reset/aspeed,ast2700-scu.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Device Tree binding constants for AST2700 reset controller. - * - * Copyright (c) 2024 Aspeed Technology Inc. - */ - -#ifndef _MACH_ASPEED_AST2700_RESET_H_ -#define _MACH_ASPEED_AST2700_RESET_H_ - -/* SOC0 */ -#define SCU0_RESET_SDRAM 0 -#define SCU0_RESET_DDRPHY 1 -#define SCU0_RESET_RSA 2 -#define SCU0_RESET_SHA3 3 -#define SCU0_RESET_HACE 4 -#define SCU0_RESET_SOC 5 -#define SCU0_RESET_VIDEO 6 -#define SCU0_RESET_2D 7 -#define SCU0_RESET_PCIS 8 -#define SCU0_RESET_RVAS0 9 -#define SCU0_RESET_RVAS1 10 -#define SCU0_RESET_SM3 11 -#define SCU0_RESET_SM4 12 -#define SCU0_RESET_CRT0 13 -#define SCU0_RESET_ECC 14 -#define SCU0_RESET_DP_PCI 15 -#define SCU0_RESET_UFS 16 -#define SCU0_RESET_EMMC 17 -#define SCU0_RESET_PCIE1RST 18 -#define SCU0_RESET_PCIE1RSTOE 19 -#define SCU0_RESET_PCIE0RST 20 -#define SCU0_RESET_PCIE0RSTOE 21 -#define SCU0_RESET_JTAG 22 -#define SCU0_RESET_MCTP0 23 -#define SCU0_RESET_MCTP1 24 -#define SCU0_RESET_XDMA0 25 -#define SCU0_RESET_XDMA1 26 -#define SCU0_RESET_H2X1 27 -#define SCU0_RESET_DP 28 -#define SCU0_RESET_DP_MCU 29 -#define SCU0_RESET_SSP 30 -#define SCU0_RESET_H2X0 31 -#define SCU0_RESET_PORTA_VHUB 32 -#define SCU0_RESET_PORTA_PHY3 33 -#define SCU0_RESET_PORTA_XHCI 34 -#define SCU0_RESET_PORTB_VHUB 35 -#define SCU0_RESET_PORTB_PHY3 36 -#define SCU0_RESET_PORTB_XHCI 37 -#define SCU0_RESET_PORTA_VHUB_EHCI 38 -#define SCU0_RESET_PORTB_VHUB_EHCI 39 -#define SCU0_RESET_UHCI 40 -#define SCU0_RESET_TSP 41 -#define SCU0_RESET_E2M0 42 -#define SCU0_RESET_E2M1 43 -#define SCU0_RESET_VLINK 44 - -/* SOC1 */ -#define SCU1_RESET_LPC0 0 -#define SCU1_RESET_LPC1 1 -#define SCU1_RESET_MII 2 -#define SCU1_RESET_PECI 3 -#define SCU1_RESET_PWM 4 -#define SCU1_RESET_MAC0 5 -#define SCU1_RESET_MAC1 6 -#define SCU1_RESET_MAC2 7 -#define SCU1_RESET_ADC 8 -#define SCU1_RESET_SD 9 -#define SCU1_RESET_ESPI0 10 -#define SCU1_RESET_ESPI1 11 -#define SCU1_RESET_JTAG1 12 -#define SCU1_RESET_SPI0 13 -#define SCU1_RESET_SPI1 14 -#define SCU1_RESET_SPI2 15 -#define SCU1_RESET_I3C0 16 -#define SCU1_RESET_I3C1 17 -#define SCU1_RESET_I3C2 18 -#define SCU1_RESET_I3C3 19 -#define SCU1_RESET_I3C4 20 -#define SCU1_RESET_I3C5 21 -#define SCU1_RESET_I3C6 22 -#define SCU1_RESET_I3C7 23 -#define SCU1_RESET_I3C8 24 -#define SCU1_RESET_I3C9 25 -#define SCU1_RESET_I3C10 26 -#define SCU1_RESET_I3C11 27 -#define SCU1_RESET_I3C12 28 -#define SCU1_RESET_I3C13 29 -#define SCU1_RESET_I3C14 30 -#define SCU1_RESET_I3C15 31 -#define SCU1_RESET_MCU0 32 -#define SCU1_RESET_MCU1 33 -#define SCU1_RESET_H2A_SPI1 34 -#define SCU1_RESET_H2A_SPI2 35 -#define SCU1_RESET_UART0 36 -#define SCU1_RESET_UART1 37 -#define SCU1_RESET_UART2 38 -#define SCU1_RESET_UART3 39 -#define SCU1_RESET_I2C_FILTER 40 -#define SCU1_RESET_CALIPTRA 41 -#define SCU1_RESET_XDMA 42 -#define SCU1_RESET_FSI 43 -#define SCU1_RESET_CAN 44 -#define SCU1_RESET_MCTP 45 -#define SCU1_RESET_I2C 46 -#define SCU1_RESET_UART6 47 -#define SCU1_RESET_UART7 48 -#define SCU1_RESET_UART8 49 -#define SCU1_RESET_UART9 50 -#define SCU1_RESET_LTPI0 51 -#define SCU1_RESET_VGAL 52 -#define SCU1_RESET_LTPI1 53 -#define SCU1_RESET_ACE 54 -#define SCU1_RESET_E2M 55 -#define SCU1_RESET_UHCI 56 -#define SCU1_RESET_PORTC_USB2UART 57 -#define SCU1_RESET_PORTC_VHUB_EHCI 58 -#define SCU1_RESET_PORTD_USB2UART 59 -#define SCU1_RESET_PORTD_VHUB_EHCI 60 -#define SCU1_RESET_H2X 61 -#define SCU1_RESET_I3CDMA 62 -#define SCU1_RESET_PCIE2RST 63 - -#endif /* _MACH_ASPEED_AST2700_RESET_H_ */ diff --git a/include/dt-bindings/reset/ast2500-reset.h b/include/dt-bindings/reset/ast2500-reset.h new file mode 100644 index 00000000000..cc85a31edf9 --- /dev/null +++ b/include/dt-bindings/reset/ast2500-reset.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017 Google, Inc + * Copyright 2020 ASPEED Technology Inc. + */ + +#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_ +#define _ABI_MACH_ASPEED_AST2500_RESET_H_ + +#define ASPEED_RESET_CRT1 (37) +#define ASPEED_RESET_RESERVED36 (36) +#define ASPEED_RESET_RESERVED35 (35) +#define ASPEED_RESET_RESERVED34 (34) +#define ASPEED_RESET_RESERVED33 (33) +#define ASPEED_RESET_RESERVED32 (32) +#define ASPEED_RESET_RESERVED31 (31) +#define ASPEED_RESET_RESERVED30 (30) +#define ASPEED_RESET_RESERVED29 (29) +#define ASPEED_RESET_RESERVED28 (28) +#define ASPEED_RESET_RESERVED27 (27) +#define ASPEED_RESET_RESERVED26 (26) +#define ASPEED_RESET_XDMA (25) +#define ASPEED_RESET_MCTP (24) +#define ASPEED_RESET_ADC (23) +#define ASPEED_RESET_JTAG_MASTER (22) +#define ASPEED_RESET_RESERVED21 (21) +#define ASPEED_RESET_RESERVED20 (20) +#define ASPEED_RESET_RESERVED19 (19) +#define ASPEED_RESET_MIC (18) +#define ASPEED_RESET_RESERVED17 (17) +#define ASPEED_RESET_SDIO (16) +#define ASPEED_RESET_UHCI (15) +#define ASPEED_RESET_EHCI_P1 (14) +#define ASPEED_RESET_CRT (13) +#define ASPEED_RESET_MAC2 (12) +#define ASPEED_RESET_MAC1 (11) +#define ASPEED_RESET_PECI (10) +#define ASPEED_RESET_PWM (9) +#define ASPEED_RESET_PCI_VGA (8) +#define ASPEED_RESET_2D (7) +#define ASPEED_RESET_VIDEO (6) +#define ASPEED_RESET_LPC_ESPI (5) +#define ASPEED_RESET_HACE (4) +#define ASPEED_RESET_EHCI_P2 (3) +#define ASPEED_RESET_I2C (2) +#define ASPEED_RESET_AHB (1) +#define ASPEED_RESET_SDRAM (0) + +#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */ diff --git a/include/dt-bindings/reset/ast2600-reset.h b/include/dt-bindings/reset/ast2600-reset.h new file mode 100644 index 00000000000..b6d0f79917a --- /dev/null +++ b/include/dt-bindings/reset/ast2600-reset.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef _ABI_MACH_ASPEED_AST2600_RESET_H_ +#define _ABI_MACH_ASPEED_AST2600_RESET_H_ + +#define ASPEED_RESET_FSI (59) +#define ASPEED_RESET_RESERVED58 (58) +#define ASPEED_RESET_RESERVED57 (57) +#define ASPEED_RESET_SD (56) +#define ASPEED_RESET_ADC (55) +#define ASPEED_RESET_JTAG_MASTER2 (54) +#define ASPEED_RESET_MAC4 (53) +#define ASPEED_RESET_MAC3 (52) +#define ASPEED_RESET_RESERVE51 (51) +#define ASPEED_RESET_RESERVE50 (50) +#define ASPEED_RESET_RESERVE49 (49) +#define ASPEED_RESET_RESERVE48 (48) +#define ASPEED_RESET_RESERVE47 (47) +#define ASPEED_RESET_RESERVE46 (46) +#define ASPEED_RESET_I3C5 (45) +#define ASPEED_RESET_I3C4 (44) +#define ASPEED_RESET_I3C3 (43) +#define ASPEED_RESET_I3C2 (42) +#define ASPEED_RESET_I3C1 (41) +#define ASPEED_RESET_I3C0 (40) +#define ASPEED_RESET_I3C_DMA (39) +#define ASPEED_RESET_RESERVED38 (38) +#define ASPEED_RESET_PWM (37) +#define ASPEED_RESET_PECI (36) +#define ASPEED_RESET_MII (35) +#define ASPEED_RESET_I2C (34) +#define ASPEED_RESET_RESERVED33 (33) +#define ASPEED_RESET_LPC_ESPI (32) +#define ASPEED_RESET_H2X (31) +#define ASPEED_RESET_GP_MCU (30) +#define ASPEED_RESET_DP_MCU (29) +#define ASPEED_RESET_DP (28) +#define ASPEED_RESET_RC_XDMA (27) +#define ASPEED_RESET_GRAPHICS (26) +#define ASPEED_RESET_DEV_XDMA (25) +#define ASPEED_RESET_DEV_MCTP (24) +#define ASPEED_RESET_RC_MCTP (23) +#define ASPEED_RESET_JTAG_MASTER (22) +#define ASPEED_RESET_PCIE_DEV_OE (21) +#define ASPEED_RESET_PCIE_DEV_O (20) +#define ASPEED_RESET_PCIE_RC_OE (19) +#define ASPEED_RESET_PCIE_RC_O (18) +#define ASPEED_RESET_RESERVED17 (17) +#define ASPEED_RESET_EMMC (16) +#define ASPEED_RESET_UHCI (15) +#define ASPEED_RESET_EHCI_P1 (14) +#define ASPEED_RESET_CRT (13) +#define ASPEED_RESET_MAC2 (12) +#define ASPEED_RESET_MAC1 (11) +#define ASPEED_RESET_RESERVED10 (10) +#define ASPEED_RESET_RVAS (9) +#define ASPEED_RESET_PCI_VGA (8) +#define ASPEED_RESET_2D (7) +#define ASPEED_RESET_VIDEO (6) +#define ASPEED_RESET_PCI_DP (5) +#define ASPEED_RESET_HACE (4) +#define ASPEED_RESET_EHCI_P2 (3) +#define ASPEED_RESET_RESERVED2 (2) +#define ASPEED_RESET_AHB (1) +#define ASPEED_RESET_SDRAM (0) + +#endif /* _ABI_MACH_ASPEED_AST2600_RESET_H_ */ diff --git a/include/dt-bindings/reset/axg-aoclkc.h b/include/dt-bindings/reset/axg-aoclkc.h deleted file mode 100644 index d342c0b6b2a..00000000000 --- a/include/dt-bindings/reset/axg-aoclkc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - * - * Copyright (c) 2018 Amlogic, inc. - * Author: Qiufang Dai <qiufang.dai@amlogic.com> - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_AXG_AOCLK - -#define RESET_AO_REMOTE 0 -#define RESET_AO_I2C_MASTER 1 -#define RESET_AO_I2C_SLAVE 2 -#define RESET_AO_UART1 3 -#define RESET_AO_UART2 4 -#define RESET_AO_IR_BLASTER 5 - -#endif diff --git a/include/dt-bindings/reset/bcm3380-reset.h b/include/dt-bindings/reset/bcm3380-reset.h new file mode 100644 index 00000000000..4cbf4d289de --- /dev/null +++ b/include/dt-bindings/reset/bcm3380-reset.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from Broadcom GPL Source Code: + * Copyright (C) Broadcom Corporation + */ + +#ifndef __DT_BINDINGS_RESET_BCM3380_H +#define __DT_BINDINGS_RESET_BCM3380_H + +#define BCM3380_RST0_SPI 0 +#define BCM3380_RST0_PCM 13 + +#endif /* __DT_BINDINGS_RESET_BCM3380_H */ diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h deleted file mode 100644 index f882662505e..00000000000 --- a/include/dt-bindings/reset/bcm6318-reset.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __DT_BINDINGS_RESET_BCM6318_H -#define __DT_BINDINGS_RESET_BCM6318_H - -#define BCM6318_RST_SPI 0 -#define BCM6318_RST_EPHY 1 -#define BCM6318_RST_SAR 2 -#define BCM6318_RST_ENETSW 3 -#define BCM6318_RST_USBD 4 -#define BCM6318_RST_USBH 5 -#define BCM6318_RST_PCIE_CORE 6 -#define BCM6318_RST_PCIE 7 -#define BCM6318_RST_PCIE_EXT 8 -#define BCM6318_RST_PCIE_HARD 9 -#define BCM6318_RST_ADSL 10 -#define BCM6318_RST_PHYMIPS 11 -#define BCM6318_RST_HOSTMIPS 12 - -#endif /* __DT_BINDINGS_RESET_BCM6318_H */ diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h deleted file mode 100644 index d87a7882782..00000000000 --- a/include/dt-bindings/reset/bcm63268-reset.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __DT_BINDINGS_RESET_BCM63268_H -#define __DT_BINDINGS_RESET_BCM63268_H - -#define BCM63268_RST_SPI 0 -#define BCM63268_RST_IPSEC 1 -#define BCM63268_RST_EPHY 2 -#define BCM63268_RST_SAR 3 -#define BCM63268_RST_ENETSW 4 -#define BCM63268_RST_USBS 5 -#define BCM63268_RST_USBH 6 -#define BCM63268_RST_PCM 7 -#define BCM63268_RST_PCIE_CORE 8 -#define BCM63268_RST_PCIE 9 -#define BCM63268_RST_PCIE_EXT 10 -#define BCM63268_RST_WLAN_SHIM 11 -#define BCM63268_RST_DDR_PHY 12 -#define BCM63268_RST_FAP0 13 -#define BCM63268_RST_WLAN_UBUS 14 -#define BCM63268_RST_DECT 15 -#define BCM63268_RST_FAP1 16 -#define BCM63268_RST_PCIE_HARD 17 -#define BCM63268_RST_GPHY 18 - -#define BCM63268_TRST_SW 29 -#define BCM63268_TRST_HW 30 -#define BCM63268_TRST_POR 31 - -#endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h deleted file mode 100644 index 0f3df87d47a..00000000000 --- a/include/dt-bindings/reset/bcm6328-reset.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __DT_BINDINGS_RESET_BCM6328_H -#define __DT_BINDINGS_RESET_BCM6328_H - -#define BCM6328_RST_SPI 0 -#define BCM6328_RST_EPHY 1 -#define BCM6328_RST_SAR 2 -#define BCM6328_RST_ENETSW 3 -#define BCM6328_RST_USBS 4 -#define BCM6328_RST_USBH 5 -#define BCM6328_RST_PCM 6 -#define BCM6328_RST_PCIE_CORE 7 -#define BCM6328_RST_PCIE 8 -#define BCM6328_RST_PCIE_EXT 9 -#define BCM6328_RST_PCIE_HARD 10 - -#endif /* __DT_BINDINGS_RESET_BCM6328_H */ diff --git a/include/dt-bindings/reset/bcm6338-reset.h b/include/dt-bindings/reset/bcm6338-reset.h new file mode 100644 index 00000000000..4aec7a4b59a --- /dev/null +++ b/include/dt-bindings/reset/bcm6338-reset.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6338_H +#define __DT_BINDINGS_RESET_BCM6338_H + +#define BCM6338_RST_SPI 0 +#define BCM6338_RST_ENET 2 +#define BCM6338_RST_USBH 3 +#define BCM6338_RST_USBS 4 +#define BCM6338_RST_ADSL 5 +#define BCM6338_RST_DMAMEM 6 +#define BCM6338_RST_SAR 7 +#define BCM6338_RST_ACLC 8 +#define BCM6338_RST_ADSL_MIPS 10 + +#endif /* __DT_BINDINGS_RESET_BCM6338_H */ diff --git a/include/dt-bindings/reset/bcm6348-reset.h b/include/dt-bindings/reset/bcm6348-reset.h new file mode 100644 index 00000000000..b298c183160 --- /dev/null +++ b/include/dt-bindings/reset/bcm6348-reset.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + */ + +#ifndef __DT_BINDINGS_RESET_BCM6348_H +#define __DT_BINDINGS_RESET_BCM6348_H + +#define BCM6348_RST_SPI 0 +#define BCM6348_RST_ENET 2 +#define BCM6348_RST_USBH 3 +#define BCM6348_RST_USBS 4 +#define BCM6348_RST_ADSL 5 +#define BCM6348_RST_DMAMEM 6 +#define BCM6348_RST_SAR 7 +#define BCM6348_RST_ACLC 8 +#define BCM6348_RST_ADSL_MIPS 10 + +#endif /* __DT_BINDINGS_RESET_BCM6348_H */ diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h deleted file mode 100644 index bda62ef84f5..00000000000 --- a/include/dt-bindings/reset/bcm6358-reset.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __DT_BINDINGS_RESET_BCM6358_H -#define __DT_BINDINGS_RESET_BCM6358_H - -#define BCM6358_RST_SPI 0 -#define BCM6358_RST_ENET 2 -#define BCM6358_RST_MPI 3 -#define BCM6358_RST_EPHY 6 -#define BCM6358_RST_SAR 7 -#define BCM6358_RST_USBH 12 -#define BCM6358_RST_PCM 13 -#define BCM6358_RST_ADSL 14 - -#endif /* __DT_BINDINGS_RESET_BCM6358_H */ diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h deleted file mode 100644 index 7ebb0546e0a..00000000000 --- a/include/dt-bindings/reset/bcm6362-reset.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __DT_BINDINGS_RESET_BCM6362_H -#define __DT_BINDINGS_RESET_BCM6362_H - -#define BCM6362_RST_SPI 0 -#define BCM6362_RST_IPSEC 1 -#define BCM6362_RST_EPHY 2 -#define BCM6362_RST_SAR 3 -#define BCM6362_RST_ENETSW 4 -#define BCM6362_RST_USBD 5 -#define BCM6362_RST_USBH 6 -#define BCM6362_RST_PCM 7 -#define BCM6362_RST_PCIE_CORE 8 -#define BCM6362_RST_PCIE 9 -#define BCM6362_RST_PCIE_EXT 10 -#define BCM6362_RST_WLAN_SHIM 11 -#define BCM6362_RST_DDR_PHY 12 -#define BCM6362_RST_FAP 13 -#define BCM6362_RST_WLAN_UBUS 14 - -#endif /* __DT_BINDINGS_RESET_BCM6362_H */ diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h deleted file mode 100644 index c81d8eb6d17..00000000000 --- a/include/dt-bindings/reset/bcm6368-reset.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef __DT_BINDINGS_RESET_BCM6368_H -#define __DT_BINDINGS_RESET_BCM6368_H - -#define BCM6368_RST_SPI 0 -#define BCM6368_RST_MPI 3 -#define BCM6368_RST_IPSEC 4 -#define BCM6368_RST_EPHY 6 -#define BCM6368_RST_SAR 7 -#define BCM6368_RST_SWITCH 10 -#define BCM6368_RST_USBD 11 -#define BCM6368_RST_USBH 12 -#define BCM6368_RST_PCM 13 - -#endif /* __DT_BINDINGS_RESET_BCM6368_H */ diff --git a/include/dt-bindings/reset/bitmain,bm1880-reset.h b/include/dt-bindings/reset/bitmain,bm1880-reset.h deleted file mode 100644 index 4c0de522377..00000000000 --- a/include/dt-bindings/reset/bitmain,bm1880-reset.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2018 Bitmain Ltd. - * Copyright (c) 2019 Linaro Ltd. - */ - -#ifndef _DT_BINDINGS_BM1880_RESET_H -#define _DT_BINDINGS_BM1880_RESET_H - -#define BM1880_RST_MAIN_AP 0 -#define BM1880_RST_SECOND_AP 1 -#define BM1880_RST_DDR 2 -#define BM1880_RST_VIDEO 3 -#define BM1880_RST_JPEG 4 -#define BM1880_RST_VPP 5 -#define BM1880_RST_GDMA 6 -#define BM1880_RST_AXI_SRAM 7 -#define BM1880_RST_TPU 8 -#define BM1880_RST_USB 9 -#define BM1880_RST_ETH0 10 -#define BM1880_RST_ETH1 11 -#define BM1880_RST_NAND 12 -#define BM1880_RST_EMMC 13 -#define BM1880_RST_SD 14 -#define BM1880_RST_SDMA 15 -#define BM1880_RST_I2S0 16 -#define BM1880_RST_I2S1 17 -#define BM1880_RST_UART0_1_CLK 18 -#define BM1880_RST_UART0_1_ACLK 19 -#define BM1880_RST_UART2_3_CLK 20 -#define BM1880_RST_UART2_3_ACLK 21 -#define BM1880_RST_MINER 22 -#define BM1880_RST_I2C0 23 -#define BM1880_RST_I2C1 24 -#define BM1880_RST_I2C2 25 -#define BM1880_RST_I2C3 26 -#define BM1880_RST_I2C4 27 -#define BM1880_RST_PWM0 28 -#define BM1880_RST_PWM1 29 -#define BM1880_RST_PWM2 30 -#define BM1880_RST_PWM3 31 -#define BM1880_RST_SPI 32 -#define BM1880_RST_GPIO0 33 -#define BM1880_RST_GPIO1 34 -#define BM1880_RST_GPIO2 35 -#define BM1880_RST_EFUSE 36 -#define BM1880_RST_WDT 37 -#define BM1880_RST_AHB_ROM 38 -#define BM1880_RST_SPIC 39 - -#endif /* _DT_BINDINGS_BM1880_RESET_H */ diff --git a/include/dt-bindings/reset/bt1-ccu.h b/include/dt-bindings/reset/bt1-ccu.h deleted file mode 100644 index c691efaa678..00000000000 --- a/include/dt-bindings/reset/bt1-ccu.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC - * - * Baikal-T1 CCU reset indices - */ -#ifndef __DT_BINDINGS_RESET_BT1_CCU_H -#define __DT_BINDINGS_RESET_BT1_CCU_H - -#define CCU_AXI_MAIN_RST 0 -#define CCU_AXI_DDR_RST 1 -#define CCU_AXI_SATA_RST 2 -#define CCU_AXI_GMAC0_RST 3 -#define CCU_AXI_GMAC1_RST 4 -#define CCU_AXI_XGMAC_RST 5 -#define CCU_AXI_PCIE_M_RST 6 -#define CCU_AXI_PCIE_S_RST 7 -#define CCU_AXI_USB_RST 8 -#define CCU_AXI_HWA_RST 9 -#define CCU_AXI_SRAM_RST 10 - -#define CCU_SYS_SATA_REF_RST 0 -#define CCU_SYS_APB_RST 1 -#define CCU_SYS_DDR_FULL_RST 2 -#define CCU_SYS_DDR_INIT_RST 3 -#define CCU_SYS_PCIE_PCS_PHY_RST 4 -#define CCU_SYS_PCIE_PIPE0_RST 5 -#define CCU_SYS_PCIE_CORE_RST 6 -#define CCU_SYS_PCIE_PWR_RST 7 -#define CCU_SYS_PCIE_STICKY_RST 8 -#define CCU_SYS_PCIE_NSTICKY_RST 9 -#define CCU_SYS_PCIE_HOT_RST 10 - -#endif /* __DT_BINDINGS_RESET_BT1_CCU_H */ diff --git a/include/dt-bindings/reset/cortina,gemini-reset.h b/include/dt-bindings/reset/cortina,gemini-reset.h deleted file mode 100644 index f48aff23847..00000000000 --- a/include/dt-bindings/reset/cortina,gemini-reset.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_RESET_CORTINA_GEMINI_H -#define _DT_BINDINGS_RESET_CORTINA_GEMINI_H - -#define GEMINI_RESET_DRAM 0 -#define GEMINI_RESET_FLASH 1 -#define GEMINI_RESET_IDE 2 -#define GEMINI_RESET_RAID 3 -#define GEMINI_RESET_SECURITY 4 -#define GEMINI_RESET_GMAC0 5 -#define GEMINI_RESET_GMAC1 6 -#define GEMINI_RESET_PCI 7 -#define GEMINI_RESET_USB0 8 -#define GEMINI_RESET_USB1 9 -#define GEMINI_RESET_DMAC 10 -#define GEMINI_RESET_APB 11 -#define GEMINI_RESET_LPC 12 -#define GEMINI_RESET_LCD 13 -#define GEMINI_RESET_INTCON0 14 -#define GEMINI_RESET_INTCON1 15 -#define GEMINI_RESET_RTC 16 -#define GEMINI_RESET_TIMER 17 -#define GEMINI_RESET_UART 18 -#define GEMINI_RESET_SSP 19 -#define GEMINI_RESET_GPIO0 20 -#define GEMINI_RESET_GPIO1 21 -#define GEMINI_RESET_GPIO2 22 -#define GEMINI_RESET_WDOG 23 -#define GEMINI_RESET_EXTERN 24 -#define GEMINI_RESET_CIR 25 -#define GEMINI_RESET_SATA0 26 -#define GEMINI_RESET_SATA1 27 -#define GEMINI_RESET_TVC 28 -#define GEMINI_RESET_CPU1 30 -#define GEMINI_RESET_GLOBAL 31 - -#endif diff --git a/include/dt-bindings/reset/delta,tn48m-reset.h b/include/dt-bindings/reset/delta,tn48m-reset.h deleted file mode 100644 index d4e9ed12de3..00000000000 --- a/include/dt-bindings/reset/delta,tn48m-reset.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Delta TN48M CPLD GPIO driver - * - * Copyright (C) 2021 Sartura Ltd. - * - * Author: Robert Marko <robert.marko@sartura.hr> - */ - -#ifndef _DT_BINDINGS_RESET_TN48M_H -#define _DT_BINDINGS_RESET_TN48M_H - -#define CPU_88F7040_RESET 0 -#define CPU_88F6820_RESET 1 -#define MAC_98DX3265_RESET 2 -#define PHY_88E1680_RESET 3 -#define PHY_88E1512_RESET 4 -#define POE_RESET 5 - -#endif /* _DT_BINDINGS_RESET_TN48M_H */ diff --git a/include/dt-bindings/reset/g12a-aoclkc.h b/include/dt-bindings/reset/g12a-aoclkc.h deleted file mode 100644 index bd2e2337135..00000000000 --- a/include/dt-bindings/reset/g12a-aoclkc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2016 BayLibre, SAS - * Author: Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_G12A_AOCLK - -#define RESET_AO_IR_IN 0 -#define RESET_AO_UART 1 -#define RESET_AO_I2C_M 2 -#define RESET_AO_I2C_S 3 -#define RESET_AO_SAR_ADC 4 -#define RESET_AO_UART2 5 -#define RESET_AO_IR_OUT 6 - -#endif diff --git a/include/dt-bindings/reset/gxbb-aoclkc.h b/include/dt-bindings/reset/gxbb-aoclkc.h deleted file mode 100644 index 9e3fd60c309..00000000000 --- a/include/dt-bindings/reset/gxbb-aoclkc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is provided under a dual BSD/GPLv2 license. When using or - * redistributing this file, you may do so under either license. - * - * GPL LICENSE SUMMARY - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - * The full GNU General Public License is included in this distribution - * in the file called COPYING. - * - * BSD LICENSE - * - * Copyright (c) 2016 BayLibre, SAS. - * Author: Neil Armstrong <narmstrong@baylibre.com> - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK -#define DT_BINDINGS_RESET_AMLOGIC_MESON_GXBB_AOCLK - -#define RESET_AO_REMOTE 0 -#define RESET_AO_I2C_MASTER 1 -#define RESET_AO_I2C_SLAVE 2 -#define RESET_AO_UART1 3 -#define RESET_AO_UART2 4 -#define RESET_AO_IR_BLASTER 5 - -#endif diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h b/include/dt-bindings/reset/hisi,hi6220-resets.h deleted file mode 100644 index 63aff7d8aa4..00000000000 --- a/include/dt-bindings/reset/hisi,hi6220-resets.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/** - * This header provides index for the reset controller - * based on hi6220 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220 -#define _DT_BINDINGS_RESET_CONTROLLER_HI6220 - -#define PERIPH_RSTDIS0_MMC0 0x000 -#define PERIPH_RSTDIS0_MMC1 0x001 -#define PERIPH_RSTDIS0_MMC2 0x002 -#define PERIPH_RSTDIS0_NANDC 0x003 -#define PERIPH_RSTDIS0_USBOTG_BUS 0x004 -#define PERIPH_RSTDIS0_POR_PICOPHY 0x005 -#define PERIPH_RSTDIS0_USBOTG 0x006 -#define PERIPH_RSTDIS0_USBOTG_32K 0x007 -#define PERIPH_RSTDIS1_HIFI 0x100 -#define PERIPH_RSTDIS1_DIGACODEC 0x105 -#define PERIPH_RSTEN2_IPF 0x200 -#define PERIPH_RSTEN2_SOCP 0x201 -#define PERIPH_RSTEN2_DMAC 0x202 -#define PERIPH_RSTEN2_SECENG 0x203 -#define PERIPH_RSTEN2_ABB 0x204 -#define PERIPH_RSTEN2_HPM0 0x205 -#define PERIPH_RSTEN2_HPM1 0x206 -#define PERIPH_RSTEN2_HPM2 0x207 -#define PERIPH_RSTEN2_HPM3 0x208 -#define PERIPH_RSTEN3_CSSYS 0x300 -#define PERIPH_RSTEN3_I2C0 0x301 -#define PERIPH_RSTEN3_I2C1 0x302 -#define PERIPH_RSTEN3_I2C2 0x303 -#define PERIPH_RSTEN3_I2C3 0x304 -#define PERIPH_RSTEN3_UART1 0x305 -#define PERIPH_RSTEN3_UART2 0x306 -#define PERIPH_RSTEN3_UART3 0x307 -#define PERIPH_RSTEN3_UART4 0x308 -#define PERIPH_RSTEN3_SSP 0x309 -#define PERIPH_RSTEN3_PWM 0x30a -#define PERIPH_RSTEN3_BLPWM 0x30b -#define PERIPH_RSTEN3_TSENSOR 0x30c -#define PERIPH_RSTEN3_DAPB 0x312 -#define PERIPH_RSTEN3_HKADC 0x313 -#define PERIPH_RSTEN3_CODEC_SSI 0x314 -#define PERIPH_RSTEN3_PMUSSI1 0x316 -#define PERIPH_RSTEN8_RS0 0x400 -#define PERIPH_RSTEN8_RS2 0x401 -#define PERIPH_RSTEN8_RS3 0x402 -#define PERIPH_RSTEN8_MS0 0x403 -#define PERIPH_RSTEN8_MS2 0x405 -#define PERIPH_RSTEN8_XG2RAM0 0x406 -#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407 -#define PERIPH_RSTEN8_SRAM 0x408 -#define PERIPH_RSTEN8_HARQ 0x40a -#define PERIPH_RSTEN8_DDRC 0x40c -#define PERIPH_RSTEN8_DDRC_APB 0x40d -#define PERIPH_RSTEN8_DDRPACK_APB 0x40e -#define PERIPH_RSTEN8_DDRT 0x411 -#define PERIPH_RSDIST9_CARM_DAP 0x500 -#define PERIPH_RSDIST9_CARM_ATB 0x501 -#define PERIPH_RSDIST9_CARM_LBUS 0x502 -#define PERIPH_RSDIST9_CARM_POR 0x503 -#define PERIPH_RSDIST9_CARM_CORE 0x504 -#define PERIPH_RSDIST9_CARM_DBG 0x505 -#define PERIPH_RSDIST9_CARM_L2 0x506 -#define PERIPH_RSDIST9_CARM_SOCDBG 0x507 -#define PERIPH_RSDIST9_CARM_ETM 0x508 - -#define MEDIA_G3D 0 -#define MEDIA_CODEC_VPU 2 -#define MEDIA_CODEC_JPEG 3 -#define MEDIA_ISP 4 -#define MEDIA_ADE 5 -#define MEDIA_MMU 6 -#define MEDIA_XG2RAM1 7 - -#define AO_G3D 1 -#define AO_CODECISP 2 -#define AO_MCPU 4 -#define AO_BBPHARQMEM 5 -#define AO_HIFI 8 -#define AO_ACPUSCUL2C 12 - -#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/ diff --git a/include/dt-bindings/reset/imx7-reset.h b/include/dt-bindings/reset/imx7-reset.h deleted file mode 100644 index a5b35b4754d..00000000000 --- a/include/dt-bindings/reset/imx7-reset.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2017 Impinj, Inc. - * - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - */ - -#ifndef DT_BINDING_RESET_IMX7_H -#define DT_BINDING_RESET_IMX7_H - -#define IMX7_RESET_A7_CORE_POR_RESET0 0 -#define IMX7_RESET_A7_CORE_POR_RESET1 1 -#define IMX7_RESET_A7_CORE_RESET0 2 -#define IMX7_RESET_A7_CORE_RESET1 3 -#define IMX7_RESET_A7_DBG_RESET0 4 -#define IMX7_RESET_A7_DBG_RESET1 5 -#define IMX7_RESET_A7_ETM_RESET0 6 -#define IMX7_RESET_A7_ETM_RESET1 7 -#define IMX7_RESET_A7_SOC_DBG_RESET 8 -#define IMX7_RESET_A7_L2RESET 9 -#define IMX7_RESET_SW_M4C_RST 10 -#define IMX7_RESET_SW_M4P_RST 11 -#define IMX7_RESET_EIM_RST 12 -#define IMX7_RESET_HSICPHY_PORT_RST 13 -#define IMX7_RESET_USBPHY1_POR 14 -#define IMX7_RESET_USBPHY1_PORT_RST 15 -#define IMX7_RESET_USBPHY2_POR 16 -#define IMX7_RESET_USBPHY2_PORT_RST 17 -#define IMX7_RESET_MIPI_PHY_MRST 18 -#define IMX7_RESET_MIPI_PHY_SRST 19 - -/* - * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN - * and PCIEPHY_G_RST - */ -#define IMX7_RESET_PCIEPHY 20 -#define IMX7_RESET_PCIEPHY_PERST 21 - -/* - * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it - * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht - * of as one - */ -#define IMX7_RESET_PCIE_CTRL_APPS_EN 22 -#define IMX7_RESET_DDRC_PRST 23 -#define IMX7_RESET_DDRC_CORE_RST 24 - -#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25 - -#define IMX7_RESET_NUM 26 - -#endif - diff --git a/include/dt-bindings/reset/imx8mp-reset-audiomix.h b/include/dt-bindings/reset/imx8mp-reset-audiomix.h deleted file mode 100644 index 746c1337ed9..00000000000 --- a/include/dt-bindings/reset/imx8mp-reset-audiomix.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -/* - * Copyright 2025 NXP - */ - -#ifndef DT_BINDING_RESET_IMX8MP_AUDIOMIX_H -#define DT_BINDING_RESET_IMX8MP_AUDIOMIX_H - -#define IMX8MP_AUDIOMIX_EARC_RESET 0 -#define IMX8MP_AUDIOMIX_EARC_PHY_RESET 1 -#define IMX8MP_AUDIOMIX_DSP_RUNSTALL 2 - -#endif /* DT_BINDING_RESET_IMX8MP_AUDIOMIX_H */ diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h deleted file mode 100644 index 2e8c9104b66..00000000000 --- a/include/dt-bindings/reset/imx8mp-reset.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 NXP - */ - -#ifndef DT_BINDING_RESET_IMX8MP_H -#define DT_BINDING_RESET_IMX8MP_H - -#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 -#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 -#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 -#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 -#define IMX8MP_RESET_A53_CORE_RESET0 4 -#define IMX8MP_RESET_A53_CORE_RESET1 5 -#define IMX8MP_RESET_A53_CORE_RESET2 6 -#define IMX8MP_RESET_A53_CORE_RESET3 7 -#define IMX8MP_RESET_A53_DBG_RESET0 8 -#define IMX8MP_RESET_A53_DBG_RESET1 9 -#define IMX8MP_RESET_A53_DBG_RESET2 10 -#define IMX8MP_RESET_A53_DBG_RESET3 11 -#define IMX8MP_RESET_A53_ETM_RESET0 12 -#define IMX8MP_RESET_A53_ETM_RESET1 13 -#define IMX8MP_RESET_A53_ETM_RESET2 14 -#define IMX8MP_RESET_A53_ETM_RESET3 15 -#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 -#define IMX8MP_RESET_A53_L2RESET 17 -#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 -#define IMX8MP_RESET_OTG1_PHY_RESET 19 -#define IMX8MP_RESET_OTG2_PHY_RESET 20 -#define IMX8MP_RESET_SUPERMIX_RESET 21 -#define IMX8MP_RESET_AUDIOMIX_RESET 22 -#define IMX8MP_RESET_MLMIX_RESET 23 -#define IMX8MP_RESET_PCIEPHY 24 -#define IMX8MP_RESET_PCIEPHY_PERST 25 -#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 -#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 -#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 -#define IMX8MP_RESET_MEDIA_RESET 29 -#define IMX8MP_RESET_GPU2D_RESET 30 -#define IMX8MP_RESET_GPU3D_RESET 31 -#define IMX8MP_RESET_GPU_RESET 32 -#define IMX8MP_RESET_VPU_RESET 33 -#define IMX8MP_RESET_VPU_G1_RESET 34 -#define IMX8MP_RESET_VPU_G2_RESET 35 -#define IMX8MP_RESET_VPUVC8KE_RESET 36 -#define IMX8MP_RESET_NOC_RESET 37 - -#define IMX8MP_RESET_NUM 38 - -#endif diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h deleted file mode 100644 index 705870693ec..00000000000 --- a/include/dt-bindings/reset/imx8mq-reset.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Zodiac Inflight Innovations - * - * Author: Andrey Smirnov <andrew.smirnov@gmail.com> - */ - -#ifndef DT_BINDING_RESET_IMX8MQ_H -#define DT_BINDING_RESET_IMX8MQ_H - -#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 -#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 -#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 -#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 -#define IMX8MQ_RESET_A53_CORE_RESET0 4 -#define IMX8MQ_RESET_A53_CORE_RESET1 5 -#define IMX8MQ_RESET_A53_CORE_RESET2 6 -#define IMX8MQ_RESET_A53_CORE_RESET3 7 -#define IMX8MQ_RESET_A53_DBG_RESET0 8 -#define IMX8MQ_RESET_A53_DBG_RESET1 9 -#define IMX8MQ_RESET_A53_DBG_RESET2 10 -#define IMX8MQ_RESET_A53_DBG_RESET3 11 -#define IMX8MQ_RESET_A53_ETM_RESET0 12 -#define IMX8MQ_RESET_A53_ETM_RESET1 13 -#define IMX8MQ_RESET_A53_ETM_RESET2 14 -#define IMX8MQ_RESET_A53_ETM_RESET3 15 -#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 -#define IMX8MQ_RESET_A53_L2RESET 17 -#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 -#define IMX8MQ_RESET_OTG1_PHY_RESET 19 -#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DISP_RESET 31 -#define IMX8MQ_RESET_GPU_RESET 32 -#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ -#define IMX8MQ_RESET_SW_M4C_RST 50 -#define IMX8MQ_RESET_SW_M4P_RST 51 -#define IMX8MQ_RESET_M4_ENABLE 52 - -#define IMX8MQ_RESET_NUM 53 - -#endif diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h deleted file mode 100644 index e99a4735c3c..00000000000 --- a/include/dt-bindings/reset/imx8ulp-pcc-reset.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2021 NXP - */ - -#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H -#define DT_BINDING_PCC_RESET_IMX8ULP_H - -/* PCC3 */ -#define PCC3_WDOG3_SWRST 0 -#define PCC3_WDOG4_SWRST 1 -#define PCC3_LPIT1_SWRST 2 -#define PCC3_TPM4_SWRST 3 -#define PCC3_TPM5_SWRST 4 -#define PCC3_FLEXIO1_SWRST 5 -#define PCC3_I3C2_SWRST 6 -#define PCC3_LPI2C4_SWRST 7 -#define PCC3_LPI2C5_SWRST 8 -#define PCC3_LPUART4_SWRST 9 -#define PCC3_LPUART5_SWRST 10 -#define PCC3_LPSPI4_SWRST 11 -#define PCC3_LPSPI5_SWRST 12 - -/* PCC4 */ -#define PCC4_FLEXSPI2_SWRST 0 -#define PCC4_TPM6_SWRST 1 -#define PCC4_TPM7_SWRST 2 -#define PCC4_LPI2C6_SWRST 3 -#define PCC4_LPI2C7_SWRST 4 -#define PCC4_LPUART6_SWRST 5 -#define PCC4_LPUART7_SWRST 6 -#define PCC4_SAI4_SWRST 7 -#define PCC4_SAI5_SWRST 8 -#define PCC4_USDHC0_SWRST 9 -#define PCC4_USDHC1_SWRST 10 -#define PCC4_USDHC2_SWRST 11 -#define PCC4_USB0_SWRST 12 -#define PCC4_USB0_PHY_SWRST 13 -#define PCC4_USB1_SWRST 14 -#define PCC4_USB1_PHY_SWRST 15 -#define PCC4_ENET_SWRST 16 - -/* PCC5 */ -#define PCC5_TPM8_SWRST 0 -#define PCC5_SAI6_SWRST 1 -#define PCC5_SAI7_SWRST 2 -#define PCC5_SPDIF_SWRST 3 -#define PCC5_ISI_SWRST 4 -#define PCC5_CSI_REGS_SWRST 5 -#define PCC5_CSI_SWRST 6 -#define PCC5_DSI_SWRST 7 -#define PCC5_WDOG5_SWRST 8 -#define PCC5_EPDC_SWRST 9 -#define PCC5_PXP_SWRST 10 -#define PCC5_GPU2D_SWRST 11 -#define PCC5_GPU3D_SWRST 12 -#define PCC5_DC_NANO_SWRST 13 - -#endif /*DT_BINDING_RESET_IMX8ULP_H */ diff --git a/include/dt-bindings/reset/k210-rst.h b/include/dt-bindings/reset/k210-rst.h deleted file mode 100644 index 883c1aed50e..00000000000 --- a/include/dt-bindings/reset/k210-rst.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> - * Copyright (c) 2020 Western Digital Corporation or its affiliates. - */ -#ifndef RESET_K210_SYSCTL_H -#define RESET_K210_SYSCTL_H - -/* - * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. - * Taken from Kendryte SDK (kendryte-standalone-sdk). - */ -#define K210_RST_ROM 0 -#define K210_RST_DMA 1 -#define K210_RST_AI 2 -#define K210_RST_DVP 3 -#define K210_RST_FFT 4 -#define K210_RST_GPIO 5 -#define K210_RST_SPI0 6 -#define K210_RST_SPI1 7 -#define K210_RST_SPI2 8 -#define K210_RST_SPI3 9 -#define K210_RST_I2S0 10 -#define K210_RST_I2S1 11 -#define K210_RST_I2S2 12 -#define K210_RST_I2C0 13 -#define K210_RST_I2C1 14 -#define K210_RST_I2C2 15 -#define K210_RST_UART1 16 -#define K210_RST_UART2 17 -#define K210_RST_UART3 18 -#define K210_RST_AES 19 -#define K210_RST_FPIOA 20 -#define K210_RST_TIMER0 21 -#define K210_RST_TIMER1 22 -#define K210_RST_TIMER2 23 -#define K210_RST_WDT0 24 -#define K210_RST_WDT1 25 -#define K210_RST_SHA 26 -#define K210_RST_RTC 29 - -#endif /* RESET_K210_SYSCTL_H */ diff --git a/include/dt-bindings/reset/k210-sysctl.h b/include/dt-bindings/reset/k210-sysctl.h new file mode 100644 index 00000000000..12bb3880d91 --- /dev/null +++ b/include/dt-bindings/reset/k210-sysctl.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h b/include/dt-bindings/reset/mediatek,mt6735-infracfg.h deleted file mode 100644 index 9df96909037..00000000000 --- a/include/dt-bindings/reset/mediatek,mt6735-infracfg.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef _DT_BINDINGS_RESET_MT6735_INFRACFG_H -#define _DT_BINDINGS_RESET_MT6735_INFRACFG_H - -#define MT6735_INFRA_RST0_EMI_REG 0 -#define MT6735_INFRA_RST0_DRAMC0_AO 1 -#define MT6735_INFRA_RST0_AP_CIRQ_EINT 2 -#define MT6735_INFRA_RST0_APXGPT 3 -#define MT6735_INFRA_RST0_SCPSYS 4 -#define MT6735_INFRA_RST0_KP 5 -#define MT6735_INFRA_RST0_PMIC_WRAP 6 -#define MT6735_INFRA_RST0_CLDMA_AO_TOP 7 -#define MT6735_INFRA_RST0_USBSIF_TOP 8 -#define MT6735_INFRA_RST0_EMI 9 -#define MT6735_INFRA_RST0_CCIF 10 -#define MT6735_INFRA_RST0_DRAMC0 11 -#define MT6735_INFRA_RST0_EMI_AO_REG 12 -#define MT6735_INFRA_RST0_CCIF_AO 13 -#define MT6735_INFRA_RST0_TRNG 14 -#define MT6735_INFRA_RST0_SYS_CIRQ 15 -#define MT6735_INFRA_RST0_GCE 16 -#define MT6735_INFRA_RST0_M4U 17 -#define MT6735_INFRA_RST0_CCIF1 18 -#define MT6735_INFRA_RST0_CLDMA_TOP_PD 19 - -#endif diff --git a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h b/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h deleted file mode 100644 index c489242b226..00000000000 --- a/include/dt-bindings/reset/mediatek,mt6735-mfgcfg.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef _DT_BINDINGS_RESET_MT6735_MFGCFG_H -#define _DT_BINDINGS_RESET_MT6735_MFGCFG_H - -#define MT6735_MFG_RST0_AXI 0 -#define MT6735_MFG_RST0_G3D 1 - -#endif /* _DT_BINDINGS_RESET_MT6735_MFGCFG_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h b/include/dt-bindings/reset/mediatek,mt6735-pericfg.h deleted file mode 100644 index a62bb192835..00000000000 --- a/include/dt-bindings/reset/mediatek,mt6735-pericfg.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef _DT_BINDINGS_RESET_MT6735_PERICFG_H -#define _DT_BINDINGS_RESET_MT6735_PERICFG_H - -#define MT6735_PERI_RST0_UART0 0 -#define MT6735_PERI_RST0_UART1 1 -#define MT6735_PERI_RST0_UART2 2 -#define MT6735_PERI_RST0_UART3 3 -#define MT6735_PERI_RST0_UART4 4 -#define MT6735_PERI_RST0_BTIF 5 -#define MT6735_PERI_RST0_DISP_PWM_PERI 6 -#define MT6735_PERI_RST0_PWM 7 -#define MT6735_PERI_RST0_AUXADC 8 -#define MT6735_PERI_RST0_DMA 9 -#define MT6735_PERI_RST0_IRDA 10 -#define MT6735_PERI_RST0_IRTX 11 -#define MT6735_PERI_RST0_THERM 12 -#define MT6735_PERI_RST0_MSDC2 13 -#define MT6735_PERI_RST0_MSDC3 14 -#define MT6735_PERI_RST0_MSDC0 15 -#define MT6735_PERI_RST0_MSDC1 16 -#define MT6735_PERI_RST0_I2C0 17 -#define MT6735_PERI_RST0_I2C1 18 -#define MT6735_PERI_RST0_I2C2 19 -#define MT6735_PERI_RST0_I2C3 20 -#define MT6735_PERI_RST0_USB 21 - -#define MT6735_PERI_RST1_SPI0 22 - -#endif diff --git a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h b/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h deleted file mode 100644 index b6ae5d24919..00000000000 --- a/include/dt-bindings/reset/mediatek,mt6735-vdecsys.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef _DT_BINDINGS_RESET_MT6735_VDECSYS_H -#define _DT_BINDINGS_RESET_MT6735_VDECSYS_H - -#define MT6735_VDEC_RST0_VDEC 0 -#define MT6735_VDEC_RST1_SMI_LARB1 1 - -#endif /* _DT_BINDINGS_RESET_MT6735_VDECSYS_H */ diff --git a/include/dt-bindings/reset/mediatek,mt6735-wdt.h b/include/dt-bindings/reset/mediatek,mt6735-wdt.h deleted file mode 100644 index c6056e676d4..00000000000 --- a/include/dt-bindings/reset/mediatek,mt6735-wdt.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef _DT_BINDINGS_RESET_MEDIATEK_MT6735_WDT_H_ -#define _DT_BINDINGS_RESET_MEDIATEK_MT6735_WDT_H_ - -#define MT6735_TOPRGU_MM_RST 1 -#define MT6735_TOPRGU_MFG_RST 2 -#define MT6735_TOPRGU_VENC_RST 3 -#define MT6735_TOPRGU_VDEC_RST 4 -#define MT6735_TOPRGU_IMG_RST 5 -#define MT6735_TOPRGU_MD_RST 7 -#define MT6735_TOPRGU_CONN_RST 9 -#define MT6735_TOPRGU_C2K_SW_RST 14 -#define MT6735_TOPRGU_C2K_RST 15 -#define MT6735_TOPRGU_RST_NUM 9 - -#endif diff --git a/include/dt-bindings/reset/mediatek,mt6795-resets.h b/include/dt-bindings/reset/mediatek,mt6795-resets.h deleted file mode 100644 index 5464a4a79a7..00000000000 --- a/include/dt-bindings/reset/mediatek,mt6795-resets.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ -/* - * Copyright (c) 2022 Collabora Ltd. - * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6795 -#define _DT_BINDINGS_RESET_CONTROLLER_MT6795 - -/* INFRACFG resets */ -#define MT6795_INFRA_RST0_SCPSYS_RST 0 -#define MT6795_INFRA_RST0_PMIC_WRAP_RST 1 -#define MT6795_INFRA_RST1_MIPI_DSI_RST 2 -#define MT6795_INFRA_RST1_MIPI_CSI_RST 3 -#define MT6795_INFRA_RST1_MM_IOMMU_RST 4 - -/* MMSYS resets */ -#define MT6795_MMSYS_SW0_RST_B_SMI_COMMON 0 -#define MT6795_MMSYS_SW0_RST_B_SMI_LARB 1 -#define MT6795_MMSYS_SW0_RST_B_CAM_MDP 2 -#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA0 3 -#define MT6795_MMSYS_SW0_RST_B_MDP_RDMA1 4 -#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ0 5 -#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ1 6 -#define MT6795_MMSYS_SW0_RST_B_MDP_RSZ2 7 -#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP0 8 -#define MT6795_MMSYS_SW0_RST_B_MDP_TDSHP1 9 -#define MT6795_MMSYS_SW0_RST_B_MDP_WDMA 10 -#define MT6795_MMSYS_SW0_RST_B_MDP_WROT0 11 -#define MT6795_MMSYS_SW0_RST_B_MDP_WROT1 12 -#define MT6795_MMSYS_SW0_RST_B_MDP_CROP 13 - -/* PERICFG resets */ -#define MT6795_PERI_NFI_SW_RST 0 -#define MT6795_PERI_THERM_SW_RST 1 -#define MT6795_PERI_MSDC1_SW_RST 2 - -/* TOPRGU resets */ -#define MT6795_TOPRGU_INFRA_SW_RST 0 -#define MT6795_TOPRGU_MM_SW_RST 1 -#define MT6795_TOPRGU_MFG_SW_RST 2 -#define MT6795_TOPRGU_VENC_SW_RST 3 -#define MT6795_TOPRGU_VDEC_SW_RST 4 -#define MT6795_TOPRGU_IMG_SW_RST 5 -#define MT6795_TOPRGU_DDRPHY_SW_RST 6 -#define MT6795_TOPRGU_MD_SW_RST 7 -#define MT6795_TOPRGU_INFRA_AO_SW_RST 8 -#define MT6795_TOPRGU_MD_LITE_SW_RST 9 -#define MT6795_TOPRGU_APMIXED_SW_RST 10 -#define MT6795_TOPRGU_PWRAP_SPI_CTL_RST 11 -#define MT6795_TOPRGU_SW_RST_NUM 12 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6795 */ diff --git a/include/dt-bindings/reset/mediatek,mt7988-resets.h b/include/dt-bindings/reset/mediatek,mt7988-resets.h deleted file mode 100644 index 0eb152889a8..00000000000 --- a/include/dt-bindings/reset/mediatek,mt7988-resets.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org> - * Author: Daniel Golle <daniel@makrotopia.org> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988 -#define _DT_BINDINGS_RESET_CONTROLLER_MT7988 - -/* ETHWARP resets */ -#define MT7988_ETHWARP_RST_SWITCH 0 - -/* INFRA resets */ -#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 -#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 - - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ - diff --git a/include/dt-bindings/reset/mt2701-resets.h b/include/dt-bindings/reset/mt2701-resets.h deleted file mode 100644 index 91e4200fd74..00000000000 --- a/include/dt-bindings/reset/mt2701-resets.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701 -#define _DT_BINDINGS_RESET_CONTROLLER_MT2701 - -/* INFRACFG resets */ -#define MT2701_INFRA_EMI_REG_RST 0 -#define MT2701_INFRA_DRAMC0_A0_RST 1 -#define MT2701_INFRA_FHCTL_RST 2 -#define MT2701_INFRA_APCIRQ_EINT_RST 3 -#define MT2701_INFRA_APXGPT_RST 4 -#define MT2701_INFRA_SCPSYS_RST 5 -#define MT2701_INFRA_KP_RST 6 -#define MT2701_INFRA_PMIC_WRAP_RST 7 -#define MT2701_INFRA_MIPI_RST 8 -#define MT2701_INFRA_IRRX_RST 9 -#define MT2701_INFRA_CEC_RST 10 -#define MT2701_INFRA_EMI_RST 32 -#define MT2701_INFRA_DRAMC0_RST 34 -#define MT2701_INFRA_TRNG_RST 37 -#define MT2701_INFRA_SYSIRQ_RST 38 - -/* PERICFG resets */ -#define MT2701_PERI_UART0_SW_RST 0 -#define MT2701_PERI_UART1_SW_RST 1 -#define MT2701_PERI_UART2_SW_RST 2 -#define MT2701_PERI_UART3_SW_RST 3 -#define MT2701_PERI_GCPU_SW_RST 5 -#define MT2701_PERI_BTIF_SW_RST 6 -#define MT2701_PERI_PWM_SW_RST 8 -#define MT2701_PERI_AUXADC_SW_RST 10 -#define MT2701_PERI_DMA_SW_RST 11 -#define MT2701_PERI_NFI_SW_RST 14 -#define MT2701_PERI_NLI_SW_RST 15 -#define MT2701_PERI_THERM_SW_RST 16 -#define MT2701_PERI_MSDC2_SW_RST 17 -#define MT2701_PERI_MSDC0_SW_RST 19 -#define MT2701_PERI_MSDC1_SW_RST 20 -#define MT2701_PERI_I2C0_SW_RST 22 -#define MT2701_PERI_I2C1_SW_RST 23 -#define MT2701_PERI_I2C2_SW_RST 24 -#define MT2701_PERI_I2C3_SW_RST 25 -#define MT2701_PERI_USB_SW_RST 28 -#define MT2701_PERI_ETH_SW_RST 29 -#define MT2701_PERI_SPI0_SW_RST 33 - -/* TOPRGU resets */ -#define MT2701_TOPRGU_INFRA_RST 0 -#define MT2701_TOPRGU_MM_RST 1 -#define MT2701_TOPRGU_MFG_RST 2 -#define MT2701_TOPRGU_ETHDMA_RST 3 -#define MT2701_TOPRGU_VDEC_RST 4 -#define MT2701_TOPRGU_VENC_IMG_RST 5 -#define MT2701_TOPRGU_DDRPHY_RST 6 -#define MT2701_TOPRGU_MD_RST 7 -#define MT2701_TOPRGU_INFRA_AO_RST 8 -#define MT2701_TOPRGU_CONN_RST 9 -#define MT2701_TOPRGU_APMIXED_RST 10 -#define MT2701_TOPRGU_HIFSYS_RST 11 -#define MT2701_TOPRGU_CONN_MCU_RST 12 -#define MT2701_TOPRGU_BDP_DISP_RST 13 - -/* HIFSYS resets */ -#define MT2701_HIFSYS_UHOST0_RST 3 -#define MT2701_HIFSYS_UHOST1_RST 4 -#define MT2701_HIFSYS_UPHY0_RST 21 -#define MT2701_HIFSYS_UPHY1_RST 22 -#define MT2701_HIFSYS_PCIE0_RST 24 -#define MT2701_HIFSYS_PCIE1_RST 25 -#define MT2701_HIFSYS_PCIE2_RST 26 - -/* ETHSYS resets */ -#define MT2701_ETHSYS_SYS_RST 0 -#define MT2701_ETHSYS_MCM_RST 2 -#define MT2701_ETHSYS_FE_RST 6 -#define MT2701_ETHSYS_GMAC_RST 23 -#define MT2701_ETHSYS_PPE_RST 31 - -/* G3DSYS resets */ -#define MT2701_G3DSYS_CORE_RST 0 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */ diff --git a/include/dt-bindings/reset/mt2712-resets.h b/include/dt-bindings/reset/mt2712-resets.h deleted file mode 100644 index 9e7ee762f07..00000000000 --- a/include/dt-bindings/reset/mt2712-resets.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Yong Liang <yong.liang@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 -#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 - -#define MT2712_TOPRGU_INFRA_SW_RST 0 -#define MT2712_TOPRGU_MM_SW_RST 1 -#define MT2712_TOPRGU_MFG_SW_RST 2 -#define MT2712_TOPRGU_VENC_SW_RST 3 -#define MT2712_TOPRGU_VDEC_SW_RST 4 -#define MT2712_TOPRGU_IMG_SW_RST 5 -#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 -#define MT2712_TOPRGU_USB_SW_RST 9 -#define MT2712_TOPRGU_APMIXED_SW_RST 10 - -#define MT2712_TOPRGU_SW_RST_NUM 11 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ diff --git a/include/dt-bindings/reset/mt7620-reset.h b/include/dt-bindings/reset/mt7620-reset.h new file mode 100644 index 00000000000..3096b29cdb1 --- /dev/null +++ b/include/dt-bindings/reset/mt7620-reset.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MT7620_RESET_H_ +#define _DT_BINDINGS_MT7620_RESET_H_ + +#define PPE_RST 31 +#define SDHC_RST 30 +#define MIPS_CNT_RST 28 +#define PCIE_RST 26 +#define UHST_RST 25 +#define EPHY_RST 24 +#define ESW_RST 23 +#define UDEV_RST 22 +#define FE_RST 21 +#define WLAN_RST 20 +#define UARTL_RST 19 +#define SPI_RST 18 +#define I2S_RST 17 +#define I2C_RST 16 +#define NAND_RST 15 +#define DMA_RST 14 +#define PIO_RST 13 +#define UARTF_RST 12 +#define PCM_RST 11 +#define MC_RST 10 +#define INTC_RST 9 +#define TIMER_RST 8 +#define SYS_RST 0 + +#endif /* _DT_BINDINGS_MT7620_RESET_H_ */ diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h index 7572c6b4145..8e4341f0407 100644 --- a/include/dt-bindings/reset/mt7621-reset.h +++ b/include/dt-bindings/reset/mt7621-reset.h @@ -1,37 +1,38 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2021 Sergio Paracuellos - * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com> + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> */ -#ifndef DT_BINDING_MT7621_RESET_H -#define DT_BINDING_MT7621_RESET_H +#ifndef _DT_BINDINGS_MT7621_RESET_H_ +#define _DT_BINDINGS_MT7621_RESET_H_ -#define MT7621_RST_SYS 0 -#define MT7621_RST_MCM 2 -#define MT7621_RST_HSDMA 5 -#define MT7621_RST_FE 6 -#define MT7621_RST_SPDIFTX 7 -#define MT7621_RST_TIMER 8 -#define MT7621_RST_INT 9 -#define MT7621_RST_MC 10 -#define MT7621_RST_PCM 11 -#define MT7621_RST_PIO 13 -#define MT7621_RST_GDMA 14 -#define MT7621_RST_NFI 15 -#define MT7621_RST_I2C 16 -#define MT7621_RST_I2S 17 -#define MT7621_RST_SPI 18 -#define MT7621_RST_UART1 19 -#define MT7621_RST_UART2 20 -#define MT7621_RST_UART3 21 -#define MT7621_RST_ETH 23 -#define MT7621_RST_PCIE0 24 -#define MT7621_RST_PCIE1 25 -#define MT7621_RST_PCIE2 26 -#define MT7621_RST_AUX_STCK 28 -#define MT7621_RST_CRYPTO 29 -#define MT7621_RST_SDXC 30 -#define MT7621_RST_PPE 31 +#define RST_PPE 31 +#define RST_SDXC 30 +#define RST_CRYPTO 29 +#define RST_AUX_STCK 28 +#define RST_PCIE2 26 +#define RST_PCIE1 25 +#define RST_PCIE0 24 +#define RST_GMAC 23 +#define RST_UART3 21 +#define RST_UART2 20 +#define RST_UART1 19 +#define RST_SPI 18 +#define RST_I2S 17 +#define RST_I2C 16 +#define RST_NFI 15 +#define RST_GDMA 14 +#define RST_PIO 13 +#define RST_PCM 11 +#define RST_MC 10 +#define RST_INTC 9 +#define RST_TIMER 8 +#define RST_SPDIFTX 7 +#define RST_FE 6 +#define RST_HSDMA 5 +#define RST_MCM 2 +#define RST_SYS 0 -#endif /* DT_BINDING_MT7621_RESET_H */ +#endif /* _DT_BINDINGS_MT7621_RESET_H_ */ diff --git a/include/dt-bindings/reset/mt7622-reset.h b/include/dt-bindings/reset/mt7622-reset.h deleted file mode 100644 index da0d1ae81cb..00000000000 --- a/include/dt-bindings/reset/mt7622-reset.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2017 MediaTek Inc. - * Author: Sean Wang <sean.wang@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622 -#define _DT_BINDINGS_RESET_CONTROLLER_MT7622 - -/* INFRACFG resets */ -#define MT7622_INFRA_EMI_REG_RST 0 -#define MT7622_INFRA_DRAMC0_A0_RST 1 -#define MT7622_INFRA_APCIRQ_EINT_RST 3 -#define MT7622_INFRA_APXGPT_RST 4 -#define MT7622_INFRA_SCPSYS_RST 5 -#define MT7622_INFRA_PMIC_WRAP_RST 7 -#define MT7622_INFRA_IRRX_RST 9 -#define MT7622_INFRA_EMI_RST 16 -#define MT7622_INFRA_WED0_RST 17 -#define MT7622_INFRA_DRAMC_RST 18 -#define MT7622_INFRA_CCI_INTF_RST 19 -#define MT7622_INFRA_TRNG_RST 21 -#define MT7622_INFRA_SYSIRQ_RST 22 -#define MT7622_INFRA_WED1_RST 25 - -/* PERICFG Subsystem resets */ -#define MT7622_PERI_UART0_SW_RST 0 -#define MT7622_PERI_UART1_SW_RST 1 -#define MT7622_PERI_UART2_SW_RST 2 -#define MT7622_PERI_UART3_SW_RST 3 -#define MT7622_PERI_UART4_SW_RST 4 -#define MT7622_PERI_BTIF_SW_RST 6 -#define MT7622_PERI_PWM_SW_RST 8 -#define MT7622_PERI_AUXADC_SW_RST 10 -#define MT7622_PERI_DMA_SW_RST 11 -#define MT7622_PERI_IRTX_SW_RST 13 -#define MT7622_PERI_NFI_SW_RST 14 -#define MT7622_PERI_THERM_SW_RST 16 -#define MT7622_PERI_MSDC0_SW_RST 19 -#define MT7622_PERI_MSDC1_SW_RST 20 -#define MT7622_PERI_I2C0_SW_RST 22 -#define MT7622_PERI_I2C1_SW_RST 23 -#define MT7622_PERI_I2C2_SW_RST 24 -#define MT7622_PERI_SPI0_SW_RST 33 -#define MT7622_PERI_SPI1_SW_RST 34 -#define MT7622_PERI_FLASHIF_SW_RST 36 - -/* TOPRGU resets */ -#define MT7622_TOPRGU_INFRA_RST 0 -#define MT7622_TOPRGU_ETHDMA_RST 1 -#define MT7622_TOPRGU_DDRPHY_RST 6 -#define MT7622_TOPRGU_INFRA_AO_RST 8 -#define MT7622_TOPRGU_CONN_RST 9 -#define MT7622_TOPRGU_APMIXED_RST 10 -#define MT7622_TOPRGU_CONN_MCU_RST 12 - -/* PCIe/SATA Subsystem resets */ -#define MT7622_SATA_PHY_REG_RST 12 -#define MT7622_SATA_PHY_SW_RST 13 -#define MT7622_SATA_AXI_BUS_RST 15 -#define MT7622_PCIE1_CORE_RST 19 -#define MT7622_PCIE1_MMIO_RST 20 -#define MT7622_PCIE1_HRST 21 -#define MT7622_PCIE1_USER_RST 22 -#define MT7622_PCIE1_PIPE_RST 23 -#define MT7622_PCIE0_CORE_RST 27 -#define MT7622_PCIE0_MMIO_RST 28 -#define MT7622_PCIE0_HRST 29 -#define MT7622_PCIE0_USER_RST 30 -#define MT7622_PCIE0_PIPE_RST 31 - -/* SSUSB Subsystem resets */ -#define MT7622_SSUSB_PHY_PWR_RST 3 -#define MT7622_SSUSB_MAC_PWR_RST 4 - -/* ETHSYS Subsystem resets */ -#define MT7622_ETHSYS_SYS_RST 0 -#define MT7622_ETHSYS_MCM_RST 2 -#define MT7622_ETHSYS_HSDMA_RST 5 -#define MT7622_ETHSYS_FE_RST 6 -#define MT7622_ETHSYS_GMAC_RST 23 -#define MT7622_ETHSYS_EPHY_RST 24 -#define MT7622_ETHSYS_CRYPTO_RST 29 -#define MT7622_ETHSYS_PPE_RST 31 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */ diff --git a/include/dt-bindings/reset/mt7623-reset.h b/include/dt-bindings/reset/mt7623-reset.h new file mode 100644 index 00000000000..a859a5b26a4 --- /dev/null +++ b/include/dt-bindings/reset/mt7623-reset.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* ETHSYS resets */ +#define ETHSYS_PPE_RST 31 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_FE_RST 6 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_SYS_RST 0 + +/* HIFSYS resets */ +#define HIFSYS_PCIE2_RST 26 +#define HIFSYS_PCIE1_RST 25 +#define HIFSYS_PCIE0_RST 24 +#define HIFSYS_UPHY1_RST 22 +#define HIFSYS_UPHY0_RST 21 +#define HIFSYS_UHOST1_RST 4 +#define HIFSYS_UHOST0_RST 3 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/include/dt-bindings/reset/mt7628-reset.h b/include/dt-bindings/reset/mt7628-reset.h new file mode 100644 index 00000000000..2a674c1ea72 --- /dev/null +++ b/include/dt-bindings/reset/mt7628-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * + * Author: Weijie Gao <weijie.gao@mediatek.com> + */ + +#ifndef _DT_BINDINGS_MT7628_RESET_H_ +#define _DT_BINDINGS_MT7628_RESET_H_ + +#define MT7628_PWM_RST 31 +#define MT7628_SDXC_RST 30 +#define MT7628_CRYPTO_RST 29 +#define MT7628_AUX_STCK_RST 28 +#define MT7628_PCIE_RST 26 +#define MT7628_EPHY_RST 24 +#define MT7628_ETH_RST 23 +#define MT7628_UPHY_RST 22 +#define MT7628_UART2_RST 20 +#define MT7628_UART1_RST 19 +#define MT7628_SPI_RST 18 +#define MT7628_I2S_RST 17 +#define MT7628_I2C_RST 16 +#define MT7628_GDMA_RST 14 +#define MT7628_PIO_RST 13 +#define MT7628_UART0_RST 12 +#define MT7628_PCM_RST 11 +#define MT7628_MC_RST 10 +#define MT7628_INT_RST 9 +#define MT7628_TIMER_RST 8 +#define MT7628_HIF_RST 5 +#define MT7628_WIFI_RST 4 +#define MT7628_SPIS_RST 3 +#define MT7628_SYS_RST 0 + +#endif /* _DT_BINDINGS_MT7628_RESET_H_ */ diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h new file mode 100644 index 00000000000..311a5cb3d00 --- /dev/null +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* PCIe/SATA Subsystem resets */ +#define MT7622_SATA_PHY_REG_RST 12 +#define MT7622_SATA_PHY_SW_RST 13 +#define MT7622_SATA_AXI_BUS_RST 15 +#define PCIE1_CORE_RST 19 +#define PCIE1_MMIO_RST 20 +#define PCIE1_HRST 21 +#define PCIE1_USER_RST 22 +#define PCIE1_PIPE_RST 23 +#define PCIE0_CORE_RST 27 +#define PCIE0_MMIO_RST 28 +#define PCIE0_HRST 29 +#define PCIE0_USER_RST 30 +#define PCIE0_PIPE_RST 31 + +/* SSUSB Subsystem resets */ +#define SSUSB_PHY_PWR_RST 3 +#define SSUSB_MAC_PWR_RST 4 + +/* ETH Subsystem resets */ +#define ETHSYS_SYS_RST 0 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_HSDMA_RST 5 +#define ETHSYS_FE_RST 6 +#define ETHSYS_ESW_RST 16 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_EPHY_RST 24 +#define ETHSYS_CRYPTO_RST 29 +#define ETHSYS_PPE_RST 31 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/include/dt-bindings/reset/mt7629-resets.h b/include/dt-bindings/reset/mt7629-resets.h deleted file mode 100644 index 6bb85734f68..00000000000 --- a/include/dt-bindings/reset/mt7629-resets.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7629 -#define _DT_BINDINGS_RESET_CONTROLLER_MT7629 - -/* INFRACFG resets */ -#define MT7629_INFRA_EMI_MPU_RST 0 -#define MT7629_INFRA_UART5_RST 2 -#define MT7629_INFRA_CIRQ_EINT_RST 3 -#define MT7629_INFRA_APXGPT_RST 4 -#define MT7629_INFRA_SCPSYS_RST 5 -#define MT7629_INFRA_KP_RST 6 -#define MT7629_INFRA_SPI1_RST 7 -#define MT7629_INFRA_SPI4_RST 8 -#define MT7629_INFRA_SYSTIMER_RST 9 -#define MT7629_INFRA_IRRX_RST 10 -#define MT7629_INFRA_AO_BUS_RST 16 -#define MT7629_INFRA_EMI_RST 32 -#define MT7629_INFRA_APMIXED_RST 35 -#define MT7629_INFRA_MIPI_RST 36 -#define MT7629_INFRA_TRNG_RST 37 -#define MT7629_INFRA_SYSCIRQ_RST 38 -#define MT7629_INFRA_MIPI_CSI_RST 39 -#define MT7629_INFRA_GCE_FAXI_RST 40 -#define MT7629_INFRA_I2C_SRAM_RST 41 -#define MT7629_INFRA_IOMMU_RST 47 - -/* PERICFG resets */ -#define MT7629_PERI_UART0_SW_RST 0 -#define MT7629_PERI_UART1_SW_RST 1 -#define MT7629_PERI_UART2_SW_RST 2 -#define MT7629_PERI_BTIF_SW_RST 6 -#define MT7629_PERI_PWN_SW_RST 8 -#define MT7629_PERI_DMA_SW_RST 11 -#define MT7629_PERI_NFI_SW_RST 14 -#define MT7629_PERI_I2C0_SW_RST 22 -#define MT7629_PERI_SPI0_SW_RST 33 -#define MT7629_PERI_SPI1_SW_RST 34 -#define MT7629_PERI_FLASHIF_SW_RST 36 - -/* PCIe Subsystem resets */ -#define MT7629_PCIE1_CORE_RST 19 -#define MT7629_PCIE1_MMIO_RST 20 -#define MT7629_PCIE1_HRST 21 -#define MT7629_PCIE1_USER_RST 22 -#define MT7629_PCIE1_PIPE_RST 23 -#define MT7629_PCIE0_CORE_RST 27 -#define MT7629_PCIE0_MMIO_RST 28 -#define MT7629_PCIE0_HRST 29 -#define MT7629_PCIE0_USER_RST 30 -#define MT7629_PCIE0_PIPE_RST 31 - -/* SSUSB Subsystem resets */ -#define MT7629_SSUSB_PHY_PWR_RST 3 -#define MT7629_SSUSB_MAC_PWR_RST 4 - -/* ETH Subsystem resets */ -#define MT7629_ETHSYS_SYS_RST 0 -#define MT7629_ETHSYS_MCM_RST 2 -#define MT7629_ETHSYS_HSDMA_RST 5 -#define MT7629_ETHSYS_FE_RST 6 -#define MT7629_ETHSYS_ESW_RST 16 -#define MT7629_ETHSYS_GMAC_RST 23 -#define MT7629_ETHSYS_EPHY_RST 24 -#define MT7629_ETHSYS_CRYPTO_RST 29 -#define MT7629_ETHSYS_PPE_RST 31 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7629 */ diff --git a/include/dt-bindings/reset/mt7986-resets.h b/include/dt-bindings/reset/mt7986-resets.h deleted file mode 100644 index af3d16c8119..00000000000 --- a/include/dt-bindings/reset/mt7986-resets.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Sam Shih <sam.shih@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7986 -#define _DT_BINDINGS_RESET_CONTROLLER_MT7986 - -/* INFRACFG resets */ -#define MT7986_INFRACFG_PEXTP_MAC_SW_RST 6 -#define MT7986_INFRACFG_SSUSB_SW_RST 7 -#define MT7986_INFRACFG_EIP97_SW_RST 8 -#define MT7986_INFRACFG_AUDIO_SW_RST 13 -#define MT7986_INFRACFG_CQ_DMA_SW_RST 14 - -#define MT7986_INFRACFG_TRNG_SW_RST 17 -#define MT7986_INFRACFG_AP_DMA_SW_RST 32 -#define MT7986_INFRACFG_I2C_SW_RST 33 -#define MT7986_INFRACFG_NFI_SW_RST 34 -#define MT7986_INFRACFG_SPI0_SW_RST 35 -#define MT7986_INFRACFG_SPI1_SW_RST 36 -#define MT7986_INFRACFG_UART0_SW_RST 37 -#define MT7986_INFRACFG_UART1_SW_RST 38 -#define MT7986_INFRACFG_UART2_SW_RST 39 -#define MT7986_INFRACFG_AUXADC_SW_RST 43 - -#define MT7986_INFRACFG_APXGPT_SW_RST 66 -#define MT7986_INFRACFG_PWM_SW_RST 68 - -#define MT7986_INFRACFG_SW_RST_NUM 69 - -/* TOPRGU resets */ -#define MT7986_TOPRGU_APMIXEDSYS_SW_RST 0 -#define MT7986_TOPRGU_SGMII0_SW_RST 1 -#define MT7986_TOPRGU_SGMII1_SW_RST 2 -#define MT7986_TOPRGU_INFRA_SW_RST 3 -#define MT7986_TOPRGU_U2PHY_SW_RST 5 -#define MT7986_TOPRGU_PCIE_SW_RST 6 -#define MT7986_TOPRGU_SSUSB_SW_RST 7 -#define MT7986_TOPRGU_ETHDMA_SW_RST 20 -#define MT7986_TOPRGU_CONSYS_SW_RST 23 - -#define MT7986_TOPRGU_SW_RST_NUM 24 - -/* ETHSYS Subsystem resets */ -#define MT7986_ETHSYS_FE_SW_RST 6 -#define MT7986_ETHSYS_PMTR_SW_RST 8 -#define MT7986_ETHSYS_GMAC_SW_RST 23 -#define MT7986_ETHSYS_PPE0_SW_RST 30 -#define MT7986_ETHSYS_PPE1_SW_RST 31 - -#define MT7986_ETHSYS_SW_RST_NUM 32 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7986 */ diff --git a/include/dt-bindings/reset/mt7988-reset.h b/include/dt-bindings/reset/mt7988-reset.h new file mode 100644 index 00000000000..d30011f941d --- /dev/null +++ b/include/dt-bindings/reset/mt7988-reset.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* ETHDMA Subsystem resets */ +#define ETHDMA_FE_RST 6 +#define ETHDMA_PMTR_RST 8 +#define ETHDMA_GMAC_RST 23 +#define ETHDMA_WDMA0_RST 24 +#define ETHDMA_WDMA1_RST 25 +#define ETHDMA_WDMA2_RST 26 +#define ETHDMA_PPE0_RST 29 +#define ETHDMA_PPE1_RST 30 +#define ETHDMA_PPE2_RST 31 + +/* ETHWARP Subsystem resets */ +#define ETHWARP_GSW_RST 9 +#define ETHWARP_EIP197_RST 10 +#define ETHWARP_WOCPU0_RST 32 +#define ETHWARP_WOCPU1_RST 33 +#define ETHWARP_WOCPU2_RST 34 +#define ETHWARP_WOX_NET_MUX_RST 35 +#define ETHWARP_WED0_RST 36 +#define ETHWARP_WED1_RST 37 +#define ETHWARP_WED2_RST 38 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/include/dt-bindings/reset/mt8135-resets.h b/include/dt-bindings/reset/mt8135-resets.h deleted file mode 100644 index 8c060d08716..00000000000 --- a/include/dt-bindings/reset/mt8135-resets.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Flora Fu, MediaTek - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8135 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8135 - -/* INFRACFG resets */ -#define MT8135_INFRA_EMI_REG_RST 0 -#define MT8135_INFRA_DRAMC0_A0_RST 1 -#define MT8135_INFRA_CCIF0_RST 2 -#define MT8135_INFRA_APCIRQ_EINT_RST 3 -#define MT8135_INFRA_APXGPT_RST 4 -#define MT8135_INFRA_SCPSYS_RST 5 -#define MT8135_INFRA_CCIF1_RST 6 -#define MT8135_INFRA_PMIC_WRAP_RST 7 -#define MT8135_INFRA_KP_RST 8 -#define MT8135_INFRA_EMI_RST 32 -#define MT8135_INFRA_DRAMC0_RST 34 -#define MT8135_INFRA_SMI_RST 35 -#define MT8135_INFRA_M4U_RST 36 - -/* PERICFG resets */ -#define MT8135_PERI_UART0_SW_RST 0 -#define MT8135_PERI_UART1_SW_RST 1 -#define MT8135_PERI_UART2_SW_RST 2 -#define MT8135_PERI_UART3_SW_RST 3 -#define MT8135_PERI_IRDA_SW_RST 4 -#define MT8135_PERI_PTP_SW_RST 5 -#define MT8135_PERI_AP_HIF_SW_RST 6 -#define MT8135_PERI_GPCU_SW_RST 7 -#define MT8135_PERI_MD_HIF_SW_RST 8 -#define MT8135_PERI_NLI_SW_RST 9 -#define MT8135_PERI_AUXADC_SW_RST 10 -#define MT8135_PERI_DMA_SW_RST 11 -#define MT8135_PERI_NFI_SW_RST 14 -#define MT8135_PERI_PWM_SW_RST 15 -#define MT8135_PERI_THERM_SW_RST 16 -#define MT8135_PERI_MSDC0_SW_RST 17 -#define MT8135_PERI_MSDC1_SW_RST 18 -#define MT8135_PERI_MSDC2_SW_RST 19 -#define MT8135_PERI_MSDC3_SW_RST 20 -#define MT8135_PERI_I2C0_SW_RST 22 -#define MT8135_PERI_I2C1_SW_RST 23 -#define MT8135_PERI_I2C2_SW_RST 24 -#define MT8135_PERI_I2C3_SW_RST 25 -#define MT8135_PERI_I2C4_SW_RST 26 -#define MT8135_PERI_I2C5_SW_RST 27 -#define MT8135_PERI_I2C6_SW_RST 28 -#define MT8135_PERI_USB_SW_RST 29 -#define MT8135_PERI_SPI1_SW_RST 33 -#define MT8135_PERI_PWRAP_BRIDGE_SW_RST 34 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8135 */ diff --git a/include/dt-bindings/reset/mt8173-resets.h b/include/dt-bindings/reset/mt8173-resets.h deleted file mode 100644 index 6a60c7cecc4..00000000000 --- a/include/dt-bindings/reset/mt8173-resets.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014 MediaTek Inc. - * Author: Flora Fu, MediaTek - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8173 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8173 - -/* INFRACFG resets */ -#define MT8173_INFRA_EMI_REG_RST 0 -#define MT8173_INFRA_DRAMC0_A0_RST 1 -#define MT8173_INFRA_APCIRQ_EINT_RST 3 -#define MT8173_INFRA_APXGPT_RST 4 -#define MT8173_INFRA_SCPSYS_RST 5 -#define MT8173_INFRA_KP_RST 6 -#define MT8173_INFRA_PMIC_WRAP_RST 7 -#define MT8173_INFRA_MPIP_RST 8 -#define MT8173_INFRA_CEC_RST 9 -#define MT8173_INFRA_EMI_RST 32 -#define MT8173_INFRA_DRAMC0_RST 34 -#define MT8173_INFRA_APMIXEDSYS_RST 35 -#define MT8173_INFRA_MIPI_DSI_RST 36 -#define MT8173_INFRA_TRNG_RST 37 -#define MT8173_INFRA_SYSIRQ_RST 38 -#define MT8173_INFRA_MIPI_CSI_RST 39 -#define MT8173_INFRA_GCE_FAXI_RST 40 -#define MT8173_INFRA_MMIOMMURST 47 - -/* MMSYS resets */ -#define MT8173_MMSYS_SW0_RST_B_DISP_DSI0 25 - -/* PERICFG resets */ -#define MT8173_PERI_UART0_SW_RST 0 -#define MT8173_PERI_UART1_SW_RST 1 -#define MT8173_PERI_UART2_SW_RST 2 -#define MT8173_PERI_UART3_SW_RST 3 -#define MT8173_PERI_IRRX_SW_RST 4 -#define MT8173_PERI_PWM_SW_RST 8 -#define MT8173_PERI_AUXADC_SW_RST 10 -#define MT8173_PERI_DMA_SW_RST 11 -#define MT8173_PERI_I2C6_SW_RST 13 -#define MT8173_PERI_NFI_SW_RST 14 -#define MT8173_PERI_THERM_SW_RST 16 -#define MT8173_PERI_MSDC2_SW_RST 17 -#define MT8173_PERI_MSDC3_SW_RST 18 -#define MT8173_PERI_MSDC0_SW_RST 19 -#define MT8173_PERI_MSDC1_SW_RST 20 -#define MT8173_PERI_I2C0_SW_RST 22 -#define MT8173_PERI_I2C1_SW_RST 23 -#define MT8173_PERI_I2C2_SW_RST 24 -#define MT8173_PERI_I2C3_SW_RST 25 -#define MT8173_PERI_I2C4_SW_RST 26 -#define MT8173_PERI_HDMI_SW_RST 29 -#define MT8173_PERI_SPI0_SW_RST 33 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8173 */ diff --git a/include/dt-bindings/reset/mt8183-resets.h b/include/dt-bindings/reset/mt8183-resets.h deleted file mode 100644 index 48c5d2de0a3..00000000000 --- a/include/dt-bindings/reset/mt8183-resets.h +++ /dev/null @@ -1,101 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 MediaTek Inc. - * Author: Yong Liang <yong.liang@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8183 - -/* INFRACFG AO resets */ -#define MT8183_INFRACFG_AO_THERM_SW_RST 0 -#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1 -#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3 -#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4 -#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5 -#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6 -#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7 -#define MT8183_INFRACFG_AO_APDMA_SW_RST 9 -#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10 -#define MT8183_INFRACFG_AO_BTIF_SW_RST 12 -#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14 -#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15 - -#define MT8183_INFRACFG_AO_IRTX_SW_RST 32 -#define MT8183_INFRACFG_AO_SPI0_SW_RST 33 -#define MT8183_INFRACFG_AO_I2C0_SW_RST 34 -#define MT8183_INFRACFG_AO_I2C1_SW_RST 35 -#define MT8183_INFRACFG_AO_I2C2_SW_RST 36 -#define MT8183_INFRACFG_AO_I2C3_SW_RST 37 -#define MT8183_INFRACFG_AO_UART0_SW_RST 38 -#define MT8183_INFRACFG_AO_UART1_SW_RST 39 -#define MT8183_INFRACFG_AO_UART2_SW_RST 40 -#define MT8183_INFRACFG_AO_PWM_SW_RST 41 -#define MT8183_INFRACFG_AO_SPI1_SW_RST 42 -#define MT8183_INFRACFG_AO_I2C4_SW_RST 43 -#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44 -#define MT8183_INFRACFG_AO_SPI2_SW_RST 45 -#define MT8183_INFRACFG_AO_SPI3_SW_RST 46 -#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47 - -#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64 -#define MT8183_INFRACFG_AO_SPM_SW_RST 65 -#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66 -#define MT8183_INFRACFG_AO_KP_SW_RST 68 -#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69 -#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70 -#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71 -#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72 -#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73 - -#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96 -#define MT8183_INFRACFG_AO_GCE_SW_RST 97 -#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98 -#define MT8183_INFRACFG_AO_TRNG_SW_RST 99 -#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103 -#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104 -#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105 -#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106 -#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107 -#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108 -#define MT8183_INFRACFG_AO_I2C5_SW_RST 109 -#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110 -#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111 -#define MT8183_INFRACFG_AO_SPI4_SW_RST 112 -#define MT8183_INFRACFG_AO_SPI5_SW_RST 113 -#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114 -#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115 -#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116 -#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117 -#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118 -#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119 -#define MT8183_INFRACFG_AO_I2C6_SW_RST 120 -#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121 -#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122 -#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123 -#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124 -#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125 -#define MT8183_INFRACFG_AO_I2C7_SW_RST 126 -#define MT8183_INFRACFG_AO_I2C8_SW_RST 127 - -#define MT8183_INFRACFG_SW_RST_NUM 128 - -/* MMSYS resets */ -#define MT8183_MMSYS_SW0_RST_B_DISP_DSI0 25 - -#define MT8183_TOPRGU_MM_SW_RST 1 -#define MT8183_TOPRGU_MFG_SW_RST 2 -#define MT8183_TOPRGU_VENC_SW_RST 3 -#define MT8183_TOPRGU_VDEC_SW_RST 4 -#define MT8183_TOPRGU_IMG_SW_RST 5 -#define MT8183_TOPRGU_MD_SW_RST 7 -#define MT8183_TOPRGU_CONN_SW_RST 9 -#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 -#define MT8183_TOPRGU_IPU0_SW_RST 14 -#define MT8183_TOPRGU_IPU1_SW_RST 15 -#define MT8183_TOPRGU_AUDIO_SW_RST 17 -#define MT8183_TOPRGU_CAMSYS_SW_RST 18 - -#define MT8183_TOPRGU_SW_RST_NUM 19 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */ diff --git a/include/dt-bindings/reset/mt8186-resets.h b/include/dt-bindings/reset/mt8186-resets.h deleted file mode 100644 index 2e9029c22f3..00000000000 --- a/include/dt-bindings/reset/mt8186-resets.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Runyang Chen <runyang.chen@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8186 - -/* TOPRGU resets */ -#define MT8186_TOPRGU_INFRA_SW_RST 0 -#define MT8186_TOPRGU_MM_SW_RST 1 -#define MT8186_TOPRGU_MFG_SW_RST 2 -#define MT8186_TOPRGU_VENC_SW_RST 3 -#define MT8186_TOPRGU_VDEC_SW_RST 4 -#define MT8186_TOPRGU_IMG_SW_RST 5 -#define MT8186_TOPRGU_DDR_SW_RST 6 -#define MT8186_TOPRGU_INFRA_AO_SW_RST 8 -#define MT8186_TOPRGU_CONNSYS_SW_RST 9 -#define MT8186_TOPRGU_APMIXED_SW_RST 10 -#define MT8186_TOPRGU_PWRAP_SW_RST 11 -#define MT8186_TOPRGU_CONN_MCU_SW_RST 12 -#define MT8186_TOPRGU_IPNNA_SW_RST 13 -#define MT8186_TOPRGU_WPE_SW_RST 14 -#define MT8186_TOPRGU_ADSP_SW_RST 15 -#define MT8186_TOPRGU_AUDIO_SW_RST 17 -#define MT8186_TOPRGU_CAM_MAIN_SW_RST 18 -#define MT8186_TOPRGU_CAM_RAWA_SW_RST 19 -#define MT8186_TOPRGU_CAM_RAWB_SW_RST 20 -#define MT8186_TOPRGU_IPE_SW_RST 21 -#define MT8186_TOPRGU_IMG2_SW_RST 22 -#define MT8186_TOPRGU_SW_RST_NUM 23 - -/* MMSYS resets */ -#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19 - -/* INFRA resets */ -#define MT8186_INFRA_THERMAL_CTRL_RST 0 -#define MT8186_INFRA_PTP_CTRL_RST 1 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */ diff --git a/include/dt-bindings/reset/mt8188-resets.h b/include/dt-bindings/reset/mt8188-resets.h deleted file mode 100644 index 5a58c54e7d2..00000000000 --- a/include/dt-bindings/reset/mt8188-resets.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Runyang Chen <runyang.chen@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8188 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8188 - -#define MT8188_TOPRGU_CONN_MCU_SW_RST 0 -#define MT8188_TOPRGU_INFRA_GRST_SW_RST 1 -#define MT8188_TOPRGU_IPU0_SW_RST 2 -#define MT8188_TOPRGU_IPU1_SW_RST 3 -#define MT8188_TOPRGU_IPU2_SW_RST 4 -#define MT8188_TOPRGU_AUD_ASRC_SW_RST 5 -#define MT8188_TOPRGU_INFRA_SW_RST 6 -#define MT8188_TOPRGU_MMSYS_SW_RST 7 -#define MT8188_TOPRGU_MFG_SW_RST 8 -#define MT8188_TOPRGU_VENC_SW_RST 9 -#define MT8188_TOPRGU_VDEC_SW_RST 10 -#define MT8188_TOPRGU_CAM_VCORE_SW_RST 11 -#define MT8188_TOPRGU_SCP_SW_RST 12 -#define MT8188_TOPRGU_APMIXEDSYS_SW_RST 13 -#define MT8188_TOPRGU_AUDIO_SW_RST 14 -#define MT8188_TOPRGU_CAMSYS_SW_RST 15 -#define MT8188_TOPRGU_MJC_SW_RST 16 -#define MT8188_TOPRGU_PERI_SW_RST 17 -#define MT8188_TOPRGU_PERI_AO_SW_RST 18 -#define MT8188_TOPRGU_PCIE_SW_RST 19 -#define MT8188_TOPRGU_ADSPSYS_SW_RST 21 -#define MT8188_TOPRGU_DPTX_SW_RST 22 -#define MT8188_TOPRGU_SPMI_MST_SW_RST 23 - -#define MT8188_TOPRGU_SW_RST_NUM 24 - -/* INFRA resets */ -#define MT8188_INFRA_RST1_THERMAL_MCU_RST 0 -#define MT8188_INFRA_RST1_THERMAL_CTRL_RST 1 -#define MT8188_INFRA_RST3_PTP_CTRL_RST 2 - -#define MT8188_VDO0_RST_DISP_OVL0 0 -#define MT8188_VDO0_RST_FAKE_ENG0 1 -#define MT8188_VDO0_RST_DISP_CCORR0 2 -#define MT8188_VDO0_RST_DISP_MUTEX0 3 -#define MT8188_VDO0_RST_DISP_GAMMA0 4 -#define MT8188_VDO0_RST_DISP_DITHER0 5 -#define MT8188_VDO0_RST_DISP_WDMA0 6 -#define MT8188_VDO0_RST_DISP_RDMA0 7 -#define MT8188_VDO0_RST_DSI0 8 -#define MT8188_VDO0_RST_DSI1 9 -#define MT8188_VDO0_RST_DSC_WRAP0 10 -#define MT8188_VDO0_RST_VPP_MERGE0 11 -#define MT8188_VDO0_RST_DP_INTF0 12 -#define MT8188_VDO0_RST_DISP_AAL0 13 -#define MT8188_VDO0_RST_INLINEROT0 14 -#define MT8188_VDO0_RST_APB_BUS 15 -#define MT8188_VDO0_RST_DISP_COLOR0 16 -#define MT8188_VDO0_RST_MDP_WROT0 17 -#define MT8188_VDO0_RST_DISP_RSZ0 18 - -#define MT8188_VDO1_RST_SMI_LARB2 0 -#define MT8188_VDO1_RST_SMI_LARB3 1 -#define MT8188_VDO1_RST_GALS 2 -#define MT8188_VDO1_RST_FAKE_ENG0 3 -#define MT8188_VDO1_RST_FAKE_ENG1 4 -#define MT8188_VDO1_RST_MDP_RDMA0 5 -#define MT8188_VDO1_RST_MDP_RDMA1 6 -#define MT8188_VDO1_RST_MDP_RDMA2 7 -#define MT8188_VDO1_RST_MDP_RDMA3 8 -#define MT8188_VDO1_RST_VPP_MERGE0 9 -#define MT8188_VDO1_RST_VPP_MERGE1 10 -#define MT8188_VDO1_RST_VPP_MERGE2 11 -#define MT8188_VDO1_RST_VPP_MERGE3 12 -#define MT8188_VDO1_RST_VPP_MERGE4 13 -#define MT8188_VDO1_RST_VPP2_TO_VDO1_DL_ASYNC 14 -#define MT8188_VDO1_RST_VPP3_TO_VDO1_DL_ASYNC 15 -#define MT8188_VDO1_RST_DISP_MUTEX 16 -#define MT8188_VDO1_RST_MDP_RDMA4 17 -#define MT8188_VDO1_RST_MDP_RDMA5 18 -#define MT8188_VDO1_RST_MDP_RDMA6 19 -#define MT8188_VDO1_RST_MDP_RDMA7 20 -#define MT8188_VDO1_RST_DP_INTF1_MMCK 21 -#define MT8188_VDO1_RST_DPI0_MM_CK 22 -#define MT8188_VDO1_RST_DPI1_MM_CK 23 -#define MT8188_VDO1_RST_MERGE0_DL_ASYNC 24 -#define MT8188_VDO1_RST_MERGE1_DL_ASYNC 25 -#define MT8188_VDO1_RST_MERGE2_DL_ASYNC 26 -#define MT8188_VDO1_RST_MERGE3_DL_ASYNC 27 -#define MT8188_VDO1_RST_MERGE4_DL_ASYNC 28 -#define MT8188_VDO1_RST_VDO0_DSC_TO_VDO1_DL_ASYNC 29 -#define MT8188_VDO1_RST_VDO0_MERGE_TO_VDO1_DL_ASYNC 30 -#define MT8188_VDO1_RST_PADDING0 31 -#define MT8188_VDO1_RST_PADDING1 32 -#define MT8188_VDO1_RST_PADDING2 33 -#define MT8188_VDO1_RST_PADDING3 34 -#define MT8188_VDO1_RST_PADDING4 35 -#define MT8188_VDO1_RST_PADDING5 36 -#define MT8188_VDO1_RST_PADDING6 37 -#define MT8188_VDO1_RST_PADDING7 38 -#define MT8188_VDO1_RST_DISP_RSZ0 39 -#define MT8188_VDO1_RST_DISP_RSZ1 40 -#define MT8188_VDO1_RST_DISP_RSZ2 41 -#define MT8188_VDO1_RST_DISP_RSZ3 42 -#define MT8188_VDO1_RST_HDR_VDO_FE0 43 -#define MT8188_VDO1_RST_HDR_GFX_FE0 44 -#define MT8188_VDO1_RST_HDR_VDO_BE 45 -#define MT8188_VDO1_RST_HDR_VDO_FE1 46 -#define MT8188_VDO1_RST_HDR_GFX_FE1 47 -#define MT8188_VDO1_RST_DISP_MIXER 48 -#define MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC 49 -#define MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC 50 -#define MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC 51 -#define MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC 52 -#define MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC 53 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8188 */ diff --git a/include/dt-bindings/reset/mt8192-resets.h b/include/dt-bindings/reset/mt8192-resets.h deleted file mode 100644 index 12e2087c90a..00000000000 --- a/include/dt-bindings/reset/mt8192-resets.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Yong Liang <yong.liang@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 - -/* TOPRGU resets */ -#define MT8192_TOPRGU_MM_SW_RST 1 -#define MT8192_TOPRGU_MFG_SW_RST 2 -#define MT8192_TOPRGU_VENC_SW_RST 3 -#define MT8192_TOPRGU_VDEC_SW_RST 4 -#define MT8192_TOPRGU_IMG_SW_RST 5 -#define MT8192_TOPRGU_MD_SW_RST 7 -#define MT8192_TOPRGU_CONN_SW_RST 9 -#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 -#define MT8192_TOPRGU_IPU0_SW_RST 14 -#define MT8192_TOPRGU_IPU1_SW_RST 15 -#define MT8192_TOPRGU_AUDIO_SW_RST 17 -#define MT8192_TOPRGU_CAMSYS_SW_RST 18 -#define MT8192_TOPRGU_MJC_SW_RST 19 -#define MT8192_TOPRGU_C2K_S2_SW_RST 20 -#define MT8192_TOPRGU_C2K_SW_RST 21 -#define MT8192_TOPRGU_PERI_SW_RST 22 -#define MT8192_TOPRGU_PERI_AO_SW_RST 23 - -#define MT8192_TOPRGU_SW_RST_NUM 23 - -/* MMSYS resets */ -#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15 - -/* INFRA resets */ -#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0 -#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1 -#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2 -#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3 -#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */ diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h deleted file mode 100644 index e61660438d6..00000000000 --- a/include/dt-bindings/reset/mt8195-resets.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/ -/* - * Copyright (c) 2021 MediaTek Inc. - * Author: Christine Zhu <christine.zhu@mediatek.com> - */ - -#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 -#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 - -/* TOPRGU resets */ -#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 -#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 -#define MT8195_TOPRGU_APU_SW_RST 2 -#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 -#define MT8195_TOPRGU_MMSYS_SW_RST 7 -#define MT8195_TOPRGU_MFG_SW_RST 8 -#define MT8195_TOPRGU_VENC_SW_RST 9 -#define MT8195_TOPRGU_VDEC_SW_RST 10 -#define MT8195_TOPRGU_IMG_SW_RST 11 -#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 -#define MT8195_TOPRGU_AUDIO_SW_RST 14 -#define MT8195_TOPRGU_CAMSYS_SW_RST 15 -#define MT8195_TOPRGU_EDPTX_SW_RST 16 -#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 -#define MT8195_TOPRGU_DPTX_SW_RST 22 -#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 - -#define MT8195_TOPRGU_SW_RST_NUM 16 - -/* INFRA resets */ -#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0 -#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1 -#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2 -#define MT8195_INFRA_RST2_PCIE_P0_SWRST 3 -#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4 -#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5 - -/* VDOSYS1 */ -#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0 -#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1 -#define MT8195_VDOSYS1_SW0_RST_B_GALS 2 -#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3 -#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4 -#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5 -#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6 -#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7 -#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8 -#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9 -#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10 -#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11 -#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12 -#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13 -#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14 -#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15 -#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16 -#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17 -#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18 -#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19 -#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20 -#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21 -#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22 -#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23 -#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24 -#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25 -#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26 -#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27 -#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28 -#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29 -#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30 -#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49 -#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54 -#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */ diff --git a/include/dt-bindings/reset/nuvoton,ma35d1-reset.h b/include/dt-bindings/reset/nuvoton,ma35d1-reset.h deleted file mode 100644 index 2e99ee0d68c..00000000000 --- a/include/dt-bindings/reset/nuvoton,ma35d1-reset.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (C) 2023 Nuvoton Technologies. - * Author: Chi-Fen Li <cfli0@nuvoton.com> - * - * Device Tree binding constants for MA35D1 reset controller. - */ - -#ifndef __DT_BINDINGS_RESET_MA35D1_H -#define __DT_BINDINGS_RESET_MA35D1_H - -#define MA35D1_RESET_CHIP 0 -#define MA35D1_RESET_CA35CR0 1 -#define MA35D1_RESET_CA35CR1 2 -#define MA35D1_RESET_CM4 3 -#define MA35D1_RESET_PDMA0 4 -#define MA35D1_RESET_PDMA1 5 -#define MA35D1_RESET_PDMA2 6 -#define MA35D1_RESET_PDMA3 7 -#define MA35D1_RESET_DISP 8 -#define MA35D1_RESET_VCAP0 9 -#define MA35D1_RESET_VCAP1 10 -#define MA35D1_RESET_GFX 11 -#define MA35D1_RESET_VDEC 12 -#define MA35D1_RESET_WHC0 13 -#define MA35D1_RESET_WHC1 14 -#define MA35D1_RESET_GMAC0 15 -#define MA35D1_RESET_GMAC1 16 -#define MA35D1_RESET_HWSEM 17 -#define MA35D1_RESET_EBI 18 -#define MA35D1_RESET_HSUSBH0 19 -#define MA35D1_RESET_HSUSBH1 20 -#define MA35D1_RESET_HSUSBD 21 -#define MA35D1_RESET_USBHL 22 -#define MA35D1_RESET_SDH0 23 -#define MA35D1_RESET_SDH1 24 -#define MA35D1_RESET_NAND 25 -#define MA35D1_RESET_GPIO 26 -#define MA35D1_RESET_MCTLP 27 -#define MA35D1_RESET_MCTLC 28 -#define MA35D1_RESET_DDRPUB 29 -#define MA35D1_RESET_TMR0 30 -#define MA35D1_RESET_TMR1 31 -#define MA35D1_RESET_TMR2 32 -#define MA35D1_RESET_TMR3 33 -#define MA35D1_RESET_I2C0 34 -#define MA35D1_RESET_I2C1 35 -#define MA35D1_RESET_I2C2 36 -#define MA35D1_RESET_I2C3 37 -#define MA35D1_RESET_QSPI0 38 -#define MA35D1_RESET_SPI0 39 -#define MA35D1_RESET_SPI1 40 -#define MA35D1_RESET_SPI2 41 -#define MA35D1_RESET_UART0 42 -#define MA35D1_RESET_UART1 43 -#define MA35D1_RESET_UART2 44 -#define MA35D1_RESET_UART3 45 -#define MA35D1_RESET_UART4 46 -#define MA35D1_RESET_UART5 47 -#define MA35D1_RESET_UART6 48 -#define MA35D1_RESET_UART7 49 -#define MA35D1_RESET_CANFD0 50 -#define MA35D1_RESET_CANFD1 51 -#define MA35D1_RESET_EADC0 52 -#define MA35D1_RESET_I2S0 53 -#define MA35D1_RESET_SC0 54 -#define MA35D1_RESET_SC1 55 -#define MA35D1_RESET_QSPI1 56 -#define MA35D1_RESET_SPI3 57 -#define MA35D1_RESET_EPWM0 58 -#define MA35D1_RESET_EPWM1 59 -#define MA35D1_RESET_QEI0 60 -#define MA35D1_RESET_QEI1 61 -#define MA35D1_RESET_ECAP0 62 -#define MA35D1_RESET_ECAP1 63 -#define MA35D1_RESET_CANFD2 64 -#define MA35D1_RESET_ADC0 65 -#define MA35D1_RESET_TMR4 66 -#define MA35D1_RESET_TMR5 67 -#define MA35D1_RESET_TMR6 68 -#define MA35D1_RESET_TMR7 69 -#define MA35D1_RESET_TMR8 70 -#define MA35D1_RESET_TMR9 71 -#define MA35D1_RESET_TMR10 72 -#define MA35D1_RESET_TMR11 73 -#define MA35D1_RESET_UART8 74 -#define MA35D1_RESET_UART9 75 -#define MA35D1_RESET_UART10 76 -#define MA35D1_RESET_UART11 77 -#define MA35D1_RESET_UART12 78 -#define MA35D1_RESET_UART13 79 -#define MA35D1_RESET_UART14 80 -#define MA35D1_RESET_UART15 81 -#define MA35D1_RESET_UART16 82 -#define MA35D1_RESET_I2S1 83 -#define MA35D1_RESET_I2C4 84 -#define MA35D1_RESET_I2C5 85 -#define MA35D1_RESET_EPWM2 86 -#define MA35D1_RESET_ECAP2 87 -#define MA35D1_RESET_QEI2 88 -#define MA35D1_RESET_CANFD3 89 -#define MA35D1_RESET_KPI 90 -#define MA35D1_RESET_GIC 91 -#define MA35D1_RESET_SSMCC 92 -#define MA35D1_RESET_SSPCC 93 -#define MA35D1_RESET_COUNT 94 - -#endif diff --git a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h deleted file mode 100644 index df088e68a9b..00000000000 --- a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (c) 2019 Nuvoton Technology corporation. - -#ifndef _DT_BINDINGS_NPCM7XX_RESET_H -#define _DT_BINDINGS_NPCM7XX_RESET_H - -#define NPCM7XX_RESET_IPSRST1 0x20 -#define NPCM7XX_RESET_IPSRST2 0x24 -#define NPCM7XX_RESET_IPSRST3 0x34 - -/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */ -#define NPCM7XX_RESET_FIU3 1 -#define NPCM7XX_RESET_UDC1 5 -#define NPCM7XX_RESET_EMC1 6 -#define NPCM7XX_RESET_UART_2_3 7 -#define NPCM7XX_RESET_UDC2 8 -#define NPCM7XX_RESET_PECI 9 -#define NPCM7XX_RESET_AES 10 -#define NPCM7XX_RESET_UART_0_1 11 -#define NPCM7XX_RESET_MC 12 -#define NPCM7XX_RESET_SMB2 13 -#define NPCM7XX_RESET_SMB3 14 -#define NPCM7XX_RESET_SMB4 15 -#define NPCM7XX_RESET_SMB5 16 -#define NPCM7XX_RESET_PWM_M0 18 -#define NPCM7XX_RESET_TIMER_0_4 19 -#define NPCM7XX_RESET_TIMER_5_9 20 -#define NPCM7XX_RESET_EMC2 21 -#define NPCM7XX_RESET_UDC4 22 -#define NPCM7XX_RESET_UDC5 23 -#define NPCM7XX_RESET_UDC6 24 -#define NPCM7XX_RESET_UDC3 25 -#define NPCM7XX_RESET_ADC 27 -#define NPCM7XX_RESET_SMB6 28 -#define NPCM7XX_RESET_SMB7 29 -#define NPCM7XX_RESET_SMB0 30 -#define NPCM7XX_RESET_SMB1 31 - -/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */ -#define NPCM7XX_RESET_MFT0 0 -#define NPCM7XX_RESET_MFT1 1 -#define NPCM7XX_RESET_MFT2 2 -#define NPCM7XX_RESET_MFT3 3 -#define NPCM7XX_RESET_MFT4 4 -#define NPCM7XX_RESET_MFT5 5 -#define NPCM7XX_RESET_MFT6 6 -#define NPCM7XX_RESET_MFT7 7 -#define NPCM7XX_RESET_MMC 8 -#define NPCM7XX_RESET_SDHC 9 -#define NPCM7XX_RESET_GFX_SYS 10 -#define NPCM7XX_RESET_AHB_PCIBRG 11 -#define NPCM7XX_RESET_VDMA 12 -#define NPCM7XX_RESET_ECE 13 -#define NPCM7XX_RESET_VCD 14 -#define NPCM7XX_RESET_OTP 16 -#define NPCM7XX_RESET_SIOX1 18 -#define NPCM7XX_RESET_SIOX2 19 -#define NPCM7XX_RESET_3DES 21 -#define NPCM7XX_RESET_PSPI1 22 -#define NPCM7XX_RESET_PSPI2 23 -#define NPCM7XX_RESET_GMAC2 25 -#define NPCM7XX_RESET_USB_HOST 26 -#define NPCM7XX_RESET_GMAC1 28 -#define NPCM7XX_RESET_CP 31 - -/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */ -#define NPCM7XX_RESET_PWM_M1 0 -#define NPCM7XX_RESET_SMB12 1 -#define NPCM7XX_RESET_SPIX 2 -#define NPCM7XX_RESET_SMB13 3 -#define NPCM7XX_RESET_UDC0 4 -#define NPCM7XX_RESET_UDC7 5 -#define NPCM7XX_RESET_UDC8 6 -#define NPCM7XX_RESET_UDC9 7 -#define NPCM7XX_RESET_PCI_MAILBOX 9 -#define NPCM7XX_RESET_SMB14 12 -#define NPCM7XX_RESET_SHA 13 -#define NPCM7XX_RESET_SEC_ECC 14 -#define NPCM7XX_RESET_PCIE_RC 15 -#define NPCM7XX_RESET_TIMER_10_14 16 -#define NPCM7XX_RESET_RNG 17 -#define NPCM7XX_RESET_SMB15 18 -#define NPCM7XX_RESET_SMB8 19 -#define NPCM7XX_RESET_SMB9 20 -#define NPCM7XX_RESET_SMB10 21 -#define NPCM7XX_RESET_SMB11 22 -#define NPCM7XX_RESET_ESPI 23 -#define NPCM7XX_RESET_USB_PHY_1 24 -#define NPCM7XX_RESET_USB_PHY_2 25 - -#endif diff --git a/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h new file mode 100644 index 00000000000..a7567988c3f --- /dev/null +++ b/include/dt-bindings/reset/nuvoton,npcm8xx-reset.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2020 Nuvoton Technology corporation. + +#ifndef _DT_BINDINGS_NPCM8XX_RESET_H +#define _DT_BINDINGS_NPCM8XX_RESET_H + +#define NPCM8XX_RESET_IPSRST1 0x20 +#define NPCM8XX_RESET_IPSRST2 0x24 +#define NPCM8XX_RESET_IPSRST3 0x34 +#define NPCM8XX_RESET_IPSRST4 0x74 + +/* Reset lines on IP1 reset module (NPCM8XX_RESET_IPSRST1) */ +#define NPCM8XX_RESET_GDMA0 3 +#define NPCM8XX_RESET_UDC1 5 +#define NPCM8XX_RESET_GMAC3 6 +#define NPCM8XX_RESET_UART_2_3 7 +#define NPCM8XX_RESET_UDC2 8 +#define NPCM8XX_RESET_PECI 9 +#define NPCM8XX_RESET_AES 10 +#define NPCM8XX_RESET_UART_0_1 11 +#define NPCM8XX_RESET_MC 12 +#define NPCM8XX_RESET_SMB2 13 +#define NPCM8XX_RESET_SMB3 14 +#define NPCM8XX_RESET_SMB4 15 +#define NPCM8XX_RESET_SMB5 16 +#define NPCM8XX_RESET_PWM_M0 18 +#define NPCM8XX_RESET_TIMER_0_4 19 +#define NPCM8XX_RESET_TIMER_5_9 20 +#define NPCM8XX_RESET_GMAC4 21 +#define NPCM8XX_RESET_UDC4 22 +#define NPCM8XX_RESET_UDC5 23 +#define NPCM8XX_RESET_UDC6 24 +#define NPCM8XX_RESET_UDC3 25 +#define NPCM8XX_RESET_ADC 27 +#define NPCM8XX_RESET_SMB6 28 +#define NPCM8XX_RESET_SMB7 29 +#define NPCM8XX_RESET_SMB0 30 +#define NPCM8XX_RESET_SMB1 31 + +/* Reset lines on IP2 reset module (NPCM8XX_RESET_IPSRST2) */ +#define NPCM8XX_RESET_MFT0 0 +#define NPCM8XX_RESET_MFT1 1 +#define NPCM8XX_RESET_MFT2 2 +#define NPCM8XX_RESET_MFT3 3 +#define NPCM8XX_RESET_MFT4 4 +#define NPCM8XX_RESET_MFT5 5 +#define NPCM8XX_RESET_MFT6 6 +#define NPCM8XX_RESET_MFT7 7 +#define NPCM8XX_RESET_MMC 8 +#define NPCM8XX_RESET_GFX_SYS 10 +#define NPCM8XX_RESET_AHB_PCIBRG 11 +#define NPCM8XX_RESET_VDMA 12 +#define NPCM8XX_RESET_ECE 13 +#define NPCM8XX_RESET_VCD 14 +#define NPCM8XX_RESET_VIRUART1 16 +#define NPCM8XX_RESET_VIRUART2 17 +#define NPCM8XX_RESET_SIOX1 18 +#define NPCM8XX_RESET_SIOX2 19 +#define NPCM8XX_RESET_BT 20 +#define NPCM8XX_RESET_3DES 21 +#define NPCM8XX_RESET_PSPI2 23 +#define NPCM8XX_RESET_GMAC2 25 +#define NPCM8XX_RESET_USBH1 26 +#define NPCM8XX_RESET_GMAC1 28 +#define NPCM8XX_RESET_CP1 31 + +/* Reset lines on IP3 reset module (NPCM8XX_RESET_IPSRST3) */ +#define NPCM8XX_RESET_PWM_M1 0 +#define NPCM8XX_RESET_SMB12 1 +#define NPCM8XX_RESET_SPIX 2 +#define NPCM8XX_RESET_SMB13 3 +#define NPCM8XX_RESET_UDC0 4 +#define NPCM8XX_RESET_UDC7 5 +#define NPCM8XX_RESET_UDC8 6 +#define NPCM8XX_RESET_UDC9 7 +#define NPCM8XX_RESET_USBHUB 8 +#define NPCM8XX_RESET_PCI_MAILBOX 9 +#define NPCM8XX_RESET_GDMA1 10 +#define NPCM8XX_RESET_GDMA2 11 +#define NPCM8XX_RESET_SMB14 12 +#define NPCM8XX_RESET_SHA 13 +#define NPCM8XX_RESET_SEC_ECC 14 +#define NPCM8XX_RESET_PCIE_RC 15 +#define NPCM8XX_RESET_TIMER_10_14 16 +#define NPCM8XX_RESET_RNG 17 +#define NPCM8XX_RESET_SMB15 18 +#define NPCM8XX_RESET_SMB8 19 +#define NPCM8XX_RESET_SMB9 20 +#define NPCM8XX_RESET_SMB10 21 +#define NPCM8XX_RESET_SMB11 22 +#define NPCM8XX_RESET_ESPI 23 +#define NPCM8XX_RESET_USBPHY1 24 +#define NPCM8XX_RESET_USBPHY2 25 + +/* Reset lines on IP4 reset module (NPCM8XX_RESET_IPSRST4) */ +#define NPCM8XX_RESET_SMB16 0 +#define NPCM8XX_RESET_SMB17 1 +#define NPCM8XX_RESET_SMB18 2 +#define NPCM8XX_RESET_SMB19 3 +#define NPCM8XX_RESET_SMB20 4 +#define NPCM8XX_RESET_SMB21 5 +#define NPCM8XX_RESET_SMB22 6 +#define NPCM8XX_RESET_SMB23 7 +#define NPCM8XX_RESET_I3C0 8 +#define NPCM8XX_RESET_I3C1 9 +#define NPCM8XX_RESET_I3C2 10 +#define NPCM8XX_RESET_I3C3 11 +#define NPCM8XX_RESET_I3C4 12 +#define NPCM8XX_RESET_I3C5 13 +#define NPCM8XX_RESET_UART4 16 +#define NPCM8XX_RESET_UART5 17 +#define NPCM8XX_RESET_UART6 18 +#define NPCM8XX_RESET_PCIMBX2 19 +#define NPCM8XX_RESET_SMB24 22 +#define NPCM8XX_RESET_SMB25 23 +#define NPCM8XX_RESET_SMB26 24 +#define NPCM8XX_RESET_USBPHY3 25 +#define NPCM8XX_RESET_PCIRCPHY 27 +#define NPCM8XX_RESET_PWM_M2 28 +#define NPCM8XX_RESET_JTM1 29 +#define NPCM8XX_RESET_JTM2 30 +#define NPCM8XX_RESET_USBH2 31 + +#endif diff --git a/include/dt-bindings/reset/oxsemi,ox810se.h b/include/dt-bindings/reset/oxsemi,ox810se.h deleted file mode 100644 index e943187e652..00000000000 --- a/include/dt-bindings/reset/oxsemi,ox810se.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef DT_RESET_OXSEMI_OX810SE_H -#define DT_RESET_OXSEMI_OX810SE_H - -#define RESET_ARM 0 -#define RESET_COPRO 1 -/* Reserved 2 */ -/* Reserved 3 */ -#define RESET_USBHS 4 -#define RESET_USBHSPHY 5 -#define RESET_MAC 6 -#define RESET_PCI 7 -#define RESET_DMA 8 -#define RESET_DPE 9 -#define RESET_DDR 10 -#define RESET_SATA 11 -#define RESET_SATA_LINK 12 -#define RESET_SATA_PHY 13 - /* Reserved 14 */ -#define RESET_NAND 15 -#define RESET_GPIO 16 -#define RESET_UART1 17 -#define RESET_UART2 18 -#define RESET_MISC 19 -#define RESET_I2S 20 -#define RESET_AHB_MON 21 -#define RESET_UART3 22 -#define RESET_UART4 23 -#define RESET_SGDMA 24 -/* Reserved 25 */ -/* Reserved 26 */ -/* Reserved 27 */ -/* Reserved 28 */ -/* Reserved 29 */ -/* Reserved 30 */ -#define RESET_BUS 31 - -#endif /* DT_RESET_OXSEMI_OX810SE_H */ diff --git a/include/dt-bindings/reset/oxsemi,ox820.h b/include/dt-bindings/reset/oxsemi,ox820.h deleted file mode 100644 index 54b58e09c1c..00000000000 --- a/include/dt-bindings/reset/oxsemi,ox820.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef DT_RESET_OXSEMI_OX820_H -#define DT_RESET_OXSEMI_OX820_H - -#define RESET_SCU 0 -#define RESET_LEON 1 -#define RESET_ARM0 2 -#define RESET_ARM1 3 -#define RESET_USBHS 4 -#define RESET_USBPHYA 5 -#define RESET_MAC 6 -#define RESET_PCIEA 7 -#define RESET_SGDMA 8 -#define RESET_CIPHER 9 -#define RESET_DDR 10 -#define RESET_SATA 11 -#define RESET_SATA_LINK 12 -#define RESET_SATA_PHY 13 -#define RESET_PCIEPHY 14 -#define RESET_NAND 15 -#define RESET_GPIO 16 -#define RESET_UART1 17 -#define RESET_UART2 18 -#define RESET_MISC 19 -#define RESET_I2S 20 -#define RESET_SD 21 -#define RESET_MAC_2 22 -#define RESET_PCIEB 23 -#define RESET_VIDEO 24 -#define RESET_DDR_PHY 25 -#define RESET_USBPHYB 26 -#define RESET_USBDEV 27 -/* Reserved 29 */ -#define RESET_ARMDBG 29 -#define RESET_PLLA 30 -#define RESET_PLLB 31 - -#endif /* DT_RESET_OXSEMI_OX820_H */ diff --git a/include/dt-bindings/reset/pistachio-resets.h b/include/dt-bindings/reset/pistachio-resets.h deleted file mode 100644 index 5bb4dd0d637..00000000000 --- a/include/dt-bindings/reset/pistachio-resets.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the reset controller - * present in the Pistachio SoC - */ - -#ifndef _PISTACHIO_RESETS_H -#define _PISTACHIO_RESETS_H - -#define PISTACHIO_RESET_I2C0 0 -#define PISTACHIO_RESET_I2C1 1 -#define PISTACHIO_RESET_I2C2 2 -#define PISTACHIO_RESET_I2C3 3 -#define PISTACHIO_RESET_I2S_IN 4 -#define PISTACHIO_RESET_PRL_OUT 5 -#define PISTACHIO_RESET_SPDIF_OUT 6 -#define PISTACHIO_RESET_SPI 7 -#define PISTACHIO_RESET_PWM_PDM 8 -#define PISTACHIO_RESET_UART0 9 -#define PISTACHIO_RESET_UART1 10 -#define PISTACHIO_RESET_QSPI 11 -#define PISTACHIO_RESET_MDC 12 -#define PISTACHIO_RESET_SDHOST 13 -#define PISTACHIO_RESET_ETHERNET 14 -#define PISTACHIO_RESET_IR 15 -#define PISTACHIO_RESET_HASH 16 -#define PISTACHIO_RESET_TIMER 17 -#define PISTACHIO_RESET_I2S_OUT 18 -#define PISTACHIO_RESET_SPDIF_IN 19 -#define PISTACHIO_RESET_EVT 20 -#define PISTACHIO_RESET_USB_H 21 -#define PISTACHIO_RESET_USB_PR 22 -#define PISTACHIO_RESET_USB_PHY_PR 23 -#define PISTACHIO_RESET_USB_PHY_PON 24 -#define PISTACHIO_RESET_MAX 24 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-apq8084.h b/include/dt-bindings/reset/qcom,gcc-apq8084.h deleted file mode 100644 index e76be38342c..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-apq8084.h +++ /dev/null @@ -1,101 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_APQ_GCC_8084_H -#define _DT_BINDINGS_RESET_APQ_GCC_8084_H - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_QDSS_BCR 5 -#define GCC_USB_30_BCR 6 -#define GCC_USB3_PHY_BCR 7 -#define GCC_USB_HS_HSIC_BCR 8 -#define GCC_USB_HS_BCR 9 -#define GCC_USB2A_PHY_BCR 10 -#define GCC_USB2B_PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_PRNG_BCR 43 -#define GCC_BAM_DMA_BCR 44 -#define GCC_TSIF_BCR 45 -#define GCC_TCSR_BCR 46 -#define GCC_BOOT_ROM_BCR 47 -#define GCC_MSG_RAM_BCR 48 -#define GCC_TLMM_BCR 49 -#define GCC_MPM_BCR 50 -#define GCC_MPM_AHB_RESET 51 -#define GCC_MPM_NON_AHB_RESET 52 -#define GCC_SEC_CTRL_BCR 53 -#define GCC_SPMI_BCR 54 -#define GCC_SPDM_BCR 55 -#define GCC_CE1_BCR 56 -#define GCC_CE2_BCR 57 -#define GCC_BIMC_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 59 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 64 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 71 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 72 -#define GCC_DEHR_BCR 73 -#define GCC_RBCPR_BCR 74 -#define GCC_MSS_RESTART 75 -#define GCC_LPASS_RESTART 76 -#define GCC_WCSS_RESTART 77 -#define GCC_VENUS_RESTART 78 -#define GCC_COPSS_SMMU_BCR 79 -#define GCC_SPSS_BCR 80 -#define GCC_PCIE_0_BCR 81 -#define GCC_PCIE_0_PHY_BCR 82 -#define GCC_PCIE_1_BCR 83 -#define GCC_PCIE_1_PHY_BCR 84 -#define GCC_USB_30_SEC_BCR 85 -#define GCC_USB3_SEC_PHY_BCR 86 -#define GCC_SATA_BCR 87 -#define GCC_CE3_BCR 88 -#define GCC_UFS_BCR 89 -#define GCC_USB30_PHY_COM_BCR 90 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h deleted file mode 100644 index 8f03c92fc23..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-ipq5018.h +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H -#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H - -#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0 -#define GCC_BLSP1_BCR 1 -#define GCC_BLSP1_QUP1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_QUP3_BCR 4 -#define GCC_BLSP1_UART1_BCR 5 -#define GCC_BLSP1_UART2_BCR 6 -#define GCC_BOOT_ROM_BCR 7 -#define GCC_BTSS_BCR 8 -#define GCC_CMN_BLK_BCR 9 -#define GCC_CMN_LDO_BCR 10 -#define GCC_CE_BCR 11 -#define GCC_CRYPTO_BCR 12 -#define GCC_DCC_BCR 13 -#define GCC_DCD_BCR 14 -#define GCC_DDRSS_BCR 15 -#define GCC_EDPD_BCR 16 -#define GCC_GEPHY_BCR 17 -#define GCC_GEPHY_MDC_SW_ARES 18 -#define GCC_GEPHY_DSP_HW_ARES 19 -#define GCC_GEPHY_RX_ARES 20 -#define GCC_GEPHY_TX_ARES 21 -#define GCC_GMAC0_BCR 22 -#define GCC_GMAC0_CFG_ARES 23 -#define GCC_GMAC0_SYS_ARES 24 -#define GCC_GMAC1_BCR 25 -#define GCC_GMAC1_CFG_ARES 26 -#define GCC_GMAC1_SYS_ARES 27 -#define GCC_IMEM_BCR 28 -#define GCC_LPASS_BCR 29 -#define GCC_MDIO0_BCR 30 -#define GCC_MDIO1_BCR 31 -#define GCC_MPM_BCR 32 -#define GCC_PCIE0_BCR 33 -#define GCC_PCIE0_LINK_DOWN_BCR 34 -#define GCC_PCIE0_PHY_BCR 35 -#define GCC_PCIE0PHY_PHY_BCR 36 -#define GCC_PCIE0_PIPE_ARES 37 -#define GCC_PCIE0_SLEEP_ARES 38 -#define GCC_PCIE0_CORE_STICKY_ARES 39 -#define GCC_PCIE0_AXI_MASTER_ARES 40 -#define GCC_PCIE0_AXI_SLAVE_ARES 41 -#define GCC_PCIE0_AHB_ARES 42 -#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43 -#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44 -#define GCC_PCIE1_BCR 45 -#define GCC_PCIE1_LINK_DOWN_BCR 46 -#define GCC_PCIE1_PHY_BCR 47 -#define GCC_PCIE1PHY_PHY_BCR 48 -#define GCC_PCIE1_PIPE_ARES 49 -#define GCC_PCIE1_SLEEP_ARES 50 -#define GCC_PCIE1_CORE_STICKY_ARES 51 -#define GCC_PCIE1_AXI_MASTER_ARES 52 -#define GCC_PCIE1_AXI_SLAVE_ARES 53 -#define GCC_PCIE1_AHB_ARES 54 -#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55 -#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56 -#define GCC_PCNOC_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 -#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68 -#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69 -#define GCC_PRNG_BCR 70 -#define GCC_Q6SS_DBG_ARES 71 -#define GCC_Q6_AHB_S_ARES 72 -#define GCC_Q6_AHB_ARES 73 -#define GCC_Q6_AXIM2_ARES 74 -#define GCC_Q6_AXIM_ARES 75 -#define GCC_Q6_AXIS_ARES 76 -#define GCC_QDSS_BCR 77 -#define GCC_QPIC_BCR 78 -#define GCC_QUSB2_0_PHY_BCR 79 -#define GCC_SDCC1_BCR 80 -#define GCC_SEC_CTRL_BCR 81 -#define GCC_SPDM_BCR 82 -#define GCC_SYSTEM_NOC_BCR 83 -#define GCC_TCSR_BCR 84 -#define GCC_TLMM_BCR 85 -#define GCC_UBI0_AXI_ARES 86 -#define GCC_UBI0_AHB_ARES 87 -#define GCC_UBI0_NC_AXI_ARES 88 -#define GCC_UBI0_DBG_ARES 89 -#define GCC_UBI0_UTCM_ARES 90 -#define GCC_UBI0_CORE_ARES 91 -#define GCC_UBI32_BCR 92 -#define GCC_UNIPHY_BCR 93 -#define GCC_UNIPHY_AHB_ARES 94 -#define GCC_UNIPHY_SYS_ARES 95 -#define GCC_UNIPHY_RX_ARES 96 -#define GCC_UNIPHY_TX_ARES 97 -#define GCC_USB0_BCR 98 -#define GCC_USB0_PHY_BCR 99 -#define GCC_WCSS_BCR 100 -#define GCC_WCSS_DBG_ARES 101 -#define GCC_WCSS_ECAHB_ARES 102 -#define GCC_WCSS_ACMT_ARES 103 -#define GCC_WCSS_DBG_BDG_ARES 104 -#define GCC_WCSS_AHB_S_ARES 105 -#define GCC_WCSS_AXI_M_ARES 106 -#define GCC_WCSS_AXI_S_ARES 107 -#define GCC_WCSS_Q6_BCR 108 -#define GCC_WCSSAON_RESET 109 -#define GCC_UNIPHY_SOFT_RESET 110 -#define GCC_GEPHY_MISC_ARES 111 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-ipq6018.h b/include/dt-bindings/reset/qcom,gcc-ipq6018.h deleted file mode 100644 index 02a220ad010..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-ipq6018.h +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_GCC_6018_H -#define _DT_BINDINGS_RESET_IPQ_GCC_6018_H - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_UART3_BCR 6 -#define GCC_BLSP1_QUP4_BCR 7 -#define GCC_BLSP1_UART4_BCR 8 -#define GCC_BLSP1_QUP5_BCR 9 -#define GCC_BLSP1_UART5_BCR 10 -#define GCC_BLSP1_QUP6_BCR 11 -#define GCC_BLSP1_UART6_BCR 12 -#define GCC_IMEM_BCR 13 -#define GCC_SMMU_BCR 14 -#define GCC_APSS_TCU_BCR 15 -#define GCC_SMMU_XPU_BCR 16 -#define GCC_PCNOC_TBU_BCR 17 -#define GCC_SMMU_CFG_BCR 18 -#define GCC_PRNG_BCR 19 -#define GCC_BOOT_ROM_BCR 20 -#define GCC_CRYPTO_BCR 21 -#define GCC_WCSS_BCR 22 -#define GCC_WCSS_Q6_BCR 23 -#define GCC_NSS_BCR 24 -#define GCC_SEC_CTRL_BCR 25 -#define GCC_DDRSS_BCR 26 -#define GCC_SYSTEM_NOC_BCR 27 -#define GCC_PCNOC_BCR 28 -#define GCC_TCSR_BCR 29 -#define GCC_QDSS_BCR 30 -#define GCC_DCD_BCR 31 -#define GCC_MSG_RAM_BCR 32 -#define GCC_MPM_BCR 33 -#define GCC_SPDM_BCR 34 -#define GCC_RBCPR_BCR 35 -#define GCC_RBCPR_MX_BCR 36 -#define GCC_TLMM_BCR 37 -#define GCC_RBCPR_WCSS_BCR 38 -#define GCC_USB0_PHY_BCR 39 -#define GCC_USB3PHY_0_PHY_BCR 40 -#define GCC_USB0_BCR 41 -#define GCC_USB1_BCR 42 -#define GCC_QUSB2_0_PHY_BCR 43 -#define GCC_QUSB2_1_PHY_BCR 44 -#define GCC_SDCC1_BCR 45 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 46 -#define GCC_SNOC_BUS_TIMEOUT1_BCR 47 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 48 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 49 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 50 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 51 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 52 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 53 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 54 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 55 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 56 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 58 -#define GCC_UNIPHY0_BCR 59 -#define GCC_UNIPHY1_BCR 60 -#define GCC_CMN_12GPLL_BCR 61 -#define GCC_QPIC_BCR 62 -#define GCC_MDIO_BCR 63 -#define GCC_WCSS_CORE_TBU_BCR 64 -#define GCC_WCSS_Q6_TBU_BCR 65 -#define GCC_USB0_TBU_BCR 66 -#define GCC_PCIE0_TBU_BCR 67 -#define GCC_PCIE0_BCR 68 -#define GCC_PCIE0_PHY_BCR 69 -#define GCC_PCIE0PHY_PHY_BCR 70 -#define GCC_PCIE0_LINK_DOWN_BCR 71 -#define GCC_DCC_BCR 72 -#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 73 -#define GCC_SMMU_CATS_BCR 74 -#define GCC_UBI0_AXI_ARES 75 -#define GCC_UBI0_AHB_ARES 76 -#define GCC_UBI0_NC_AXI_ARES 77 -#define GCC_UBI0_DBG_ARES 78 -#define GCC_UBI0_CORE_CLAMP_ENABLE 79 -#define GCC_UBI0_CLKRST_CLAMP_ENABLE 80 -#define GCC_UBI0_UTCM_ARES 81 -#define GCC_NSS_CFG_ARES 82 -#define GCC_NSS_NOC_ARES 83 -#define GCC_NSS_CRYPTO_ARES 84 -#define GCC_NSS_CSR_ARES 85 -#define GCC_NSS_CE_APB_ARES 86 -#define GCC_NSS_CE_AXI_ARES 87 -#define GCC_NSSNOC_CE_APB_ARES 88 -#define GCC_NSSNOC_CE_AXI_ARES 89 -#define GCC_NSSNOC_UBI0_AHB_ARES 90 -#define GCC_NSSNOC_SNOC_ARES 91 -#define GCC_NSSNOC_CRYPTO_ARES 92 -#define GCC_NSSNOC_ATB_ARES 93 -#define GCC_NSSNOC_QOSGEN_REF_ARES 94 -#define GCC_NSSNOC_TIMEOUT_REF_ARES 95 -#define GCC_PCIE0_PIPE_ARES 96 -#define GCC_PCIE0_SLEEP_ARES 97 -#define GCC_PCIE0_CORE_STICKY_ARES 98 -#define GCC_PCIE0_AXI_MASTER_ARES 99 -#define GCC_PCIE0_AXI_SLAVE_ARES 100 -#define GCC_PCIE0_AHB_ARES 101 -#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 102 -#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 103 -#define GCC_PPE_FULL_RESET 104 -#define GCC_UNIPHY0_SOFT_RESET 105 -#define GCC_UNIPHY0_XPCS_RESET 106 -#define GCC_UNIPHY1_SOFT_RESET 107 -#define GCC_UNIPHY1_XPCS_RESET 108 -#define GCC_EDMA_HW_RESET 109 -#define GCC_ADSS_BCR 110 -#define GCC_NSS_NOC_TBU_BCR 111 -#define GCC_NSSPORT1_RESET 112 -#define GCC_NSSPORT2_RESET 113 -#define GCC_NSSPORT3_RESET 114 -#define GCC_NSSPORT4_RESET 115 -#define GCC_NSSPORT5_RESET 116 -#define GCC_UNIPHY0_PORT1_ARES 117 -#define GCC_UNIPHY0_PORT2_ARES 118 -#define GCC_UNIPHY0_PORT3_ARES 119 -#define GCC_UNIPHY0_PORT4_ARES 120 -#define GCC_UNIPHY0_PORT5_ARES 121 -#define GCC_UNIPHY0_PORT_4_5_RESET 122 -#define GCC_UNIPHY0_PORT_4_RESET 123 -#define GCC_LPASS_BCR 124 -#define GCC_UBI32_TBU_BCR 125 -#define GCC_LPASS_TBU_BCR 126 -#define GCC_WCSSAON_RESET 127 -#define GCC_LPASS_Q6_AXIM_ARES 128 -#define GCC_LPASS_Q6SS_TSCTR_1TO2_ARES 129 -#define GCC_LPASS_Q6SS_TRIG_ARES 130 -#define GCC_LPASS_Q6_ATBM_AT_ARES 131 -#define GCC_LPASS_Q6_PCLKDBG_ARES 132 -#define GCC_LPASS_CORE_AXIM_ARES 133 -#define GCC_LPASS_SNOC_CFG_ARES 134 -#define GCC_WCSS_DBG_ARES 135 -#define GCC_WCSS_ECAHB_ARES 136 -#define GCC_WCSS_ACMT_ARES 137 -#define GCC_WCSS_DBG_BDG_ARES 138 -#define GCC_WCSS_AHB_S_ARES 139 -#define GCC_WCSS_AXI_M_ARES 140 -#define GCC_Q6SS_DBG_ARES 141 -#define GCC_Q6_AHB_S_ARES 142 -#define GCC_Q6_AHB_ARES 143 -#define GCC_Q6_AXIM2_ARES 144 -#define GCC_Q6_AXIM_ARES 145 -#define GCC_UBI0_CORE_ARES 146 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h deleted file mode 100644 index 020c9cf1875..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_806X_H -#define _DT_BINDINGS_RESET_IPQ_806X_H - -#define QDSS_STM_RESET 0 -#define AFAB_SMPSS_S_RESET 1 -#define AFAB_SMPSS_M1_RESET 2 -#define AFAB_SMPSS_M0_RESET 3 -#define AFAB_EBI1_CH0_RESET 4 -#define AFAB_EBI1_CH1_RESET 5 -#define SFAB_ADM0_M0_RESET 6 -#define SFAB_ADM0_M1_RESET 7 -#define SFAB_ADM0_M2_RESET 8 -#define ADM0_C2_RESET 9 -#define ADM0_C1_RESET 10 -#define ADM0_C0_RESET 11 -#define ADM0_PBUS_RESET 12 -#define ADM0_RESET 13 -#define QDSS_CLKS_SW_RESET 14 -#define QDSS_POR_RESET 15 -#define QDSS_TSCTR_RESET 16 -#define QDSS_HRESET_RESET 17 -#define QDSS_AXI_RESET 18 -#define QDSS_DBG_RESET 19 -#define SFAB_PCIE_M_RESET 20 -#define SFAB_PCIE_S_RESET 21 -#define PCIE_EXT_RESET 22 -#define PCIE_PHY_RESET 23 -#define PCIE_PCI_RESET 24 -#define PCIE_POR_RESET 25 -#define PCIE_HCLK_RESET 26 -#define PCIE_ACLK_RESET 27 -#define SFAB_LPASS_RESET 28 -#define SFAB_AFAB_M_RESET 29 -#define AFAB_SFAB_M0_RESET 30 -#define AFAB_SFAB_M1_RESET 31 -#define SFAB_SATA_S_RESET 32 -#define SFAB_DFAB_M_RESET 33 -#define DFAB_SFAB_M_RESET 34 -#define DFAB_SWAY0_RESET 35 -#define DFAB_SWAY1_RESET 36 -#define DFAB_ARB0_RESET 37 -#define DFAB_ARB1_RESET 38 -#define PPSS_PROC_RESET 39 -#define PPSS_RESET 40 -#define DMA_BAM_RESET 41 -#define SPS_TIC_H_RESET 42 -#define SFAB_CFPB_M_RESET 43 -#define SFAB_CFPB_S_RESET 44 -#define TSIF_H_RESET 45 -#define CE1_H_RESET 46 -#define CE1_CORE_RESET 47 -#define CE1_SLEEP_RESET 48 -#define CE2_H_RESET 49 -#define CE2_CORE_RESET 50 -#define SFAB_SFPB_M_RESET 51 -#define SFAB_SFPB_S_RESET 52 -#define RPM_PROC_RESET 53 -#define PMIC_SSBI2_RESET 54 -#define SDC1_RESET 55 -#define SDC2_RESET 56 -#define SDC3_RESET 57 -#define SDC4_RESET 58 -#define USB_HS1_RESET 59 -#define USB_HSIC_RESET 60 -#define USB_FS1_XCVR_RESET 61 -#define USB_FS1_RESET 62 -#define GSBI1_RESET 63 -#define GSBI2_RESET 64 -#define GSBI3_RESET 65 -#define GSBI4_RESET 66 -#define GSBI5_RESET 67 -#define GSBI6_RESET 68 -#define GSBI7_RESET 69 -#define SPDM_RESET 70 -#define SEC_CTRL_RESET 71 -#define TLMM_H_RESET 72 -#define SFAB_SATA_M_RESET 73 -#define SATA_RESET 74 -#define TSSC_RESET 75 -#define PDM_RESET 76 -#define MPM_H_RESET 77 -#define MPM_RESET 78 -#define SFAB_SMPSS_S_RESET 79 -#define PRNG_RESET 80 -#define SFAB_CE3_M_RESET 81 -#define SFAB_CE3_S_RESET 82 -#define CE3_SLEEP_RESET 83 -#define PCIE_1_M_RESET 84 -#define PCIE_1_S_RESET 85 -#define PCIE_1_EXT_RESET 86 -#define PCIE_1_PHY_RESET 87 -#define PCIE_1_PCI_RESET 88 -#define PCIE_1_POR_RESET 89 -#define PCIE_1_HCLK_RESET 90 -#define PCIE_1_ACLK_RESET 91 -#define PCIE_2_M_RESET 92 -#define PCIE_2_S_RESET 93 -#define PCIE_2_EXT_RESET 94 -#define PCIE_2_PHY_RESET 95 -#define PCIE_2_PCI_RESET 96 -#define PCIE_2_POR_RESET 97 -#define PCIE_2_HCLK_RESET 98 -#define PCIE_2_ACLK_RESET 99 -#define SFAB_USB30_S_RESET 100 -#define SFAB_USB30_M_RESET 101 -#define USB30_0_PORT2_HS_PHY_RESET 102 -#define USB30_0_MASTER_RESET 103 -#define USB30_0_SLEEP_RESET 104 -#define USB30_0_UTMI_PHY_RESET 105 -#define USB30_0_POWERON_RESET 106 -#define USB30_0_PHY_RESET 107 -#define USB30_1_MASTER_RESET 108 -#define USB30_1_SLEEP_RESET 109 -#define USB30_1_UTMI_PHY_RESET 110 -#define USB30_1_POWERON_RESET 111 -#define USB30_1_PHY_RESET 112 -#define NSSFB0_RESET 113 -#define NSSFB1_RESET 114 -#define UBI32_CORE1_CLKRST_CLAMP_RESET 115 -#define UBI32_CORE1_CLAMP_RESET 116 -#define UBI32_CORE1_AHB_RESET 117 -#define UBI32_CORE1_AXI_RESET 118 -#define UBI32_CORE2_CLKRST_CLAMP_RESET 119 -#define UBI32_CORE2_CLAMP_RESET 120 -#define UBI32_CORE2_AHB_RESET 121 -#define UBI32_CORE2_AXI_RESET 122 -#define GMAC_CORE1_RESET 123 -#define GMAC_CORE2_RESET 124 -#define GMAC_CORE3_RESET 125 -#define GMAC_CORE4_RESET 126 -#define GMAC_AHB_RESET 127 -#define NSS_CH0_RST_RX_CLK_N_RESET 128 -#define NSS_CH0_RST_TX_CLK_N_RESET 129 -#define NSS_CH0_RST_RX_125M_N_RESET 130 -#define NSS_CH0_HW_RST_RX_125M_N_RESET 131 -#define NSS_CH0_RST_TX_125M_N_RESET 132 -#define NSS_CH1_RST_RX_CLK_N_RESET 133 -#define NSS_CH1_RST_TX_CLK_N_RESET 134 -#define NSS_CH1_RST_RX_125M_N_RESET 135 -#define NSS_CH1_HW_RST_RX_125M_N_RESET 136 -#define NSS_CH1_RST_TX_125M_N_RESET 137 -#define NSS_CH2_RST_RX_CLK_N_RESET 138 -#define NSS_CH2_RST_TX_CLK_N_RESET 139 -#define NSS_CH2_RST_RX_125M_N_RESET 140 -#define NSS_CH2_HW_RST_RX_125M_N_RESET 141 -#define NSS_CH2_RST_TX_125M_N_RESET 142 -#define NSS_CH3_RST_RX_CLK_N_RESET 143 -#define NSS_CH3_RST_TX_CLK_N_RESET 144 -#define NSS_CH3_RST_RX_125M_N_RESET 145 -#define NSS_CH3_HW_RST_RX_125M_N_RESET 146 -#define NSS_CH3_RST_TX_125M_N_RESET 147 -#define NSS_RST_RX_250M_125M_N_RESET 148 -#define NSS_RST_TX_250M_125M_N_RESET 149 -#define NSS_QSGMII_TXPI_RST_N_RESET 150 -#define NSS_QSGMII_CDR_RST_N_RESET 151 -#define NSS_SGMII2_CDR_RST_N_RESET 152 -#define NSS_SGMII3_CDR_RST_N_RESET 153 -#define NSS_CAL_PRBS_RST_N_RESET 154 -#define NSS_LCKDT_RST_N_RESET 155 -#define NSS_SRDS_N_RESET 156 -#define CRYPTO_ENG1_RESET 157 -#define CRYPTO_ENG2_RESET 158 -#define CRYPTO_ENG3_RESET 159 -#define CRYPTO_ENG4_RESET 160 -#define CRYPTO_AHB_RESET 161 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-mdm9615.h b/include/dt-bindings/reset/qcom,gcc-mdm9615.h deleted file mode 100644 index 5faf02d7e28..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-mdm9615.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - * Copyright (c) BayLibre, SAS. - * Author : Neil Armstrong <narmstrong@baylibre.com> - */ - -#ifndef _DT_BINDINGS_RESET_GCC_MDM9615_H -#define _DT_BINDINGS_RESET_GCC_MDM9615_H - -#define SFAB_MSS_Q6_SW_RESET 0 -#define SFAB_MSS_Q6_FW_RESET 1 -#define QDSS_STM_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_CH0_RESET 6 -#define AFAB_EBI1_CH1_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define QDSS_CLKS_SW_RESET 16 -#define QDSS_POR_RESET 17 -#define QDSS_TSCTR_RESET 18 -#define QDSS_HRESET_RESET 19 -#define QDSS_AXI_RESET 20 -#define QDSS_DBG_RESET 21 -#define PCIE_A_RESET 22 -#define PCIE_AUX_RESET 23 -#define PCIE_H_RESET 24 -#define SFAB_PCIE_M_RESET 25 -#define SFAB_PCIE_S_RESET 26 -#define SFAB_MSS_M_RESET 27 -#define SFAB_USB3_M_RESET 28 -#define SFAB_RIVA_M_RESET 29 -#define SFAB_LPASS_RESET 30 -#define SFAB_AFAB_M_RESET 31 -#define AFAB_SFAB_M0_RESET 32 -#define AFAB_SFAB_M1_RESET 33 -#define SFAB_SATA_S_RESET 34 -#define SFAB_DFAB_M_RESET 35 -#define DFAB_SFAB_M_RESET 36 -#define DFAB_SWAY0_RESET 37 -#define DFAB_SWAY1_RESET 38 -#define DFAB_ARB0_RESET 39 -#define DFAB_ARB1_RESET 40 -#define PPSS_PROC_RESET 41 -#define PPSS_RESET 42 -#define DMA_BAM_RESET 43 -#define SPS_TIC_H_RESET 44 -#define SLIMBUS_H_RESET 45 -#define SFAB_CFPB_M_RESET 46 -#define SFAB_CFPB_S_RESET 47 -#define TSIF_H_RESET 48 -#define CE1_H_RESET 49 -#define CE1_CORE_RESET 50 -#define CE1_SLEEP_RESET 51 -#define CE2_H_RESET 52 -#define CE2_CORE_RESET 53 -#define SFAB_SFPB_M_RESET 54 -#define SFAB_SFPB_S_RESET 55 -#define RPM_PROC_RESET 56 -#define PMIC_SSBI2_RESET 57 -#define SDC1_RESET 58 -#define SDC2_RESET 59 -#define SDC3_RESET 60 -#define SDC4_RESET 61 -#define SDC5_RESET 62 -#define DFAB_A2_RESET 63 -#define USB_HS1_RESET 64 -#define USB_HSIC_RESET 65 -#define USB_FS1_XCVR_RESET 66 -#define USB_FS1_RESET 67 -#define USB_FS2_XCVR_RESET 68 -#define USB_FS2_RESET 69 -#define GSBI1_RESET 70 -#define GSBI2_RESET 71 -#define GSBI3_RESET 72 -#define GSBI4_RESET 73 -#define GSBI5_RESET 74 -#define GSBI6_RESET 75 -#define GSBI7_RESET 76 -#define GSBI8_RESET 77 -#define GSBI9_RESET 78 -#define GSBI10_RESET 79 -#define GSBI11_RESET 80 -#define GSBI12_RESET 81 -#define SPDM_RESET 82 -#define TLMM_H_RESET 83 -#define SFAB_MSS_S_RESET 84 -#define MSS_SLP_RESET 85 -#define MSS_Q6SW_JTAG_RESET 86 -#define MSS_Q6FW_JTAG_RESET 87 -#define MSS_RESET 88 -#define SATA_H_RESET 89 -#define SATA_RXOOB_RESE 90 -#define SATA_PMALIVE_RESET 91 -#define SATA_SFAB_M_RESET 92 -#define TSSC_RESET 93 -#define PDM_RESET 94 -#define MPM_H_RESET 95 -#define MPM_RESET 96 -#define SFAB_SMPSS_S_RESET 97 -#define PRNG_RESET 98 -#define RIVA_RESET 99 -#define USB_HS3_RESET 100 -#define USB_HS4_RESET 101 -#define CE3_RESET 102 -#define PCIE_EXT_PCI_RESET 103 -#define PCIE_PHY_RESET 104 -#define PCIE_PCI_RESET 105 -#define PCIE_POR_RESET 106 -#define PCIE_HCLK_RESET 107 -#define PCIE_ACLK_RESET 108 -#define CE3_H_RESET 109 -#define SFAB_CE3_M_RESET 110 -#define SFAB_CE3_S_RESET 111 -#define SATA_RESET 112 -#define CE3_SLEEP_RESET 113 -#define GSS_SLP_RESET 114 -#define GSS_RESET 115 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8660.h b/include/dt-bindings/reset/qcom,gcc-msm8660.h deleted file mode 100644 index f6d2b3cbe7b..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-msm8660.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H -#define _DT_BINDINGS_RESET_MSM_GCC_8660_H - -#define AFAB_CORE_RESET 0 -#define SCSS_SYS_RESET 1 -#define SCSS_SYS_POR_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_S_RESET 6 -#define SFAB_CORE_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define SFAB_ADM1_M0_RESET 16 -#define SFAB_ADM1_M1_RESET 17 -#define SFAB_ADM1_M2_RESET 18 -#define MMFAB_ADM1_M3_RESET 19 -#define ADM1_C3_RESET 20 -#define ADM1_C2_RESET 21 -#define ADM1_C1_RESET 22 -#define ADM1_C0_RESET 23 -#define ADM1_PBUS_RESET 24 -#define ADM1_RESET 25 -#define IMEM0_RESET 26 -#define SFAB_LPASS_Q6_RESET 27 -#define SFAB_AFAB_M_RESET 28 -#define AFAB_SFAB_M0_RESET 29 -#define AFAB_SFAB_M1_RESET 30 -#define DFAB_CORE_RESET 31 -#define SFAB_DFAB_M_RESET 32 -#define DFAB_SFAB_M_RESET 33 -#define DFAB_SWAY0_RESET 34 -#define DFAB_SWAY1_RESET 35 -#define DFAB_ARB0_RESET 36 -#define DFAB_ARB1_RESET 37 -#define PPSS_PROC_RESET 38 -#define PPSS_RESET 39 -#define PMEM_RESET 40 -#define DMA_BAM_RESET 41 -#define SIC_RESET 42 -#define SPS_TIC_RESET 43 -#define CFBP0_RESET 44 -#define CFBP1_RESET 45 -#define CFBP2_RESET 46 -#define EBI2_RESET 47 -#define SFAB_CFPB_M_RESET 48 -#define CFPB_MASTER_RESET 49 -#define SFAB_CFPB_S_RESET 50 -#define CFPB_SPLITTER_RESET 51 -#define TSIF_RESET 52 -#define CE1_RESET 53 -#define CE2_RESET 54 -#define SFAB_SFPB_M_RESET 55 -#define SFAB_SFPB_S_RESET 56 -#define RPM_PROC_RESET 57 -#define RPM_BUS_RESET 58 -#define RPM_MSG_RAM_RESET 59 -#define PMIC_ARB0_RESET 60 -#define PMIC_ARB1_RESET 61 -#define PMIC_SSBI2_RESET 62 -#define SDC1_RESET 63 -#define SDC2_RESET 64 -#define SDC3_RESET 65 -#define SDC4_RESET 66 -#define SDC5_RESET 67 -#define USB_HS1_RESET 68 -#define USB_HS2_XCVR_RESET 69 -#define USB_HS2_RESET 70 -#define USB_FS1_XCVR_RESET 71 -#define USB_FS1_RESET 72 -#define USB_FS2_XCVR_RESET 73 -#define USB_FS2_RESET 74 -#define GSBI1_RESET 75 -#define GSBI2_RESET 76 -#define GSBI3_RESET 77 -#define GSBI4_RESET 78 -#define GSBI5_RESET 79 -#define GSBI6_RESET 80 -#define GSBI7_RESET 81 -#define GSBI8_RESET 82 -#define GSBI9_RESET 83 -#define GSBI10_RESET 84 -#define GSBI11_RESET 85 -#define GSBI12_RESET 86 -#define SPDM_RESET 87 -#define SEC_CTRL_RESET 88 -#define TLMM_H_RESET 89 -#define TLMM_RESET 90 -#define MARRM_PWRON_RESET 91 -#define MARM_RESET 92 -#define MAHB1_RESET 93 -#define SFAB_MSS_S_RESET 94 -#define MAHB2_RESET 95 -#define MODEM_SW_AHB_RESET 96 -#define MODEM_RESET 97 -#define SFAB_MSS_MDM1_RESET 98 -#define SFAB_MSS_MDM0_RESET 99 -#define MSS_SLP_RESET 100 -#define MSS_MARM_SAW_RESET 101 -#define MSS_WDOG_RESET 102 -#define TSSC_RESET 103 -#define PDM_RESET 104 -#define SCSS_CORE0_RESET 105 -#define SCSS_CORE0_POR_RESET 106 -#define SCSS_CORE1_RESET 107 -#define SCSS_CORE1_POR_RESET 108 -#define MPM_RESET 109 -#define EBI1_1X_DIV_RESET 110 -#define EBI1_RESET 111 -#define SFAB_SMPSS_S_RESET 112 -#define USB_PHY0_RESET 113 -#define USB_PHY1_RESET 114 -#define PRNG_RESET 115 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8916.h b/include/dt-bindings/reset/qcom,gcc-msm8916.h deleted file mode 100644 index 1f9be10872d..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-msm8916.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2015 Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8916_H -#define _DT_BINDINGS_RESET_MSM_GCC_8916_H - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_QUP4_BCR 6 -#define GCC_BLSP1_QUP5_BCR 7 -#define GCC_BLSP1_QUP6_BCR 8 -#define GCC_IMEM_BCR 9 -#define GCC_SMMU_BCR 10 -#define GCC_APSS_TCU_BCR 11 -#define GCC_SMMU_XPU_BCR 12 -#define GCC_PCNOC_TBU_BCR 13 -#define GCC_PRNG_BCR 14 -#define GCC_BOOT_ROM_BCR 15 -#define GCC_CRYPTO_BCR 16 -#define GCC_SEC_CTRL_BCR 17 -#define GCC_AUDIO_CORE_BCR 18 -#define GCC_ULT_AUDIO_BCR 19 -#define GCC_DEHR_BCR 20 -#define GCC_SYSTEM_NOC_BCR 21 -#define GCC_PCNOC_BCR 22 -#define GCC_TCSR_BCR 23 -#define GCC_QDSS_BCR 24 -#define GCC_DCD_BCR 25 -#define GCC_MSG_RAM_BCR 26 -#define GCC_MPM_BCR 27 -#define GCC_SPMI_BCR 28 -#define GCC_SPDM_BCR 29 -#define GCC_MM_SPDM_BCR 30 -#define GCC_BIMC_BCR 31 -#define GCC_RBCPR_BCR 32 -#define GCC_TLMM_BCR 33 -#define GCC_USB_HS_BCR 34 -#define GCC_USB2A_PHY_BCR 35 -#define GCC_SDCC1_BCR 36 -#define GCC_SDCC2_BCR 37 -#define GCC_PDM_BCR 38 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 -#define GCC_MMSS_BCR 50 -#define GCC_VENUS0_BCR 51 -#define GCC_MDSS_BCR 52 -#define GCC_CAMSS_PHY0_BCR 53 -#define GCC_CAMSS_CSI0_BCR 54 -#define GCC_CAMSS_CSI0PHY_BCR 55 -#define GCC_CAMSS_CSI0RDI_BCR 56 -#define GCC_CAMSS_CSI0PIX_BCR 57 -#define GCC_CAMSS_PHY1_BCR 58 -#define GCC_CAMSS_CSI1_BCR 59 -#define GCC_CAMSS_CSI1PHY_BCR 60 -#define GCC_CAMSS_CSI1RDI_BCR 61 -#define GCC_CAMSS_CSI1PIX_BCR 62 -#define GCC_CAMSS_ISPIF_BCR 63 -#define GCC_CAMSS_CCI_BCR 64 -#define GCC_CAMSS_MCLK0_BCR 65 -#define GCC_CAMSS_MCLK1_BCR 66 -#define GCC_CAMSS_GP0_BCR 67 -#define GCC_CAMSS_GP1_BCR 68 -#define GCC_CAMSS_TOP_BCR 69 -#define GCC_CAMSS_MICRO_BCR 70 -#define GCC_CAMSS_JPEG_BCR 71 -#define GCC_CAMSS_VFE_BCR 72 -#define GCC_CAMSS_CSI_VFE0_BCR 73 -#define GCC_OXILI_BCR 74 -#define GCC_GMEM_BCR 75 -#define GCC_CAMSS_AHB_BCR 76 -#define GCC_MDP_TBU_BCR 77 -#define GCC_GFX_TBU_BCR 78 -#define GCC_GFX_TCU_BCR 79 -#define GCC_MSS_TBU_AXI_BCR 80 -#define GCC_MSS_TBU_GSS_AXI_BCR 81 -#define GCC_MSS_TBU_Q6_AXI_BCR 82 -#define GCC_GTCU_AHB_BCR 83 -#define GCC_SMMU_CFG_BCR 84 -#define GCC_VFE_TBU_BCR 85 -#define GCC_VENUS_TBU_BCR 86 -#define GCC_JPEG_TBU_BCR 87 -#define GCC_PRONTO_TBU_BCR 88 -#define GCC_SMMU_CATS_BCR 89 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8939.h b/include/dt-bindings/reset/qcom,gcc-msm8939.h deleted file mode 100644 index fa41ffeae7a..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-msm8939.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2020 Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8939_H -#define _DT_BINDINGS_RESET_MSM_GCC_8939_H - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR 2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_QUP4_BCR 6 -#define GCC_BLSP1_QUP5_BCR 7 -#define GCC_BLSP1_QUP6_BCR 8 -#define GCC_IMEM_BCR 9 -#define GCC_SMMU_BCR 10 -#define GCC_APSS_TCU_BCR 11 -#define GCC_SMMU_XPU_BCR 12 -#define GCC_PCNOC_TBU_BCR 13 -#define GCC_PRNG_BCR 14 -#define GCC_BOOT_ROM_BCR 15 -#define GCC_CRYPTO_BCR 16 -#define GCC_SEC_CTRL_BCR 17 -#define GCC_AUDIO_CORE_BCR 18 -#define GCC_ULT_AUDIO_BCR 19 -#define GCC_DEHR_BCR 20 -#define GCC_SYSTEM_NOC_BCR 21 -#define GCC_PCNOC_BCR 22 -#define GCC_TCSR_BCR 23 -#define GCC_QDSS_BCR 24 -#define GCC_DCD_BCR 25 -#define GCC_MSG_RAM_BCR 26 -#define GCC_MPM_BCR 27 -#define GCC_SPMI_BCR 28 -#define GCC_SPDM_BCR 29 -#define GCC_MM_SPDM_BCR 30 -#define GCC_BIMC_BCR 31 -#define GCC_RBCPR_BCR 32 -#define GCC_TLMM_BCR 33 -#define GCC_USB_HS_BCR 34 -#define GCC_USB2A_PHY_BCR 35 -#define GCC_SDCC1_BCR 36 -#define GCC_SDCC2_BCR 37 -#define GCC_PDM_BCR 38 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 39 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 40 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 41 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 42 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 43 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 44 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 45 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 46 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 47 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 48 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 49 -#define GCC_MMSS_BCR 50 -#define GCC_VENUS0_BCR 51 -#define GCC_MDSS_BCR 52 -#define GCC_CAMSS_PHY0_BCR 53 -#define GCC_CAMSS_CSI0_BCR 54 -#define GCC_CAMSS_CSI0PHY_BCR 55 -#define GCC_CAMSS_CSI0RDI_BCR 56 -#define GCC_CAMSS_CSI0PIX_BCR 57 -#define GCC_CAMSS_PHY1_BCR 58 -#define GCC_CAMSS_CSI1_BCR 59 -#define GCC_CAMSS_CSI1PHY_BCR 60 -#define GCC_CAMSS_CSI1RDI_BCR 61 -#define GCC_CAMSS_CSI1PIX_BCR 62 -#define GCC_CAMSS_ISPIF_BCR 63 -#define GCC_CAMSS_CCI_BCR 64 -#define GCC_CAMSS_MCLK0_BCR 65 -#define GCC_CAMSS_MCLK1_BCR 66 -#define GCC_CAMSS_GP0_BCR 67 -#define GCC_CAMSS_GP1_BCR 68 -#define GCC_CAMSS_TOP_BCR 69 -#define GCC_CAMSS_MICRO_BCR 70 -#define GCC_CAMSS_JPEG_BCR 71 -#define GCC_CAMSS_VFE_BCR 72 -#define GCC_CAMSS_CSI_VFE0_BCR 73 -#define GCC_OXILI_BCR 74 -#define GCC_GMEM_BCR 75 -#define GCC_CAMSS_AHB_BCR 76 -#define GCC_MDP_TBU_BCR 77 -#define GCC_GFX_TBU_BCR 78 -#define GCC_GFX_TCU_BCR 79 -#define GCC_MSS_TBU_AXI_BCR 80 -#define GCC_MSS_TBU_GSS_AXI_BCR 81 -#define GCC_MSS_TBU_Q6_AXI_BCR 82 -#define GCC_GTCU_AHB_BCR 83 -#define GCC_SMMU_CFG_BCR 84 -#define GCC_VFE_TBU_BCR 85 -#define GCC_VENUS_TBU_BCR 86 -#define GCC_JPEG_TBU_BCR 87 -#define GCC_PRONTO_TBU_BCR 88 -#define GCC_SMMU_CATS_BCR 89 -#define GCC_BLSP1_UART3_BCR 90 -#define GCC_CAMSS_CSI2_BCR 91 -#define GCC_CAMSS_CSI2PHY_BCR 92 -#define GCC_CAMSS_CSI2RDI_BCR 93 -#define GCC_CAMSS_CSI2PIX_BCR 94 -#define GCC_USB_FS_BCR 95 -#define GCC_BLSP1_QUP4_SPI_APPS_CBCR 96 -#define GCC_CAMSS_MCLK2_BCR 97 -#define GCC_CPP_TBU_BCR 98 -#define GCC_MDP_RT_TBU_BCR 99 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8960.h b/include/dt-bindings/reset/qcom,gcc-msm8960.h deleted file mode 100644 index c7ebae7bb25..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-msm8960.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8960_H -#define _DT_BINDINGS_RESET_MSM_GCC_8960_H - -#define SFAB_MSS_Q6_SW_RESET 0 -#define SFAB_MSS_Q6_FW_RESET 1 -#define QDSS_STM_RESET 2 -#define AFAB_SMPSS_S_RESET 3 -#define AFAB_SMPSS_M1_RESET 4 -#define AFAB_SMPSS_M0_RESET 5 -#define AFAB_EBI1_CH0_RESET 6 -#define AFAB_EBI1_CH1_RESET 7 -#define SFAB_ADM0_M0_RESET 8 -#define SFAB_ADM0_M1_RESET 9 -#define SFAB_ADM0_M2_RESET 10 -#define ADM0_C2_RESET 11 -#define ADM0_C1_RESET 12 -#define ADM0_C0_RESET 13 -#define ADM0_PBUS_RESET 14 -#define ADM0_RESET 15 -#define QDSS_CLKS_SW_RESET 16 -#define QDSS_POR_RESET 17 -#define QDSS_TSCTR_RESET 18 -#define QDSS_HRESET_RESET 19 -#define QDSS_AXI_RESET 20 -#define QDSS_DBG_RESET 21 -#define PCIE_A_RESET 22 -#define PCIE_AUX_RESET 23 -#define PCIE_H_RESET 24 -#define SFAB_PCIE_M_RESET 25 -#define SFAB_PCIE_S_RESET 26 -#define SFAB_MSS_M_RESET 27 -#define SFAB_USB3_M_RESET 28 -#define SFAB_RIVA_M_RESET 29 -#define SFAB_LPASS_RESET 30 -#define SFAB_AFAB_M_RESET 31 -#define AFAB_SFAB_M0_RESET 32 -#define AFAB_SFAB_M1_RESET 33 -#define SFAB_SATA_S_RESET 34 -#define SFAB_DFAB_M_RESET 35 -#define DFAB_SFAB_M_RESET 36 -#define DFAB_SWAY0_RESET 37 -#define DFAB_SWAY1_RESET 38 -#define DFAB_ARB0_RESET 39 -#define DFAB_ARB1_RESET 40 -#define PPSS_PROC_RESET 41 -#define PPSS_RESET 42 -#define DMA_BAM_RESET 43 -#define SPS_TIC_H_RESET 44 -#define SLIMBUS_H_RESET 45 -#define SFAB_CFPB_M_RESET 46 -#define SFAB_CFPB_S_RESET 47 -#define TSIF_H_RESET 48 -#define CE1_H_RESET 49 -#define CE1_CORE_RESET 50 -#define CE1_SLEEP_RESET 51 -#define CE2_H_RESET 52 -#define CE2_CORE_RESET 53 -#define SFAB_SFPB_M_RESET 54 -#define SFAB_SFPB_S_RESET 55 -#define RPM_PROC_RESET 56 -#define PMIC_SSBI2_RESET 57 -#define SDC1_RESET 58 -#define SDC2_RESET 59 -#define SDC3_RESET 60 -#define SDC4_RESET 61 -#define SDC5_RESET 62 -#define DFAB_A2_RESET 63 -#define USB_HS1_RESET 64 -#define USB_HSIC_RESET 65 -#define USB_FS1_XCVR_RESET 66 -#define USB_FS1_RESET 67 -#define USB_FS2_XCVR_RESET 68 -#define USB_FS2_RESET 69 -#define GSBI1_RESET 70 -#define GSBI2_RESET 71 -#define GSBI3_RESET 72 -#define GSBI4_RESET 73 -#define GSBI5_RESET 74 -#define GSBI6_RESET 75 -#define GSBI7_RESET 76 -#define GSBI8_RESET 77 -#define GSBI9_RESET 78 -#define GSBI10_RESET 79 -#define GSBI11_RESET 80 -#define GSBI12_RESET 81 -#define SPDM_RESET 82 -#define TLMM_H_RESET 83 -#define SFAB_MSS_S_RESET 84 -#define MSS_SLP_RESET 85 -#define MSS_Q6SW_JTAG_RESET 86 -#define MSS_Q6FW_JTAG_RESET 87 -#define MSS_RESET 88 -#define SATA_H_RESET 89 -#define SATA_RXOOB_RESE 90 -#define SATA_PMALIVE_RESET 91 -#define SATA_SFAB_M_RESET 92 -#define TSSC_RESET 93 -#define PDM_RESET 94 -#define MPM_H_RESET 95 -#define MPM_RESET 96 -#define SFAB_SMPSS_S_RESET 97 -#define PRNG_RESET 98 -#define RIVA_RESET 99 -#define USB_HS3_RESET 100 -#define USB_HS4_RESET 101 -#define CE3_RESET 102 -#define PCIE_EXT_PCI_RESET 103 -#define PCIE_PHY_RESET 104 -#define PCIE_PCI_RESET 105 -#define PCIE_POR_RESET 106 -#define PCIE_HCLK_RESET 107 -#define PCIE_ACLK_RESET 108 -#define CE3_H_RESET 109 -#define SFAB_CE3_M_RESET 110 -#define SFAB_CE3_S_RESET 111 -#define SATA_RESET 112 -#define CE3_SLEEP_RESET 113 -#define GSS_SLP_RESET 114 -#define GSS_RESET 115 - -#endif diff --git a/include/dt-bindings/reset/qcom,gcc-msm8974.h b/include/dt-bindings/reset/qcom,gcc-msm8974.h deleted file mode 100644 index 23777e5ca4e..00000000000 --- a/include/dt-bindings/reset/qcom,gcc-msm8974.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_GCC_8974_H -#define _DT_BINDINGS_RESET_MSM_GCC_8974_H - -#define GCC_SYSTEM_NOC_BCR 0 -#define GCC_CONFIG_NOC_BCR 1 -#define GCC_PERIPH_NOC_BCR 2 -#define GCC_IMEM_BCR 3 -#define GCC_MMSS_BCR 4 -#define GCC_QDSS_BCR 5 -#define GCC_USB_30_BCR 6 -#define GCC_USB3_PHY_BCR 7 -#define GCC_USB_HS_HSIC_BCR 8 -#define GCC_USB_HS_BCR 9 -#define GCC_USB2A_PHY_BCR 10 -#define GCC_USB2B_PHY_BCR 11 -#define GCC_SDCC1_BCR 12 -#define GCC_SDCC2_BCR 13 -#define GCC_SDCC3_BCR 14 -#define GCC_SDCC4_BCR 15 -#define GCC_BLSP1_BCR 16 -#define GCC_BLSP1_QUP1_BCR 17 -#define GCC_BLSP1_UART1_BCR 18 -#define GCC_BLSP1_QUP2_BCR 19 -#define GCC_BLSP1_UART2_BCR 20 -#define GCC_BLSP1_QUP3_BCR 21 -#define GCC_BLSP1_UART3_BCR 22 -#define GCC_BLSP1_QUP4_BCR 23 -#define GCC_BLSP1_UART4_BCR 24 -#define GCC_BLSP1_QUP5_BCR 25 -#define GCC_BLSP1_UART5_BCR 26 -#define GCC_BLSP1_QUP6_BCR 27 -#define GCC_BLSP1_UART6_BCR 28 -#define GCC_BLSP2_BCR 29 -#define GCC_BLSP2_QUP1_BCR 30 -#define GCC_BLSP2_UART1_BCR 31 -#define GCC_BLSP2_QUP2_BCR 32 -#define GCC_BLSP2_UART2_BCR 33 -#define GCC_BLSP2_QUP3_BCR 34 -#define GCC_BLSP2_UART3_BCR 35 -#define GCC_BLSP2_QUP4_BCR 36 -#define GCC_BLSP2_UART4_BCR 37 -#define GCC_BLSP2_QUP5_BCR 38 -#define GCC_BLSP2_UART5_BCR 39 -#define GCC_BLSP2_QUP6_BCR 40 -#define GCC_BLSP2_UART6_BCR 41 -#define GCC_PDM_BCR 42 -#define GCC_BAM_DMA_BCR 43 -#define GCC_TSIF_BCR 44 -#define GCC_TCSR_BCR 45 -#define GCC_BOOT_ROM_BCR 46 -#define GCC_MSG_RAM_BCR 47 -#define GCC_TLMM_BCR 48 -#define GCC_MPM_BCR 49 -#define GCC_SEC_CTRL_BCR 50 -#define GCC_SPMI_BCR 51 -#define GCC_SPDM_BCR 52 -#define GCC_CE1_BCR 53 -#define GCC_CE2_BCR 54 -#define GCC_BIMC_BCR 55 -#define GCC_MPM_NON_AHB_RESET 56 -#define GCC_MPM_AHB_RESET 57 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 58 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 59 -#define GCC_PNOC_BUS_TIMEOUT0_BCR 60 -#define GCC_PNOC_BUS_TIMEOUT1_BCR 61 -#define GCC_PNOC_BUS_TIMEOUT2_BCR 62 -#define GCC_PNOC_BUS_TIMEOUT3_BCR 63 -#define GCC_PNOC_BUS_TIMEOUT4_BCR 64 -#define GCC_CNOC_BUS_TIMEOUT0_BCR 65 -#define GCC_CNOC_BUS_TIMEOUT1_BCR 66 -#define GCC_CNOC_BUS_TIMEOUT2_BCR 67 -#define GCC_CNOC_BUS_TIMEOUT3_BCR 68 -#define GCC_CNOC_BUS_TIMEOUT4_BCR 69 -#define GCC_CNOC_BUS_TIMEOUT5_BCR 70 -#define GCC_CNOC_BUS_TIMEOUT6_BCR 71 -#define GCC_DEHR_BCR 72 -#define GCC_RBCPR_BCR 73 -#define GCC_MSS_RESTART 74 -#define GCC_LPASS_RESTART 75 -#define GCC_WCSS_RESTART 76 -#define GCC_VENUS_RESTART 77 - -#endif diff --git a/include/dt-bindings/reset/qcom,ipq5424-gcc.h b/include/dt-bindings/reset/qcom,ipq5424-gcc.h deleted file mode 100644 index 16a72771c79..00000000000 --- a/include/dt-bindings/reset/qcom,ipq5424-gcc.h +++ /dev/null @@ -1,310 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H -#define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H - -#define GCC_QUPV3_BCR 0 -#define GCC_QUPV3_I2C0_BCR 1 -#define GCC_QUPV3_UART0_BCR 2 -#define GCC_QUPV3_I2C1_BCR 3 -#define GCC_QUPV3_UART1_BCR 4 -#define GCC_QUPV3_SPI0_BCR 5 -#define GCC_QUPV3_SPI1_BCR 6 -#define GCC_IMEM_BCR 7 -#define GCC_TME_BCR 8 -#define GCC_DDRSS_BCR 9 -#define GCC_PRNG_BCR 10 -#define GCC_BOOT_ROM_BCR 11 -#define GCC_NSS_BCR 12 -#define GCC_MDIO_BCR 13 -#define GCC_UNIPHY0_BCR 14 -#define GCC_UNIPHY1_BCR 15 -#define GCC_UNIPHY2_BCR 16 -#define GCC_WCSS_BCR 17 -#define GCC_SEC_CTRL_BCR 19 -#define GCC_TME_SEC_BUS_BCR 20 -#define GCC_ADSS_BCR 21 -#define GCC_LPASS_BCR 22 -#define GCC_PCIE0_BCR 23 -#define GCC_PCIE0_LINK_DOWN_BCR 24 -#define GCC_PCIE0PHY_PHY_BCR 25 -#define GCC_PCIE0_PHY_BCR 26 -#define GCC_PCIE1_BCR 27 -#define GCC_PCIE1_LINK_DOWN_BCR 28 -#define GCC_PCIE1PHY_PHY_BCR 29 -#define GCC_PCIE1_PHY_BCR 30 -#define GCC_PCIE2_BCR 31 -#define GCC_PCIE2_LINK_DOWN_BCR 32 -#define GCC_PCIE2PHY_PHY_BCR 33 -#define GCC_PCIE2_PHY_BCR 34 -#define GCC_PCIE3_BCR 35 -#define GCC_PCIE3_LINK_DOWN_BCR 36 -#define GCC_PCIE3PHY_PHY_BCR 37 -#define GCC_PCIE3_PHY_BCR 38 -#define GCC_USB_BCR 39 -#define GCC_QUSB2_0_PHY_BCR 40 -#define GCC_USB0_PHY_BCR 41 -#define GCC_USB3PHY_0_PHY_BCR 42 -#define GCC_QDSS_BCR 43 -#define GCC_SNOC_BCR 44 -#define GCC_ANOC_BCR 45 -#define GCC_PCNOC_BCR 46 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 47 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 48 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 49 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 50 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 51 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 52 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 53 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 54 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 55 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 56 -#define GCC_QPIC_BCR 57 -#define GCC_SDCC_BCR 58 -#define GCC_DCC_BCR 59 -#define GCC_SPDM_BCR 60 -#define GCC_MPM_BCR 61 -#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 62 -#define GCC_RBCPR_BCR 63 -#define GCC_CMN_BLK_BCR 64 -#define GCC_TCSR_BCR 65 -#define GCC_TLMM_BCR 66 -#define GCC_QUPV3_AHB_MST_ARES 67 -#define GCC_QUPV3_CORE_ARES 68 -#define GCC_QUPV3_2X_CORE_ARES 69 -#define GCC_QUPV3_SLEEP_ARES 70 -#define GCC_QUPV3_AHB_SLV_ARES 71 -#define GCC_QUPV3_I2C0_ARES 72 -#define GCC_QUPV3_UART0_ARES 73 -#define GCC_QUPV3_I2C1_ARES 74 -#define GCC_QUPV3_UART1_ARES 75 -#define GCC_QUPV3_SPI0_ARES 76 -#define GCC_QUPV3_SPI1_ARES 77 -#define GCC_DEBUG_ARES 78 -#define GCC_GP1_ARES 79 -#define GCC_GP2_ARES 80 -#define GCC_GP3_ARES 81 -#define GCC_IMEM_AXI_ARES 82 -#define GCC_IMEM_CFG_AHB_ARES 83 -#define GCC_TME_ARES 84 -#define GCC_TME_TS_ARES 85 -#define GCC_TME_SLOW_ARES 86 -#define GCC_TME_RTC_TOGGLE_ARES 87 -#define GCC_TIC_ARES 88 -#define GCC_PRNG_AHB_ARES 89 -#define GCC_BOOT_ROM_AHB_ARES 90 -#define GCC_NSSNOC_ATB_ARES 91 -#define GCC_NSS_TS_ARES 92 -#define GCC_NSSNOC_QOSGEN_REF_ARES 93 -#define GCC_NSSNOC_TIMEOUT_REF_ARES 94 -#define GCC_NSSNOC_MEMNOC_ARES 95 -#define GCC_NSSNOC_SNOC_ARES 96 -#define GCC_NSSCFG_ARES 97 -#define GCC_NSSNOC_NSSCC_ARES 98 -#define GCC_NSSCC_ARES 99 -#define GCC_MDIO_AHB_ARES 100 -#define GCC_UNIPHY0_SYS_ARES 101 -#define GCC_UNIPHY0_AHB_ARES 102 -#define GCC_UNIPHY1_SYS_ARES 103 -#define GCC_UNIPHY1_AHB_ARES 104 -#define GCC_UNIPHY2_SYS_ARES 105 -#define GCC_UNIPHY2_AHB_ARES 106 -#define GCC_NSSNOC_XO_DCD_ARES 107 -#define GCC_NSSNOC_SNOC_1_ARES 108 -#define GCC_NSSNOC_PCNOC_1_ARES 109 -#define GCC_NSSNOC_MEMNOC_1_ARES 110 -#define GCC_DDRSS_ATB_ARES 111 -#define GCC_DDRSS_AHB_ARES 112 -#define GCC_GEMNOC_AHB_ARES 113 -#define GCC_GEMNOC_Q6_AXI_ARES 114 -#define GCC_GEMNOC_NSSNOC_ARES 115 -#define GCC_GEMNOC_SNOC_ARES 116 -#define GCC_GEMNOC_APSS_ARES 117 -#define GCC_GEMNOC_QOSGEN_EXTREF_ARES 118 -#define GCC_GEMNOC_TS_ARES 119 -#define GCC_DDRSS_SMS_SLOW_ARES 120 -#define GCC_GEMNOC_CNOC_ARES 121 -#define GCC_GEMNOC_XO_DBG_ARES 122 -#define GCC_GEMNOC_ANOC_ARES 123 -#define GCC_DDRSS_LLCC_ATB_ARES 124 -#define GCC_LLCC_TPDM_CFG_ARES 125 -#define GCC_TME_BUS_ARES 126 -#define GCC_SEC_CTRL_ACC_ARES 127 -#define GCC_SEC_CTRL_ARES 128 -#define GCC_SEC_CTRL_SENSE_ARES 129 -#define GCC_SEC_CTRL_AHB_ARES 130 -#define GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES 131 -#define GCC_ADSS_PWM_ARES 132 -#define GCC_TME_ATB_ARES 133 -#define GCC_TME_DBGAPB_ARES 134 -#define GCC_TME_DEBUG_ARES 135 -#define GCC_TME_AT_ARES 136 -#define GCC_TME_APB_ARES 137 -#define GCC_TME_DMI_DBG_HS_ARES 138 -#define GCC_APSS_AHB_ARES 139 -#define GCC_APSS_AXI_ARES 140 -#define GCC_CPUSS_TRIG_ARES 141 -#define GCC_APSS_DBG_ARES 142 -#define GCC_APSS_TS_ARES 143 -#define GCC_APSS_ATB_ARES 144 -#define GCC_Q6_AXIM_ARES 145 -#define GCC_Q6_AXIS_ARES 146 -#define GCC_Q6_AHB_ARES 147 -#define GCC_Q6_AHB_S_ARES 148 -#define GCC_Q6SS_ATBM_ARES 149 -#define GCC_Q6_TSCTR_1TO2_ARES 150 -#define GCC_Q6SS_PCLKDBG_ARES 151 -#define GCC_Q6SS_TRIG_ARES 152 -#define GCC_Q6SS_BOOT_CBCR_ARES 153 -#define GCC_WCSS_DBG_IFC_APB_ARES 154 -#define GCC_WCSS_DBG_IFC_ATB_ARES 155 -#define GCC_WCSS_DBG_IFC_NTS_ARES 156 -#define GCC_WCSS_DBG_IFC_DAPBUS_ARES 157 -#define GCC_WCSS_DBG_IFC_APB_BDG_ARES 158 -#define GCC_WCSS_DBG_IFC_NTS_BDG_ARES 159 -#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES 160 -#define GCC_WCSS_ECAHB_ARES 161 -#define GCC_WCSS_ACMT_ARES 162 -#define GCC_WCSS_AHB_S_ARES 163 -#define GCC_WCSS_AXI_M_ARES 164 -#define GCC_PCNOC_WAPSS_ARES 165 -#define GCC_SNOC_WAPSS_ARES 166 -#define GCC_LPASS_SWAY_ARES 167 -#define GCC_LPASS_CORE_AXIM_ARES 168 -#define GCC_PCIE0_AHB_ARES 169 -#define GCC_PCIE0_AXI_M_ARES 170 -#define GCC_PCIE0_AXI_S_ARES 171 -#define GCC_PCIE0_AXI_S_BRIDGE_ARES 172 -#define GCC_PCIE0_PIPE_ARES 173 -#define GCC_PCIE0_AUX_ARES 174 -#define GCC_PCIE1_AHB_ARES 175 -#define GCC_PCIE1_AXI_M_ARES 176 -#define GCC_PCIE1_AXI_S_ARES 177 -#define GCC_PCIE1_AXI_S_BRIDGE_ARES 178 -#define GCC_PCIE1_PIPE_ARES 179 -#define GCC_PCIE1_AUX_ARES 180 -#define GCC_PCIE2_AHB_ARES 181 -#define GCC_PCIE2_AXI_M_ARES 182 -#define GCC_PCIE2_AXI_S_ARES 183 -#define GCC_PCIE2_AXI_S_BRIDGE_ARES 184 -#define GCC_PCIE2_PIPE_ARES 185 -#define GCC_PCIE2_AUX_ARES 186 -#define GCC_PCIE3_AHB_ARES 187 -#define GCC_PCIE3_AXI_M_ARES 188 -#define GCC_PCIE3_AXI_S_ARES 189 -#define GCC_PCIE3_AXI_S_BRIDGE_ARES 190 -#define GCC_PCIE3_PIPE_ARES 191 -#define GCC_PCIE3_AUX_ARES 192 -#define GCC_USB0_MASTER_ARES 193 -#define GCC_USB0_AUX_ARES 194 -#define GCC_USB0_MOCK_UTMI_ARES 195 -#define GCC_USB0_PIPE_ARES 196 -#define GCC_USB0_SLEEP_ARES 197 -#define GCC_USB0_PHY_CFG_AHB_ARES 198 -#define GCC_QDSS_AT_ARES 199 -#define GCC_QDSS_STM_ARES 200 -#define GCC_QDSS_TRACECLKIN_ARES 201 -#define GCC_QDSS_TSCTR_DIV2_ARES 202 -#define GCC_QDSS_TSCTR_DIV3_ARES 203 -#define GCC_QDSS_TSCTR_DIV4_ARES 204 -#define GCC_QDSS_TSCTR_DIV8_ARES 205 -#define GCC_QDSS_TSCTR_DIV16_ARES 206 -#define GCC_QDSS_DAP_ARES 207 -#define GCC_QDSS_APB2JTAG_ARES 208 -#define GCC_QDSS_ETR_USB_ARES 209 -#define GCC_QDSS_DAP_AHB_ARES 210 -#define GCC_QDSS_CFG_AHB_ARES 211 -#define GCC_QDSS_EUD_AT_ARES 212 -#define GCC_QDSS_TS_ARES 213 -#define GCC_QDSS_USB_ARES 214 -#define GCC_SYS_NOC_AXI_ARES 215 -#define GCC_SNOC_QOSGEN_EXTREF_ARES 216 -#define GCC_CNOC_LPASS_CFG_ARES 217 -#define GCC_SYS_NOC_AT_ARES 218 -#define GCC_SNOC_PCNOC_AHB_ARES 219 -#define GCC_SNOC_TME_ARES 220 -#define GCC_SNOC_XO_DCD_ARES 221 -#define GCC_SNOC_TS_ARES 222 -#define GCC_ANOC0_AXI_ARES 223 -#define GCC_ANOC_PCIE0_1LANE_M_ARES 224 -#define GCC_ANOC_PCIE2_2LANE_M_ARES 225 -#define GCC_ANOC_PCIE1_1LANE_M_ARES 226 -#define GCC_ANOC_PCIE3_2LANE_M_ARES 227 -#define GCC_ANOC_PCNOC_AHB_ARES 228 -#define GCC_ANOC_QOSGEN_EXTREF_ARES 229 -#define GCC_ANOC_XO_DCD_ARES 230 -#define GCC_SNOC_XO_DBG_ARES 231 -#define GCC_AGGRNOC_ATB_ARES 232 -#define GCC_AGGRNOC_TS_ARES 233 -#define GCC_USB0_EUD_AT_ARES 234 -#define GCC_PCNOC_TIC_ARES 235 -#define GCC_PCNOC_AHB_ARES 236 -#define GCC_PCNOC_XO_DBG_ARES 237 -#define GCC_SNOC_LPASS_ARES 238 -#define GCC_PCNOC_AT_ARES 239 -#define GCC_PCNOC_XO_DCD_ARES 240 -#define GCC_PCNOC_TS_ARES 241 -#define GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES 242 -#define GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES 243 -#define GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES 244 -#define GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES 245 -#define GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES 246 -#define GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES 247 -#define GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES 248 -#define GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES 249 -#define GCC_Q6_AXIM_RESET 250 -#define GCC_Q6_AXIS_RESET 251 -#define GCC_Q6_AHB_S_RESET 252 -#define GCC_Q6_AHB_RESET 253 -#define GCC_Q6SS_DBG_RESET 254 -#define GCC_WCSS_ECAHB_RESET 255 -#define GCC_WCSS_DBG_BDG_RESET 256 -#define GCC_WCSS_DBG_RESET 257 -#define GCC_WCSS_AXI_M_RESET 258 -#define GCC_WCSS_AHB_S_RESET 259 -#define GCC_WCSS_ACMT_RESET 260 -#define GCC_WCSSAON_RESET 261 -#define GCC_PCIE0_PIPE_RESET 262 -#define GCC_PCIE0_CORE_STICKY_RESET 263 -#define GCC_PCIE0_AXI_S_STICKY_RESET 264 -#define GCC_PCIE0_AXI_S_RESET 265 -#define GCC_PCIE0_AXI_M_STICKY_RESET 266 -#define GCC_PCIE0_AXI_M_RESET 267 -#define GCC_PCIE0_AUX_RESET 268 -#define GCC_PCIE0_AHB_RESET 269 -#define GCC_PCIE1_PIPE_RESET 270 -#define GCC_PCIE1_CORE_STICKY_RESET 271 -#define GCC_PCIE1_AXI_S_STICKY_RESET 272 -#define GCC_PCIE1_AXI_S_RESET 273 -#define GCC_PCIE1_AXI_M_STICKY_RESET 274 -#define GCC_PCIE1_AXI_M_RESET 275 -#define GCC_PCIE1_AUX_RESET 276 -#define GCC_PCIE1_AHB_RESET 277 -#define GCC_PCIE2_PIPE_RESET 278 -#define GCC_PCIE2_CORE_STICKY_RESET 279 -#define GCC_PCIE2_AXI_S_STICKY_RESET 280 -#define GCC_PCIE2_AXI_S_RESET 281 -#define GCC_PCIE2_AXI_M_STICKY_RESET 282 -#define GCC_PCIE2_AXI_M_RESET 283 -#define GCC_PCIE2_AUX_RESET 284 -#define GCC_PCIE2_AHB_RESET 285 -#define GCC_PCIE3_PIPE_RESET 286 -#define GCC_PCIE3_CORE_STICKY_RESET 287 -#define GCC_PCIE3_AXI_S_STICKY_RESET 288 -#define GCC_PCIE3_AXI_S_RESET 289 -#define GCC_PCIE3_AXI_M_STICKY_RESET 290 -#define GCC_PCIE3_AXI_M_RESET 291 -#define GCC_PCIE3_AUX_RESET 292 -#define GCC_PCIE3_AHB_RESET 293 -#define GCC_NSS_PARTIAL_RESET 294 -#define GCC_UNIPHY0_XPCS_ARES 295 -#define GCC_UNIPHY1_XPCS_ARES 296 -#define GCC_UNIPHY2_XPCS_ARES 297 -#define GCC_USB1_BCR 298 -#define GCC_QUSB2_1_PHY_BCR 299 - -#endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h deleted file mode 100644 index c709d103673..00000000000 --- a/include/dt-bindings/reset/qcom,ipq9574-gcc.h +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2018-2023, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H -#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H - -#define GCC_ADSS_BCR 0 -#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 1 -#define GCC_BLSP1_BCR 2 -#define GCC_BLSP1_QUP1_BCR 3 -#define GCC_BLSP1_QUP2_BCR 4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_QUP4_BCR 6 -#define GCC_BLSP1_QUP5_BCR 7 -#define GCC_BLSP1_QUP6_BCR 8 -#define GCC_BLSP1_UART1_BCR 9 -#define GCC_BLSP1_UART2_BCR 10 -#define GCC_BLSP1_UART3_BCR 11 -#define GCC_BLSP1_UART4_BCR 12 -#define GCC_BLSP1_UART5_BCR 13 -#define GCC_BLSP1_UART6_BCR 14 -#define GCC_BOOT_ROM_BCR 15 -#define GCC_MDIO_BCR 16 -#define GCC_NSS_BCR 17 -#define GCC_NSS_TBU_BCR 18 -#define GCC_PCIE0_BCR 19 -#define GCC_PCIE0_LINK_DOWN_BCR 20 -#define GCC_PCIE0_PHY_BCR 21 -#define GCC_PCIE0PHY_PHY_BCR 22 -#define GCC_PCIE1_BCR 23 -#define GCC_PCIE1_LINK_DOWN_BCR 24 -#define GCC_PCIE1_PHY_BCR 25 -#define GCC_PCIE1PHY_PHY_BCR 26 -#define GCC_PCIE2_BCR 27 -#define GCC_PCIE2_LINK_DOWN_BCR 28 -#define GCC_PCIE2_PHY_BCR 29 -#define GCC_PCIE2PHY_PHY_BCR 30 -#define GCC_PCIE3_BCR 31 -#define GCC_PCIE3_LINK_DOWN_BCR 32 -#define GCC_PCIE3_PHY_BCR 33 -#define GCC_PCIE3PHY_PHY_BCR 34 -#define GCC_PRNG_BCR 35 -#define GCC_QUSB2_0_PHY_BCR 36 -#define GCC_SDCC_BCR 37 -#define GCC_TLMM_BCR 38 -#define GCC_UNIPHY0_BCR 39 -#define GCC_UNIPHY1_BCR 40 -#define GCC_UNIPHY2_BCR 41 -#define GCC_USB0_PHY_BCR 42 -#define GCC_USB3PHY_0_PHY_BCR 43 -#define GCC_USB_BCR 44 -#define GCC_ANOC0_TBU_BCR 45 -#define GCC_ANOC1_TBU_BCR 46 -#define GCC_ANOC_BCR 47 -#define GCC_APSS_TCU_BCR 48 -#define GCC_CMN_BLK_BCR 49 -#define GCC_CMN_BLK_AHB_ARES 50 -#define GCC_CMN_BLK_SYS_ARES 51 -#define GCC_CMN_BLK_APU_ARES 52 -#define GCC_DCC_BCR 53 -#define GCC_DDRSS_BCR 54 -#define GCC_IMEM_BCR 55 -#define GCC_LPASS_BCR 56 -#define GCC_MPM_BCR 57 -#define GCC_MSG_RAM_BCR 58 -#define GCC_NSSNOC_MEMNOC_1_ARES 59 -#define GCC_NSSNOC_PCNOC_1_ARES 60 -#define GCC_NSSNOC_SNOC_1_ARES 61 -#define GCC_NSSNOC_XO_DCD_ARES 62 -#define GCC_NSSNOC_TS_ARES 63 -#define GCC_NSSCC_ARES 64 -#define GCC_NSSNOC_NSSCC_ARES 65 -#define GCC_NSSNOC_ATB_ARES 66 -#define GCC_NSSNOC_MEMNOC_ARES 67 -#define GCC_NSSNOC_QOSGEN_REF_ARES 68 -#define GCC_NSSNOC_SNOC_ARES 69 -#define GCC_NSSNOC_TIMEOUT_REF_ARES 70 -#define GCC_NSS_CFG_ARES 71 -#define GCC_UBI0_DBG_ARES 72 -#define GCC_PCIE0_AHB_ARES 73 -#define GCC_PCIE0_AUX_ARES 74 -#define GCC_PCIE0_AXI_M_ARES 75 -#define GCC_PCIE0_AXI_M_STICKY_ARES 76 -#define GCC_PCIE0_AXI_S_ARES 77 -#define GCC_PCIE0_AXI_S_STICKY_ARES 78 -#define GCC_PCIE0_CORE_STICKY_ARES 79 -#define GCC_PCIE0_PIPE_ARES 80 -#define GCC_PCIE1_AHB_ARES 81 -#define GCC_PCIE1_AUX_ARES 82 -#define GCC_PCIE1_AXI_M_ARES 83 -#define GCC_PCIE1_AXI_M_STICKY_ARES 84 -#define GCC_PCIE1_AXI_S_ARES 85 -#define GCC_PCIE1_AXI_S_STICKY_ARES 86 -#define GCC_PCIE1_CORE_STICKY_ARES 87 -#define GCC_PCIE1_PIPE_ARES 88 -#define GCC_PCIE2_AHB_ARES 89 -#define GCC_PCIE2_AUX_ARES 90 -#define GCC_PCIE2_AXI_M_ARES 91 -#define GCC_PCIE2_AXI_M_STICKY_ARES 92 -#define GCC_PCIE2_AXI_S_ARES 93 -#define GCC_PCIE2_AXI_S_STICKY_ARES 94 -#define GCC_PCIE2_CORE_STICKY_ARES 95 -#define GCC_PCIE2_PIPE_ARES 96 -#define GCC_PCIE3_AHB_ARES 97 -#define GCC_PCIE3_AUX_ARES 98 -#define GCC_PCIE3_AXI_M_ARES 99 -#define GCC_PCIE3_AXI_M_STICKY_ARES 100 -#define GCC_PCIE3_AXI_S_ARES 101 -#define GCC_PCIE3_AXI_S_STICKY_ARES 102 -#define GCC_PCIE3_CORE_STICKY_ARES 103 -#define GCC_PCIE3_PIPE_ARES 104 -#define GCC_PCNOC_BCR 105 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 106 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 107 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 108 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 109 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 110 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 111 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 112 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 113 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 114 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 115 -#define GCC_PCNOC_TBU_BCR 116 -#define GCC_Q6SS_DBG_ARES 117 -#define GCC_Q6_AHB_ARES 118 -#define GCC_Q6_AHB_S_ARES 119 -#define GCC_Q6_AXIM2_ARES 120 -#define GCC_Q6_AXIM_ARES 121 -#define GCC_QDSS_BCR 122 -#define GCC_QPIC_BCR 123 -#define GCC_QPIC_AHB_ARES 124 -#define GCC_QPIC_ARES 125 -#define GCC_RBCPR_BCR 126 -#define GCC_RBCPR_MX_BCR 127 -#define GCC_SEC_CTRL_BCR 128 -#define GCC_SMMU_CFG_BCR 129 -#define GCC_SNOC_BCR 130 -#define GCC_SPDM_BCR 131 -#define GCC_TME_BCR 132 -#define GCC_UNIPHY0_SYS_RESET 133 -#define GCC_UNIPHY0_AHB_RESET 134 -#define GCC_UNIPHY0_XPCS_RESET 135 -#define GCC_UNIPHY1_SYS_RESET 136 -#define GCC_UNIPHY1_AHB_RESET 137 -#define GCC_UNIPHY1_XPCS_RESET 138 -#define GCC_UNIPHY2_SYS_RESET 139 -#define GCC_UNIPHY2_AHB_RESET 140 -#define GCC_UNIPHY2_XPCS_RESET 141 -#define GCC_USB_MISC_RESET 142 -#define GCC_WCSSAON_RESET 143 -#define GCC_WCSS_ACMT_ARES 144 -#define GCC_WCSS_AHB_S_ARES 145 -#define GCC_WCSS_AXI_M_ARES 146 -#define GCC_WCSS_BCR 147 -#define GCC_WCSS_DBG_ARES 148 -#define GCC_WCSS_DBG_BDG_ARES 149 -#define GCC_WCSS_ECAHB_ARES 150 -#define GCC_WCSS_Q6_BCR 151 -#define GCC_WCSS_Q6_TBU_BCR 152 -#define GCC_TCSR_BCR 153 -#define GCC_CRYPTO_BCR 154 - -#endif diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h deleted file mode 100644 index 7f152e98b99..00000000000 --- a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H -#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H - -#define EDMA_HW_RESET 0 -#define NSS_CC_CE_BCR 1 -#define NSS_CC_CLC_BCR 2 -#define NSS_CC_EIP197_BCR 3 -#define NSS_CC_HAQ_BCR 4 -#define NSS_CC_IMEM_BCR 5 -#define NSS_CC_MAC_BCR 6 -#define NSS_CC_PPE_BCR 7 -#define NSS_CC_UBI_BCR 8 -#define NSS_CC_UNIPHY_BCR 9 -#define UBI3_CLKRST_CLAMP_ENABLE 10 -#define UBI3_CORE_CLAMP_ENABLE 11 -#define UBI2_CLKRST_CLAMP_ENABLE 12 -#define UBI2_CORE_CLAMP_ENABLE 13 -#define UBI1_CLKRST_CLAMP_ENABLE 14 -#define UBI1_CORE_CLAMP_ENABLE 15 -#define UBI0_CLKRST_CLAMP_ENABLE 16 -#define UBI0_CORE_CLAMP_ENABLE 17 -#define NSSNOC_NSS_CSR_ARES 18 -#define NSS_CSR_ARES 19 -#define PPE_BTQ_ARES 20 -#define PPE_IPE_ARES 21 -#define PPE_ARES 22 -#define PPE_CFG_ARES 23 -#define PPE_EDMA_ARES 24 -#define PPE_EDMA_CFG_ARES 25 -#define CRY_PPE_ARES 26 -#define NSSNOC_PPE_ARES 27 -#define NSSNOC_PPE_CFG_ARES 28 -#define PORT1_MAC_ARES 29 -#define PORT2_MAC_ARES 30 -#define PORT3_MAC_ARES 31 -#define PORT4_MAC_ARES 32 -#define PORT5_MAC_ARES 33 -#define PORT6_MAC_ARES 34 -#define XGMAC0_PTP_REF_ARES 35 -#define XGMAC1_PTP_REF_ARES 36 -#define XGMAC2_PTP_REF_ARES 37 -#define XGMAC3_PTP_REF_ARES 38 -#define XGMAC4_PTP_REF_ARES 39 -#define XGMAC5_PTP_REF_ARES 40 -#define HAQ_AHB_ARES 41 -#define HAQ_AXI_ARES 42 -#define NSSNOC_HAQ_AHB_ARES 43 -#define NSSNOC_HAQ_AXI_ARES 44 -#define CE_APB_ARES 45 -#define CE_AXI_ARES 46 -#define NSSNOC_CE_APB_ARES 47 -#define NSSNOC_CE_AXI_ARES 48 -#define CRYPTO_ARES 49 -#define NSSNOC_CRYPTO_ARES 50 -#define NSSNOC_NC_AXI0_1_ARES 51 -#define UBI0_CORE_ARES 52 -#define UBI1_CORE_ARES 53 -#define UBI2_CORE_ARES 54 -#define UBI3_CORE_ARES 55 -#define NC_AXI0_ARES 56 -#define UTCM0_ARES 57 -#define NC_AXI1_ARES 58 -#define UTCM1_ARES 59 -#define NC_AXI2_ARES 60 -#define UTCM2_ARES 61 -#define NC_AXI3_ARES 62 -#define UTCM3_ARES 63 -#define NSSNOC_NC_AXI0_ARES 64 -#define AHB0_ARES 65 -#define INTR0_AHB_ARES 66 -#define AHB1_ARES 67 -#define INTR1_AHB_ARES 68 -#define AHB2_ARES 69 -#define INTR2_AHB_ARES 70 -#define AHB3_ARES 71 -#define INTR3_AHB_ARES 72 -#define NSSNOC_AHB0_ARES 73 -#define NSSNOC_INT0_AHB_ARES 74 -#define AXI0_ARES 75 -#define AXI1_ARES 76 -#define AXI2_ARES 77 -#define AXI3_ARES 78 -#define NSSNOC_AXI0_ARES 79 -#define IMEM_QSB_ARES 80 -#define NSSNOC_IMEM_QSB_ARES 81 -#define IMEM_AHB_ARES 82 -#define NSSNOC_IMEM_AHB_ARES 83 -#define UNIPHY_PORT1_RX_ARES 84 -#define UNIPHY_PORT1_TX_ARES 85 -#define UNIPHY_PORT2_RX_ARES 86 -#define UNIPHY_PORT2_TX_ARES 87 -#define UNIPHY_PORT3_RX_ARES 88 -#define UNIPHY_PORT3_TX_ARES 89 -#define UNIPHY_PORT4_RX_ARES 90 -#define UNIPHY_PORT4_TX_ARES 91 -#define UNIPHY_PORT5_RX_ARES 92 -#define UNIPHY_PORT5_TX_ARES 93 -#define UNIPHY_PORT6_RX_ARES 94 -#define UNIPHY_PORT6_TX_ARES 95 -#define PORT1_RX_ARES 96 -#define PORT1_TX_ARES 97 -#define PORT2_RX_ARES 98 -#define PORT2_TX_ARES 99 -#define PORT3_RX_ARES 100 -#define PORT3_TX_ARES 101 -#define PORT4_RX_ARES 102 -#define PORT4_TX_ARES 103 -#define PORT5_RX_ARES 104 -#define PORT5_TX_ARES 105 -#define PORT6_RX_ARES 106 -#define PORT6_TX_ARES 107 -#define PPE_FULL_RESET 108 -#define UNIPHY0_SOFT_RESET 109 -#define UNIPHY1_SOFT_RESET 110 -#define UNIPHY2_SOFT_RESET 111 -#define UNIPHY_PORT1_ARES 112 -#define UNIPHY_PORT2_ARES 113 -#define UNIPHY_PORT3_ARES 114 -#define UNIPHY_PORT4_ARES 115 -#define UNIPHY_PORT5_ARES 116 -#define UNIPHY_PORT6_ARES 117 -#define NSSPORT1_RESET 118 -#define NSSPORT2_RESET 119 -#define NSSPORT3_RESET 120 -#define NSSPORT4_RESET 121 -#define NSSPORT5_RESET 122 -#define NSSPORT6_RESET 123 - -#endif diff --git a/include/dt-bindings/reset/qcom,mmcc-apq8084.h b/include/dt-bindings/reset/qcom,mmcc-apq8084.h deleted file mode 100644 index faaeb40959f..00000000000 --- a/include/dt-bindings/reset/qcom,mmcc-apq8084.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2014, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_APQ_MMCC_8084_H -#define _DT_BINDINGS_RESET_APQ_MMCC_8084_H - -#define MMSS_SPDM_RESET 0 -#define MMSS_SPDM_RM_RESET 1 -#define VENUS0_RESET 2 -#define VPU_RESET 3 -#define MDSS_RESET 4 -#define AVSYNC_RESET 5 -#define CAMSS_PHY0_RESET 6 -#define CAMSS_PHY1_RESET 7 -#define CAMSS_PHY2_RESET 8 -#define CAMSS_CSI0_RESET 9 -#define CAMSS_CSI0PHY_RESET 10 -#define CAMSS_CSI0RDI_RESET 11 -#define CAMSS_CSI0PIX_RESET 12 -#define CAMSS_CSI1_RESET 13 -#define CAMSS_CSI1PHY_RESET 14 -#define CAMSS_CSI1RDI_RESET 15 -#define CAMSS_CSI1PIX_RESET 16 -#define CAMSS_CSI2_RESET 17 -#define CAMSS_CSI2PHY_RESET 18 -#define CAMSS_CSI2RDI_RESET 19 -#define CAMSS_CSI2PIX_RESET 20 -#define CAMSS_CSI3_RESET 21 -#define CAMSS_CSI3PHY_RESET 22 -#define CAMSS_CSI3RDI_RESET 23 -#define CAMSS_CSI3PIX_RESET 24 -#define CAMSS_ISPIF_RESET 25 -#define CAMSS_CCI_RESET 26 -#define CAMSS_MCLK0_RESET 27 -#define CAMSS_MCLK1_RESET 28 -#define CAMSS_MCLK2_RESET 29 -#define CAMSS_MCLK3_RESET 30 -#define CAMSS_GP0_RESET 31 -#define CAMSS_GP1_RESET 32 -#define CAMSS_TOP_RESET 33 -#define CAMSS_AHB_RESET 34 -#define CAMSS_MICRO_RESET 35 -#define CAMSS_JPEG_RESET 36 -#define CAMSS_VFE_RESET 37 -#define CAMSS_CSI_VFE0_RESET 38 -#define CAMSS_CSI_VFE1_RESET 39 -#define OXILI_RESET 40 -#define OXILICX_RESET 41 -#define OCMEMCX_RESET 42 -#define MMSS_RBCRP_RESET 43 -#define MMSSNOCAHB_RESET 44 -#define MMSSNOCAXI_RESET 45 - -#endif diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8960.h b/include/dt-bindings/reset/qcom,mmcc-msm8960.h deleted file mode 100644 index eb4186aa2c0..00000000000 --- a/include/dt-bindings/reset/qcom,mmcc-msm8960.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8960_H -#define _DT_BINDINGS_RESET_MSM_MMCC_8960_H - -#define VPE_AXI_RESET 0 -#define IJPEG_AXI_RESET 1 -#define MPD_AXI_RESET 2 -#define VFE_AXI_RESET 3 -#define SP_AXI_RESET 4 -#define VCODEC_AXI_RESET 5 -#define ROT_AXI_RESET 6 -#define VCODEC_AXI_A_RESET 7 -#define VCODEC_AXI_B_RESET 8 -#define FAB_S3_AXI_RESET 9 -#define FAB_S2_AXI_RESET 10 -#define FAB_S1_AXI_RESET 11 -#define FAB_S0_AXI_RESET 12 -#define SMMU_GFX3D_ABH_RESET 13 -#define SMMU_VPE_AHB_RESET 14 -#define SMMU_VFE_AHB_RESET 15 -#define SMMU_ROT_AHB_RESET 16 -#define SMMU_VCODEC_B_AHB_RESET 17 -#define SMMU_VCODEC_A_AHB_RESET 18 -#define SMMU_MDP1_AHB_RESET 19 -#define SMMU_MDP0_AHB_RESET 20 -#define SMMU_JPEGD_AHB_RESET 21 -#define SMMU_IJPEG_AHB_RESET 22 -#define SMMU_GFX2D0_AHB_RESET 23 -#define SMMU_GFX2D1_AHB_RESET 24 -#define APU_AHB_RESET 25 -#define CSI_AHB_RESET 26 -#define TV_ENC_AHB_RESET 27 -#define VPE_AHB_RESET 28 -#define FABRIC_AHB_RESET 29 -#define GFX2D0_AHB_RESET 30 -#define GFX2D1_AHB_RESET 31 -#define GFX3D_AHB_RESET 32 -#define HDMI_AHB_RESET 33 -#define MSSS_IMEM_AHB_RESET 34 -#define IJPEG_AHB_RESET 35 -#define DSI_M_AHB_RESET 36 -#define DSI_S_AHB_RESET 37 -#define JPEGD_AHB_RESET 38 -#define MDP_AHB_RESET 39 -#define ROT_AHB_RESET 40 -#define VCODEC_AHB_RESET 41 -#define VFE_AHB_RESET 42 -#define DSI2_M_AHB_RESET 43 -#define DSI2_S_AHB_RESET 44 -#define CSIPHY2_RESET 45 -#define CSI_PIX1_RESET 46 -#define CSIPHY0_RESET 47 -#define CSIPHY1_RESET 48 -#define DSI2_RESET 49 -#define VFE_CSI_RESET 50 -#define MDP_RESET 51 -#define AMP_RESET 52 -#define JPEGD_RESET 53 -#define CSI1_RESET 54 -#define VPE_RESET 55 -#define MMSS_FABRIC_RESET 56 -#define VFE_RESET 57 -#define GFX2D0_RESET 58 -#define GFX2D1_RESET 59 -#define GFX3D_RESET 60 -#define HDMI_RESET 61 -#define MMSS_IMEM_RESET 62 -#define IJPEG_RESET 63 -#define CSI0_RESET 64 -#define DSI_RESET 65 -#define VCODEC_RESET 66 -#define MDP_TV_RESET 67 -#define MDP_VSYNC_RESET 68 -#define ROT_RESET 69 -#define TV_HDMI_RESET 70 -#define TV_ENC_RESET 71 -#define CSI2_RESET 72 -#define CSI_RDI1_RESET 73 -#define CSI_RDI2_RESET 74 -#define GFX3D_AXI_RESET 75 -#define VCAP_AXI_RESET 76 -#define SMMU_VCAP_AHB_RESET 77 -#define VCAP_AHB_RESET 78 -#define CSI_RDI_RESET 79 -#define CSI_PIX_RESET 80 -#define VCAP_NPL_RESET 81 -#define VCAP_RESET 82 - -#endif diff --git a/include/dt-bindings/reset/qcom,mmcc-msm8974.h b/include/dt-bindings/reset/qcom,mmcc-msm8974.h deleted file mode 100644 index d61b077e911..00000000000 --- a/include/dt-bindings/reset/qcom,mmcc-msm8974.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2013, The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_MSM_MMCC_8974_H -#define _DT_BINDINGS_RESET_MSM_MMCC_8974_H - -#define SPDM_RESET 0 -#define SPDM_RM_RESET 1 -#define VENUS0_RESET 2 -#define MDSS_RESET 3 -#define CAMSS_PHY0_RESET 4 -#define CAMSS_PHY1_RESET 5 -#define CAMSS_PHY2_RESET 6 -#define CAMSS_CSI0_RESET 7 -#define CAMSS_CSI0PHY_RESET 8 -#define CAMSS_CSI0RDI_RESET 9 -#define CAMSS_CSI0PIX_RESET 10 -#define CAMSS_CSI1_RESET 11 -#define CAMSS_CSI1PHY_RESET 12 -#define CAMSS_CSI1RDI_RESET 13 -#define CAMSS_CSI1PIX_RESET 14 -#define CAMSS_CSI2_RESET 15 -#define CAMSS_CSI2PHY_RESET 16 -#define CAMSS_CSI2RDI_RESET 17 -#define CAMSS_CSI2PIX_RESET 18 -#define CAMSS_CSI3_RESET 19 -#define CAMSS_CSI3PHY_RESET 20 -#define CAMSS_CSI3RDI_RESET 21 -#define CAMSS_CSI3PIX_RESET 22 -#define CAMSS_ISPIF_RESET 23 -#define CAMSS_CCI_RESET 24 -#define CAMSS_MCLK0_RESET 25 -#define CAMSS_MCLK1_RESET 26 -#define CAMSS_MCLK2_RESET 27 -#define CAMSS_MCLK3_RESET 28 -#define CAMSS_GP0_RESET 29 -#define CAMSS_GP1_RESET 30 -#define CAMSS_TOP_RESET 31 -#define CAMSS_MICRO_RESET 32 -#define CAMSS_JPEG_RESET 33 -#define CAMSS_VFE_RESET 34 -#define CAMSS_CSI_VFE0_RESET 35 -#define CAMSS_CSI_VFE1_RESET 36 -#define OXILI_RESET 37 -#define OXILICX_RESET 38 -#define OCMEMCX_RESET 39 -#define MMSS_RBCRP_RESET 40 -#define MMSSNOCAHB_RESET 41 -#define MMSSNOCAXI_RESET 42 -#define OCMEMNOC_RESET 43 - -#endif diff --git a/include/dt-bindings/reset/qcom,qca8k-nsscc.h b/include/dt-bindings/reset/qcom,qca8k-nsscc.h deleted file mode 100644 index c71167a3bd4..00000000000 --- a/include/dt-bindings/reset/qcom,qca8k-nsscc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H -#define _DT_BINDINGS_RESET_QCOM_QCA8K_NSS_CC_H - -#define NSS_CC_SWITCH_CORE_ARES 1 -#define NSS_CC_APB_BRIDGE_ARES 2 -#define NSS_CC_MAC0_TX_ARES 3 -#define NSS_CC_MAC0_TX_SRDS1_ARES 4 -#define NSS_CC_MAC0_RX_ARES 5 -#define NSS_CC_MAC0_RX_SRDS1_ARES 6 -#define NSS_CC_MAC1_SRDS1_CH0_RX_ARES 7 -#define NSS_CC_MAC1_TX_ARES 8 -#define NSS_CC_MAC1_GEPHY0_TX_ARES 9 -#define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_ARES 10 -#define NSS_CC_MAC1_SRDS1_CH0_TX_ARES 11 -#define NSS_CC_MAC1_RX_ARES 12 -#define NSS_CC_MAC1_GEPHY0_RX_ARES 13 -#define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_ARES 14 -#define NSS_CC_MAC2_SRDS1_CH1_RX_ARES 15 -#define NSS_CC_MAC2_TX_ARES 16 -#define NSS_CC_MAC2_GEPHY1_TX_ARES 17 -#define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_ARES 18 -#define NSS_CC_MAC2_SRDS1_CH1_TX_ARES 19 -#define NSS_CC_MAC2_RX_ARES 20 -#define NSS_CC_MAC2_GEPHY1_RX_ARES 21 -#define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_ARES 22 -#define NSS_CC_MAC3_SRDS1_CH2_RX_ARES 23 -#define NSS_CC_MAC3_TX_ARES 24 -#define NSS_CC_MAC3_GEPHY2_TX_ARES 25 -#define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_ARES 26 -#define NSS_CC_MAC3_SRDS1_CH2_TX_ARES 27 -#define NSS_CC_MAC3_RX_ARES 28 -#define NSS_CC_MAC3_GEPHY2_RX_ARES 29 -#define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_ARES 30 -#define NSS_CC_MAC4_SRDS1_CH3_RX_ARES 31 -#define NSS_CC_MAC4_TX_ARES 32 -#define NSS_CC_MAC4_GEPHY3_TX_ARES 33 -#define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_ARES 34 -#define NSS_CC_MAC4_SRDS1_CH3_TX_ARES 35 -#define NSS_CC_MAC4_RX_ARES 36 -#define NSS_CC_MAC4_GEPHY3_RX_ARES 37 -#define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_ARES 38 -#define NSS_CC_MAC5_TX_ARES 39 -#define NSS_CC_MAC5_TX_SRDS0_ARES 40 -#define NSS_CC_MAC5_RX_ARES 41 -#define NSS_CC_MAC5_RX_SRDS0_ARES 42 -#define NSS_CC_AHB_ARES 43 -#define NSS_CC_SEC_CTRL_AHB_ARES 44 -#define NSS_CC_TLMM_ARES 45 -#define NSS_CC_TLMM_AHB_ARES 46 -#define NSS_CC_CNOC_AHB_ARES 47 -#define NSS_CC_MDIO_AHB_ARES 48 -#define NSS_CC_MDIO_MASTER_AHB_ARES 49 -#define NSS_CC_SRDS0_SYS_ARES 50 -#define NSS_CC_SRDS1_SYS_ARES 51 -#define NSS_CC_GEPHY0_SYS_ARES 52 -#define NSS_CC_GEPHY1_SYS_ARES 53 -#define NSS_CC_GEPHY2_SYS_ARES 54 -#define NSS_CC_GEPHY3_SYS_ARES 55 -#define NSS_CC_SEC_CTRL_ARES 56 -#define NSS_CC_SEC_CTRL_SENSE_ARES 57 -#define NSS_CC_SLEEP_ARES 58 -#define NSS_CC_DEBUG_ARES 59 -#define NSS_CC_GEPHY0_ARES 60 -#define NSS_CC_GEPHY1_ARES 61 -#define NSS_CC_GEPHY2_ARES 62 -#define NSS_CC_GEPHY3_ARES 63 -#define NSS_CC_DSP_ARES 64 -#define NSS_CC_GEPHY_FULL_ARES 65 -#define NSS_CC_GLOBAL_ARES 66 -#define NSS_CC_XPCS_ARES 67 -#endif diff --git a/include/dt-bindings/reset/qcom,sar2130p-gpucc.h b/include/dt-bindings/reset/qcom,sar2130p-gpucc.h deleted file mode 100644 index 99ba5f092e2..00000000000 --- a/include/dt-bindings/reset/qcom,sar2130p-gpucc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2024, Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H -#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SAR2130P_H - -#define GPUCC_GPU_CC_GX_BCR 0 -#define GPUCC_GPU_CC_ACD_BCR 1 -#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 2 - -#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-aoss.h b/include/dt-bindings/reset/qcom,sdm845-aoss.h deleted file mode 100644 index 476c5fc873b..00000000000 --- a/include/dt-bindings/reset/qcom,sdm845-aoss.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H -#define _DT_BINDINGS_RESET_AOSS_SDM_845_H - -#define AOSS_CC_MSS_RESTART 0 -#define AOSS_CC_CAMSS_RESTART 1 -#define AOSS_CC_VENUS_RESTART 2 -#define AOSS_CC_GPU_RESTART 3 -#define AOSS_CC_DISPSS_RESTART 4 -#define AOSS_CC_WCSS_RESTART 5 -#define AOSS_CC_LPASS_RESTART 6 - -#endif diff --git a/include/dt-bindings/reset/qcom,sdm845-pdc.h b/include/dt-bindings/reset/qcom,sdm845-pdc.h deleted file mode 100644 index 03a0c0eb814..00000000000 --- a/include/dt-bindings/reset/qcom,sdm845-pdc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 The Linux Foundation. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_PDC_SDM_845_H -#define _DT_BINDINGS_RESET_PDC_SDM_845_H - -#define PDC_APPS_SYNC_RESET 0 -#define PDC_SP_SYNC_RESET 1 -#define PDC_AUDIO_SYNC_RESET 2 -#define PDC_SENSORS_SYNC_RESET 3 -#define PDC_AOP_SYNC_RESET 4 -#define PDC_DEBUG_SYNC_RESET 5 -#define PDC_GPU_SYNC_RESET 6 -#define PDC_DISPLAY_SYNC_RESET 7 -#define PDC_COMPUTE_SYNC_RESET 8 -#define PDC_MODEM_SYNC_RESET 9 -#define PDC_WLAN_RF_SYNC_RESET 10 -#define PDC_WPSS_SYNC_RESET 11 - -#endif diff --git a/include/dt-bindings/reset/qcom,sm8350-videocc.h b/include/dt-bindings/reset/qcom,sm8350-videocc.h deleted file mode 100644 index cd356b207a4..00000000000 --- a/include/dt-bindings/reset/qcom,sm8350-videocc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H -#define _DT_BINDINGS_RESET_QCOM_VIDEO_CC_SM8350_H - -#define VIDEO_CC_CVP_INTERFACE_BCR 0 -#define VIDEO_CC_CVP_MVS0_BCR 1 -#define VIDEO_CC_MVS0C_CLK_ARES 2 -#define VIDEO_CC_CVP_MVS0C_BCR 3 -#define VIDEO_CC_CVP_MVS1_BCR 4 -#define VIDEO_CC_MVS1C_CLK_ARES 5 -#define VIDEO_CC_CVP_MVS1C_BCR 6 - -#endif diff --git a/include/dt-bindings/reset/qcom,sm8450-gpucc.h b/include/dt-bindings/reset/qcom,sm8450-gpucc.h deleted file mode 100644 index 58ba8f98710..00000000000 --- a/include/dt-bindings/reset/qcom,sm8450-gpucc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H -#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8450_H - -#define GPUCC_GPU_CC_ACD_BCR 0 -#define GPUCC_GPU_CC_CX_BCR 1 -#define GPUCC_GPU_CC_FAST_HUB_BCR 2 -#define GPUCC_GPU_CC_FF_BCR 3 -#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 -#define GPUCC_GPU_CC_GMU_BCR 5 -#define GPUCC_GPU_CC_GX_BCR 6 -#define GPUCC_GPU_CC_XO_BCR 7 -#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8 - -#endif diff --git a/include/dt-bindings/reset/qcom,sm8650-gpucc.h b/include/dt-bindings/reset/qcom,sm8650-gpucc.h deleted file mode 100644 index f021a6cccc6..00000000000 --- a/include/dt-bindings/reset/qcom,sm8650-gpucc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Linaro Limited - */ - -#ifndef _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H -#define _DT_BINDINGS_RESET_QCOM_GPU_CC_SM8650_H - -#define GPUCC_GPU_CC_ACD_BCR 0 -#define GPUCC_GPU_CC_CX_BCR 1 -#define GPUCC_GPU_CC_FAST_HUB_BCR 2 -#define GPUCC_GPU_CC_FF_BCR 3 -#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 -#define GPUCC_GPU_CC_GMU_BCR 5 -#define GPUCC_GPU_CC_GX_BCR 6 -#define GPUCC_GPU_CC_XO_BCR 7 -#define GPUCC_GPU_CC_GX_ACD_IROOT_BCR 8 - -#endif diff --git a/include/dt-bindings/reset/qcom,x1e80100-gpucc.h b/include/dt-bindings/reset/qcom,x1e80100-gpucc.h deleted file mode 100644 index 32b43e71a16..00000000000 --- a/include/dt-bindings/reset/qcom,x1e80100-gpucc.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H -#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H - -#define GPUCC_GPU_CC_ACD_BCR 0 -#define GPUCC_GPU_CC_CB_BCR 1 -#define GPUCC_GPU_CC_CX_BCR 2 -#define GPUCC_GPU_CC_FAST_HUB_BCR 3 -#define GPUCC_GPU_CC_FF_BCR 4 -#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 -#define GPUCC_GPU_CC_GMU_BCR 6 -#define GPUCC_GPU_CC_GX_BCR 7 -#define GPUCC_GPU_CC_XO_BCR 8 - -#endif diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h deleted file mode 100644 index 1a4f4c79272..00000000000 --- a/include/dt-bindings/reset/raspberrypi,firmware-reset.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 Nicolas Saenz Julienne - * Author: Nicolas Saenz Julienne <nsaenzjulienne@suse.com> - */ - -#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H -#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H - -#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0 -#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1 - -#endif diff --git a/include/dt-bindings/reset/realtek,rtd1195.h b/include/dt-bindings/reset/realtek,rtd1195.h deleted file mode 100644 index 27902abf935..00000000000 --- a/include/dt-bindings/reset/realtek,rtd1195.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ -/* - * Realtek RTD1195 reset controllers - * - * Copyright (c) 2017 Andreas Färber - */ -#ifndef DT_BINDINGS_RESET_RTD1195_H -#define DT_BINDINGS_RESET_RTD1195_H - -/* soft reset 1 */ -#define RTD1195_RSTN_MISC 0 -#define RTD1195_RSTN_RNG 1 -#define RTD1195_RSTN_USB3_POW 2 -#define RTD1195_RSTN_GSPI 3 -#define RTD1195_RSTN_USB3_P0_MDIO 4 -#define RTD1195_RSTN_VE_H265 5 -#define RTD1195_RSTN_USB 6 -#define RTD1195_RSTN_USB_PHY0 8 -#define RTD1195_RSTN_USB_PHY1 9 -#define RTD1195_RSTN_HDMIRX 11 -#define RTD1195_RSTN_HDMI 12 -#define RTD1195_RSTN_ETN 14 -#define RTD1195_RSTN_AIO 15 -#define RTD1195_RSTN_GPU 16 -#define RTD1195_RSTN_VE_H264 17 -#define RTD1195_RSTN_VE_JPEG 18 -#define RTD1195_RSTN_TVE 19 -#define RTD1195_RSTN_VO 20 -#define RTD1195_RSTN_LVDS 21 -#define RTD1195_RSTN_SE 22 -#define RTD1195_RSTN_DCU 23 -#define RTD1195_RSTN_DC_PHY 24 -#define RTD1195_RSTN_CP 25 -#define RTD1195_RSTN_MD 26 -#define RTD1195_RSTN_TP 27 -#define RTD1195_RSTN_AE 28 -#define RTD1195_RSTN_NF 29 -#define RTD1195_RSTN_MIPI 30 - -/* soft reset 2 */ -#define RTD1195_RSTN_ACPU 0 -#define RTD1195_RSTN_VCPU 1 -#define RTD1195_RSTN_PCR 9 -#define RTD1195_RSTN_CR 10 -#define RTD1195_RSTN_EMMC 11 -#define RTD1195_RSTN_SDIO 12 -#define RTD1195_RSTN_I2C_5 18 -#define RTD1195_RSTN_RTC 20 -#define RTD1195_RSTN_I2C_4 23 -#define RTD1195_RSTN_I2C_3 24 -#define RTD1195_RSTN_I2C_2 25 -#define RTD1195_RSTN_I2C_1 26 -#define RTD1195_RSTN_UR1 28 - -/* soft reset 3 */ -#define RTD1195_RSTN_SB2 0 - -/* iso soft reset */ -#define RTD1195_ISO_RSTN_VFD 0 -#define RTD1195_ISO_RSTN_IR 1 -#define RTD1195_ISO_RSTN_CEC0 2 -#define RTD1195_ISO_RSTN_CEC1 3 -#define RTD1195_ISO_RSTN_DP 4 -#define RTD1195_ISO_RSTN_CBUSTX 5 -#define RTD1195_ISO_RSTN_CBUSRX 6 -#define RTD1195_ISO_RSTN_EFUSE 7 -#define RTD1195_ISO_RSTN_UR0 8 -#define RTD1195_ISO_RSTN_GMAC 9 -#define RTD1195_ISO_RSTN_GPHY 10 -#define RTD1195_ISO_RSTN_I2C_0 11 -#define RTD1195_ISO_RSTN_I2C_6 12 -#define RTD1195_ISO_RSTN_CBUS 13 - -#endif diff --git a/include/dt-bindings/reset/realtek,rtd1295.h b/include/dt-bindings/reset/realtek,rtd1295.h deleted file mode 100644 index dd89e4c8026..00000000000 --- a/include/dt-bindings/reset/realtek,rtd1295.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ -/* - * Realtek RTD1295 reset controllers - * - * Copyright (c) 2017 Andreas Färber - */ -#ifndef DT_BINDINGS_RESET_RTD1295_H -#define DT_BINDINGS_RESET_RTD1295_H - -/* soft reset 1 */ -#define RTD1295_RSTN_MISC 0 -#define RTD1295_RSTN_NAT 1 -#define RTD1295_RSTN_USB3_PHY0_POW 2 -#define RTD1295_RSTN_GSPI 3 -#define RTD1295_RSTN_USB3_P0_MDIO 4 -#define RTD1295_RSTN_SATA_0 5 -#define RTD1295_RSTN_USB 6 -#define RTD1295_RSTN_SATA_PHY_0 7 -#define RTD1295_RSTN_USB_PHY0 8 -#define RTD1295_RSTN_USB_PHY1 9 -#define RTD1295_RSTN_SATA_PHY_POW_0 10 -#define RTD1295_RSTN_SATA_FUNC_EXIST_0 11 -#define RTD1295_RSTN_HDMI 12 -#define RTD1295_RSTN_VE1 13 -#define RTD1295_RSTN_VE2 14 -#define RTD1295_RSTN_VE3 15 -#define RTD1295_RSTN_ETN 16 -#define RTD1295_RSTN_AIO 17 -#define RTD1295_RSTN_GPU 18 -#define RTD1295_RSTN_TVE 19 -#define RTD1295_RSTN_VO 20 -#define RTD1295_RSTN_LVDS 21 -#define RTD1295_RSTN_SE 22 -#define RTD1295_RSTN_DCU 23 -#define RTD1295_RSTN_DC_PHY 24 -#define RTD1295_RSTN_CP 25 -#define RTD1295_RSTN_MD 26 -#define RTD1295_RSTN_TP 27 -#define RTD1295_RSTN_AE 28 -#define RTD1295_RSTN_NF 29 -#define RTD1295_RSTN_MIPI 30 -#define RTD1295_RSTN_RSA 31 - -/* soft reset 2 */ -#define RTD1295_RSTN_ACPU 0 -#define RTD1295_RSTN_JPEG 1 -#define RTD1295_RSTN_USB_PHY3 2 -#define RTD1295_RSTN_USB_PHY2 3 -#define RTD1295_RSTN_USB3_PHY1_POW 4 -#define RTD1295_RSTN_USB3_P1_MDIO 5 -#define RTD1295_RSTN_PCIE0_STITCH 6 -#define RTD1295_RSTN_PCIE0_PHY 7 -#define RTD1295_RSTN_PCIE0 8 -#define RTD1295_RSTN_PCR_CNT 9 -#define RTD1295_RSTN_CR 10 -#define RTD1295_RSTN_EMMC 11 -#define RTD1295_RSTN_SDIO 12 -#define RTD1295_RSTN_PCIE0_CORE 13 -#define RTD1295_RSTN_PCIE0_POWER 14 -#define RTD1295_RSTN_PCIE0_NONSTICH 15 -#define RTD1295_RSTN_PCIE1_PHY 16 -#define RTD1295_RSTN_PCIE1 17 -#define RTD1295_RSTN_I2C_5 18 -#define RTD1295_RSTN_PCIE1_STITCH 19 -#define RTD1295_RSTN_PCIE1_CORE 20 -#define RTD1295_RSTN_PCIE1_POWER 21 -#define RTD1295_RSTN_PCIE1_NONSTICH 22 -#define RTD1295_RSTN_I2C_4 23 -#define RTD1295_RSTN_I2C_3 24 -#define RTD1295_RSTN_I2C_2 25 -#define RTD1295_RSTN_I2C_1 26 -#define RTD1295_RSTN_UR2 27 -#define RTD1295_RSTN_UR1 28 -#define RTD1295_RSTN_MISC_SC 29 -#define RTD1295_RSTN_CBUS_TX 30 -#define RTD1295_RSTN_SDS_PHY 31 - -/* soft reset 3 */ -#define RTD1295_RSTN_SB2 0 - -/* soft reset 4 */ -#define RTD1295_RSTN_DCPHY_CRT 0 -#define RTD1295_RSTN_DCPHY_ALERT_RX 1 -#define RTD1295_RSTN_DCPHY_PTR 2 -#define RTD1295_RSTN_DCPHY_LDO 3 -#define RTD1295_RSTN_DCPHY_SSC_DIG 4 -#define RTD1295_RSTN_HDMIRX 5 -#define RTD1295_RSTN_CBUSRX 6 -#define RTD1295_RSTN_SATA_PHY_POW_1 7 -#define RTD1295_RSTN_SATA_FUNC_EXIST_1 8 -#define RTD1295_RSTN_SATA_PHY_1 9 -#define RTD1295_RSTN_SATA_1 10 -#define RTD1295_RSTN_FAN 11 -#define RTD1295_RSTN_HDMIRX_WRAP 12 -#define RTD1295_RSTN_PCIE0_PHY_MDIO 13 -#define RTD1295_RSTN_PCIE1_PHY_MDIO 14 -#define RTD1295_RSTN_DISP 15 - -/* iso reset */ -#define RTD1295_ISO_RSTN_IR 1 -#define RTD1295_ISO_RSTN_CEC0 2 -#define RTD1295_ISO_RSTN_CEC1 3 -#define RTD1295_ISO_RSTN_DP 4 -#define RTD1295_ISO_RSTN_CBUSTX 5 -#define RTD1295_ISO_RSTN_CBUSRX 6 -#define RTD1295_ISO_RSTN_EFUSE 7 -#define RTD1295_ISO_RSTN_UR0 8 -#define RTD1295_ISO_RSTN_GMAC 9 -#define RTD1295_ISO_RSTN_GPHY 10 -#define RTD1295_ISO_RSTN_I2C_0 11 -#define RTD1295_ISO_RSTN_I2C_1 12 -#define RTD1295_ISO_RSTN_CBUS 13 - -#endif diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-bindings/reset/rockchip,rk3528-cru.h deleted file mode 100644 index 6b024c5f2e1..00000000000 --- a/include/dt-bindings/reset/rockchip,rk3528-cru.h +++ /dev/null @@ -1,241 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Copyright (c) 2022 Rockchip Electronics Co. Ltd. - * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> - * Author: Joseph Chen <chenjh@rock-chips.com> - */ - -#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H -#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H - -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_NL2 8 -#define SRST_CORE_BIU 9 -#define SRST_CORE_CRYPTO 10 -#define SRST_P_DBG 11 -#define SRST_POT_DBG 12 -#define SRST_NT_DBG 13 -#define SRST_P_CORE_GRF 14 -#define SRST_P_DAPLITE_BIU 15 -#define SRST_P_CPU_BIU 16 -#define SRST_REF_PVTPLL_CORE 17 -#define SRST_A_BUS_VOPGL_BIU 18 -#define SRST_A_BUS_H_BIU 19 -#define SRST_A_SYSMEM_BIU 20 -#define SRST_A_BUS_BIU 21 -#define SRST_H_BUS_BIU 22 -#define SRST_P_BUS_BIU 23 -#define SRST_P_DFT2APB 24 -#define SRST_P_BUS_GRF 25 -#define SRST_A_BUS_M_BIU 26 -#define SRST_A_GIC 27 -#define SRST_A_SPINLOCK 28 -#define SRST_A_DMAC 29 -#define SRST_P_TIMER 30 -#define SRST_TIMER0 31 -#define SRST_TIMER1 32 -#define SRST_TIMER2 33 -#define SRST_TIMER3 34 -#define SRST_TIMER4 35 -#define SRST_TIMER5 36 -#define SRST_P_JDBCK_DAP 37 -#define SRST_JDBCK_DAP 38 -#define SRST_P_WDT_NS 39 -#define SRST_T_WDT_NS 40 -#define SRST_H_TRNG_NS 41 -#define SRST_P_UART0 42 -#define SRST_S_UART0 43 -#define SRST_PKA_CRYPTO 44 -#define SRST_A_CRYPTO 45 -#define SRST_H_CRYPTO 46 -#define SRST_P_DMA2DDR 47 -#define SRST_A_DMA2DDR 48 -#define SRST_P_PWM0 49 -#define SRST_PWM0 50 -#define SRST_P_PWM1 51 -#define SRST_PWM1 52 -#define SRST_P_SCR 53 -#define SRST_A_DCF 54 -#define SRST_P_INTMUX 55 -#define SRST_A_VPU_BIU 56 -#define SRST_H_VPU_BIU 57 -#define SRST_P_VPU_BIU 58 -#define SRST_A_VPU 59 -#define SRST_H_VPU 60 -#define SRST_P_CRU_PCIE 61 -#define SRST_P_VPU_GRF 62 -#define SRST_H_SFC 63 -#define SRST_S_SFC 64 -#define SRST_C_EMMC 65 -#define SRST_H_EMMC 66 -#define SRST_A_EMMC 67 -#define SRST_B_EMMC 68 -#define SRST_T_EMMC 69 -#define SRST_P_GPIO1 70 -#define SRST_DB_GPIO1 71 -#define SRST_A_VPU_L_BIU 72 -#define SRST_P_VPU_IOC 73 -#define SRST_H_SAI_I2S0 74 -#define SRST_M_SAI_I2S0 75 -#define SRST_H_SAI_I2S2 76 -#define SRST_M_SAI_I2S2 77 -#define SRST_P_ACODEC 78 -#define SRST_P_GPIO3 79 -#define SRST_DB_GPIO3 80 -#define SRST_P_SPI1 81 -#define SRST_SPI1 82 -#define SRST_P_UART2 83 -#define SRST_S_UART2 84 -#define SRST_P_UART5 85 -#define SRST_S_UART5 86 -#define SRST_P_UART6 87 -#define SRST_S_UART6 88 -#define SRST_P_UART7 89 -#define SRST_S_UART7 90 -#define SRST_P_I2C3 91 -#define SRST_I2C3 92 -#define SRST_P_I2C5 93 -#define SRST_I2C5 94 -#define SRST_P_I2C6 95 -#define SRST_I2C6 96 -#define SRST_A_MAC 97 -#define SRST_P_PCIE 98 -#define SRST_PCIE_PIPE_PHY 99 -#define SRST_PCIE_POWER_UP 100 -#define SRST_P_PCIE_PHY 101 -#define SRST_P_PIPE_GRF 102 -#define SRST_H_SDIO0 103 -#define SRST_H_SDIO1 104 -#define SRST_TS_0 105 -#define SRST_TS_1 106 -#define SRST_P_CAN2 107 -#define SRST_CAN2 108 -#define SRST_P_CAN3 109 -#define SRST_CAN3 110 -#define SRST_P_SARADC 111 -#define SRST_SARADC 112 -#define SRST_SARADC_PHY 113 -#define SRST_P_TSADC 114 -#define SRST_TSADC 115 -#define SRST_A_USB3OTG 116 -#define SRST_A_GPU_BIU 117 -#define SRST_P_GPU_BIU 118 -#define SRST_A_GPU 119 -#define SRST_REF_PVTPLL_GPU 120 -#define SRST_H_RKVENC_BIU 121 -#define SRST_A_RKVENC_BIU 122 -#define SRST_P_RKVENC_BIU 123 -#define SRST_H_RKVENC 124 -#define SRST_A_RKVENC 125 -#define SRST_CORE_RKVENC 126 -#define SRST_H_SAI_I2S1 127 -#define SRST_M_SAI_I2S1 128 -#define SRST_P_I2C1 129 -#define SRST_I2C1 130 -#define SRST_P_I2C0 131 -#define SRST_I2C0 132 -#define SRST_P_SPI0 133 -#define SRST_SPI0 134 -#define SRST_P_GPIO4 135 -#define SRST_DB_GPIO4 136 -#define SRST_P_RKVENC_IOC 137 -#define SRST_H_SPDIF 138 -#define SRST_M_SPDIF 139 -#define SRST_H_PDM 140 -#define SRST_M_PDM 141 -#define SRST_P_UART1 142 -#define SRST_S_UART1 143 -#define SRST_P_UART3 144 -#define SRST_S_UART3 145 -#define SRST_P_RKVENC_GRF 146 -#define SRST_P_CAN0 147 -#define SRST_CAN0 148 -#define SRST_P_CAN1 149 -#define SRST_CAN1 150 -#define SRST_A_VO_BIU 151 -#define SRST_H_VO_BIU 152 -#define SRST_P_VO_BIU 153 -#define SRST_H_RGA2E 154 -#define SRST_A_RGA2E 155 -#define SRST_CORE_RGA2E 156 -#define SRST_H_VDPP 157 -#define SRST_A_VDPP 158 -#define SRST_CORE_VDPP 159 -#define SRST_P_VO_GRF 160 -#define SRST_P_CRU 161 -#define SRST_A_VOP_BIU 162 -#define SRST_H_VOP 163 -#define SRST_D_VOP0 164 -#define SRST_D_VOP1 165 -#define SRST_A_VOP 166 -#define SRST_P_HDMI 167 -#define SRST_HDMI 168 -#define SRST_P_HDMIPHY 169 -#define SRST_H_HDCP_KEY 170 -#define SRST_A_HDCP 171 -#define SRST_H_HDCP 172 -#define SRST_P_HDCP 173 -#define SRST_H_CVBS 174 -#define SRST_D_CVBS_VOP 175 -#define SRST_D_4X_CVBS_VOP 176 -#define SRST_A_JPEG_DECODER 177 -#define SRST_H_JPEG_DECODER 178 -#define SRST_A_VO_L_BIU 179 -#define SRST_A_MAC_VO 180 -#define SRST_A_JPEG_BIU 181 -#define SRST_H_SAI_I2S3 182 -#define SRST_M_SAI_I2S3 183 -#define SRST_MACPHY 184 -#define SRST_P_VCDCPHY 185 -#define SRST_P_GPIO2 186 -#define SRST_DB_GPIO2 187 -#define SRST_P_VO_IOC 188 -#define SRST_H_SDMMC0 189 -#define SRST_P_OTPC_NS 190 -#define SRST_SBPI_OTPC_NS 191 -#define SRST_USER_OTPC_NS 192 -#define SRST_HDMIHDP0 193 -#define SRST_H_USBHOST 194 -#define SRST_H_USBHOST_ARB 195 -#define SRST_HOST_UTMI 196 -#define SRST_P_UART4 197 -#define SRST_S_UART4 198 -#define SRST_P_I2C4 199 -#define SRST_I2C4 200 -#define SRST_P_I2C7 201 -#define SRST_I2C7 202 -#define SRST_P_USBPHY 203 -#define SRST_USBPHY_POR 204 -#define SRST_USBPHY_OTG 205 -#define SRST_USBPHY_HOST 206 -#define SRST_P_DDRPHY_CRU 207 -#define SRST_H_RKVDEC_BIU 208 -#define SRST_A_RKVDEC_BIU 209 -#define SRST_A_RKVDEC 210 -#define SRST_H_RKVDEC 211 -#define SRST_HEVC_CA_RKVDEC 212 -#define SRST_REF_PVTPLL_RKVDEC 213 -#define SRST_P_DDR_BIU 214 -#define SRST_P_DDRC 215 -#define SRST_P_DDRMON 216 -#define SRST_TIMER_DDRMON 217 -#define SRST_P_MSCH_BIU 218 -#define SRST_P_DDR_GRF 219 -#define SRST_P_DDR_HWLP 220 -#define SRST_P_DDRPHY 221 -#define SRST_MSCH_BIU 222 -#define SRST_A_DDR_UPCTL 223 -#define SRST_DDR_UPCTL 224 -#define SRST_DDRMON 225 -#define SRST_A_DDR_SCRAMBLE 226 -#define SRST_A_SPLIT 227 -#define SRST_DDR_PHY 228 - -#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/reset/rockchip,rk3562-cru.h b/include/dt-bindings/reset/rockchip,rk3562-cru.h deleted file mode 100644 index 8df95113056..00000000000 --- a/include/dt-bindings/reset/rockchip,rk3562-cru.h +++ /dev/null @@ -1,358 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd. - * - * Author: Elaine Zhang <zhangqing@rock-chips.com> - */ - -#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H -#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H - -/********Name=SOFTRST_CON01,Offset=0x404********/ -#define SRST_A_TOP_BIU 0 -#define SRST_A_TOP_VIO_BIU 1 -#define SRST_REF_PVTPLL_LOGIC 2 -/********Name=SOFTRST_CON03,Offset=0x40C********/ -#define SRST_NCOREPORESET0 3 -#define SRST_NCOREPORESET1 4 -#define SRST_NCOREPORESET2 5 -#define SRST_NCOREPORESET3 6 -#define SRST_NCORESET0 7 -#define SRST_NCORESET1 8 -#define SRST_NCORESET2 9 -#define SRST_NCORESET3 10 -#define SRST_NL2RESET 11 -/********Name=SOFTRST_CON04,Offset=0x410********/ -#define SRST_DAP 12 -#define SRST_P_DBG_DAPLITE 13 -#define SRST_REF_PVTPLL_CORE 14 -/********Name=SOFTRST_CON05,Offset=0x414********/ -#define SRST_A_CORE_BIU 15 -#define SRST_P_CORE_BIU 16 -#define SRST_H_CORE_BIU 17 -/********Name=SOFTRST_CON06,Offset=0x418********/ -#define SRST_A_NPU_BIU 18 -#define SRST_H_NPU_BIU 19 -#define SRST_A_RKNN 20 -#define SRST_H_RKNN 21 -#define SRST_REF_PVTPLL_NPU 22 -/********Name=SOFTRST_CON08,Offset=0x420********/ -#define SRST_A_GPU_BIU 23 -#define SRST_GPU 24 -#define SRST_REF_PVTPLL_GPU 25 -#define SRST_GPU_BRG_BIU 26 -/********Name=SOFTRST_CON09,Offset=0x424********/ -#define SRST_RKVENC_CORE 27 -#define SRST_A_VEPU_BIU 28 -#define SRST_H_VEPU_BIU 29 -#define SRST_A_RKVENC 30 -#define SRST_H_RKVENC 31 -/********Name=SOFTRST_CON10,Offset=0x428********/ -#define SRST_RKVDEC_HEVC_CA 32 -#define SRST_A_VDPU_BIU 33 -#define SRST_H_VDPU_BIU 34 -#define SRST_A_RKVDEC 35 -#define SRST_H_RKVDEC 36 -/********Name=SOFTRST_CON11,Offset=0x42C********/ -#define SRST_A_VI_BIU 37 -#define SRST_H_VI_BIU 38 -#define SRST_P_VI_BIU 39 -#define SRST_ISP 40 -#define SRST_A_VICAP 41 -#define SRST_H_VICAP 42 -#define SRST_D_VICAP 43 -#define SRST_I0_VICAP 44 -#define SRST_I1_VICAP 45 -#define SRST_I2_VICAP 46 -#define SRST_I3_VICAP 47 -/********Name=SOFTRST_CON12,Offset=0x430********/ -#define SRST_P_CSIHOST0 48 -#define SRST_P_CSIHOST1 49 -#define SRST_P_CSIHOST2 50 -#define SRST_P_CSIHOST3 51 -#define SRST_P_CSIPHY0 52 -#define SRST_P_CSIPHY1 53 -/********Name=SOFTRST_CON13,Offset=0x434********/ -#define SRST_A_VO_BIU 54 -#define SRST_H_VO_BIU 55 -#define SRST_A_VOP 56 -#define SRST_H_VOP 57 -#define SRST_D_VOP 58 -#define SRST_D_VOP1 59 -/********Name=SOFTRST_CON14,Offset=0x438********/ -#define SRST_A_RGA_BIU 60 -#define SRST_H_RGA_BIU 61 -#define SRST_A_RGA 62 -#define SRST_H_RGA 63 -#define SRST_RGA_CORE 64 -#define SRST_A_JDEC 65 -#define SRST_H_JDEC 66 -/********Name=SOFTRST_CON15,Offset=0x43C********/ -#define SRST_B_EBK_BIU 67 -#define SRST_P_EBK_BIU 68 -#define SRST_AHB2AXI_EBC 69 -#define SRST_H_EBC 70 -#define SRST_D_EBC 71 -#define SRST_H_EINK 72 -#define SRST_P_EINK 73 -/********Name=SOFTRST_CON16,Offset=0x440********/ -#define SRST_P_PHP_BIU 74 -#define SRST_A_PHP_BIU 75 -#define SRST_P_PCIE20 76 -#define SRST_PCIE20_POWERUP 77 -#define SRST_USB3OTG 78 -/********Name=SOFTRST_CON17,Offset=0x444********/ -#define SRST_PIPEPHY 79 -/********Name=SOFTRST_CON18,Offset=0x448********/ -#define SRST_A_BUS_BIU 80 -#define SRST_H_BUS_BIU 81 -#define SRST_P_BUS_BIU 82 -/********Name=SOFTRST_CON19,Offset=0x44C********/ -#define SRST_P_I2C1 83 -#define SRST_P_I2C2 84 -#define SRST_P_I2C3 85 -#define SRST_P_I2C4 86 -#define SRST_P_I2C5 87 -#define SRST_I2C1 88 -#define SRST_I2C2 89 -#define SRST_I2C3 90 -#define SRST_I2C4 91 -#define SRST_I2C5 92 -/********Name=SOFTRST_CON20,Offset=0x450********/ -#define SRST_BUS_GPIO3 93 -#define SRST_BUS_GPIO4 94 -/********Name=SOFTRST_CON21,Offset=0x454********/ -#define SRST_P_TIMER 95 -#define SRST_TIMER0 96 -#define SRST_TIMER1 97 -#define SRST_TIMER2 98 -#define SRST_TIMER3 99 -#define SRST_TIMER4 100 -#define SRST_TIMER5 101 -#define SRST_P_STIMER 102 -#define SRST_STIMER0 103 -#define SRST_STIMER1 104 -/********Name=SOFTRST_CON22,Offset=0x458********/ -#define SRST_P_WDTNS 105 -#define SRST_WDTNS 106 -#define SRST_P_GRF 107 -#define SRST_P_SGRF 108 -#define SRST_P_MAILBOX 109 -#define SRST_P_INTC 110 -#define SRST_A_BUS_GIC400 111 -#define SRST_A_BUS_GIC400_DEBUG 112 -/********Name=SOFTRST_CON23,Offset=0x45C********/ -#define SRST_A_BUS_SPINLOCK 113 -#define SRST_A_DCF 114 -#define SRST_P_DCF 115 -#define SRST_F_BUS_CM0_CORE 116 -#define SRST_T_BUS_CM0_JTAG 117 -#define SRST_H_ICACHE 118 -#define SRST_H_DCACHE 119 -/********Name=SOFTRST_CON24,Offset=0x460********/ -#define SRST_P_TSADC 120 -#define SRST_TSADC 121 -#define SRST_TSADCPHY 122 -#define SRST_P_DFT2APB 123 -/********Name=SOFTRST_CON25,Offset=0x464********/ -#define SRST_A_GMAC 124 -#define SRST_P_APB2ASB_VCCIO156 125 -#define SRST_P_DSIPHY 126 -#define SRST_P_DSITX 127 -#define SRST_P_CPU_EMA_DET 128 -#define SRST_P_HASH 129 -#define SRST_P_TOPCRU 130 -/********Name=SOFTRST_CON26,Offset=0x468********/ -#define SRST_P_ASB2APB_VCCIO156 131 -#define SRST_P_IOC_VCCIO156 132 -#define SRST_P_GPIO3_VCCIO156 133 -#define SRST_P_GPIO4_VCCIO156 134 -#define SRST_P_SARADC_VCCIO156 135 -#define SRST_SARADC_VCCIO156 136 -#define SRST_SARADC_VCCIO156_PHY 137 -/********Name=SOFTRST_CON27,Offset=0x46c********/ -#define SRST_A_MAC100 138 - -/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/ -#define SRST_P_PMU0_CRU 139 -#define SRST_P_PMU0_PMU 140 -#define SRST_PMU0_PMU 141 -#define SRST_P_PMU0_HP_TIMER 142 -#define SRST_PMU0_HP_TIMER 143 -#define SRST_PMU0_32K_HP_TIMER 144 -#define SRST_P_PMU0_PVTM 145 -#define SRST_PMU0_PVTM 146 -#define SRST_P_IOC_PMUIO 147 -#define SRST_P_PMU0_GPIO0 148 -#define SRST_PMU0_GPIO0 149 -#define SRST_P_PMU0_GRF 150 -#define SRST_P_PMU0_SGRF 151 -/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/ -#define SRST_DDR_FAIL_SAFE 152 -#define SRST_P_PMU0_SCRKEYGEN 153 -/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/ -#define SRST_P_PMU0_I2C0 154 -#define SRST_PMU0_I2C0 155 - -/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/ -#define SRST_P_PMU1_CRU 156 -#define SRST_H_PMU1_MEM 157 -#define SRST_H_PMU1_BIU 158 -#define SRST_P_PMU1_BIU 159 -#define SRST_P_PMU1_UART0 160 -#define SRST_S_PMU1_UART0 161 -/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/ -#define SRST_P_PMU1_SPI0 162 -#define SRST_PMU1_SPI0 163 -#define SRST_P_PMU1_PWM0 164 -#define SRST_PMU1_PWM0 165 -/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/ -#define SRST_F_PMU1_CM0_CORE 166 -#define SRST_T_PMU1_CM0_JTAG 167 -#define SRST_P_PMU1_WDTNS 168 -#define SRST_PMU1_WDTNS 169 -#define SRST_PMU1_MAILBOX 170 - -/********Name=DDRSOFTRST_CON00,Offset=0x20200********/ -#define SRST_MSCH_BRG_BIU 171 -#define SRST_P_MSCH_BIU 172 -#define SRST_P_DDR_HWLP 173 -#define SRST_P_DDR_PHY 290 -#define SRST_P_DDR_DFICTL 174 -#define SRST_P_DDR_DMA2DDR 175 -/********Name=DDRSOFTRST_CON01,Offset=0x20204********/ -#define SRST_P_DDR_MON 176 -#define SRST_TM_DDR_MON 177 -#define SRST_P_DDR_GRF 178 -#define SRST_P_DDR_CRU 179 -#define SRST_P_SUBDDR_CRU 180 - -/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/ -#define SRST_MSCH_BIU 181 -#define SRST_DDR_PHY 182 -#define SRST_DDR_DFICTL 183 -#define SRST_DDR_SCRAMBLE 184 -#define SRST_DDR_MON 185 -#define SRST_A_DDR_SPLIT 186 -#define SRST_DDR_DMA2DDR 187 - -/********Name=PERISOFTRST_CON01,Offset=0x30404********/ -#define SRST_A_PERI_BIU 188 -#define SRST_H_PERI_BIU 189 -#define SRST_P_PERI_BIU 190 -#define SRST_P_PERICRU 191 -/********Name=PERISOFTRST_CON02,Offset=0x30408********/ -#define SRST_H_SAI0_8CH 192 -#define SRST_M_SAI0_8CH 193 -#define SRST_H_SAI1_8CH 194 -#define SRST_M_SAI1_8CH 195 -#define SRST_H_SAI2_2CH 196 -#define SRST_M_SAI2_2CH 197 -/********Name=PERISOFTRST_CON03,Offset=0x3040C********/ -#define SRST_H_DSM 198 -#define SRST_DSM 199 -#define SRST_H_PDM 200 -#define SRST_M_PDM 201 -#define SRST_H_SPDIF 202 -#define SRST_M_SPDIF 203 -/********Name=PERISOFTRST_CON04,Offset=0x30410********/ -#define SRST_H_SDMMC0 204 -#define SRST_H_SDMMC1 205 -#define SRST_H_EMMC 206 -#define SRST_A_EMMC 207 -#define SRST_C_EMMC 208 -#define SRST_B_EMMC 209 -#define SRST_T_EMMC 210 -#define SRST_S_SFC 211 -#define SRST_H_SFC 212 -/********Name=PERISOFTRST_CON05,Offset=0x30414********/ -#define SRST_H_USB2HOST 213 -#define SRST_H_USB2HOST_ARB 214 -#define SRST_USB2HOST_UTMI 215 -/********Name=PERISOFTRST_CON06,Offset=0x30418********/ -#define SRST_P_SPI1 216 -#define SRST_SPI1 217 -#define SRST_P_SPI2 218 -#define SRST_SPI2 219 -/********Name=PERISOFTRST_CON07,Offset=0x3041C********/ -#define SRST_P_UART1 220 -#define SRST_P_UART2 221 -#define SRST_P_UART3 222 -#define SRST_P_UART4 223 -#define SRST_P_UART5 224 -#define SRST_P_UART6 225 -#define SRST_P_UART7 226 -#define SRST_P_UART8 227 -#define SRST_P_UART9 228 -#define SRST_S_UART1 229 -#define SRST_S_UART2 230 -/********Name=PERISOFTRST_CON08,Offset=0x30420********/ -#define SRST_S_UART3 231 -#define SRST_S_UART4 232 -#define SRST_S_UART5 233 -#define SRST_S_UART6 234 -#define SRST_S_UART7 235 -/********Name=PERISOFTRST_CON09,Offset=0x30424********/ -#define SRST_S_UART8 236 -#define SRST_S_UART9 237 -/********Name=PERISOFTRST_CON10,Offset=0x30428********/ -#define SRST_P_PWM1_PERI 238 -#define SRST_PWM1_PERI 239 -#define SRST_P_PWM2_PERI 240 -#define SRST_PWM2_PERI 241 -#define SRST_P_PWM3_PERI 242 -#define SRST_PWM3_PERI 243 -/********Name=PERISOFTRST_CON11,Offset=0x3042C********/ -#define SRST_P_CAN0 244 -#define SRST_CAN0 245 -#define SRST_P_CAN1 246 -#define SRST_CAN1 247 -/********Name=PERISOFTRST_CON12,Offset=0x30430********/ -#define SRST_A_CRYPTO 248 -#define SRST_H_CRYPTO 249 -#define SRST_P_CRYPTO 250 -#define SRST_CORE_CRYPTO 251 -#define SRST_PKA_CRYPTO 252 -#define SRST_H_KLAD 253 -#define SRST_P_KEY_READER 254 -#define SRST_H_RK_RNG_NS 255 -#define SRST_H_RK_RNG_S 256 -#define SRST_H_TRNG_NS 257 -#define SRST_H_TRNG_S 258 -#define SRST_H_CRYPTO_S 259 -/********Name=PERISOFTRST_CON13,Offset=0x30434********/ -#define SRST_P_PERI_WDT 260 -#define SRST_T_PERI_WDT 261 -#define SRST_A_SYSMEM 262 -#define SRST_H_BOOTROM 263 -#define SRST_P_PERI_GRF 264 -#define SRST_A_DMAC 265 -#define SRST_A_RKDMAC 267 -/********Name=PERISOFTRST_CON14,Offset=0x30438********/ -#define SRST_P_OTPC_NS 268 -#define SRST_SBPI_OTPC_NS 269 -#define SRST_USER_OTPC_NS 270 -#define SRST_P_OTPC_S 271 -#define SRST_SBPI_OTPC_S 272 -#define SRST_USER_OTPC_S 273 -#define SRST_OTPC_ARB 274 -#define SRST_P_OTPPHY 275 -#define SRST_OTP_NPOR 276 -/********Name=PERISOFTRST_CON15,Offset=0x3043C********/ -#define SRST_P_USB2PHY 277 -#define SRST_USB2PHY_POR 278 -#define SRST_USB2PHY_OTG 279 -#define SRST_USB2PHY_HOST 280 -#define SRST_P_PIPEPHY 281 -/********Name=PERISOFTRST_CON16,Offset=0x30440********/ -#define SRST_P_SARADC 282 -#define SRST_SARADC 283 -#define SRST_SARADC_PHY 284 -#define SRST_P_IOC_VCCIO234 285 -/********Name=PERISOFTRST_CON17,Offset=0x30444********/ -#define SRST_P_PERI_GPIO1 286 -#define SRST_P_PERI_GPIO2 287 -#define SRST_PERI_GPIO1 288 -#define SRST_PERI_GPIO2 289 - -#endif diff --git a/include/dt-bindings/reset/rockchip,rk3576-cru.h b/include/dt-bindings/reset/rockchip,rk3576-cru.h deleted file mode 100644 index ae856906f3a..00000000000 --- a/include/dt-bindings/reset/rockchip,rk3576-cru.h +++ /dev/null @@ -1,564 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2023 Rockchip Electronics Co. Ltd. - * Copyright (c) 2024 Collabora Ltd. - * - * Author: Elaine Zhang <zhangqing@rock-chips.com> - * Author: Detlev Casanova <detlev.casanova@collabora.com> - */ - -#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H -#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H - -#define SRST_A_TOP_BIU 0 -#define SRST_P_TOP_BIU 1 -#define SRST_A_TOP_MID_BIU 2 -#define SRST_A_SECURE_HIGH_BIU 3 -#define SRST_H_TOP_BIU 4 - -#define SRST_H_VO0VOP_CHANNEL_BIU 5 -#define SRST_A_VO0VOP_CHANNEL_BIU 6 - -#define SRST_BISRINTF 7 - -#define SRST_H_AUDIO_BIU 8 -#define SRST_H_ASRC_2CH_0 9 -#define SRST_H_ASRC_2CH_1 10 -#define SRST_H_ASRC_4CH_0 11 -#define SRST_H_ASRC_4CH_1 12 -#define SRST_ASRC_2CH_0 13 -#define SRST_ASRC_2CH_1 14 -#define SRST_ASRC_4CH_0 15 -#define SRST_ASRC_4CH_1 16 -#define SRST_M_SAI0_8CH 17 -#define SRST_H_SAI0_8CH 18 -#define SRST_H_SPDIF_RX0 19 -#define SRST_M_SPDIF_RX0 20 - -#define SRST_H_SPDIF_RX1 21 -#define SRST_M_SPDIF_RX1 22 -#define SRST_M_SAI1_8CH 23 -#define SRST_H_SAI1_8CH 24 -#define SRST_M_SAI2_2CH 25 -#define SRST_H_SAI2_2CH 26 -#define SRST_M_SAI3_2CH 27 -#define SRST_H_SAI3_2CH 28 - -#define SRST_M_SAI4_2CH 29 -#define SRST_H_SAI4_2CH 30 -#define SRST_H_ACDCDIG_DSM 31 -#define SRST_M_ACDCDIG_DSM 32 -#define SRST_PDM1 33 -#define SRST_H_PDM1 34 -#define SRST_M_PDM1 35 -#define SRST_H_SPDIF_TX0 36 -#define SRST_M_SPDIF_TX0 37 -#define SRST_H_SPDIF_TX1 38 -#define SRST_M_SPDIF_TX1 39 - -#define SRST_A_BUS_BIU 40 -#define SRST_P_BUS_BIU 41 -#define SRST_P_CRU 42 -#define SRST_H_CAN0 43 -#define SRST_CAN0 44 -#define SRST_H_CAN1 45 -#define SRST_CAN1 46 -#define SRST_P_INTMUX2BUS 47 -#define SRST_P_VCCIO_IOC 48 -#define SRST_H_BUS_BIU 49 -#define SRST_KEY_SHIFT 50 - -#define SRST_P_I2C1 51 -#define SRST_P_I2C2 52 -#define SRST_P_I2C3 53 -#define SRST_P_I2C4 54 -#define SRST_P_I2C5 55 -#define SRST_P_I2C6 56 -#define SRST_P_I2C7 57 -#define SRST_P_I2C8 58 -#define SRST_P_I2C9 59 -#define SRST_P_WDT_BUSMCU 60 -#define SRST_T_WDT_BUSMCU 61 -#define SRST_A_GIC 62 -#define SRST_I2C1 63 -#define SRST_I2C2 64 -#define SRST_I2C3 65 -#define SRST_I2C4 66 - -#define SRST_I2C5 67 -#define SRST_I2C6 68 -#define SRST_I2C7 69 -#define SRST_I2C8 70 -#define SRST_I2C9 71 -#define SRST_P_SARADC 72 -#define SRST_SARADC 73 -#define SRST_P_TSADC 74 -#define SRST_TSADC 75 -#define SRST_P_UART0 76 -#define SRST_P_UART2 77 -#define SRST_P_UART3 78 -#define SRST_P_UART4 79 -#define SRST_P_UART5 80 -#define SRST_P_UART6 81 - -#define SRST_P_UART7 82 -#define SRST_P_UART8 83 -#define SRST_P_UART9 84 -#define SRST_P_UART10 85 -#define SRST_P_UART11 86 -#define SRST_S_UART0 87 -#define SRST_S_UART2 88 -#define SRST_S_UART3 89 -#define SRST_S_UART4 90 -#define SRST_S_UART5 91 - -#define SRST_S_UART6 92 -#define SRST_S_UART7 93 -#define SRST_S_UART8 94 -#define SRST_S_UART9 95 -#define SRST_S_UART10 96 -#define SRST_S_UART11 97 -#define SRST_P_SPI0 98 -#define SRST_P_SPI1 99 -#define SRST_P_SPI2 100 - -#define SRST_P_SPI3 101 -#define SRST_P_SPI4 102 -#define SRST_SPI0 103 -#define SRST_SPI1 104 -#define SRST_SPI2 105 -#define SRST_SPI3 106 -#define SRST_SPI4 107 -#define SRST_P_WDT0 108 -#define SRST_T_WDT0 109 -#define SRST_P_SYS_GRF 110 -#define SRST_P_PWM1 111 -#define SRST_PWM1 112 - -#define SRST_P_BUSTIMER0 113 -#define SRST_P_BUSTIMER1 114 -#define SRST_TIMER0 115 -#define SRST_TIMER1 116 -#define SRST_TIMER2 117 -#define SRST_TIMER3 118 -#define SRST_TIMER4 119 -#define SRST_TIMER5 120 -#define SRST_P_BUSIOC 121 -#define SRST_P_MAILBOX0 122 -#define SRST_P_GPIO1 123 - -#define SRST_GPIO1 124 -#define SRST_P_GPIO2 125 -#define SRST_GPIO2 126 -#define SRST_P_GPIO3 127 -#define SRST_GPIO3 128 -#define SRST_P_GPIO4 129 -#define SRST_GPIO4 130 -#define SRST_A_DECOM 131 -#define SRST_P_DECOM 132 -#define SRST_D_DECOM 133 -#define SRST_TIMER6 134 -#define SRST_TIMER7 135 -#define SRST_TIMER8 136 -#define SRST_TIMER9 137 -#define SRST_TIMER10 138 - -#define SRST_TIMER11 139 -#define SRST_A_DMAC0 140 -#define SRST_A_DMAC1 141 -#define SRST_A_DMAC2 142 -#define SRST_A_SPINLOCK 143 -#define SRST_REF_PVTPLL_BUS 144 -#define SRST_H_I3C0 145 -#define SRST_H_I3C1 146 -#define SRST_H_BUS_CM0_BIU 147 -#define SRST_F_BUS_CM0_CORE 148 -#define SRST_T_BUS_CM0_JTAG 149 - -#define SRST_P_INTMUX2PMU 150 -#define SRST_P_INTMUX2DDR 151 -#define SRST_P_PVTPLL_BUS 152 -#define SRST_P_PWM2 153 -#define SRST_PWM2 154 -#define SRST_FREQ_PWM1 155 -#define SRST_COUNTER_PWM1 156 -#define SRST_I3C0 157 -#define SRST_I3C1 158 - -#define SRST_P_DDR_MON_CH0 159 -#define SRST_P_DDR_BIU 160 -#define SRST_P_DDR_UPCTL_CH0 161 -#define SRST_TM_DDR_MON_CH0 162 -#define SRST_A_DDR_BIU 163 -#define SRST_DFI_CH0 164 -#define SRST_DDR_MON_CH0 165 -#define SRST_P_DDR_HWLP_CH0 166 -#define SRST_P_DDR_MON_CH1 167 -#define SRST_P_DDR_HWLP_CH1 168 - -#define SRST_P_DDR_UPCTL_CH1 169 -#define SRST_TM_DDR_MON_CH1 170 -#define SRST_DFI_CH1 171 -#define SRST_A_DDR01_MSCH0 172 -#define SRST_A_DDR01_MSCH1 173 -#define SRST_DDR_MON_CH1 174 -#define SRST_DDR_SCRAMBLE_CH0 175 -#define SRST_DDR_SCRAMBLE_CH1 176 -#define SRST_P_AHB2APB 177 -#define SRST_H_AHB2APB 178 -#define SRST_H_DDR_BIU 179 -#define SRST_F_DDR_CM0_CORE 180 - -#define SRST_P_DDR01_MSCH0 181 -#define SRST_P_DDR01_MSCH1 182 -#define SRST_DDR_TIMER0 183 -#define SRST_DDR_TIMER1 184 -#define SRST_T_WDT_DDR 185 -#define SRST_P_WDT 186 -#define SRST_P_TIMER 187 -#define SRST_T_DDR_CM0_JTAG 188 -#define SRST_P_DDR_GRF 189 - -#define SRST_DDR_UPCTL_CH0 190 -#define SRST_A_DDR_UPCTL_0_CH0 191 -#define SRST_A_DDR_UPCTL_1_CH0 192 -#define SRST_A_DDR_UPCTL_2_CH0 193 -#define SRST_A_DDR_UPCTL_3_CH0 194 -#define SRST_A_DDR_UPCTL_4_CH0 195 - -#define SRST_DDR_UPCTL_CH1 196 -#define SRST_A_DDR_UPCTL_0_CH1 197 -#define SRST_A_DDR_UPCTL_1_CH1 198 -#define SRST_A_DDR_UPCTL_2_CH1 199 -#define SRST_A_DDR_UPCTL_3_CH1 200 -#define SRST_A_DDR_UPCTL_4_CH1 201 - -#define SRST_REF_PVTPLL_DDR 202 -#define SRST_P_PVTPLL_DDR 203 - -#define SRST_A_RKNN0 204 -#define SRST_A_RKNN0_BIU 205 -#define SRST_L_RKNN0_BIU 206 - -#define SRST_A_RKNN1 207 -#define SRST_A_RKNN1_BIU 208 -#define SRST_L_RKNN1_BIU 209 - -#define SRST_NPU_DAP 210 -#define SRST_L_NPUSUBSYS_BIU 211 -#define SRST_P_NPUTOP_BIU 212 -#define SRST_P_NPU_TIMER 213 -#define SRST_NPUTIMER0 214 -#define SRST_NPUTIMER1 215 -#define SRST_P_NPU_WDT 216 -#define SRST_T_NPU_WDT 217 - -#define SRST_A_RKNN_CBUF 218 -#define SRST_A_RVCORE0 219 -#define SRST_P_NPU_GRF 220 -#define SRST_P_PVTPLL_NPU 221 -#define SRST_NPU_PVTPLL 222 -#define SRST_H_NPU_CM0_BIU 223 -#define SRST_F_NPU_CM0_CORE 224 -#define SRST_T_NPU_CM0_JTAG 225 -#define SRST_A_RKNNTOP_BIU 226 -#define SRST_H_RKNN_CBUF 227 -#define SRST_H_RKNNTOP_BIU 228 - -#define SRST_H_NVM_BIU 229 -#define SRST_A_NVM_BIU 230 -#define SRST_S_FSPI 231 -#define SRST_H_FSPI 232 -#define SRST_C_EMMC 233 -#define SRST_H_EMMC 234 -#define SRST_A_EMMC 235 -#define SRST_B_EMMC 236 -#define SRST_T_EMMC 237 - -#define SRST_P_GRF 238 -#define SRST_P_PHP_BIU 239 -#define SRST_A_PHP_BIU 240 -#define SRST_P_PCIE0 241 -#define SRST_PCIE0_POWER_UP 242 - -#define SRST_A_USB3OTG1 243 -#define SRST_A_MMU0 244 -#define SRST_A_SLV_MMU0 245 -#define SRST_A_MMU1 246 - -#define SRST_A_SLV_MMU1 247 -#define SRST_P_PCIE1 248 -#define SRST_PCIE1_POWER_UP 249 - -#define SRST_RXOOB0 250 -#define SRST_RXOOB1 251 -#define SRST_PMALIVE0 252 -#define SRST_PMALIVE1 253 -#define SRST_A_SATA0 254 -#define SRST_A_SATA1 255 -#define SRST_ASIC1 256 -#define SRST_ASIC0 257 - -#define SRST_P_CSIDPHY1 258 -#define SRST_SCAN_CSIDPHY1 259 - -#define SRST_P_SDGMAC_GRF 260 -#define SRST_P_SDGMAC_BIU 261 -#define SRST_A_SDGMAC_BIU 262 -#define SRST_H_SDGMAC_BIU 263 -#define SRST_A_GMAC0 264 -#define SRST_A_GMAC1 265 -#define SRST_P_GMAC0 266 -#define SRST_P_GMAC1 267 -#define SRST_H_SDIO 268 - -#define SRST_H_SDMMC0 269 -#define SRST_S_FSPI1 270 -#define SRST_H_FSPI1 271 -#define SRST_A_DSMC_BIU 272 -#define SRST_A_DSMC 273 -#define SRST_P_DSMC 274 -#define SRST_H_HSGPIO 275 -#define SRST_HSGPIO 276 -#define SRST_A_HSGPIO 277 - -#define SRST_H_RKVDEC 278 -#define SRST_H_RKVDEC_BIU 279 -#define SRST_A_RKVDEC_BIU 280 -#define SRST_RKVDEC_HEVC_CA 281 -#define SRST_RKVDEC_CORE 282 - -#define SRST_A_USB_BIU 283 -#define SRST_P_USBUFS_BIU 284 -#define SRST_A_USB3OTG0 285 -#define SRST_A_UFS_BIU 286 -#define SRST_A_MMU2 287 -#define SRST_A_SLV_MMU2 288 -#define SRST_A_UFS_SYS 289 - -#define SRST_A_UFS 290 -#define SRST_P_USBUFS_GRF 291 -#define SRST_P_UFS_GRF 292 - -#define SRST_H_VPU_BIU 293 -#define SRST_A_JPEG_BIU 294 -#define SRST_A_RGA_BIU 295 -#define SRST_A_VDPP_BIU 296 -#define SRST_A_EBC_BIU 297 -#define SRST_H_RGA2E_0 298 -#define SRST_A_RGA2E_0 299 -#define SRST_CORE_RGA2E_0 300 - -#define SRST_A_JPEG 301 -#define SRST_H_JPEG 302 -#define SRST_H_VDPP 303 -#define SRST_A_VDPP 304 -#define SRST_CORE_VDPP 305 -#define SRST_H_RGA2E_1 306 -#define SRST_A_RGA2E_1 307 -#define SRST_CORE_RGA2E_1 308 -#define SRST_H_EBC 309 -#define SRST_A_EBC 310 -#define SRST_D_EBC 311 - -#define SRST_H_VEPU0_BIU 312 -#define SRST_A_VEPU0_BIU 313 -#define SRST_H_VEPU0 314 -#define SRST_A_VEPU0 315 -#define SRST_VEPU0_CORE 316 - -#define SRST_A_VI_BIU 317 -#define SRST_H_VI_BIU 318 -#define SRST_P_VI_BIU 319 -#define SRST_D_VICAP 320 -#define SRST_A_VICAP 321 -#define SRST_H_VICAP 322 -#define SRST_ISP0 323 -#define SRST_ISP0_VICAP 324 - -#define SRST_CORE_VPSS 325 -#define SRST_P_CSI_HOST_0 326 -#define SRST_P_CSI_HOST_1 327 -#define SRST_P_CSI_HOST_2 328 -#define SRST_P_CSI_HOST_3 329 -#define SRST_P_CSI_HOST_4 330 - -#define SRST_CIFIN 331 -#define SRST_VICAP_I0CLK 332 -#define SRST_VICAP_I1CLK 333 -#define SRST_VICAP_I2CLK 334 -#define SRST_VICAP_I3CLK 335 -#define SRST_VICAP_I4CLK 336 - -#define SRST_A_VOP_BIU 337 -#define SRST_A_VOP2_BIU 338 -#define SRST_H_VOP_BIU 339 -#define SRST_P_VOP_BIU 340 -#define SRST_H_VOP 341 -#define SRST_A_VOP 342 -#define SRST_D_VP0 343 - -#define SRST_D_VP1 344 -#define SRST_D_VP2 345 -#define SRST_P_VOP2_BIU 346 -#define SRST_P_VOPGRF 347 - -#define SRST_H_VO0_BIU 348 -#define SRST_P_VO0_BIU 349 -#define SRST_A_HDCP0_BIU 350 -#define SRST_P_VO0_GRF 351 -#define SRST_A_HDCP0 352 -#define SRST_H_HDCP0 353 -#define SRST_HDCP0 354 - -#define SRST_P_DSIHOST0 355 -#define SRST_DSIHOST0 356 -#define SRST_P_HDMITX0 357 -#define SRST_HDMITX0_REF 358 -#define SRST_P_EDP0 359 -#define SRST_EDP0_24M 360 - -#define SRST_M_SAI5_8CH 361 -#define SRST_H_SAI5_8CH 362 -#define SRST_M_SAI6_8CH 363 -#define SRST_H_SAI6_8CH 364 -#define SRST_H_SPDIF_TX2 365 -#define SRST_M_SPDIF_TX2 366 -#define SRST_H_SPDIF_RX2 367 -#define SRST_M_SPDIF_RX2 368 - -#define SRST_H_SAI8_8CH 369 -#define SRST_M_SAI8_8CH 370 - -#define SRST_H_VO1_BIU 371 -#define SRST_P_VO1_BIU 372 -#define SRST_M_SAI7_8CH 373 -#define SRST_H_SAI7_8CH 374 -#define SRST_H_SPDIF_TX3 375 -#define SRST_H_SPDIF_TX4 376 -#define SRST_H_SPDIF_TX5 377 -#define SRST_M_SPDIF_TX3 378 - -#define SRST_DP0 379 -#define SRST_P_VO1_GRF 380 -#define SRST_A_HDCP1_BIU 381 -#define SRST_A_HDCP1 382 -#define SRST_H_HDCP1 383 -#define SRST_HDCP1 384 -#define SRST_H_SAI9_8CH 385 -#define SRST_M_SAI9_8CH 386 -#define SRST_M_SPDIF_TX4 387 -#define SRST_M_SPDIF_TX5 388 - -#define SRST_GPU 389 -#define SRST_A_S_GPU_BIU 390 -#define SRST_A_M0_GPU_BIU 391 -#define SRST_P_GPU_BIU 392 -#define SRST_P_GPU_GRF 393 -#define SRST_GPU_PVTPLL 394 -#define SRST_P_PVTPLL_GPU 395 - -#define SRST_A_CENTER_BIU 396 -#define SRST_A_DMA2DDR 397 -#define SRST_A_DDR_SHAREMEM 398 -#define SRST_A_DDR_SHAREMEM_BIU 399 -#define SRST_H_CENTER_BIU 400 -#define SRST_P_CENTER_GRF 401 -#define SRST_P_DMA2DDR 402 -#define SRST_P_SHAREMEM 403 -#define SRST_P_CENTER_BIU 404 - -#define SRST_LINKSYM_HDMITXPHY0 405 - -#define SRST_DP0_PIXELCLK 406 -#define SRST_PHY_DP0_TX 407 -#define SRST_DP1_PIXELCLK 408 -#define SRST_DP2_PIXELCLK 409 - -#define SRST_H_VEPU1_BIU 410 -#define SRST_A_VEPU1_BIU 411 -#define SRST_H_VEPU1 412 -#define SRST_A_VEPU1 413 -#define SRST_VEPU1_CORE 414 - -#define SRST_P_PHPPHY_CRU 415 -#define SRST_P_APB2ASB_SLV_CHIP_TOP 416 -#define SRST_P_PCIE2_COMBOPHY0 417 -#define SRST_P_PCIE2_COMBOPHY0_GRF 418 -#define SRST_P_PCIE2_COMBOPHY1 419 -#define SRST_P_PCIE2_COMBOPHY1_GRF 420 - -#define SRST_PCIE0_PIPE_PHY 421 -#define SRST_PCIE1_PIPE_PHY 422 - -#define SRST_H_CRYPTO_NS 423 -#define SRST_H_TRNG_NS 424 -#define SRST_P_OTPC_NS 425 -#define SRST_OTPC_NS 426 - -#define SRST_P_HDPTX_GRF 427 -#define SRST_P_HDPTX_APB 428 -#define SRST_P_MIPI_DCPHY 429 -#define SRST_P_DCPHY_GRF 430 -#define SRST_P_BOT0_APB2ASB 431 -#define SRST_P_BOT1_APB2ASB 432 -#define SRST_USB2DEBUG 433 -#define SRST_P_CSIPHY_GRF 434 -#define SRST_P_CSIPHY 435 -#define SRST_P_USBPHY_GRF_0 436 -#define SRST_P_USBPHY_GRF_1 437 -#define SRST_P_USBDP_GRF 438 -#define SRST_P_USBDPPHY 439 -#define SRST_USBDP_COMBO_PHY_INIT 440 - -#define SRST_USBDP_COMBO_PHY_CMN 441 -#define SRST_USBDP_COMBO_PHY_LANE 442 -#define SRST_USBDP_COMBO_PHY_PCS 443 -#define SRST_M_MIPI_DCPHY 444 -#define SRST_S_MIPI_DCPHY 445 -#define SRST_SCAN_CSIPHY 446 -#define SRST_P_VCCIO6_IOC 447 -#define SRST_OTGPHY_0 448 -#define SRST_OTGPHY_1 449 -#define SRST_HDPTX_INIT 450 -#define SRST_HDPTX_CMN 451 -#define SRST_HDPTX_LANE 452 -#define SRST_HDMITXHDP 453 - -#define SRST_MPHY_INIT 454 -#define SRST_P_MPHY_GRF 455 -#define SRST_P_VCCIO7_IOC 456 - -#define SRST_H_PMU1_BIU 457 -#define SRST_P_PMU1_NIU 458 -#define SRST_H_PMU_CM0_BIU 459 -#define SRST_PMU_CM0_CORE 460 -#define SRST_PMU_CM0_JTAG 461 - -#define SRST_P_CRU_PMU1 462 -#define SRST_P_PMU1_GRF 463 -#define SRST_P_PMU1_IOC 464 -#define SRST_P_PMU1WDT 465 -#define SRST_T_PMU1WDT 466 -#define SRST_P_PMUTIMER 467 -#define SRST_PMUTIMER0 468 -#define SRST_PMUTIMER1 469 -#define SRST_P_PMU1PWM 470 -#define SRST_PMU1PWM 471 - -#define SRST_P_I2C0 472 -#define SRST_I2C0 473 -#define SRST_S_UART1 474 -#define SRST_P_UART1 475 -#define SRST_PDM0 476 -#define SRST_H_PDM0 477 - -#define SRST_M_PDM0 478 -#define SRST_H_VAD 479 - -#define SRST_P_PMU0GRF 480 -#define SRST_P_PMU0IOC 481 -#define SRST_P_GPIO0 482 -#define SRST_DB_GPIO0 483 - -#endif diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h deleted file mode 100644 index 878beae6dc3..00000000000 --- a/include/dt-bindings/reset/rockchip,rk3588-cru.h +++ /dev/null @@ -1,795 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd. - * Copyright (c) 2022 Collabora Ltd. - * - * Author: Elaine Zhang <zhangqing@rock-chips.com> - * Author: Sebastian Reichel <sebastian.reichel@collabora.com> - */ - -#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H -#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H - -#define SRST_A_TOP_BIU 0 -#define SRST_P_TOP_BIU 1 -#define SRST_P_CSIPHY0 2 -#define SRST_CSIPHY0 3 -#define SRST_P_CSIPHY1 4 -#define SRST_CSIPHY1 5 -#define SRST_A_TOP_M500_BIU 6 - -#define SRST_A_TOP_M400_BIU 7 -#define SRST_A_TOP_S200_BIU 8 -#define SRST_A_TOP_S400_BIU 9 -#define SRST_A_TOP_M300_BIU 10 -#define SRST_USBDP_COMBO_PHY0_INIT 11 -#define SRST_USBDP_COMBO_PHY0_CMN 12 -#define SRST_USBDP_COMBO_PHY0_LANE 13 -#define SRST_USBDP_COMBO_PHY0_PCS 14 -#define SRST_USBDP_COMBO_PHY1_INIT 15 - -#define SRST_USBDP_COMBO_PHY1_CMN 16 -#define SRST_USBDP_COMBO_PHY1_LANE 17 -#define SRST_USBDP_COMBO_PHY1_PCS 18 -#define SRST_DCPHY0 19 -#define SRST_P_MIPI_DCPHY0 20 -#define SRST_P_MIPI_DCPHY0_GRF 21 - -#define SRST_DCPHY1 22 -#define SRST_P_MIPI_DCPHY1 23 -#define SRST_P_MIPI_DCPHY1_GRF 24 -#define SRST_P_APB2ASB_SLV_CDPHY 25 -#define SRST_P_APB2ASB_SLV_CSIPHY 26 -#define SRST_P_APB2ASB_SLV_VCCIO3_5 27 -#define SRST_P_APB2ASB_SLV_VCCIO6 28 -#define SRST_P_APB2ASB_SLV_EMMCIO 29 -#define SRST_P_APB2ASB_SLV_IOC_TOP 30 -#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31 - -#define SRST_P_CRU 32 -#define SRST_A_CHANNEL_SECURE2VO1USB 33 -#define SRST_A_CHANNEL_SECURE2CENTER 34 -#define SRST_H_CHANNEL_SECURE2VO1USB 35 -#define SRST_H_CHANNEL_SECURE2CENTER 36 - -#define SRST_P_CHANNEL_SECURE2VO1USB 37 -#define SRST_P_CHANNEL_SECURE2CENTER 38 - -#define SRST_H_AUDIO_BIU 39 -#define SRST_P_AUDIO_BIU 40 -#define SRST_H_I2S0_8CH 41 -#define SRST_M_I2S0_8CH_TX 42 -#define SRST_M_I2S0_8CH_RX 43 -#define SRST_P_ACDCDIG 44 -#define SRST_H_I2S2_2CH 45 -#define SRST_H_I2S3_2CH 46 - -#define SRST_M_I2S2_2CH 47 -#define SRST_M_I2S3_2CH 48 -#define SRST_DAC_ACDCDIG 49 -#define SRST_H_SPDIF0 50 - -#define SRST_M_SPDIF0 51 -#define SRST_H_SPDIF1 52 -#define SRST_M_SPDIF1 53 -#define SRST_H_PDM1 54 -#define SRST_PDM1 55 - -#define SRST_A_BUS_BIU 56 -#define SRST_P_BUS_BIU 57 -#define SRST_A_GIC 58 -#define SRST_A_GIC_DBG 59 -#define SRST_A_DMAC0 60 -#define SRST_A_DMAC1 61 -#define SRST_A_DMAC2 62 -#define SRST_P_I2C1 63 -#define SRST_P_I2C2 64 -#define SRST_P_I2C3 65 -#define SRST_P_I2C4 66 -#define SRST_P_I2C5 67 -#define SRST_P_I2C6 68 -#define SRST_P_I2C7 69 -#define SRST_P_I2C8 70 - -#define SRST_I2C1 71 -#define SRST_I2C2 72 -#define SRST_I2C3 73 -#define SRST_I2C4 74 -#define SRST_I2C5 75 -#define SRST_I2C6 76 -#define SRST_I2C7 77 -#define SRST_I2C8 78 -#define SRST_P_CAN0 79 -#define SRST_CAN0 80 -#define SRST_P_CAN1 81 -#define SRST_CAN1 82 -#define SRST_P_CAN2 83 -#define SRST_CAN2 84 -#define SRST_P_SARADC 85 - -#define SRST_P_TSADC 86 -#define SRST_TSADC 87 -#define SRST_P_UART1 88 -#define SRST_P_UART2 89 -#define SRST_P_UART3 90 -#define SRST_P_UART4 91 -#define SRST_P_UART5 92 -#define SRST_P_UART6 93 -#define SRST_P_UART7 94 -#define SRST_P_UART8 95 -#define SRST_P_UART9 96 -#define SRST_S_UART1 97 - -#define SRST_S_UART2 98 -#define SRST_S_UART3 99 -#define SRST_S_UART4 100 -#define SRST_S_UART5 101 -#define SRST_S_UART6 102 -#define SRST_S_UART7 103 - -#define SRST_S_UART8 104 -#define SRST_S_UART9 105 -#define SRST_P_SPI0 106 -#define SRST_P_SPI1 107 -#define SRST_P_SPI2 108 -#define SRST_P_SPI3 109 -#define SRST_P_SPI4 110 -#define SRST_SPI0 111 -#define SRST_SPI1 112 -#define SRST_SPI2 113 -#define SRST_SPI3 114 -#define SRST_SPI4 115 - -#define SRST_P_WDT0 116 -#define SRST_T_WDT0 117 -#define SRST_P_SYS_GRF 118 -#define SRST_P_PWM1 119 -#define SRST_PWM1 120 -#define SRST_P_PWM2 121 -#define SRST_PWM2 122 -#define SRST_P_PWM3 123 -#define SRST_PWM3 124 -#define SRST_P_BUSTIMER0 125 -#define SRST_P_BUSTIMER1 126 -#define SRST_BUSTIMER0 127 - -#define SRST_BUSTIMER1 128 -#define SRST_BUSTIMER2 129 -#define SRST_BUSTIMER3 130 -#define SRST_BUSTIMER4 131 -#define SRST_BUSTIMER5 132 -#define SRST_BUSTIMER6 133 -#define SRST_BUSTIMER7 134 -#define SRST_BUSTIMER8 135 -#define SRST_BUSTIMER9 136 -#define SRST_BUSTIMER10 137 -#define SRST_BUSTIMER11 138 -#define SRST_P_MAILBOX0 139 -#define SRST_P_MAILBOX1 140 -#define SRST_P_MAILBOX2 141 -#define SRST_P_GPIO1 142 -#define SRST_GPIO1 143 - -#define SRST_P_GPIO2 144 -#define SRST_GPIO2 145 -#define SRST_P_GPIO3 146 -#define SRST_GPIO3 147 -#define SRST_P_GPIO4 148 -#define SRST_GPIO4 149 -#define SRST_A_DECOM 150 -#define SRST_P_DECOM 151 -#define SRST_D_DECOM 152 -#define SRST_P_TOP 153 -#define SRST_A_GICADB_GIC2CORE_BUS 154 -#define SRST_P_DFT2APB 155 -#define SRST_P_APB2ASB_MST_TOP 156 -#define SRST_P_APB2ASB_MST_CDPHY 157 -#define SRST_P_APB2ASB_MST_BOT_RIGHT 158 - -#define SRST_P_APB2ASB_MST_IOC_TOP 159 -#define SRST_P_APB2ASB_MST_IOC_RIGHT 160 -#define SRST_P_APB2ASB_MST_CSIPHY 161 -#define SRST_P_APB2ASB_MST_VCCIO3_5 162 -#define SRST_P_APB2ASB_MST_VCCIO6 163 -#define SRST_P_APB2ASB_MST_EMMCIO 164 -#define SRST_A_SPINLOCK 165 -#define SRST_P_OTPC_NS 166 -#define SRST_OTPC_NS 167 -#define SRST_OTPC_ARB 168 - -#define SRST_P_BUSIOC 169 -#define SRST_P_PMUCM0_INTMUX 170 -#define SRST_P_DDRCM0_INTMUX 171 - -#define SRST_P_DDR_DFICTL_CH0 172 -#define SRST_P_DDR_MON_CH0 173 -#define SRST_P_DDR_STANDBY_CH0 174 -#define SRST_P_DDR_UPCTL_CH0 175 -#define SRST_TM_DDR_MON_CH0 176 -#define SRST_P_DDR_GRF_CH01 177 -#define SRST_DFI_CH0 178 -#define SRST_SBR_CH0 179 -#define SRST_DDR_UPCTL_CH0 180 -#define SRST_DDR_DFICTL_CH0 181 -#define SRST_DDR_MON_CH0 182 -#define SRST_DDR_STANDBY_CH0 183 -#define SRST_A_DDR_UPCTL_CH0 184 -#define SRST_P_DDR_DFICTL_CH1 185 -#define SRST_P_DDR_MON_CH1 186 -#define SRST_P_DDR_STANDBY_CH1 187 - -#define SRST_P_DDR_UPCTL_CH1 188 -#define SRST_TM_DDR_MON_CH1 189 -#define SRST_DFI_CH1 190 -#define SRST_SBR_CH1 191 -#define SRST_DDR_UPCTL_CH1 192 -#define SRST_DDR_DFICTL_CH1 193 -#define SRST_DDR_MON_CH1 194 -#define SRST_DDR_STANDBY_CH1 195 -#define SRST_A_DDR_UPCTL_CH1 196 -#define SRST_A_DDR01_MSCH0 197 -#define SRST_A_DDR01_RS_MSCH0 198 -#define SRST_A_DDR01_FRS_MSCH0 199 - -#define SRST_A_DDR01_SCRAMBLE0 200 -#define SRST_A_DDR01_FRS_SCRAMBLE0 201 -#define SRST_A_DDR01_MSCH1 202 -#define SRST_A_DDR01_RS_MSCH1 203 -#define SRST_A_DDR01_FRS_MSCH1 204 -#define SRST_A_DDR01_SCRAMBLE1 205 -#define SRST_A_DDR01_FRS_SCRAMBLE1 206 -#define SRST_P_DDR01_MSCH0 207 -#define SRST_P_DDR01_MSCH1 208 - -#define SRST_P_DDR_DFICTL_CH2 209 -#define SRST_P_DDR_MON_CH2 210 -#define SRST_P_DDR_STANDBY_CH2 211 -#define SRST_P_DDR_UPCTL_CH2 212 -#define SRST_TM_DDR_MON_CH2 213 -#define SRST_P_DDR_GRF_CH23 214 -#define SRST_DFI_CH2 215 -#define SRST_SBR_CH2 216 -#define SRST_DDR_UPCTL_CH2 217 -#define SRST_DDR_DFICTL_CH2 218 -#define SRST_DDR_MON_CH2 219 -#define SRST_DDR_STANDBY_CH2 220 -#define SRST_A_DDR_UPCTL_CH2 221 -#define SRST_P_DDR_DFICTL_CH3 222 -#define SRST_P_DDR_MON_CH3 223 -#define SRST_P_DDR_STANDBY_CH3 224 - -#define SRST_P_DDR_UPCTL_CH3 225 -#define SRST_TM_DDR_MON_CH3 226 -#define SRST_DFI_CH3 227 -#define SRST_SBR_CH3 228 -#define SRST_DDR_UPCTL_CH3 229 -#define SRST_DDR_DFICTL_CH3 230 -#define SRST_DDR_MON_CH3 231 -#define SRST_DDR_STANDBY_CH3 232 -#define SRST_A_DDR_UPCTL_CH3 233 -#define SRST_A_DDR23_MSCH2 234 -#define SRST_A_DDR23_RS_MSCH2 235 -#define SRST_A_DDR23_FRS_MSCH2 236 - -#define SRST_A_DDR23_SCRAMBLE2 237 -#define SRST_A_DDR23_FRS_SCRAMBLE2 238 -#define SRST_A_DDR23_MSCH3 239 -#define SRST_A_DDR23_RS_MSCH3 240 -#define SRST_A_DDR23_FRS_MSCH3 241 -#define SRST_A_DDR23_SCRAMBLE3 242 -#define SRST_A_DDR23_FRS_SCRAMBLE3 243 -#define SRST_P_DDR23_MSCH2 244 -#define SRST_P_DDR23_MSCH3 245 - -#define SRST_ISP1 246 -#define SRST_ISP1_VICAP 247 -#define SRST_A_ISP1_BIU 248 -#define SRST_H_ISP1_BIU 249 - -#define SRST_A_RKNN1 250 -#define SRST_A_RKNN1_BIU 251 -#define SRST_H_RKNN1 252 -#define SRST_H_RKNN1_BIU 253 - -#define SRST_A_RKNN2 254 -#define SRST_A_RKNN2_BIU 255 -#define SRST_H_RKNN2 256 -#define SRST_H_RKNN2_BIU 257 - -#define SRST_A_RKNN_DSU0 258 -#define SRST_P_NPUTOP_BIU 259 -#define SRST_P_NPU_TIMER 260 -#define SRST_NPUTIMER0 261 -#define SRST_NPUTIMER1 262 -#define SRST_P_NPU_WDT 263 -#define SRST_T_NPU_WDT 264 -#define SRST_P_NPU_PVTM 265 -#define SRST_P_NPU_GRF 266 -#define SRST_NPU_PVTM 267 - -#define SRST_NPU_PVTPLL 268 -#define SRST_H_NPU_CM0_BIU 269 -#define SRST_F_NPU_CM0_CORE 270 -#define SRST_T_NPU_CM0_JTAG 271 -#define SRST_A_RKNN0 272 -#define SRST_A_RKNN0_BIU 273 -#define SRST_H_RKNN0 274 -#define SRST_H_RKNN0_BIU 275 - -#define SRST_H_NVM_BIU 276 -#define SRST_A_NVM_BIU 277 -#define SRST_H_EMMC 278 -#define SRST_A_EMMC 279 -#define SRST_C_EMMC 280 -#define SRST_B_EMMC 281 -#define SRST_T_EMMC 282 -#define SRST_S_SFC 283 -#define SRST_H_SFC 284 -#define SRST_H_SFC_XIP 285 - -#define SRST_P_GRF 286 -#define SRST_P_DEC_BIU 287 -#define SRST_P_PHP_BIU 288 -#define SRST_A_PCIE_GRIDGE 289 -#define SRST_A_PHP_BIU 290 -#define SRST_A_GMAC0 291 -#define SRST_A_GMAC1 292 -#define SRST_A_PCIE_BIU 293 -#define SRST_PCIE0_POWER_UP 294 -#define SRST_PCIE1_POWER_UP 295 -#define SRST_PCIE2_POWER_UP 296 - -#define SRST_PCIE3_POWER_UP 297 -#define SRST_PCIE4_POWER_UP 298 -#define SRST_P_PCIE0 299 -#define SRST_P_PCIE1 300 -#define SRST_P_PCIE2 301 -#define SRST_P_PCIE3 302 - -#define SRST_P_PCIE4 303 -#define SRST_A_PHP_GIC_ITS 304 -#define SRST_A_MMU_PCIE 305 -#define SRST_A_MMU_PHP 306 -#define SRST_A_MMU_BIU 307 - -#define SRST_A_USB3OTG2 308 - -#define SRST_PMALIVE0 309 -#define SRST_PMALIVE1 310 -#define SRST_PMALIVE2 311 -#define SRST_A_SATA0 312 -#define SRST_A_SATA1 313 -#define SRST_A_SATA2 314 -#define SRST_RXOOB0 315 -#define SRST_RXOOB1 316 -#define SRST_RXOOB2 317 -#define SRST_ASIC0 318 -#define SRST_ASIC1 319 -#define SRST_ASIC2 320 - -#define SRST_A_RKVDEC_CCU 321 -#define SRST_H_RKVDEC0 322 -#define SRST_A_RKVDEC0 323 -#define SRST_H_RKVDEC0_BIU 324 -#define SRST_A_RKVDEC0_BIU 325 -#define SRST_RKVDEC0_CA 326 -#define SRST_RKVDEC0_HEVC_CA 327 -#define SRST_RKVDEC0_CORE 328 - -#define SRST_H_RKVDEC1 329 -#define SRST_A_RKVDEC1 330 -#define SRST_H_RKVDEC1_BIU 331 -#define SRST_A_RKVDEC1_BIU 332 -#define SRST_RKVDEC1_CA 333 -#define SRST_RKVDEC1_HEVC_CA 334 -#define SRST_RKVDEC1_CORE 335 - -#define SRST_A_USB_BIU 336 -#define SRST_H_USB_BIU 337 -#define SRST_A_USB3OTG0 338 -#define SRST_A_USB3OTG1 339 -#define SRST_H_HOST0 340 -#define SRST_H_HOST_ARB0 341 -#define SRST_H_HOST1 342 -#define SRST_H_HOST_ARB1 343 -#define SRST_A_USB_GRF 344 -#define SRST_C_USB2P0_HOST0 345 - -#define SRST_C_USB2P0_HOST1 346 -#define SRST_HOST_UTMI0 347 -#define SRST_HOST_UTMI1 348 - -#define SRST_A_VDPU_BIU 349 -#define SRST_A_VDPU_LOW_BIU 350 -#define SRST_H_VDPU_BIU 351 -#define SRST_A_JPEG_DECODER_BIU 352 -#define SRST_A_VPU 353 -#define SRST_H_VPU 354 -#define SRST_A_JPEG_ENCODER0 355 -#define SRST_H_JPEG_ENCODER0 356 -#define SRST_A_JPEG_ENCODER1 357 -#define SRST_H_JPEG_ENCODER1 358 -#define SRST_A_JPEG_ENCODER2 359 -#define SRST_H_JPEG_ENCODER2 360 - -#define SRST_A_JPEG_ENCODER3 361 -#define SRST_H_JPEG_ENCODER3 362 -#define SRST_A_JPEG_DECODER 363 -#define SRST_H_JPEG_DECODER 364 -#define SRST_H_IEP2P0 365 -#define SRST_A_IEP2P0 366 -#define SRST_IEP2P0_CORE 367 -#define SRST_H_RGA2 368 -#define SRST_A_RGA2 369 -#define SRST_RGA2_CORE 370 -#define SRST_H_RGA3_0 371 -#define SRST_A_RGA3_0 372 -#define SRST_RGA3_0_CORE 373 - -#define SRST_H_RKVENC0_BIU 374 -#define SRST_A_RKVENC0_BIU 375 -#define SRST_H_RKVENC0 376 -#define SRST_A_RKVENC0 377 -#define SRST_RKVENC0_CORE 378 - -#define SRST_H_RKVENC1_BIU 379 -#define SRST_A_RKVENC1_BIU 380 -#define SRST_H_RKVENC1 381 -#define SRST_A_RKVENC1 382 -#define SRST_RKVENC1_CORE 383 - -#define SRST_A_VI_BIU 384 -#define SRST_H_VI_BIU 385 -#define SRST_P_VI_BIU 386 -#define SRST_D_VICAP 387 -#define SRST_A_VICAP 388 -#define SRST_H_VICAP 389 -#define SRST_ISP0 390 -#define SRST_ISP0_VICAP 391 - -#define SRST_FISHEYE0 392 -#define SRST_FISHEYE1 393 -#define SRST_P_CSI_HOST_0 394 -#define SRST_P_CSI_HOST_1 395 -#define SRST_P_CSI_HOST_2 396 -#define SRST_P_CSI_HOST_3 397 -#define SRST_P_CSI_HOST_4 398 -#define SRST_P_CSI_HOST_5 399 - -#define SRST_CSIHOST0_VICAP 400 -#define SRST_CSIHOST1_VICAP 401 -#define SRST_CSIHOST2_VICAP 402 -#define SRST_CSIHOST3_VICAP 403 -#define SRST_CSIHOST4_VICAP 404 -#define SRST_CSIHOST5_VICAP 405 -#define SRST_CIFIN 406 - -#define SRST_A_VOP_BIU 407 -#define SRST_A_VOP_LOW_BIU 408 -#define SRST_H_VOP_BIU 409 -#define SRST_P_VOP_BIU 410 -#define SRST_H_VOP 411 -#define SRST_A_VOP 412 -#define SRST_D_VOP0 413 -#define SRST_D_VOP2HDMI_BRIDGE0 414 -#define SRST_D_VOP2HDMI_BRIDGE1 415 - -#define SRST_D_VOP1 416 -#define SRST_D_VOP2 417 -#define SRST_D_VOP3 418 -#define SRST_P_VOPGRF 419 -#define SRST_P_DSIHOST0 420 -#define SRST_P_DSIHOST1 421 -#define SRST_DSIHOST0 422 -#define SRST_DSIHOST1 423 -#define SRST_VOP_PMU 424 -#define SRST_P_VOP_CHANNEL_BIU 425 - -#define SRST_H_VO0_BIU 426 -#define SRST_H_VO0_S_BIU 427 -#define SRST_P_VO0_BIU 428 -#define SRST_P_VO0_S_BIU 429 -#define SRST_A_HDCP0_BIU 430 -#define SRST_P_VO0GRF 431 -#define SRST_H_HDCP_KEY0 432 -#define SRST_A_HDCP0 433 -#define SRST_H_HDCP0 434 -#define SRST_HDCP0 435 - -#define SRST_P_TRNG0 436 -#define SRST_DP0 437 -#define SRST_DP1 438 -#define SRST_H_I2S4_8CH 439 -#define SRST_M_I2S4_8CH_TX 440 -#define SRST_H_I2S8_8CH 441 - -#define SRST_M_I2S8_8CH_TX 442 -#define SRST_H_SPDIF2_DP0 443 -#define SRST_M_SPDIF2_DP0 444 -#define SRST_H_SPDIF5_DP1 445 -#define SRST_M_SPDIF5_DP1 446 - -#define SRST_A_HDCP1_BIU 447 -#define SRST_A_VO1_BIU 448 -#define SRST_H_VOP1_BIU 449 -#define SRST_H_VOP1_S_BIU 450 -#define SRST_P_VOP1_BIU 451 -#define SRST_P_VO1GRF 452 -#define SRST_P_VO1_S_BIU 453 - -#define SRST_H_I2S7_8CH 454 -#define SRST_M_I2S7_8CH_RX 455 -#define SRST_H_HDCP_KEY1 456 -#define SRST_A_HDCP1 457 -#define SRST_H_HDCP1 458 -#define SRST_HDCP1 459 -#define SRST_P_TRNG1 460 -#define SRST_P_HDMITX0 461 - -#define SRST_HDMITX0_REF 462 -#define SRST_P_HDMITX1 463 -#define SRST_HDMITX1_REF 464 -#define SRST_A_HDMIRX 465 -#define SRST_P_HDMIRX 466 -#define SRST_HDMIRX_REF 467 - -#define SRST_P_EDP0 468 -#define SRST_EDP0_24M 469 -#define SRST_P_EDP1 470 -#define SRST_EDP1_24M 471 -#define SRST_M_I2S5_8CH_TX 472 -#define SRST_H_I2S5_8CH 473 -#define SRST_M_I2S6_8CH_TX 474 - -#define SRST_M_I2S6_8CH_RX 475 -#define SRST_H_I2S6_8CH 476 -#define SRST_H_SPDIF3 477 -#define SRST_M_SPDIF3 478 -#define SRST_H_SPDIF4 479 -#define SRST_M_SPDIF4 480 -#define SRST_H_SPDIFRX0 481 -#define SRST_M_SPDIFRX0 482 -#define SRST_H_SPDIFRX1 483 -#define SRST_M_SPDIFRX1 484 - -#define SRST_H_SPDIFRX2 485 -#define SRST_M_SPDIFRX2 486 -#define SRST_LINKSYM_HDMITXPHY0 487 -#define SRST_LINKSYM_HDMITXPHY1 488 -#define SRST_VO1_BRIDGE0 489 -#define SRST_VO1_BRIDGE1 490 - -#define SRST_H_I2S9_8CH 491 -#define SRST_M_I2S9_8CH_RX 492 -#define SRST_H_I2S10_8CH 493 -#define SRST_M_I2S10_8CH_RX 494 -#define SRST_P_S_HDMIRX 495 - -#define SRST_GPU 496 -#define SRST_SYS_GPU 497 -#define SRST_A_S_GPU_BIU 498 -#define SRST_A_M0_GPU_BIU 499 -#define SRST_A_M1_GPU_BIU 500 -#define SRST_A_M2_GPU_BIU 501 -#define SRST_A_M3_GPU_BIU 502 -#define SRST_P_GPU_BIU 503 -#define SRST_P_GPU_PVTM 504 - -#define SRST_GPU_PVTM 505 -#define SRST_P_GPU_GRF 506 -#define SRST_GPU_PVTPLL 507 -#define SRST_GPU_JTAG 508 - -#define SRST_A_AV1_BIU 509 -#define SRST_A_AV1 510 -#define SRST_P_AV1_BIU 511 -#define SRST_P_AV1 512 - -#define SRST_A_DDR_BIU 513 -#define SRST_A_DMA2DDR 514 -#define SRST_A_DDR_SHAREMEM 515 -#define SRST_A_DDR_SHAREMEM_BIU 516 -#define SRST_A_CENTER_S200_BIU 517 -#define SRST_A_CENTER_S400_BIU 518 -#define SRST_H_AHB2APB 519 -#define SRST_H_CENTER_BIU 520 -#define SRST_F_DDR_CM0_CORE 521 - -#define SRST_DDR_TIMER0 522 -#define SRST_DDR_TIMER1 523 -#define SRST_T_WDT_DDR 524 -#define SRST_T_DDR_CM0_JTAG 525 -#define SRST_P_CENTER_GRF 526 -#define SRST_P_AHB2APB 527 -#define SRST_P_WDT 528 -#define SRST_P_TIMER 529 -#define SRST_P_DMA2DDR 530 -#define SRST_P_SHAREMEM 531 -#define SRST_P_CENTER_BIU 532 -#define SRST_P_CENTER_CHANNEL_BIU 533 - -#define SRST_P_USBDPGRF0 534 -#define SRST_P_USBDPPHY0 535 -#define SRST_P_USBDPGRF1 536 -#define SRST_P_USBDPPHY1 537 -#define SRST_P_HDPTX0 538 -#define SRST_P_HDPTX1 539 -#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540 -#define SRST_P_USB2PHY_U3_0_GRF0 541 -#define SRST_P_USB2PHY_U3_1_GRF0 542 -#define SRST_P_USB2PHY_U2_0_GRF0 543 -#define SRST_P_USB2PHY_U2_1_GRF0 544 -#define SRST_HDPTX0_ROPLL 545 -#define SRST_HDPTX0_LCPLL 546 -#define SRST_HDPTX0 547 -#define SRST_HDPTX1_ROPLL 548 - -#define SRST_HDPTX1_LCPLL 549 -#define SRST_HDPTX1 550 -#define SRST_HDPTX0_HDMIRXPHY_SET 551 -#define SRST_USBDP_COMBO_PHY0 552 -#define SRST_USBDP_COMBO_PHY0_LCPLL 553 -#define SRST_USBDP_COMBO_PHY0_ROPLL 554 -#define SRST_USBDP_COMBO_PHY0_PCS_HS 555 -#define SRST_USBDP_COMBO_PHY1 556 -#define SRST_USBDP_COMBO_PHY1_LCPLL 557 -#define SRST_USBDP_COMBO_PHY1_ROPLL 558 -#define SRST_USBDP_COMBO_PHY1_PCS_HS 559 -#define SRST_HDMIHDP0 560 -#define SRST_HDMIHDP1 561 - -#define SRST_A_VO1USB_TOP_BIU 562 -#define SRST_H_VO1USB_TOP_BIU 563 - -#define SRST_H_SDIO_BIU 564 -#define SRST_H_SDIO 565 -#define SRST_SDIO 566 - -#define SRST_H_RGA3_BIU 567 -#define SRST_A_RGA3_BIU 568 -#define SRST_H_RGA3_1 569 -#define SRST_A_RGA3_1 570 -#define SRST_RGA3_1_CORE 571 - -#define SRST_REF_PIPE_PHY0 572 -#define SRST_REF_PIPE_PHY1 573 -#define SRST_REF_PIPE_PHY2 574 - -#define SRST_P_PHPTOP_CRU 575 -#define SRST_P_PCIE2_GRF0 576 -#define SRST_P_PCIE2_GRF1 577 -#define SRST_P_PCIE2_GRF2 578 -#define SRST_P_PCIE2_PHY0 579 -#define SRST_P_PCIE2_PHY1 580 -#define SRST_P_PCIE2_PHY2 581 -#define SRST_P_PCIE3_PHY 582 -#define SRST_P_APB2ASB_SLV_CHIP_TOP 583 -#define SRST_PCIE30_PHY 584 - -#define SRST_H_PMU1_BIU 585 -#define SRST_P_PMU1_BIU 586 -#define SRST_H_PMU_CM0_BIU 587 -#define SRST_F_PMU_CM0_CORE 588 -#define SRST_T_PMU1_CM0_JTAG 589 - -#define SRST_DDR_FAIL_SAFE 590 -#define SRST_P_CRU_PMU1 591 -#define SRST_P_PMU1_GRF 592 -#define SRST_P_PMU1_IOC 593 -#define SRST_P_PMU1WDT 594 -#define SRST_T_PMU1WDT 595 -#define SRST_P_PMU1TIMER 596 -#define SRST_PMU1TIMER0 597 -#define SRST_PMU1TIMER1 598 -#define SRST_P_PMU1PWM 599 -#define SRST_PMU1PWM 600 - -#define SRST_P_I2C0 601 -#define SRST_I2C0 602 -#define SRST_S_UART0 603 -#define SRST_P_UART0 604 -#define SRST_H_I2S1_8CH 605 -#define SRST_M_I2S1_8CH_TX 606 -#define SRST_M_I2S1_8CH_RX 607 -#define SRST_H_PDM0 608 -#define SRST_PDM0 609 - -#define SRST_H_VAD 610 -#define SRST_HDPTX0_INIT 611 -#define SRST_HDPTX0_CMN 612 -#define SRST_HDPTX0_LANE 613 -#define SRST_HDPTX1_INIT 614 - -#define SRST_HDPTX1_CMN 615 -#define SRST_HDPTX1_LANE 616 -#define SRST_M_MIPI_DCPHY0 617 -#define SRST_S_MIPI_DCPHY0 618 -#define SRST_M_MIPI_DCPHY1 619 -#define SRST_S_MIPI_DCPHY1 620 -#define SRST_OTGPHY_U3_0 621 -#define SRST_OTGPHY_U3_1 622 -#define SRST_OTGPHY_U2_0 623 -#define SRST_OTGPHY_U2_1 624 - -#define SRST_P_PMU0GRF 625 -#define SRST_P_PMU0IOC 626 -#define SRST_P_GPIO0 627 -#define SRST_GPIO0 628 - -#define SRST_A_SECURE_NS_BIU 629 -#define SRST_H_SECURE_NS_BIU 630 -#define SRST_A_SECURE_S_BIU 631 -#define SRST_H_SECURE_S_BIU 632 -#define SRST_P_SECURE_S_BIU 633 -#define SRST_CRYPTO_CORE 634 - -#define SRST_CRYPTO_PKA 635 -#define SRST_CRYPTO_RNG 636 -#define SRST_A_CRYPTO 637 -#define SRST_H_CRYPTO 638 -#define SRST_KEYLADDER_CORE 639 -#define SRST_KEYLADDER_RNG 640 -#define SRST_A_KEYLADDER 641 -#define SRST_H_KEYLADDER 642 -#define SRST_P_OTPC_S 643 -#define SRST_OTPC_S 644 -#define SRST_WDT_S 645 - -#define SRST_T_WDT_S 646 -#define SRST_H_BOOTROM 647 -#define SRST_A_DCF 648 -#define SRST_P_DCF 649 -#define SRST_H_BOOTROM_NS 650 -#define SRST_P_KEYLADDER 651 -#define SRST_H_TRNG_S 652 - -#define SRST_H_TRNG_NS 653 -#define SRST_D_SDMMC_BUFFER 654 -#define SRST_H_SDMMC 655 -#define SRST_H_SDMMC_BUFFER 656 -#define SRST_SDMMC 657 -#define SRST_P_TRNG_CHK 658 -#define SRST_TRNG_S 659 - -#define SRST_A_HDMIRX_BIU 660 - -/* SCMI Secure Resets */ - -/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */ -#define SCMI_SRST_A_SECURE_NS_BIU 10 -#define SCMI_SRST_H_SECURE_NS_BIU 11 -#define SCMI_SRST_A_SECURE_S_BIU 12 -#define SCMI_SRST_H_SECURE_S_BIU 13 -#define SCMI_SRST_P_SECURE_S_BIU 14 -#define SCMI_SRST_CRYPTO_CORE 15 -/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */ -#define SCMI_SRST_CRYPTO_PKA 16 -#define SCMI_SRST_CRYPTO_RNG 17 -#define SCMI_SRST_A_CRYPTO 18 -#define SCMI_SRST_H_CRYPTO 19 -#define SCMI_SRST_KEYLADDER_CORE 25 -#define SCMI_SRST_KEYLADDER_RNG 26 -#define SCMI_SRST_A_KEYLADDER 27 -#define SCMI_SRST_H_KEYLADDER 28 -#define SCMI_SRST_P_OTPC_S 29 -#define SCMI_SRST_OTPC_S 30 -#define SCMI_SRST_WDT_S 31 -/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */ -#define SCMI_SRST_T_WDT_S 32 -#define SCMI_SRST_H_BOOTROM 33 -#define SCMI_SRST_A_DCF 34 -#define SCMI_SRST_P_DCF 35 -#define SCMI_SRST_H_BOOTROM_NS 37 -#define SCMI_SRST_P_KEYLADDER 46 -#define SCMI_SRST_H_TRNG_S 47 -/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */ -#define SCMI_SRST_H_TRNG_NS 48 -#define SCMI_SRST_D_SDMMC_BUFFER 49 -#define SCMI_SRST_H_SDMMC 50 -#define SCMI_SRST_H_SDMMC_BUFFER 51 -#define SCMI_SRST_SDMMC 52 -#define SCMI_SRST_P_TRNG_CHK 53 -#define SCMI_SRST_TRNG_S 54 - - -#endif diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h deleted file mode 100644 index 2116f41d04e..00000000000 --- a/include/dt-bindings/reset/sama7g5-reset.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef __DT_BINDINGS_RESET_SAMA7G5_H -#define __DT_BINDINGS_RESET_SAMA7G5_H - -#define SAMA7G5_RESET_USB_PHY1 4 -#define SAMA7G5_RESET_USB_PHY2 5 -#define SAMA7G5_RESET_USB_PHY3 6 - -#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ diff --git a/include/dt-bindings/reset/sifive-fu540-prci.h b/include/dt-bindings/reset/sifive-fu540-prci.h new file mode 100644 index 00000000000..89aa5b6679f --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu540-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Sifive, Inc. + * Author: Sagar Kadam <sagar.kadam@sifive.com> + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +/* bit 4 is reserved bit */ +#define PRCI_RST_RSVD_N 4 +#define PRCI_RST_GEMGXL_N 5 + +#endif diff --git a/include/dt-bindings/reset/sifive-fu740-prci.h b/include/dt-bindings/reset/sifive-fu740-prci.h new file mode 100644 index 00000000000..02210f4105c --- /dev/null +++ b/include/dt-bindings/reset/sifive-fu740-prci.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2020-2021 Sifive, Inc. + * Author: Pragnesh Patel <pragnesh.patel@sifive.com> + */ + +#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H +#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H + +/* Reset indexes for use by device tree data and the PRCI driver */ +#define PRCI_RST_DDR_CTRL_N 0 +#define PRCI_RST_DDR_AXI_N 1 +#define PRCI_RST_DDR_AHB_N 2 +#define PRCI_RST_DDR_PHY_N 3 +#define PRCI_RST_PCIE_POWER_UP_N 4 +#define PRCI_RST_GEMGXL_N 5 +#define PRCI_RST_CLTX_N 6 + +#endif diff --git a/include/dt-bindings/reset/snps,hsdk-reset.h b/include/dt-bindings/reset/snps,hsdk-reset.h deleted file mode 100644 index e1a643e4bc9..00000000000 --- a/include/dt-bindings/reset/snps,hsdk-reset.h +++ /dev/null @@ -1,17 +0,0 @@ -/** - * This header provides index for the HSDK reset controller. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK -#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK - -#define HSDK_APB_RESET 0 -#define HSDK_AXI_RESET 1 -#define HSDK_ETH_RESET 2 -#define HSDK_USB_RESET 3 -#define HSDK_SDIO_RESET 4 -#define HSDK_HDMI_RESET 5 -#define HSDK_GFX_RESET 6 -#define HSDK_DMAC_RESET 7 -#define HSDK_EBI_RESET 8 - -#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/ diff --git a/include/dt-bindings/reset/sophgo,sg2042-reset.h b/include/dt-bindings/reset/sophgo,sg2042-reset.h deleted file mode 100644 index 9ab0980625c..00000000000 --- a/include/dt-bindings/reset/sophgo,sg2042-reset.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ -/* - * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved. - */ - -#ifndef __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ -#define __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ - -#define RST_MAIN_AP 0 -#define RST_RISCV_CPU 1 -#define RST_RISCV_LOW_SPEED_LOGIC 2 -#define RST_RISCV_CMN 3 -#define RST_HSDMA 4 -#define RST_SYSDMA 5 -#define RST_EFUSE0 6 -#define RST_EFUSE1 7 -#define RST_RTC 8 -#define RST_TIMER 9 -#define RST_WDT 10 -#define RST_AHB_ROM0 11 -#define RST_AHB_ROM1 12 -#define RST_I2C0 13 -#define RST_I2C1 14 -#define RST_I2C2 15 -#define RST_I2C3 16 -#define RST_GPIO0 17 -#define RST_GPIO1 18 -#define RST_GPIO2 19 -#define RST_PWM 20 -#define RST_AXI_SRAM0 21 -#define RST_AXI_SRAM1 22 -#define RST_SF0 23 -#define RST_SF1 24 -#define RST_LPC 25 -#define RST_ETH0 26 -#define RST_EMMC 27 -#define RST_SD 28 -#define RST_UART0 29 -#define RST_UART1 30 -#define RST_UART2 31 -#define RST_UART3 32 -#define RST_SPI0 33 -#define RST_SPI1 34 -#define RST_DBG_I2C 35 -#define RST_PCIE0 36 -#define RST_PCIE1 37 -#define RST_DDR0 38 -#define RST_DDR1 39 -#define RST_DDR2 40 -#define RST_DDR3 41 -#define RST_FAU0 42 -#define RST_FAU1 43 -#define RST_FAU2 44 -#define RST_RXU0 45 -#define RST_RXU1 46 -#define RST_RXU2 47 -#define RST_RXU3 48 -#define RST_RXU4 49 -#define RST_RXU5 50 -#define RST_RXU6 51 -#define RST_RXU7 52 -#define RST_RXU8 53 -#define RST_RXU9 54 -#define RST_RXU10 55 -#define RST_RXU11 56 -#define RST_RXU12 57 -#define RST_RXU13 58 -#define RST_RXU14 59 -#define RST_RXU15 60 -#define RST_RXU16 61 -#define RST_RXU17 62 -#define RST_RXU18 63 -#define RST_RXU19 64 -#define RST_RXU20 65 -#define RST_RXU21 66 -#define RST_RXU22 67 -#define RST_RXU23 68 -#define RST_RXU24 69 -#define RST_RXU25 70 -#define RST_RXU26 71 -#define RST_RXU27 72 -#define RST_RXU28 73 -#define RST_RXU29 74 -#define RST_RXU30 75 -#define RST_RXU31 76 - -#endif /* __DT_BINDINGS_RESET_SOPHGO_SG2042_H_ */ diff --git a/include/dt-bindings/reset/spacemit-k1-reset.h b/include/dt-bindings/reset/spacemit-k1-reset.h new file mode 100644 index 00000000000..74db58b27ef --- /dev/null +++ b/include/dt-bindings/reset/spacemit-k1-reset.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022 Spacemit Inc. + * Copyright (C) 2025 Huan Zhou <pericycle.cc@gmail.com> + */ + +#ifndef __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ +#define __DT_BINDINGS_RESET_SAPCEMIT_K1_H__ +/* APBC */ +#define RESET_UART1 1 +#define RESET_UART2 2 +#define RESET_GPIO 3 +#define RESET_PWM0 4 +#define RESET_PWM1 5 +#define RESET_PWM2 6 +#define RESET_PWM3 7 +#define RESET_PWM4 8 +#define RESET_PWM5 9 +#define RESET_PWM6 10 +#define RESET_PWM7 11 +#define RESET_PWM8 12 +#define RESET_PWM9 13 +#define RESET_PWM10 14 +#define RESET_PWM11 15 +#define RESET_PWM12 16 +#define RESET_PWM13 17 +#define RESET_PWM14 18 +#define RESET_PWM15 19 +#define RESET_PWM16 20 +#define RESET_PWM17 21 +#define RESET_PWM18 22 +#define RESET_PWM19 23 +#define RESET_SSP3 24 +#define RESET_UART3 25 +#define RESET_RTC 26 +#define RESET_TWSI0 27 +#define RESET_TIMERS1 28 +#define RESET_AIB 29 +#define RESET_TIMERS2 30 +#define RESET_ONEWIRE 31 +#define RESET_SSPA0 32 +#define RESET_SSPA1 33 +#define RESET_DRO 34 +#define RESET_IR 35 +#define RESET_TWSI1 36 +#define RESET_TSEN 37 +#define RESET_TWSI2 38 +#define RESET_TWSI4 39 +#define RESET_TWSI5 40 +#define RESET_TWSI6 41 +#define RESET_TWSI7 42 +#define RESET_TWSI8 43 +#define RESET_IPC_AP2AUD 44 +#define RESET_UART4 45 +#define RESET_UART5 46 +#define RESET_UART6 47 +#define RESET_UART7 48 +#define RESET_UART8 49 +#define RESET_UART9 50 +#define RESET_CAN0 51 + +/* MPMU */ +#define RESET_WDT 52 + +/* APMU */ +#define RESET_JPG 53 +#define RESET_CSI 54 +#define RESET_CCIC2_PHY 55 +#define RESET_CCIC3_PHY 56 +#define RESET_ISP 57 +#define RESET_ISP_AHB 58 +#define RESET_ISP_CI 59 +#define RESET_ISP_CPP 60 +#define RESET_LCD 61 +#define RESET_DSI_ESC 62 +#define RESET_V2D 63 +#define RESET_MIPI 64 +#define RESET_LCD_SPI 65 +#define RESET_LCD_SPI_BUS 66 +#define RESET_LCD_SPI_HBUS 67 +#define RESET_LCD_MCLK 68 +#define RESET_CCIC_4X 69 +#define RESET_CCIC1_PHY 70 +#define RESET_SDH_AXI 71 +#define RESET_SDH0 72 +#define RESET_SDH1 73 +#define RESET_USB_AXI 74 +#define RESET_USBP1_AXI 75 +#define RESET_USB3_0 76 +#define RESET_QSPI 77 +#define RESET_QSPI_BUS 78 +#define RESET_DMA 79 +#define RESET_AES 80 +#define RESET_VPU 81 +#define RESET_GPU 82 +#define RESET_SDH2 83 +#define RESET_MC 84 +#define RESET_EM_AXI 85 +#define RESET_EM 86 +#define RESET_AUDIO_SYS 87 +#define RESET_HDMI 88 +#define RESET_PCIE0 89 +#define RESET_PCIE1 90 +#define RESET_PCIE2 91 +#define RESET_EMAC0 92 +#define RESET_EMAC1 93 + +/* APBC2 */ +#define RESET_SEC_UART1 94 +#define RESET_SEC_SSP2 95 +#define RESET_SEC_TWSI3 96 +#define RESET_SEC_RTC 97 +#define RESET_SEC_TIMERS0 98 +#define RESET_SEC_KPC 99 +#define RESET_SEC_GPIO 100 +#define RESET_NUMBER 101 + +#endif diff --git a/include/dt-bindings/reset/st,stm32mp25-rcc.h b/include/dt-bindings/reset/st,stm32mp25-rcc.h deleted file mode 100644 index 748e78ae20b..00000000000 --- a/include/dt-bindings/reset/st,stm32mp25-rcc.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (C) STMicroelectronics 2023 - All Rights Reserved - * Author(s): Gabriel Fernandez <gabriel.fernandez@foss.st.com> - */ - -#ifndef _DT_BINDINGS_STM32MP25_RESET_H_ -#define _DT_BINDINGS_STM32MP25_RESET_H_ - -#define TIM1_R 0 -#define TIM2_R 1 -#define TIM3_R 2 -#define TIM4_R 3 -#define TIM5_R 4 -#define TIM6_R 5 -#define TIM7_R 6 -#define TIM8_R 7 -#define TIM10_R 8 -#define TIM11_R 9 -#define TIM12_R 10 -#define TIM13_R 11 -#define TIM14_R 12 -#define TIM15_R 13 -#define TIM16_R 14 -#define TIM17_R 15 -#define TIM20_R 16 -#define LPTIM1_R 17 -#define LPTIM2_R 18 -#define LPTIM3_R 19 -#define LPTIM4_R 20 -#define LPTIM5_R 21 -#define SPI1_R 22 -#define SPI2_R 23 -#define SPI3_R 24 -#define SPI4_R 25 -#define SPI5_R 26 -#define SPI6_R 27 -#define SPI7_R 28 -#define SPI8_R 29 -#define SPDIFRX_R 30 -#define USART1_R 31 -#define USART2_R 32 -#define USART3_R 33 -#define UART4_R 34 -#define UART5_R 35 -#define USART6_R 36 -#define UART7_R 37 -#define UART8_R 38 -#define UART9_R 39 -#define LPUART1_R 40 -#define IS2M_R 41 -#define I2C1_R 42 -#define I2C2_R 43 -#define I2C3_R 44 -#define I2C4_R 45 -#define I2C5_R 46 -#define I2C6_R 47 -#define I2C7_R 48 -#define I2C8_R 49 -#define SAI1_R 50 -#define SAI2_R 51 -#define SAI3_R 52 -#define SAI4_R 53 -#define MDF1_R 54 -#define MDF2_R 55 -#define FDCAN_R 56 -#define HDP_R 57 -#define ADC12_R 58 -#define ADC3_R 59 -#define ETH1_R 60 -#define ETH2_R 61 -#define USBH_R 62 -#define USB2PHY1_R 63 -#define USB2PHY2_R 64 -#define USB3DR_R 65 -#define USB3PCIEPHY_R 66 -#define USBTC_R 67 -#define ETHSW_R 68 -#define SDMMC1_R 69 -#define SDMMC1DLL_R 70 -#define SDMMC2_R 71 -#define SDMMC2DLL_R 72 -#define SDMMC3_R 73 -#define SDMMC3DLL_R 74 -#define GPU_R 75 -#define LTDC_R 76 -#define DSI_R 77 -#define LVDS_R 78 -#define CSI_R 79 -#define DCMIPP_R 80 -#define CCI_R 81 -#define VDEC_R 82 -#define VENC_R 83 -#define WWDG1_R 84 -#define WWDG2_R 85 -#define VREF_R 86 -#define DTS_R 87 -#define CRC_R 88 -#define SERC_R 89 -#define OSPIIOM_R 90 -#define I3C1_R 91 -#define I3C2_R 92 -#define I3C3_R 93 -#define I3C4_R 94 -#define IWDG2_KER_R 95 -#define IWDG4_KER_R 96 -#define RNG_R 97 -#define PKA_R 98 -#define SAES_R 99 -#define HASH_R 100 -#define CRYP1_R 101 -#define CRYP2_R 102 -#define PCIE_R 103 -#define OSPI1_R 104 -#define OSPI1DLL_R 105 -#define OSPI2_R 106 -#define OSPI2DLL_R 107 -#define FMC_R 108 -#define DBG_R 109 -#define GPIOA_R 110 -#define GPIOB_R 111 -#define GPIOC_R 112 -#define GPIOD_R 113 -#define GPIOE_R 114 -#define GPIOF_R 115 -#define GPIOG_R 116 -#define GPIOH_R 117 -#define GPIOI_R 118 -#define GPIOJ_R 119 -#define GPIOK_R 120 -#define GPIOZ_R 121 -#define HPDMA1_R 122 -#define HPDMA2_R 123 -#define HPDMA3_R 124 -#define LPDMA_R 125 -#define HSEM_R 126 -#define IPCC1_R 127 -#define IPCC2_R 128 -#define C2_HOLDBOOT_R 129 -#define C1_HOLDBOOT_R 130 -#define C1_R 131 -#define C1P1POR_R 132 -#define C1P1_R 133 -#define C2_R 134 -#define C3_R 135 -#define SYS_R 136 -#define VSW_R 137 -#define C1MS_R 138 -#define DDRCP_R 139 -#define DDRCAPB_R 140 -#define DDRPHYCAPB_R 141 -#define DDRCFG_R 142 -#define DDR_R 143 - -#define STM32MP25_LAST_RESET 144 - -#define RST_SCMI_C1_R 0 -#define RST_SCMI_C2_R 1 -#define RST_SCMI_C1_HOLDBOOT_R 2 -#define RST_SCMI_C2_HOLDBOOT_R 3 -#define RST_SCMI_FMC 4 -#define RST_SCMI_OSPI1 5 -#define RST_SCMI_OSPI1DLL 6 -#define RST_SCMI_OSPI2 7 -#define RST_SCMI_OSPI2DLL 8 - -#endif /* _DT_BINDINGS_STM32MP25_RESET_H_ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h deleted file mode 100644 index eaf4a0d84f6..00000000000 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ /dev/null @@ -1,214 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ -#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ - -/* SYSCRG resets */ -#define JH7110_SYSRST_JTAG_APB 0 -#define JH7110_SYSRST_SYSCON_APB 1 -#define JH7110_SYSRST_IOMUX_APB 2 -#define JH7110_SYSRST_BUS 3 -#define JH7110_SYSRST_DEBUG 4 -#define JH7110_SYSRST_CORE0 5 -#define JH7110_SYSRST_CORE1 6 -#define JH7110_SYSRST_CORE2 7 -#define JH7110_SYSRST_CORE3 8 -#define JH7110_SYSRST_CORE4 9 -#define JH7110_SYSRST_CORE0_ST 10 -#define JH7110_SYSRST_CORE1_ST 11 -#define JH7110_SYSRST_CORE2_ST 12 -#define JH7110_SYSRST_CORE3_ST 13 -#define JH7110_SYSRST_CORE4_ST 14 -#define JH7110_SYSRST_TRACE0 15 -#define JH7110_SYSRST_TRACE1 16 -#define JH7110_SYSRST_TRACE2 17 -#define JH7110_SYSRST_TRACE3 18 -#define JH7110_SYSRST_TRACE4 19 -#define JH7110_SYSRST_TRACE_COM 20 -#define JH7110_SYSRST_GPU_APB 21 -#define JH7110_SYSRST_GPU_DOMA 22 -#define JH7110_SYSRST_NOC_BUS_APB 23 -#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 -#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 -#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 -#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 -#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 -#define JH7110_SYSRST_NOC_BUS_DDRC 29 -#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 -#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 - -#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 -#define JH7110_SYSRST_AXI_CFG1_AHB 33 -#define JH7110_SYSRST_AXI_CFG1_MAIN 34 -#define JH7110_SYSRST_AXI_CFG0_MAIN 35 -#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36 -#define JH7110_SYSRST_AXI_CFG0_HIFI4 37 -#define JH7110_SYSRST_DDR_AXI 38 -#define JH7110_SYSRST_DDR_OSC 39 -#define JH7110_SYSRST_DDR_APB 40 -#define JH7110_SYSRST_ISP_TOP 41 -#define JH7110_SYSRST_ISP_TOP_AXI 42 -#define JH7110_SYSRST_VOUT_TOP_SRC 43 -#define JH7110_SYSRST_CODAJ12_AXI 44 -#define JH7110_SYSRST_CODAJ12_CORE 45 -#define JH7110_SYSRST_CODAJ12_APB 46 -#define JH7110_SYSRST_WAVE511_AXI 47 -#define JH7110_SYSRST_WAVE511_BPU 48 -#define JH7110_SYSRST_WAVE511_VCE 49 -#define JH7110_SYSRST_WAVE511_APB 50 -#define JH7110_SYSRST_VDEC_JPG 51 -#define JH7110_SYSRST_VDEC_MAIN 52 -#define JH7110_SYSRST_AXIMEM0_AXI 53 -#define JH7110_SYSRST_WAVE420L_AXI 54 -#define JH7110_SYSRST_WAVE420L_BPU 55 -#define JH7110_SYSRST_WAVE420L_VCE 56 -#define JH7110_SYSRST_WAVE420L_APB 57 -#define JH7110_SYSRST_AXIMEM1_AXI 58 -#define JH7110_SYSRST_AXIMEM2_AXI 59 -#define JH7110_SYSRST_INTMEM 60 -#define JH7110_SYSRST_QSPI_AHB 61 -#define JH7110_SYSRST_QSPI_APB 62 -#define JH7110_SYSRST_QSPI_REF 63 - -#define JH7110_SYSRST_SDIO0_AHB 64 -#define JH7110_SYSRST_SDIO1_AHB 65 -#define JH7110_SYSRST_GMAC1_AXI 66 -#define JH7110_SYSRST_GMAC1_AHB 67 -#define JH7110_SYSRST_MAILBOX_APB 68 -#define JH7110_SYSRST_SPI0_APB 69 -#define JH7110_SYSRST_SPI1_APB 70 -#define JH7110_SYSRST_SPI2_APB 71 -#define JH7110_SYSRST_SPI3_APB 72 -#define JH7110_SYSRST_SPI4_APB 73 -#define JH7110_SYSRST_SPI5_APB 74 -#define JH7110_SYSRST_SPI6_APB 75 -#define JH7110_SYSRST_I2C0_APB 76 -#define JH7110_SYSRST_I2C1_APB 77 -#define JH7110_SYSRST_I2C2_APB 78 -#define JH7110_SYSRST_I2C3_APB 79 -#define JH7110_SYSRST_I2C4_APB 80 -#define JH7110_SYSRST_I2C5_APB 81 -#define JH7110_SYSRST_I2C6_APB 82 -#define JH7110_SYSRST_UART0_APB 83 -#define JH7110_SYSRST_UART0_CORE 84 -#define JH7110_SYSRST_UART1_APB 85 -#define JH7110_SYSRST_UART1_CORE 86 -#define JH7110_SYSRST_UART2_APB 87 -#define JH7110_SYSRST_UART2_CORE 88 -#define JH7110_SYSRST_UART3_APB 89 -#define JH7110_SYSRST_UART3_CORE 90 -#define JH7110_SYSRST_UART4_APB 91 -#define JH7110_SYSRST_UART4_CORE 92 -#define JH7110_SYSRST_UART5_APB 93 -#define JH7110_SYSRST_UART5_CORE 94 -#define JH7110_SYSRST_SPDIF_APB 95 - -#define JH7110_SYSRST_PWMDAC_APB 96 -#define JH7110_SYSRST_PDM_DMIC 97 -#define JH7110_SYSRST_PDM_APB 98 -#define JH7110_SYSRST_I2SRX_APB 99 -#define JH7110_SYSRST_I2SRX_BCLK 100 -#define JH7110_SYSRST_I2STX0_APB 101 -#define JH7110_SYSRST_I2STX0_BCLK 102 -#define JH7110_SYSRST_I2STX1_APB 103 -#define JH7110_SYSRST_I2STX1_BCLK 104 -#define JH7110_SYSRST_TDM_AHB 105 -#define JH7110_SYSRST_TDM_CORE 106 -#define JH7110_SYSRST_TDM_APB 107 -#define JH7110_SYSRST_PWM_APB 108 -#define JH7110_SYSRST_WDT_APB 109 -#define JH7110_SYSRST_WDT_CORE 110 -#define JH7110_SYSRST_CAN0_APB 111 -#define JH7110_SYSRST_CAN0_CORE 112 -#define JH7110_SYSRST_CAN0_TIMER 113 -#define JH7110_SYSRST_CAN1_APB 114 -#define JH7110_SYSRST_CAN1_CORE 115 -#define JH7110_SYSRST_CAN1_TIMER 116 -#define JH7110_SYSRST_TIMER_APB 117 -#define JH7110_SYSRST_TIMER0 118 -#define JH7110_SYSRST_TIMER1 119 -#define JH7110_SYSRST_TIMER2 120 -#define JH7110_SYSRST_TIMER3 121 -#define JH7110_SYSRST_INT_CTRL_APB 122 -#define JH7110_SYSRST_TEMP_APB 123 -#define JH7110_SYSRST_TEMP_CORE 124 -#define JH7110_SYSRST_JTAG_CERTIFICATION 125 - -#define JH7110_SYSRST_END 126 - -/* AONCRG resets */ -#define JH7110_AONRST_GMAC0_AXI 0 -#define JH7110_AONRST_GMAC0_AHB 1 -#define JH7110_AONRST_IOMUX 2 -#define JH7110_AONRST_PMU_APB 3 -#define JH7110_AONRST_PMU_WKUP 4 -#define JH7110_AONRST_RTC_APB 5 -#define JH7110_AONRST_RTC_CAL 6 -#define JH7110_AONRST_RTC_32K 7 - -#define JH7110_AONRST_END 8 - -/* STGCRG resets */ -#define JH7110_STGRST_SYSCON 0 -#define JH7110_STGRST_HIFI4_CORE 1 -#define JH7110_STGRST_HIFI4_AXI 2 -#define JH7110_STGRST_SEC_AHB 3 -#define JH7110_STGRST_E24_CORE 4 -#define JH7110_STGRST_DMA1P_AXI 5 -#define JH7110_STGRST_DMA1P_AHB 6 -#define JH7110_STGRST_USB0_AXI 7 -#define JH7110_STGRST_USB0_APB 8 -#define JH7110_STGRST_USB0_UTMI_APB 9 -#define JH7110_STGRST_USB0_PWRUP 10 -#define JH7110_STGRST_PCIE0_AXI_MST0 11 -#define JH7110_STGRST_PCIE0_AXI_SLV0 12 -#define JH7110_STGRST_PCIE0_AXI_SLV 13 -#define JH7110_STGRST_PCIE0_BRG 14 -#define JH7110_STGRST_PCIE0_CORE 15 -#define JH7110_STGRST_PCIE0_APB 16 -#define JH7110_STGRST_PCIE1_AXI_MST0 17 -#define JH7110_STGRST_PCIE1_AXI_SLV0 18 -#define JH7110_STGRST_PCIE1_AXI_SLV 19 -#define JH7110_STGRST_PCIE1_BRG 20 -#define JH7110_STGRST_PCIE1_CORE 21 -#define JH7110_STGRST_PCIE1_APB 22 - -#define JH7110_STGRST_END 23 - -/* ISPCRG resets */ -#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0 -#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1 -#define JH7110_ISPRST_M31DPHY_HW 2 -#define JH7110_ISPRST_M31DPHY_B09_AON 3 -#define JH7110_ISPRST_VIN_APB 4 -#define JH7110_ISPRST_VIN_PIXEL_IF0 5 -#define JH7110_ISPRST_VIN_PIXEL_IF1 6 -#define JH7110_ISPRST_VIN_PIXEL_IF2 7 -#define JH7110_ISPRST_VIN_PIXEL_IF3 8 -#define JH7110_ISPRST_VIN_SYS 9 -#define JH7110_ISPRST_VIN_P_AXI_RD 10 -#define JH7110_ISPRST_VIN_P_AXI_WR 11 - -#define JH7110_ISPRST_END 12 - -/* VOUTCRG resets */ -#define JH7110_VOUTRST_DC8200_AXI 0 -#define JH7110_VOUTRST_DC8200_AHB 1 -#define JH7110_VOUTRST_DC8200_CORE 2 -#define JH7110_VOUTRST_DSITX_DPI 3 -#define JH7110_VOUTRST_DSITX_APB 4 -#define JH7110_VOUTRST_DSITX_RXESC 5 -#define JH7110_VOUTRST_DSITX_SYS 6 -#define JH7110_VOUTRST_DSITX_TXBYTEHS 7 -#define JH7110_VOUTRST_DSITX_TXESC 8 -#define JH7110_VOUTRST_HDMI_TX_HDMI 9 -#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10 -#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11 - -#define JH7110_VOUTRST_END 12 - -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/reset/starfive-jh7100.h b/include/dt-bindings/reset/starfive-jh7100.h deleted file mode 100644 index 540e19254f3..00000000000 --- a/include/dt-bindings/reset/starfive-jh7100.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR MIT */ -/* - * Copyright (C) 2021 Ahmad Fatoum, Pengutronix - */ - -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ -#define __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ - -#define JH7100_RSTN_DOM3AHB_BUS 0 -#define JH7100_RSTN_DOM7AHB_BUS 1 -#define JH7100_RST_U74 2 -#define JH7100_RSTN_U74_AXI 3 -#define JH7100_RSTN_SGDMA2P_AHB 4 -#define JH7100_RSTN_SGDMA2P_AXI 5 -#define JH7100_RSTN_DMA2PNOC_AXI 6 -#define JH7100_RSTN_DLA_AXI 7 -#define JH7100_RSTN_DLANOC_AXI 8 -#define JH7100_RSTN_DLA_APB 9 -#define JH7100_RST_VP6_DRESET 10 -#define JH7100_RST_VP6_BRESET 11 -#define JH7100_RSTN_VP6_AXI 12 -#define JH7100_RSTN_VDECBRG_MAIN 13 -#define JH7100_RSTN_VDEC_AXI 14 -#define JH7100_RSTN_VDEC_BCLK 15 -#define JH7100_RSTN_VDEC_CCLK 16 -#define JH7100_RSTN_VDEC_APB 17 -#define JH7100_RSTN_JPEG_AXI 18 -#define JH7100_RSTN_JPEG_CCLK 19 -#define JH7100_RSTN_JPEG_APB 20 -#define JH7100_RSTN_JPCGC300_MAIN 21 -#define JH7100_RSTN_GC300_2X 22 -#define JH7100_RSTN_GC300_AXI 23 -#define JH7100_RSTN_GC300_AHB 24 -#define JH7100_RSTN_VENC_AXI 25 -#define JH7100_RSTN_VENCBRG_MAIN 26 -#define JH7100_RSTN_VENC_BCLK 27 -#define JH7100_RSTN_VENC_CCLK 28 -#define JH7100_RSTN_VENC_APB 29 -#define JH7100_RSTN_DDRPHY_APB 30 -#define JH7100_RSTN_NOC_ROB 31 -#define JH7100_RSTN_NOC_COG 32 -#define JH7100_RSTN_HIFI4_AXI 33 -#define JH7100_RSTN_HIFI4NOC_AXI 34 -#define JH7100_RST_HIFI4_DRESET 35 -#define JH7100_RST_HIFI4_BRESET 36 -#define JH7100_RSTN_USB_AXI 37 -#define JH7100_RSTN_USBNOC_AXI 38 -#define JH7100_RSTN_SGDMA1P_AXI 39 -#define JH7100_RSTN_DMA1P_AXI 40 -#define JH7100_RSTN_X2C_AXI 41 -#define JH7100_RSTN_NNE_AHB 42 -#define JH7100_RSTN_NNE_AXI 43 -#define JH7100_RSTN_NNENOC_AXI 44 -#define JH7100_RSTN_DLASLV_AXI 45 -#define JH7100_RSTN_DSPX2C_AXI 46 -#define JH7100_RSTN_VIN_SRC 47 -#define JH7100_RSTN_ISPSLV_AXI 48 -#define JH7100_RSTN_VIN_AXI 49 -#define JH7100_RSTN_VINNOC_AXI 50 -#define JH7100_RSTN_ISP0_AXI 51 -#define JH7100_RSTN_ISP0NOC_AXI 52 -#define JH7100_RSTN_ISP1_AXI 53 -#define JH7100_RSTN_ISP1NOC_AXI 54 -#define JH7100_RSTN_VOUT_SRC 55 -#define JH7100_RSTN_DISP_AXI 56 -#define JH7100_RSTN_DISPNOC_AXI 57 -#define JH7100_RSTN_SDIO0_AHB 58 -#define JH7100_RSTN_SDIO1_AHB 59 -#define JH7100_RSTN_GMAC_AHB 60 -#define JH7100_RSTN_SPI2AHB_AHB 61 -#define JH7100_RSTN_SPI2AHB_CORE 62 -#define JH7100_RSTN_EZMASTER_AHB 63 -#define JH7100_RST_E24 64 -#define JH7100_RSTN_QSPI_AHB 65 -#define JH7100_RSTN_QSPI_CORE 66 -#define JH7100_RSTN_QSPI_APB 67 -#define JH7100_RSTN_SEC_AHB 68 -#define JH7100_RSTN_AES 69 -#define JH7100_RSTN_PKA 70 -#define JH7100_RSTN_SHA 71 -#define JH7100_RSTN_TRNG_APB 72 -#define JH7100_RSTN_OTP_APB 73 -#define JH7100_RSTN_UART0_APB 74 -#define JH7100_RSTN_UART0_CORE 75 -#define JH7100_RSTN_UART1_APB 76 -#define JH7100_RSTN_UART1_CORE 77 -#define JH7100_RSTN_SPI0_APB 78 -#define JH7100_RSTN_SPI0_CORE 79 -#define JH7100_RSTN_SPI1_APB 80 -#define JH7100_RSTN_SPI1_CORE 81 -#define JH7100_RSTN_I2C0_APB 82 -#define JH7100_RSTN_I2C0_CORE 83 -#define JH7100_RSTN_I2C1_APB 84 -#define JH7100_RSTN_I2C1_CORE 85 -#define JH7100_RSTN_GPIO_APB 86 -#define JH7100_RSTN_UART2_APB 87 -#define JH7100_RSTN_UART2_CORE 88 -#define JH7100_RSTN_UART3_APB 89 -#define JH7100_RSTN_UART3_CORE 90 -#define JH7100_RSTN_SPI2_APB 91 -#define JH7100_RSTN_SPI2_CORE 92 -#define JH7100_RSTN_SPI3_APB 93 -#define JH7100_RSTN_SPI3_CORE 94 -#define JH7100_RSTN_I2C2_APB 95 -#define JH7100_RSTN_I2C2_CORE 96 -#define JH7100_RSTN_I2C3_APB 97 -#define JH7100_RSTN_I2C3_CORE 98 -#define JH7100_RSTN_WDTIMER_APB 99 -#define JH7100_RSTN_WDT 100 -#define JH7100_RSTN_TIMER0 101 -#define JH7100_RSTN_TIMER1 102 -#define JH7100_RSTN_TIMER2 103 -#define JH7100_RSTN_TIMER3 104 -#define JH7100_RSTN_TIMER4 105 -#define JH7100_RSTN_TIMER5 106 -#define JH7100_RSTN_TIMER6 107 -#define JH7100_RSTN_VP6INTC_APB 108 -#define JH7100_RSTN_PWM_APB 109 -#define JH7100_RSTN_MSI_APB 110 -#define JH7100_RSTN_TEMP_APB 111 -#define JH7100_RSTN_TEMP_SENSE 112 -#define JH7100_RSTN_SYSERR_APB 113 - -#define JH7100_RSTN_END 114 - -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7100_H__ */ diff --git a/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h b/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h deleted file mode 100644 index ea906896c70..00000000000 --- a/include/dt-bindings/reset/stericsson,db8500-prcc-reset.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _DT_BINDINGS_STE_PRCC_RESET -#define _DT_BINDINGS_STE_PRCC_RESET - -#define DB8500_PRCC_1 1 -#define DB8500_PRCC_2 2 -#define DB8500_PRCC_3 3 -#define DB8500_PRCC_6 6 - -/* Reset lines on PRCC 1 */ -#define DB8500_PRCC_1_RESET_UART0 0 -#define DB8500_PRCC_1_RESET_UART1 1 -#define DB8500_PRCC_1_RESET_I2C1 2 -#define DB8500_PRCC_1_RESET_MSP0 3 -#define DB8500_PRCC_1_RESET_MSP1 4 -#define DB8500_PRCC_1_RESET_SDI0 5 -#define DB8500_PRCC_1_RESET_I2C2 6 -#define DB8500_PRCC_1_RESET_SPI3 7 -#define DB8500_PRCC_1_RESET_SLIMBUS0 8 -#define DB8500_PRCC_1_RESET_I2C4 9 -#define DB8500_PRCC_1_RESET_MSP3 10 -#define DB8500_PRCC_1_RESET_PER_MSP3 11 -#define DB8500_PRCC_1_RESET_PER_MSP1 12 -#define DB8500_PRCC_1_RESET_PER_MSP0 13 -#define DB8500_PRCC_1_RESET_PER_SLIMBUS 14 - -/* Reset lines on PRCC 2 */ -#define DB8500_PRCC_2_RESET_I2C3 0 -#define DB8500_PRCC_2_RESET_PWL 1 -#define DB8500_PRCC_2_RESET_SDI4 2 -#define DB8500_PRCC_2_RESET_MSP2 3 -#define DB8500_PRCC_2_RESET_SDI1 4 -#define DB8500_PRCC_2_RESET_SDI3 5 -#define DB8500_PRCC_2_RESET_HSIRX 6 -#define DB8500_PRCC_2_RESET_HSITX 7 -#define DB8500_PRCC_1_RESET_PER_MSP2 8 - -/* Reset lines on PRCC 3 */ -#define DB8500_PRCC_3_RESET_SSP0 1 -#define DB8500_PRCC_3_RESET_SSP1 2 -#define DB8500_PRCC_3_RESET_I2C0 3 -#define DB8500_PRCC_3_RESET_SDI2 4 -#define DB8500_PRCC_3_RESET_SKE 5 -#define DB8500_PRCC_3_RESET_UART2 6 -#define DB8500_PRCC_3_RESET_SDI5 7 - -/* Reset lines on PRCC 6 */ -#define DB8500_PRCC_3_RESET_RNG 0 - -#endif diff --git a/include/dt-bindings/reset/stih407-resets.h b/include/dt-bindings/reset/stih407-resets.h deleted file mode 100644 index f2a2c4f7f06..00000000000 --- a/include/dt-bindings/reset/stih407-resets.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the reset controller - * based peripheral powerdown requests on the STMicroelectronics - * STiH407 SoC. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407 -#define _DT_BINDINGS_RESET_CONTROLLER_STIH407 - -/* Powerdown requests control 0 */ -#define STIH407_EMISS_POWERDOWN 0 -#define STIH407_NAND_POWERDOWN 1 - -/* Synp GMAC PowerDown */ -#define STIH407_ETH1_POWERDOWN 2 - -/* Powerdown requests control 1 */ -#define STIH407_USB3_POWERDOWN 3 -#define STIH407_USB2_PORT1_POWERDOWN 4 -#define STIH407_USB2_PORT0_POWERDOWN 5 -#define STIH407_PCIE1_POWERDOWN 6 -#define STIH407_PCIE0_POWERDOWN 7 -#define STIH407_SATA1_POWERDOWN 8 -#define STIH407_SATA0_POWERDOWN 9 - -/* Reset defines */ -#define STIH407_ETH1_SOFTRESET 0 -#define STIH407_MMC1_SOFTRESET 1 -#define STIH407_PICOPHY_SOFTRESET 2 -#define STIH407_IRB_SOFTRESET 3 -#define STIH407_PCIE0_SOFTRESET 4 -#define STIH407_PCIE1_SOFTRESET 5 -#define STIH407_SATA0_SOFTRESET 6 -#define STIH407_SATA1_SOFTRESET 7 -#define STIH407_MIPHY0_SOFTRESET 8 -#define STIH407_MIPHY1_SOFTRESET 9 -#define STIH407_MIPHY2_SOFTRESET 10 -#define STIH407_SATA0_PWR_SOFTRESET 11 -#define STIH407_SATA1_PWR_SOFTRESET 12 -#define STIH407_DELTA_SOFTRESET 13 -#define STIH407_BLITTER_SOFTRESET 14 -#define STIH407_HDTVOUT_SOFTRESET 15 -#define STIH407_HDQVDP_SOFTRESET 16 -#define STIH407_VDP_AUX_SOFTRESET 17 -#define STIH407_COMPO_SOFTRESET 18 -#define STIH407_HDMI_TX_PHY_SOFTRESET 19 -#define STIH407_JPEG_DEC_SOFTRESET 20 -#define STIH407_VP8_DEC_SOFTRESET 21 -#define STIH407_GPU_SOFTRESET 22 -#define STIH407_HVA_SOFTRESET 23 -#define STIH407_ERAM_HVA_SOFTRESET 24 -#define STIH407_LPM_SOFTRESET 25 -#define STIH407_KEYSCAN_SOFTRESET 26 -#define STIH407_USB2_PORT0_SOFTRESET 27 -#define STIH407_USB2_PORT1_SOFTRESET 28 -#define STIH407_ST231_AUD_SOFTRESET 29 -#define STIH407_ST231_DMU_SOFTRESET 30 -#define STIH407_ST231_GP0_SOFTRESET 31 -#define STIH407_ST231_GP1_SOFTRESET 32 - -/* Picophy reset defines */ -#define STIH407_PICOPHY0_RESET 0 -#define STIH407_PICOPHY1_RESET 1 -#define STIH407_PICOPHY2_RESET 2 - -#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h deleted file mode 100644 index 9071f139649..00000000000 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ -#define _DT_BINDINGS_STM32MP1_RESET_H_ - -#define MCU_HOLD_BOOT_R 2144 -#define LTDC_R 3072 -#define DSI_R 3076 -#define DDRPERFM_R 3080 -#define USBPHY_R 3088 -#define SPI6_R 3136 -#define I2C4_R 3138 -#define I2C6_R 3139 -#define USART1_R 3140 -#define STGEN_R 3156 -#define GPIOZ_R 3200 -#define CRYP1_R 3204 -#define HASH1_R 3205 -#define RNG1_R 3206 -#define AXIM_R 3216 -#define GPU_R 3269 -#define ETHMAC_R 3274 -#define FMC_R 3276 -#define QSPI_R 3278 -#define SDMMC1_R 3280 -#define SDMMC2_R 3281 -#define CRC1_R 3284 -#define USBH_R 3288 -#define MDMA_R 3328 -#define MCU_R 8225 -#define TIM2_R 19456 -#define TIM3_R 19457 -#define TIM4_R 19458 -#define TIM5_R 19459 -#define TIM6_R 19460 -#define TIM7_R 19461 -#define TIM12_R 16462 -#define TIM13_R 16463 -#define TIM14_R 16464 -#define LPTIM1_R 19465 -#define SPI2_R 19467 -#define SPI3_R 19468 -#define USART2_R 19470 -#define USART3_R 19471 -#define UART4_R 19472 -#define UART5_R 19473 -#define UART7_R 19474 -#define UART8_R 19475 -#define I2C1_R 19477 -#define I2C2_R 19478 -#define I2C3_R 19479 -#define I2C5_R 19480 -#define SPDIF_R 19482 -#define CEC_R 19483 -#define DAC12_R 19485 -#define MDIO_R 19847 -#define TIM1_R 19520 -#define TIM8_R 19521 -#define TIM15_R 19522 -#define TIM16_R 19523 -#define TIM17_R 19524 -#define SPI1_R 19528 -#define SPI4_R 19529 -#define SPI5_R 19530 -#define USART6_R 19533 -#define SAI1_R 19536 -#define SAI2_R 19537 -#define SAI3_R 19538 -#define DFSDM_R 19540 -#define FDCAN_R 19544 -#define LPTIM2_R 19584 -#define LPTIM3_R 19585 -#define LPTIM4_R 19586 -#define LPTIM5_R 19587 -#define SAI4_R 19592 -#define SYSCFG_R 19595 -#define VREF_R 19597 -#define TMPSENS_R 19600 -#define PMBCTRL_R 19601 -#define DMA1_R 19648 -#define DMA2_R 19649 -#define DMAMUX_R 19650 -#define ADC12_R 19653 -#define USBO_R 19656 -#define SDMMC3_R 19664 -#define CAMITF_R 19712 -#define CRYP2_R 19716 -#define HASH2_R 19717 -#define RNG2_R 19718 -#define CRC2_R 19719 -#define HSEM_R 19723 -#define MBOX_R 19724 -#define GPIOA_R 19776 -#define GPIOB_R 19777 -#define GPIOC_R 19778 -#define GPIOD_R 19779 -#define GPIOE_R 19780 -#define GPIOF_R 19781 -#define GPIOG_R 19782 -#define GPIOH_R 19783 -#define GPIOI_R 19784 -#define GPIOJ_R 19785 -#define GPIOK_R 19786 - -/* SCMI reset domain identifiers */ -#define RST_SCMI_SPI6 0 -#define RST_SCMI_I2C4 1 -#define RST_SCMI_I2C6 2 -#define RST_SCMI_USART1 3 -#define RST_SCMI_STGEN 4 -#define RST_SCMI_GPIOZ 5 -#define RST_SCMI_CRYP1 6 -#define RST_SCMI_HASH1 7 -#define RST_SCMI_RNG1 8 -#define RST_SCMI_MDMA 9 -#define RST_SCMI_MCU 10 -#define RST_SCMI_MCU_HOLD_BOOT 11 - -#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h deleted file mode 100644 index ecb37c7ddde..00000000000 --- a/include/dt-bindings/reset/stm32mp13-resets.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. - */ - -#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ -#define _DT_BINDINGS_STM32MP13_RESET_H_ - -#define TIM2_R 13568 -#define TIM3_R 13569 -#define TIM4_R 13570 -#define TIM5_R 13571 -#define TIM6_R 13572 -#define TIM7_R 13573 -#define LPTIM1_R 13577 -#define SPI2_R 13579 -#define SPI3_R 13580 -#define USART3_R 13583 -#define UART4_R 13584 -#define UART5_R 13585 -#define UART7_R 13586 -#define UART8_R 13587 -#define I2C1_R 13589 -#define I2C2_R 13590 -#define SPDIF_R 13594 -#define TIM1_R 13632 -#define TIM8_R 13633 -#define SPI1_R 13640 -#define USART6_R 13645 -#define SAI1_R 13648 -#define SAI2_R 13649 -#define DFSDM_R 13652 -#define FDCAN_R 13656 -#define LPTIM2_R 13696 -#define LPTIM3_R 13697 -#define LPTIM4_R 13698 -#define LPTIM5_R 13699 -#define SYSCFG_R 13707 -#define VREF_R 13709 -#define DTS_R 13712 -#define PMBCTRL_R 13713 -#define LTDC_R 13760 -#define DCMIPP_R 13761 -#define DDRPERFM_R 13768 -#define USBPHY_R 13776 -#define STGEN_R 13844 -#define USART1_R 13888 -#define USART2_R 13889 -#define SPI4_R 13890 -#define SPI5_R 13891 -#define I2C3_R 13892 -#define I2C4_R 13893 -#define I2C5_R 13894 -#define TIM12_R 13895 -#define TIM13_R 13896 -#define TIM14_R 13897 -#define TIM15_R 13898 -#define TIM16_R 13899 -#define TIM17_R 13900 -#define DMA1_R 13952 -#define DMA2_R 13953 -#define DMAMUX1_R 13954 -#define DMA3_R 13955 -#define DMAMUX2_R 13956 -#define ADC1_R 13957 -#define ADC2_R 13958 -#define USBO_R 13960 -#define GPIOA_R 14080 -#define GPIOB_R 14081 -#define GPIOC_R 14082 -#define GPIOD_R 14083 -#define GPIOE_R 14084 -#define GPIOF_R 14085 -#define GPIOG_R 14086 -#define GPIOH_R 14087 -#define GPIOI_R 14088 -#define TSC_R 14095 -#define PKA_R 14146 -#define SAES_R 14147 -#define CRYP1_R 14148 -#define HASH1_R 14149 -#define RNG1_R 14150 -#define AXIMC_R 14160 -#define MDMA_R 14208 -#define MCE_R 14209 -#define ETH1MAC_R 14218 -#define FMC_R 14220 -#define QSPI_R 14222 -#define SDMMC1_R 14224 -#define SDMMC2_R 14225 -#define CRC1_R 14228 -#define USBH_R 14232 -#define ETH2MAC_R 14238 - -/* SCMI reset domain identifiers */ -#define RST_SCMI_LTDC 0 -#define RST_SCMI_MDMA 1 - -#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h deleted file mode 100644 index 79e52aca591..00000000000 --- a/include/dt-bindings/reset/sun20i-d1-ccu.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2020 huangzhenwei@allwinnertech.com - * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> - */ - -#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ -#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ - -#define RST_MBUS 0 -#define RST_BUS_DE 1 -#define RST_BUS_DI 2 -#define RST_BUS_G2D 3 -#define RST_BUS_CE 4 -#define RST_BUS_VE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MSGBOX0 7 -#define RST_BUS_MSGBOX1 8 -#define RST_BUS_MSGBOX2 9 -#define RST_BUS_SPINLOCK 10 -#define RST_BUS_HSTIMER 11 -#define RST_BUS_DBG 12 -#define RST_BUS_PWM 13 -#define RST_BUS_DRAM 14 -#define RST_BUS_MMC0 15 -#define RST_BUS_MMC1 16 -#define RST_BUS_MMC2 17 -#define RST_BUS_UART0 18 -#define RST_BUS_UART1 19 -#define RST_BUS_UART2 20 -#define RST_BUS_UART3 21 -#define RST_BUS_UART4 22 -#define RST_BUS_UART5 23 -#define RST_BUS_I2C0 24 -#define RST_BUS_I2C1 25 -#define RST_BUS_I2C2 26 -#define RST_BUS_I2C3 27 -#define RST_BUS_SPI0 28 -#define RST_BUS_SPI1 29 -#define RST_BUS_EMAC 30 -#define RST_BUS_IR_TX 31 -#define RST_BUS_GPADC 32 -#define RST_BUS_THS 33 -#define RST_BUS_I2S0 34 -#define RST_BUS_I2S1 35 -#define RST_BUS_I2S2 36 -#define RST_BUS_SPDIF 37 -#define RST_BUS_DMIC 38 -#define RST_BUS_AUDIO 39 -#define RST_USB_PHY0 40 -#define RST_USB_PHY1 41 -#define RST_BUS_OHCI0 42 -#define RST_BUS_OHCI1 43 -#define RST_BUS_EHCI0 44 -#define RST_BUS_EHCI1 45 -#define RST_BUS_OTG 46 -#define RST_BUS_LRADC 47 -#define RST_BUS_DPSS_TOP 48 -#define RST_BUS_HDMI_SUB 49 -#define RST_BUS_HDMI_MAIN 50 -#define RST_BUS_MIPI_DSI 51 -#define RST_BUS_TCON_LCD0 52 -#define RST_BUS_TCON_TV 53 -#define RST_BUS_LVDS0 54 -#define RST_BUS_TVE 55 -#define RST_BUS_TVE_TOP 56 -#define RST_BUS_TVD 57 -#define RST_BUS_TVD_TOP 58 -#define RST_BUS_LEDC 59 -#define RST_BUS_CSI 60 -#define RST_BUS_TPADC 61 -#define RST_DSP 62 -#define RST_BUS_DSP_CFG 63 -#define RST_BUS_DSP_DBG 64 -#define RST_BUS_RISCV_CFG 65 -#define RST_BUS_CAN0 66 -#define RST_BUS_CAN1 67 - -#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h deleted file mode 100644 index e20babc990a..00000000000 --- a/include/dt-bindings/reset/sun20i-d1-r-ccu.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2021 Samuel Holland <samuel@sholland.org> - */ - -#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ - -#define RST_BUS_R_TIMER 0 -#define RST_BUS_R_TWD 1 -#define RST_BUS_R_PPU 2 -#define RST_BUS_R_IR_RX 3 -#define RST_BUS_R_RTC 4 -#define RST_BUS_R_CPUCFG 5 - -#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun4i-a10-ccu.h b/include/dt-bindings/reset/sun4i-a10-ccu.h deleted file mode 100644 index 5f4480bedc8..00000000000 --- a/include/dt-bindings/reset/sun4i-a10-ccu.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes <plaes@plaes.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN4I_A10_H -#define _DT_BINDINGS_RST_SUN4I_A10_H - -#define RST_USB_PHY0 1 -#define RST_USB_PHY1 2 -#define RST_USB_PHY2 3 -#define RST_GPS 4 -#define RST_DE_BE0 5 -#define RST_DE_BE1 6 -#define RST_DE_FE0 7 -#define RST_DE_FE1 8 -#define RST_DE_MP 9 -#define RST_TVE0 10 -#define RST_TCON0 11 -#define RST_TVE1 12 -#define RST_TCON1 13 -#define RST_CSI0 14 -#define RST_CSI1 15 -#define RST_VE 16 -#define RST_ACE 17 -#define RST_LVDS 18 -#define RST_GPU 19 -#define RST_HDMI_H 20 -#define RST_HDMI_SYS 21 -#define RST_HDMI_AUDIO_DMA 22 - -#endif /* DT_BINDINGS_RST_SUN4I_A10_H */ diff --git a/include/dt-bindings/reset/sun50i-a100-ccu.h b/include/dt-bindings/reset/sun50i-a100-ccu.h deleted file mode 100644 index d13764bc186..00000000000 --- a/include/dt-bindings/reset/sun50i-a100-ccu.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> - */ - -#ifndef _DT_BINDINGS_RESET_SUN50I_A100_H_ -#define _DT_BINDINGS_RESET_SUN50I_A100_H_ - -#define RST_MBUS 0 -#define RST_BUS_DE 1 -#define RST_BUS_G2D 2 -#define RST_BUS_GPU 3 -#define RST_BUS_CE 4 -#define RST_BUS_VE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MSGBOX 7 -#define RST_BUS_SPINLOCK 8 -#define RST_BUS_HSTIMER 9 -#define RST_BUS_DBG 10 -#define RST_BUS_PSI 11 -#define RST_BUS_PWM 12 -#define RST_BUS_DRAM 13 -#define RST_BUS_NAND 14 -#define RST_BUS_MMC0 15 -#define RST_BUS_MMC1 16 -#define RST_BUS_MMC2 17 -#define RST_BUS_UART0 18 -#define RST_BUS_UART1 19 -#define RST_BUS_UART2 20 -#define RST_BUS_UART3 21 -#define RST_BUS_UART4 22 -#define RST_BUS_I2C0 23 -#define RST_BUS_I2C1 24 -#define RST_BUS_I2C2 25 -#define RST_BUS_I2C3 26 -#define RST_BUS_SPI0 27 -#define RST_BUS_SPI1 28 -#define RST_BUS_SPI2 29 -#define RST_BUS_EMAC 30 -#define RST_BUS_IR_RX 31 -#define RST_BUS_IR_TX 32 -#define RST_BUS_GPADC 33 -#define RST_BUS_THS 34 -#define RST_BUS_I2S0 35 -#define RST_BUS_I2S1 36 -#define RST_BUS_I2S2 37 -#define RST_BUS_I2S3 38 -#define RST_BUS_SPDIF 39 -#define RST_BUS_DMIC 40 -#define RST_BUS_AUDIO_CODEC 41 -#define RST_USB_PHY0 42 -#define RST_USB_PHY1 43 -#define RST_BUS_OHCI0 44 -#define RST_BUS_OHCI1 45 -#define RST_BUS_EHCI0 46 -#define RST_BUS_EHCI1 47 -#define RST_BUS_OTG 48 -#define RST_BUS_LRADC 49 -#define RST_BUS_DPSS_TOP0 50 -#define RST_BUS_DPSS_TOP1 51 -#define RST_BUS_MIPI_DSI 52 -#define RST_BUS_TCON_LCD 53 -#define RST_BUS_LVDS 54 -#define RST_BUS_LEDC 55 -#define RST_BUS_CSI 56 -#define RST_BUS_CSI_ISP 57 - -#endif /* _DT_BINDINGS_RESET_SUN50I_A100_H_ */ diff --git a/include/dt-bindings/reset/sun50i-a100-r-ccu.h b/include/dt-bindings/reset/sun50i-a100-r-ccu.h deleted file mode 100644 index 1e7c4431f03..00000000000 --- a/include/dt-bindings/reset/sun50i-a100-r-ccu.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> - */ - -#ifndef _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ - -#define RST_R_APB1_TIMER 0 -#define RST_R_APB1_BUS_PWM 1 -#define RST_R_APB1_PPU 2 -#define RST_R_APB2_UART 3 -#define RST_R_APB2_I2C0 4 -#define RST_R_APB2_I2C1 5 -#define RST_R_APB1_BUS_IR 6 -#define RST_R_AHB_BUS_RTC 7 - -#endif /* _DT_BINDINGS_RST_SUN50I_A100_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h deleted file mode 100644 index db60b29ddb1..00000000000 --- a/include/dt-bindings/reset/sun50i-a64-ccu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ -#define _DT_BINDINGS_RST_SUN50I_A64_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 -#define RST_DRAM 3 -#define RST_MBUS 4 -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_CE 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_NAND 11 -#define RST_BUS_DRAM 12 -#define RST_BUS_EMAC 13 -#define RST_BUS_TS 14 -#define RST_BUS_HSTIMER 15 -#define RST_BUS_SPI0 16 -#define RST_BUS_SPI1 17 -#define RST_BUS_OTG 18 -#define RST_BUS_EHCI0 19 -#define RST_BUS_EHCI1 20 -#define RST_BUS_OHCI0 21 -#define RST_BUS_OHCI1 22 -#define RST_BUS_VE 23 -#define RST_BUS_TCON0 24 -#define RST_BUS_TCON1 25 -#define RST_BUS_DEINTERLACE 26 -#define RST_BUS_CSI 27 -#define RST_BUS_HDMI0 28 -#define RST_BUS_HDMI1 29 -#define RST_BUS_DE 30 -#define RST_BUS_GPU 31 -#define RST_BUS_MSGBOX 32 -#define RST_BUS_SPINLOCK 33 -#define RST_BUS_DBG 34 -#define RST_BUS_LVDS 35 -#define RST_BUS_CODEC 36 -#define RST_BUS_SPDIF 37 -#define RST_BUS_THS 38 -#define RST_BUS_I2S0 39 -#define RST_BUS_I2S1 40 -#define RST_BUS_I2S2 41 -#define RST_BUS_I2C0 42 -#define RST_BUS_I2C1 43 -#define RST_BUS_I2C2 44 -#define RST_BUS_SCR 45 -#define RST_BUS_UART0 46 -#define RST_BUS_UART1 47 -#define RST_BUS_UART2 48 -#define RST_BUS_UART3 49 -#define RST_BUS_UART4 50 - -#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h deleted file mode 100644 index d038ddfa481..00000000000 --- a/include/dt-bindings/reset/sun50i-h6-ccu.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> - */ - -#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ -#define _DT_BINDINGS_RESET_SUN50I_H6_H_ - -#define RST_MBUS 0 -#define RST_BUS_DE 1 -#define RST_BUS_DEINTERLACE 2 -#define RST_BUS_GPU 3 -#define RST_BUS_CE 4 -#define RST_BUS_VE 5 -#define RST_BUS_EMCE 6 -#define RST_BUS_VP9 7 -#define RST_BUS_DMA 8 -#define RST_BUS_MSGBOX 9 -#define RST_BUS_SPINLOCK 10 -#define RST_BUS_HSTIMER 11 -#define RST_BUS_DBG 12 -#define RST_BUS_PSI 13 -#define RST_BUS_PWM 14 -#define RST_BUS_IOMMU 15 -#define RST_BUS_DRAM 16 -#define RST_BUS_NAND 17 -#define RST_BUS_MMC0 18 -#define RST_BUS_MMC1 19 -#define RST_BUS_MMC2 20 -#define RST_BUS_UART0 21 -#define RST_BUS_UART1 22 -#define RST_BUS_UART2 23 -#define RST_BUS_UART3 24 -#define RST_BUS_I2C0 25 -#define RST_BUS_I2C1 26 -#define RST_BUS_I2C2 27 -#define RST_BUS_I2C3 28 -#define RST_BUS_SCR0 29 -#define RST_BUS_SCR1 30 -#define RST_BUS_SPI0 31 -#define RST_BUS_SPI1 32 -#define RST_BUS_EMAC 33 -#define RST_BUS_TS 34 -#define RST_BUS_IR_TX 35 -#define RST_BUS_THS 36 -#define RST_BUS_I2S0 37 -#define RST_BUS_I2S1 38 -#define RST_BUS_I2S2 39 -#define RST_BUS_I2S3 40 -#define RST_BUS_SPDIF 41 -#define RST_BUS_DMIC 42 -#define RST_BUS_AUDIO_HUB 43 -#define RST_USB_PHY0 44 -#define RST_USB_PHY1 45 -#define RST_USB_PHY3 46 -#define RST_USB_HSIC 47 -#define RST_BUS_OHCI0 48 -#define RST_BUS_OHCI3 49 -#define RST_BUS_EHCI0 50 -#define RST_BUS_XHCI 51 -#define RST_BUS_EHCI3 52 -#define RST_BUS_OTG 53 -#define RST_BUS_PCIE 54 -#define RST_PCIE_POWERUP 55 -#define RST_BUS_HDMI 56 -#define RST_BUS_HDMI_SUB 57 -#define RST_BUS_TCON_TOP 58 -#define RST_BUS_TCON_LCD0 59 -#define RST_BUS_TCON_TV0 60 -#define RST_BUS_CSI 61 -#define RST_BUS_HDCP 62 - -#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h deleted file mode 100644 index d541ade884f..00000000000 --- a/include/dt-bindings/reset/sun50i-h6-r-ccu.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - */ - -#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ - -#define RST_R_APB1_TIMER 0 -#define RST_R_APB1_TWD 1 -#define RST_R_APB1_PWM 2 -#define RST_R_APB2_UART 3 -#define RST_R_APB2_I2C 4 -#define RST_R_APB1_IR 5 -#define RST_R_APB1_W1 6 -#define RST_R_APB2_RSB 7 - -#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h deleted file mode 100644 index ba626f7015b..00000000000 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 Arm Ltd. - */ - -#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_ -#define _DT_BINDINGS_RESET_SUN50I_H616_H_ - -#define RST_MBUS 0 -#define RST_BUS_DE 1 -#define RST_BUS_DEINTERLACE 2 -#define RST_BUS_GPU 3 -#define RST_BUS_CE 4 -#define RST_BUS_VE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_HSTIMER 7 -#define RST_BUS_DBG 8 -#define RST_BUS_PSI 9 -#define RST_BUS_PWM 10 -#define RST_BUS_IOMMU 11 -#define RST_BUS_DRAM 12 -#define RST_BUS_NAND 13 -#define RST_BUS_MMC0 14 -#define RST_BUS_MMC1 15 -#define RST_BUS_MMC2 16 -#define RST_BUS_UART0 17 -#define RST_BUS_UART1 18 -#define RST_BUS_UART2 19 -#define RST_BUS_UART3 20 -#define RST_BUS_UART4 21 -#define RST_BUS_UART5 22 -#define RST_BUS_I2C0 23 -#define RST_BUS_I2C1 24 -#define RST_BUS_I2C2 25 -#define RST_BUS_I2C3 26 -#define RST_BUS_I2C4 27 -#define RST_BUS_SPI0 28 -#define RST_BUS_SPI1 29 -#define RST_BUS_EMAC0 30 -#define RST_BUS_EMAC1 31 -#define RST_BUS_TS 32 -#define RST_BUS_THS 33 -#define RST_BUS_SPDIF 34 -#define RST_BUS_DMIC 35 -#define RST_BUS_AUDIO_CODEC 36 -#define RST_BUS_AUDIO_HUB 37 -#define RST_USB_PHY0 38 -#define RST_USB_PHY1 39 -#define RST_USB_PHY2 40 -#define RST_USB_PHY3 41 -#define RST_BUS_OHCI0 42 -#define RST_BUS_OHCI1 43 -#define RST_BUS_OHCI2 44 -#define RST_BUS_OHCI3 45 -#define RST_BUS_EHCI0 46 -#define RST_BUS_EHCI1 47 -#define RST_BUS_EHCI2 48 -#define RST_BUS_EHCI3 49 -#define RST_BUS_OTG 50 -#define RST_BUS_HDMI 51 -#define RST_BUS_HDMI_SUB 52 -#define RST_BUS_TCON_TOP 53 -#define RST_BUS_TCON_TV0 54 -#define RST_BUS_TCON_TV1 55 -#define RST_BUS_TVE_TOP 56 -#define RST_BUS_TVE0 57 -#define RST_BUS_HDCP 58 -#define RST_BUS_KEYADC 59 -#define RST_BUS_GPADC 60 -#define RST_BUS_TCON_LCD0 61 -#define RST_BUS_TCON_LCD1 62 -#define RST_BUS_LVDS 63 - -#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-ccu.h b/include/dt-bindings/reset/sun55i-a523-ccu.h deleted file mode 100644 index 70df503f34f..00000000000 --- a/include/dt-bindings/reset/sun55i-a523-ccu.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Copyright (c) 2024 Arm Ltd. - */ - -#ifndef _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ -#define _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ - -#define RST_MBUS 0 -#define RST_BUS_NSI 1 -#define RST_BUS_DE 2 -#define RST_BUS_DI 3 -#define RST_BUS_G2D 4 -#define RST_BUS_SYS 5 -#define RST_BUS_GPU 6 -#define RST_BUS_CE 7 -#define RST_BUS_SYS_CE 8 -#define RST_BUS_VE 9 -#define RST_BUS_DMA 10 -#define RST_BUS_MSGBOX 11 -#define RST_BUS_SPINLOCK 12 -#define RST_BUS_CPUXTIMER 13 -#define RST_BUS_DBG 14 -#define RST_BUS_PWM0 15 -#define RST_BUS_PWM1 16 -#define RST_BUS_DRAM 17 -#define RST_BUS_NAND 18 -#define RST_BUS_MMC0 19 -#define RST_BUS_MMC1 20 -#define RST_BUS_MMC2 21 -#define RST_BUS_SYSDAP 22 -#define RST_BUS_UART0 23 -#define RST_BUS_UART1 24 -#define RST_BUS_UART2 25 -#define RST_BUS_UART3 26 -#define RST_BUS_UART4 27 -#define RST_BUS_UART5 28 -#define RST_BUS_UART6 29 -#define RST_BUS_UART7 30 -#define RST_BUS_I2C0 31 -#define RST_BUS_I2C1 32 -#define RST_BUS_I2C2 33 -#define RST_BUS_I2C3 34 -#define RST_BUS_I2C4 35 -#define RST_BUS_I2C5 36 -#define RST_BUS_CAN 37 -#define RST_BUS_SPI0 38 -#define RST_BUS_SPI1 39 -#define RST_BUS_SPI2 40 -#define RST_BUS_SPIFC 41 -#define RST_BUS_EMAC0 42 -#define RST_BUS_EMAC1 43 -#define RST_BUS_IR_RX 44 -#define RST_BUS_IR_TX 45 -#define RST_BUS_GPADC0 46 -#define RST_BUS_GPADC1 47 -#define RST_BUS_THS 48 -#define RST_USB_PHY0 49 -#define RST_USB_PHY1 50 -#define RST_BUS_OHCI0 51 -#define RST_BUS_OHCI1 52 -#define RST_BUS_EHCI0 53 -#define RST_BUS_EHCI1 54 -#define RST_BUS_OTG 55 -#define RST_BUS_3 56 -#define RST_BUS_LRADC 57 -#define RST_BUS_PCIE_USB3 58 -#define RST_BUS_DISPLAY0_TOP 59 -#define RST_BUS_DISPLAY1_TOP 60 -#define RST_BUS_HDMI_MAIN 61 -#define RST_BUS_HDMI_SUB 62 -#define RST_BUS_MIPI_DSI0 63 -#define RST_BUS_MIPI_DSI1 64 -#define RST_BUS_TCON_LCD0 65 -#define RST_BUS_TCON_LCD1 66 -#define RST_BUS_TCON_LCD2 67 -#define RST_BUS_TCON_TV0 68 -#define RST_BUS_TCON_TV1 69 -#define RST_BUS_LVDS0 70 -#define RST_BUS_LVDS1 71 -#define RST_BUS_EDP 72 -#define RST_BUS_VIDEO_OUT0 73 -#define RST_BUS_VIDEO_OUT1 74 -#define RST_BUS_LEDC 75 -#define RST_BUS_CSI 76 -#define RST_BUS_ISP 77 - -#endif /* _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-r-ccu.h b/include/dt-bindings/reset/sun55i-a523-r-ccu.h deleted file mode 100644 index dd6fbb372e1..00000000000 --- a/include/dt-bindings/reset/sun55i-a523-r-ccu.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -/* - * Copyright (C) 2024 Arm Ltd. - */ - -#ifndef _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ - -#define RST_BUS_R_TIMER 0 -#define RST_BUS_R_TWD 1 -#define RST_BUS_R_PWMCTRL 2 -#define RST_BUS_R_SPI 3 -#define RST_BUS_R_SPINLOCK 4 -#define RST_BUS_R_MSGBOX 5 -#define RST_BUS_R_UART0 6 -#define RST_BUS_R_UART1 7 -#define RST_BUS_R_I2C0 8 -#define RST_BUS_R_I2C1 9 -#define RST_BUS_R_I2C2 10 -#define RST_BUS_R_PPU1 11 -#define RST_BUS_R_IR_RX 12 -#define RST_BUS_R_RTC 13 -#define RST_BUS_R_CPUCFG 14 - -#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h deleted file mode 100644 index 40cc22ae763..00000000000 --- a/include/dt-bindings/reset/sun5i-ccu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2016 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - */ - -#ifndef _RST_SUN5I_H_ -#define _RST_SUN5I_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_GPS 2 -#define RST_DE_BE 3 -#define RST_DE_FE 4 -#define RST_TVE 5 -#define RST_LCD 6 -#define RST_CSI 7 -#define RST_VE 8 -#define RST_GPU 9 -#define RST_IEP 10 - -#endif /* _RST_SUN5I_H_ */ diff --git a/include/dt-bindings/reset/sun6i-a31-ccu.h b/include/dt-bindings/reset/sun6i-a31-ccu.h deleted file mode 100644 index fbff365ed6e..00000000000 --- a/include/dt-bindings/reset/sun6i-a31-ccu.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_ -#define _DT_BINDINGS_RST_SUN6I_A31_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 - -#define RST_AHB1_MIPI_DSI 3 -#define RST_AHB1_SS 4 -#define RST_AHB1_DMA 5 -#define RST_AHB1_MMC0 6 -#define RST_AHB1_MMC1 7 -#define RST_AHB1_MMC2 8 -#define RST_AHB1_MMC3 9 -#define RST_AHB1_NAND1 10 -#define RST_AHB1_NAND0 11 -#define RST_AHB1_SDRAM 12 -#define RST_AHB1_EMAC 13 -#define RST_AHB1_TS 14 -#define RST_AHB1_HSTIMER 15 -#define RST_AHB1_SPI0 16 -#define RST_AHB1_SPI1 17 -#define RST_AHB1_SPI2 18 -#define RST_AHB1_SPI3 19 -#define RST_AHB1_OTG 20 -#define RST_AHB1_EHCI0 21 -#define RST_AHB1_EHCI1 22 -#define RST_AHB1_OHCI0 23 -#define RST_AHB1_OHCI1 24 -#define RST_AHB1_OHCI2 25 -#define RST_AHB1_VE 26 -#define RST_AHB1_LCD0 27 -#define RST_AHB1_LCD1 28 -#define RST_AHB1_CSI 29 -#define RST_AHB1_HDMI 30 -#define RST_AHB1_BE0 31 -#define RST_AHB1_BE1 32 -#define RST_AHB1_FE0 33 -#define RST_AHB1_FE1 34 -#define RST_AHB1_MP 35 -#define RST_AHB1_GPU 36 -#define RST_AHB1_DEU0 37 -#define RST_AHB1_DEU1 38 -#define RST_AHB1_DRC0 39 -#define RST_AHB1_DRC1 40 -#define RST_AHB1_LVDS 41 - -#define RST_APB1_CODEC 42 -#define RST_APB1_SPDIF 43 -#define RST_APB1_DIGITAL_MIC 44 -#define RST_APB1_DAUDIO0 45 -#define RST_APB1_DAUDIO1 46 -#define RST_APB2_I2C0 47 -#define RST_APB2_I2C1 48 -#define RST_APB2_I2C2 49 -#define RST_APB2_I2C3 50 -#define RST_APB2_UART0 51 -#define RST_APB2_UART1 52 -#define RST_APB2_UART2 53 -#define RST_APB2_UART3 54 -#define RST_APB2_UART4 55 -#define RST_APB2_UART5 56 - -#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h deleted file mode 100644 index 6121f2b0cd0..00000000000 --- a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_ -#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 -#define RST_MBUS 3 -#define RST_BUS_MIPI_DSI 4 -#define RST_BUS_SS 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_NAND 10 -#define RST_BUS_DRAM 11 -#define RST_BUS_HSTIMER 12 -#define RST_BUS_SPI0 13 -#define RST_BUS_SPI1 14 -#define RST_BUS_OTG 15 -#define RST_BUS_EHCI 16 -#define RST_BUS_OHCI 17 -#define RST_BUS_VE 18 -#define RST_BUS_LCD 19 -#define RST_BUS_CSI 20 -#define RST_BUS_DE_BE 21 -#define RST_BUS_DE_FE 22 -#define RST_BUS_GPU 23 -#define RST_BUS_MSGBOX 24 -#define RST_BUS_SPINLOCK 25 -#define RST_BUS_DRC 26 -#define RST_BUS_SAT 27 -#define RST_BUS_LVDS 28 -#define RST_BUS_CODEC 29 -#define RST_BUS_I2S0 30 -#define RST_BUS_I2S1 31 -#define RST_BUS_I2C0 32 -#define RST_BUS_I2C1 33 -#define RST_BUS_I2C2 34 -#define RST_BUS_UART0 35 -#define RST_BUS_UART1 36 -#define RST_BUS_UART2 37 -#define RST_BUS_UART3 38 -#define RST_BUS_UART4 39 - -#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */ diff --git a/include/dt-bindings/reset/sun8i-a83t-ccu.h b/include/dt-bindings/reset/sun8i-a83t-ccu.h deleted file mode 100644 index 784f6e11664..00000000000 --- a/include/dt-bindings/reset/sun8i-a83t-ccu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ -#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 - -#define RST_DRAM 3 -#define RST_MBUS 4 - -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_SS 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_NAND 11 -#define RST_BUS_DRAM 12 -#define RST_BUS_EMAC 13 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_SPI1 16 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_EHCI1 19 -#define RST_BUS_OHCI0 20 - -#define RST_BUS_VE 21 -#define RST_BUS_TCON0 22 -#define RST_BUS_TCON1 23 -#define RST_BUS_CSI 24 -#define RST_BUS_HDMI0 25 -#define RST_BUS_HDMI1 26 -#define RST_BUS_DE 27 -#define RST_BUS_GPU 28 -#define RST_BUS_MSGBOX 29 -#define RST_BUS_SPINLOCK 30 - -#define RST_BUS_LVDS 31 - -#define RST_BUS_SPDIF 32 -#define RST_BUS_I2S0 33 -#define RST_BUS_I2S1 34 -#define RST_BUS_I2S2 35 -#define RST_BUS_TDM 36 - -#define RST_BUS_I2C0 37 -#define RST_BUS_I2C1 38 -#define RST_BUS_I2C2 39 -#define RST_BUS_UART0 40 -#define RST_BUS_UART1 41 -#define RST_BUS_UART2 42 -#define RST_BUS_UART3 43 -#define RST_BUS_UART4 44 - -#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h deleted file mode 100644 index 1c36a6ac86d..00000000000 --- a/include/dt-bindings/reset/sun8i-de2.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_ -#define _DT_BINDINGS_RESET_SUN8I_DE2_H_ - -#define RST_MIXER0 0 -#define RST_MIXER1 1 -#define RST_WB 2 -#define RST_ROT 3 - -#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h deleted file mode 100644 index 484c2a22919..00000000000 --- a/include/dt-bindings/reset/sun8i-h3-ccu.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_ -#define _DT_BINDINGS_RST_SUN8I_H3_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 -#define RST_USB_PHY3 3 - -#define RST_MBUS 4 - -#define RST_BUS_CE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_NAND 10 -#define RST_BUS_DRAM 11 -#define RST_BUS_EMAC 12 -#define RST_BUS_TS 13 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_SPI1 16 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_EHCI1 19 -#define RST_BUS_EHCI2 20 -#define RST_BUS_EHCI3 21 -#define RST_BUS_OHCI0 22 -#define RST_BUS_OHCI1 23 -#define RST_BUS_OHCI2 24 -#define RST_BUS_OHCI3 25 -#define RST_BUS_VE 26 -#define RST_BUS_TCON0 27 -#define RST_BUS_TCON1 28 -#define RST_BUS_DEINTERLACE 29 -#define RST_BUS_CSI 30 -#define RST_BUS_TVE 31 -#define RST_BUS_HDMI0 32 -#define RST_BUS_HDMI1 33 -#define RST_BUS_DE 34 -#define RST_BUS_GPU 35 -#define RST_BUS_MSGBOX 36 -#define RST_BUS_SPINLOCK 37 -#define RST_BUS_DBG 38 -#define RST_BUS_EPHY 39 -#define RST_BUS_CODEC 40 -#define RST_BUS_SPDIF 41 -#define RST_BUS_THS 42 -#define RST_BUS_I2S0 43 -#define RST_BUS_I2S1 44 -#define RST_BUS_I2S2 45 -#define RST_BUS_I2C0 46 -#define RST_BUS_I2C1 47 -#define RST_BUS_I2C2 48 -#define RST_BUS_UART0 49 -#define RST_BUS_UART1 50 -#define RST_BUS_UART2 51 -#define RST_BUS_UART3 52 -#define RST_BUS_SCR0 53 - -/* New resets imported in H5 */ -#define RST_BUS_SCR1 54 - -#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h deleted file mode 100644 index 4ba64f3d6fc..00000000000 --- a/include/dt-bindings/reset/sun8i-r-ccu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ - -#define RST_APB0_IR 0 -#define RST_APB0_TIMER 1 -#define RST_APB0_RSB 2 -#define RST_APB0_UART 3 -/* 4 is reserved for RST_APB0_W1 on A31 */ -#define RST_APB0_I2C 5 - -#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-r40-ccu.h b/include/dt-bindings/reset/sun8i-r40-ccu.h deleted file mode 100644 index c5ebcf6672e..00000000000 --- a/include/dt-bindings/reset/sun8i-r40-ccu.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_ -#define _DT_BINDINGS_RST_SUN8I_R40_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 - -#define RST_DRAM 3 -#define RST_MBUS 4 - -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_CE 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_MMC3 11 -#define RST_BUS_NAND 12 -#define RST_BUS_DRAM 13 -#define RST_BUS_EMAC 14 -#define RST_BUS_TS 15 -#define RST_BUS_HSTIMER 16 -#define RST_BUS_SPI0 17 -#define RST_BUS_SPI1 18 -#define RST_BUS_SPI2 19 -#define RST_BUS_SPI3 20 -#define RST_BUS_SATA 21 -#define RST_BUS_OTG 22 -#define RST_BUS_EHCI0 23 -#define RST_BUS_EHCI1 24 -#define RST_BUS_EHCI2 25 -#define RST_BUS_OHCI0 26 -#define RST_BUS_OHCI1 27 -#define RST_BUS_OHCI2 28 -#define RST_BUS_VE 29 -#define RST_BUS_MP 30 -#define RST_BUS_DEINTERLACE 31 -#define RST_BUS_CSI0 32 -#define RST_BUS_CSI1 33 -#define RST_BUS_HDMI0 34 -#define RST_BUS_HDMI1 35 -#define RST_BUS_DE 36 -#define RST_BUS_TVE0 37 -#define RST_BUS_TVE1 38 -#define RST_BUS_TVE_TOP 39 -#define RST_BUS_GMAC 40 -#define RST_BUS_GPU 41 -#define RST_BUS_TVD0 42 -#define RST_BUS_TVD1 43 -#define RST_BUS_TVD2 44 -#define RST_BUS_TVD3 45 -#define RST_BUS_TVD_TOP 46 -#define RST_BUS_TCON_LCD0 47 -#define RST_BUS_TCON_LCD1 48 -#define RST_BUS_TCON_TV0 49 -#define RST_BUS_TCON_TV1 50 -#define RST_BUS_TCON_TOP 51 -#define RST_BUS_DBG 52 -#define RST_BUS_LVDS 53 -#define RST_BUS_CODEC 54 -#define RST_BUS_SPDIF 55 -#define RST_BUS_AC97 56 -#define RST_BUS_IR0 57 -#define RST_BUS_IR1 58 -#define RST_BUS_THS 59 -#define RST_BUS_KEYPAD 60 -#define RST_BUS_I2S0 61 -#define RST_BUS_I2S1 62 -#define RST_BUS_I2S2 63 -#define RST_BUS_I2C0 64 -#define RST_BUS_I2C1 65 -#define RST_BUS_I2C2 66 -#define RST_BUS_I2C3 67 -#define RST_BUS_CAN 68 -#define RST_BUS_SCR 69 -#define RST_BUS_PS20 70 -#define RST_BUS_PS21 71 -#define RST_BUS_I2C4 72 -#define RST_BUS_UART0 73 -#define RST_BUS_UART1 74 -#define RST_BUS_UART2 75 -#define RST_BUS_UART3 76 -#define RST_BUS_UART4 77 -#define RST_BUS_UART5 78 -#define RST_BUS_UART6 79 -#define RST_BUS_UART7 80 - -#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */ diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h deleted file mode 100644 index b6790173afd..00000000000 --- a/include/dt-bindings/reset/sun8i-v3s-ccu.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * Based on sun8i-v3s-ccu.h, which is - * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_ -#define _DT_BINDINGS_RST_SUN8I_V3S_H_ - -#define RST_USB_PHY0 0 - -#define RST_MBUS 1 - -#define RST_BUS_CE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_DRAM 11 -#define RST_BUS_EMAC 12 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_OHCI0 22 -#define RST_BUS_VE 26 -#define RST_BUS_TCON0 27 -#define RST_BUS_CSI 30 -#define RST_BUS_DE 34 -#define RST_BUS_DBG 38 -#define RST_BUS_EPHY 39 -#define RST_BUS_CODEC 40 -#define RST_BUS_I2C0 46 -#define RST_BUS_I2C1 47 -#define RST_BUS_UART0 49 -#define RST_BUS_UART1 50 -#define RST_BUS_UART2 51 - -/* Reset lines not available on V3s */ -#define RST_BUS_I2S0 52 - -#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-ccu.h b/include/dt-bindings/reset/sun9i-a80-ccu.h deleted file mode 100644 index 4b8df4b3678..00000000000 --- a/include/dt-bindings/reset/sun9i-a80-ccu.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ - -#define RST_BUS_FD 0 -#define RST_BUS_VE 1 -#define RST_BUS_GPU_CTRL 2 -#define RST_BUS_SS 3 -#define RST_BUS_MMC 4 -#define RST_BUS_NAND0 5 -#define RST_BUS_NAND1 6 -#define RST_BUS_SDRAM 7 -#define RST_BUS_SATA 8 -#define RST_BUS_TS 9 -#define RST_BUS_SPI0 10 -#define RST_BUS_SPI1 11 -#define RST_BUS_SPI2 12 -#define RST_BUS_SPI3 13 - -#define RST_BUS_OTG 14 -#define RST_BUS_OTG_PHY 15 -#define RST_BUS_MIPI_HSI 16 -#define RST_BUS_GMAC 17 -#define RST_BUS_MSGBOX 18 -#define RST_BUS_SPINLOCK 19 -#define RST_BUS_HSTIMER 20 -#define RST_BUS_DMA 21 - -#define RST_BUS_LCD0 22 -#define RST_BUS_LCD1 23 -#define RST_BUS_EDP 24 -#define RST_BUS_LVDS 25 -#define RST_BUS_CSI 26 -#define RST_BUS_HDMI0 27 -#define RST_BUS_HDMI1 28 -#define RST_BUS_DE 29 -#define RST_BUS_MP 30 -#define RST_BUS_GPU 31 -#define RST_BUS_MIPI_DSI 32 - -#define RST_BUS_SPDIF 33 -#define RST_BUS_AC97 34 -#define RST_BUS_I2S0 35 -#define RST_BUS_I2S1 36 -#define RST_BUS_LRADC 37 -#define RST_BUS_GPADC 38 -#define RST_BUS_CIR_TX 39 - -#define RST_BUS_I2C0 40 -#define RST_BUS_I2C1 41 -#define RST_BUS_I2C2 42 -#define RST_BUS_I2C3 43 -#define RST_BUS_I2C4 44 -#define RST_BUS_UART0 45 -#define RST_BUS_UART1 46 -#define RST_BUS_UART2 47 -#define RST_BUS_UART3 48 -#define RST_BUS_UART4 49 -#define RST_BUS_UART5 50 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-de.h b/include/dt-bindings/reset/sun9i-a80-de.h deleted file mode 100644 index 20507277017..00000000000 --- a/include/dt-bindings/reset/sun9i-a80-de.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ - -#define RST_FE0 0 -#define RST_FE1 1 -#define RST_FE2 2 -#define RST_DEU0 3 -#define RST_DEU1 4 -#define RST_BE0 5 -#define RST_BE1 6 -#define RST_BE2 7 -#define RST_DRC0 8 -#define RST_DRC1 9 -#define RST_MERGE 10 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-usb.h b/include/dt-bindings/reset/sun9i-a80-usb.h deleted file mode 100644 index ee492864c2a..00000000000 --- a/include/dt-bindings/reset/sun9i-a80-usb.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ - -#define RST_USB0_HCI 0 -#define RST_USB1_HCI 1 -#define RST_USB2_HCI 2 - -#define RST_USB0_PHY 3 -#define RST_USB1_HSIC 4 -#define RST_USB1_PHY 5 -#define RST_USB2_HSIC 6 -#define RST_USB2_PHY 7 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */ diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h deleted file mode 100644 index 6a4b4385fe5..00000000000 --- a/include/dt-bindings/reset/suniv-ccu-f1c100s.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz> - * - */ - -#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ -#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ - -#define RST_USB_PHY0 0 -#define RST_BUS_DMA 1 -#define RST_BUS_MMC0 2 -#define RST_BUS_MMC1 3 -#define RST_BUS_DRAM 4 -#define RST_BUS_SPI0 5 -#define RST_BUS_SPI1 6 -#define RST_BUS_OTG 7 -#define RST_BUS_VE 8 -#define RST_BUS_LCD 9 -#define RST_BUS_DEINTERLACE 10 -#define RST_BUS_CSI 11 -#define RST_BUS_TVD 12 -#define RST_BUS_TVE 13 -#define RST_BUS_DE_BE 14 -#define RST_BUS_DE_FE 15 -#define RST_BUS_CODEC 16 -#define RST_BUS_SPDIF 17 -#define RST_BUS_IR 18 -#define RST_BUS_RSB 19 -#define RST_BUS_I2S0 20 -#define RST_BUS_I2C0 21 -#define RST_BUS_I2C1 22 -#define RST_BUS_I2C2 23 -#define RST_BUS_UART0 24 -#define RST_BUS_UART1 25 -#define RST_BUS_UART2 26 - -#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ diff --git a/include/dt-bindings/reset/sunplus,sp7021-reset.h b/include/dt-bindings/reset/sunplus,sp7021-reset.h deleted file mode 100644 index ab486707387..00000000000 --- a/include/dt-bindings/reset/sunplus,sp7021-reset.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (C) Sunplus Technology Co., Ltd. - * All rights reserved. - */ -#ifndef _DT_BINDINGS_RST_SUNPLUS_SP7021_H -#define _DT_BINDINGS_RST_SUNPLUS_SP7021_H - -#define RST_SYSTEM 0 -#define RST_RTC 1 -#define RST_IOCTL 2 -#define RST_IOP 3 -#define RST_OTPRX 4 -#define RST_NOC 5 -#define RST_BR 6 -#define RST_RBUS_L00 7 -#define RST_SPIFL 8 -#define RST_SDCTRL0 9 -#define RST_PERI0 10 -#define RST_A926 11 -#define RST_UMCTL2 12 -#define RST_PERI1 13 -#define RST_DDR_PHY0 14 -#define RST_ACHIP 15 -#define RST_STC0 16 -#define RST_STC_AV0 17 -#define RST_STC_AV1 18 -#define RST_STC_AV2 19 -#define RST_UA0 20 -#define RST_UA1 21 -#define RST_UA2 22 -#define RST_UA3 23 -#define RST_UA4 24 -#define RST_HWUA 25 -#define RST_DDC0 26 -#define RST_UADMA 27 -#define RST_CBDMA0 28 -#define RST_CBDMA1 29 -#define RST_SPI_COMBO_0 30 -#define RST_SPI_COMBO_1 31 -#define RST_SPI_COMBO_2 32 -#define RST_SPI_COMBO_3 33 -#define RST_AUD 34 -#define RST_USBC0 35 -#define RST_USBC1 36 -#define RST_UPHY0 37 -#define RST_UPHY1 38 -#define RST_I2CM0 39 -#define RST_I2CM1 40 -#define RST_I2CM2 41 -#define RST_I2CM3 42 -#define RST_PMC 43 -#define RST_CARD_CTL0 44 -#define RST_CARD_CTL1 45 -#define RST_CARD_CTL4 46 -#define RST_BCH 47 -#define RST_DDFCH 48 -#define RST_CSIIW0 49 -#define RST_CSIIW1 50 -#define RST_MIPICSI0 51 -#define RST_MIPICSI1 52 -#define RST_HDMI_TX 53 -#define RST_VPOST 54 -#define RST_TGEN 55 -#define RST_DMIX 56 -#define RST_TCON 57 -#define RST_INTERRUPT 58 -#define RST_RGST 59 -#define RST_GPIO 60 -#define RST_RBUS_TOP 61 -#define RST_MAILBOX 62 -#define RST_SPIND 63 -#define RST_I2C2CBUS 64 -#define RST_SEC 65 -#define RST_DVE 66 -#define RST_GPOST0 67 -#define RST_OSD0 68 -#define RST_DISP_PWM 69 -#define RST_UADBG 70 -#define RST_DUMMY_MASTER 71 -#define RST_FIO_CTL 72 -#define RST_FPGA 73 -#define RST_L2SW 74 -#define RST_ICM 75 -#define RST_AXI_GLOBAL 76 - -#endif diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h deleted file mode 100644 index 97d2f3db82b..00000000000 --- a/include/dt-bindings/reset/tegra124-car.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides Tegra124-specific constants for binding - * nvidia,tegra124-car. - */ - -#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H -#define _DT_BINDINGS_RESET_TEGRA124_CAR_H - -#define TEGRA124_RESET(x) (6 * 32 + (x)) -#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) - -#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h deleted file mode 100644 index 3c60e3e03eb..00000000000 --- a/include/dt-bindings/reset/tegra186-reset.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _ABI_MACH_T186_RESET_T186_H_ -#define _ABI_MACH_T186_RESET_T186_H_ - - -#define TEGRA186_RESET_ACTMON 0 -#define TEGRA186_RESET_AFI 1 -#define TEGRA186_RESET_CEC 2 -#define TEGRA186_RESET_CSITE 3 -#define TEGRA186_RESET_DP2 4 -#define TEGRA186_RESET_DPAUX 5 -#define TEGRA186_RESET_DSI 6 -#define TEGRA186_RESET_DSIB 7 -#define TEGRA186_RESET_DTV 8 -#define TEGRA186_RESET_DVFS 9 -#define TEGRA186_RESET_ENTROPY 10 -#define TEGRA186_RESET_EXTPERIPH1 11 -#define TEGRA186_RESET_EXTPERIPH2 12 -#define TEGRA186_RESET_EXTPERIPH3 13 -#define TEGRA186_RESET_GPU 14 -#define TEGRA186_RESET_HDA 15 -#define TEGRA186_RESET_HDA2CODEC_2X 16 -#define TEGRA186_RESET_HDA2HDMICODEC 17 -#define TEGRA186_RESET_HOST1X 18 -#define TEGRA186_RESET_I2C1 19 -#define TEGRA186_RESET_I2C2 20 -#define TEGRA186_RESET_I2C3 21 -#define TEGRA186_RESET_I2C4 22 -#define TEGRA186_RESET_I2C5 23 -#define TEGRA186_RESET_I2C6 24 -#define TEGRA186_RESET_ISP 25 -#define TEGRA186_RESET_KFUSE 26 -#define TEGRA186_RESET_LA 27 -#define TEGRA186_RESET_MIPI_CAL 28 -#define TEGRA186_RESET_PCIE 29 -#define TEGRA186_RESET_PCIEXCLK 30 -#define TEGRA186_RESET_SATA 31 -#define TEGRA186_RESET_SATACOLD 32 -#define TEGRA186_RESET_SDMMC1 33 -#define TEGRA186_RESET_SDMMC2 34 -#define TEGRA186_RESET_SDMMC3 35 -#define TEGRA186_RESET_SDMMC4 36 -#define TEGRA186_RESET_SE 37 -#define TEGRA186_RESET_SOC_THERM 38 -#define TEGRA186_RESET_SOR0 39 -#define TEGRA186_RESET_SPI1 40 -#define TEGRA186_RESET_SPI2 41 -#define TEGRA186_RESET_SPI3 42 -#define TEGRA186_RESET_SPI4 43 -#define TEGRA186_RESET_TMR 44 -#define TEGRA186_RESET_TRIG_SYS 45 -#define TEGRA186_RESET_TSEC 46 -#define TEGRA186_RESET_UARTA 47 -#define TEGRA186_RESET_UARTB 48 -#define TEGRA186_RESET_UARTC 49 -#define TEGRA186_RESET_UARTD 50 -#define TEGRA186_RESET_VI 51 -#define TEGRA186_RESET_VIC 52 -#define TEGRA186_RESET_XUSB_DEV 53 -#define TEGRA186_RESET_XUSB_HOST 54 -#define TEGRA186_RESET_XUSB_PADCTL 55 -#define TEGRA186_RESET_XUSB_SS 56 -#define TEGRA186_RESET_AON_APB 57 -#define TEGRA186_RESET_AXI_CBB 58 -#define TEGRA186_RESET_BPMP_APB 59 -#define TEGRA186_RESET_CAN1 60 -#define TEGRA186_RESET_CAN2 61 -#define TEGRA186_RESET_DMIC5 62 -#define TEGRA186_RESET_DSIC 63 -#define TEGRA186_RESET_DSID 64 -#define TEGRA186_RESET_EMC_EMC 65 -#define TEGRA186_RESET_EMC_MEM 66 -#define TEGRA186_RESET_EMCSB_EMC 67 -#define TEGRA186_RESET_EMCSB_MEM 68 -#define TEGRA186_RESET_EQOS 69 -#define TEGRA186_RESET_GPCDMA 70 -#define TEGRA186_RESET_GPIO_CTL0 71 -#define TEGRA186_RESET_GPIO_CTL1 72 -#define TEGRA186_RESET_GPIO_CTL2 73 -#define TEGRA186_RESET_GPIO_CTL3 74 -#define TEGRA186_RESET_GPIO_CTL4 75 -#define TEGRA186_RESET_GPIO_CTL5 76 -#define TEGRA186_RESET_I2C10 77 -#define TEGRA186_RESET_I2C12 78 -#define TEGRA186_RESET_I2C13 79 -#define TEGRA186_RESET_I2C14 80 -#define TEGRA186_RESET_I2C7 81 -#define TEGRA186_RESET_I2C8 82 -#define TEGRA186_RESET_I2C9 83 -#define TEGRA186_RESET_JTAG2AXI 84 -#define TEGRA186_RESET_MPHY_IOBIST 85 -#define TEGRA186_RESET_MPHY_L0_RX 86 -#define TEGRA186_RESET_MPHY_L0_TX 87 -#define TEGRA186_RESET_NVCSI 88 -#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 -#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 -#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 -#define TEGRA186_RESET_NVDISPLAY0_MISC 92 -#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 -#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 -#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 -#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 -#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 -#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 -#define TEGRA186_RESET_PWM1 99 -#define TEGRA186_RESET_PWM2 100 -#define TEGRA186_RESET_PWM3 101 -#define TEGRA186_RESET_PWM4 102 -#define TEGRA186_RESET_PWM5 103 -#define TEGRA186_RESET_PWM6 104 -#define TEGRA186_RESET_PWM7 105 -#define TEGRA186_RESET_PWM8 106 -#define TEGRA186_RESET_SCE_APB 107 -#define TEGRA186_RESET_SOR1 108 -#define TEGRA186_RESET_TACH 109 -#define TEGRA186_RESET_TSC 110 -#define TEGRA186_RESET_UARTF 111 -#define TEGRA186_RESET_UARTG 112 -#define TEGRA186_RESET_UFSHC 113 -#define TEGRA186_RESET_UFSHC_AXI_M 114 -#define TEGRA186_RESET_UPHY 115 -#define TEGRA186_RESET_ADSP 116 -#define TEGRA186_RESET_ADSPDBG 117 -#define TEGRA186_RESET_ADSPINTF 118 -#define TEGRA186_RESET_ADSPNEON 119 -#define TEGRA186_RESET_ADSPPERIPH 120 -#define TEGRA186_RESET_ADSPSCU 121 -#define TEGRA186_RESET_ADSPWDT 122 -#define TEGRA186_RESET_APE 123 -#define TEGRA186_RESET_DPAUX1 124 -#define TEGRA186_RESET_NVDEC 125 -#define TEGRA186_RESET_NVENC 126 -#define TEGRA186_RESET_NVJPG 127 -#define TEGRA186_RESET_PEX_USB_UPHY 128 -#define TEGRA186_RESET_QSPI 129 -#define TEGRA186_RESET_TSECB 130 -#define TEGRA186_RESET_VI_I2C 131 -#define TEGRA186_RESET_UARTE 132 -#define TEGRA186_RESET_TOP_GTE 133 -#define TEGRA186_RESET_SHSP 134 -#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 -#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 -#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 -#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 -#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 -#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 -#define TEGRA186_RESET_TSCTNVI 143 -#define TEGRA186_RESET_EXTPERIPH4 144 -#define TEGRA186_RESET_DSIPADCTL 145 -#define TEGRA186_RESET_AUD_MCLK 146 -#define TEGRA186_RESET_MPHY_CLK_CTL 147 -#define TEGRA186_RESET_MPHY_L1_RX 148 -#define TEGRA186_RESET_MPHY_L1_TX 149 -#define TEGRA186_RESET_UFSHC_LP 150 -#define TEGRA186_RESET_BPMP_NIC 151 -#define TEGRA186_RESET_BPMP_NSYSPORESET 152 -#define TEGRA186_RESET_BPMP_NRESET 153 -#define TEGRA186_RESET_BPMP_DBGRESETN 154 -#define TEGRA186_RESET_BPMP_PRESETDBGN 155 -#define TEGRA186_RESET_BPMP_PM 156 -#define TEGRA186_RESET_BPMP_CVC 157 -#define TEGRA186_RESET_BPMP_DMA 158 -#define TEGRA186_RESET_BPMP_HSP 159 -#define TEGRA186_RESET_TSCTNBPMP 160 -#define TEGRA186_RESET_BPMP_TKE 161 -#define TEGRA186_RESET_BPMP_GTE 162 -#define TEGRA186_RESET_BPMP_PM_ACTMON 163 -#define TEGRA186_RESET_AON_NIC 164 -#define TEGRA186_RESET_AON_NSYSPORESET 165 -#define TEGRA186_RESET_AON_NRESET 166 -#define TEGRA186_RESET_AON_DBGRESETN 167 -#define TEGRA186_RESET_AON_PRESETDBGN 168 -#define TEGRA186_RESET_AON_ACTMON 169 -#define TEGRA186_RESET_AOPM 170 -#define TEGRA186_RESET_AOVC 171 -#define TEGRA186_RESET_AON_DMA 172 -#define TEGRA186_RESET_AON_GPIO 173 -#define TEGRA186_RESET_AON_HSP 174 -#define TEGRA186_RESET_TSCTNAON 175 -#define TEGRA186_RESET_AON_TKE 176 -#define TEGRA186_RESET_AON_GTE 177 -#define TEGRA186_RESET_SCE_NIC 178 -#define TEGRA186_RESET_SCE_NSYSPORESET 179 -#define TEGRA186_RESET_SCE_NRESET 180 -#define TEGRA186_RESET_SCE_DBGRESETN 181 -#define TEGRA186_RESET_SCE_PRESETDBGN 182 -#define TEGRA186_RESET_SCE_ACTMON 183 -#define TEGRA186_RESET_SCE_PM 184 -#define TEGRA186_RESET_SCE_DMA 185 -#define TEGRA186_RESET_SCE_HSP 186 -#define TEGRA186_RESET_TSCTNSCE 187 -#define TEGRA186_RESET_SCE_TKE 188 -#define TEGRA186_RESET_SCE_GTE 189 -#define TEGRA186_RESET_SCE_CFG 190 -#define TEGRA186_RESET_ADSP_ALL 191 -/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ -#define TEGRA186_RESET_UFSHC_LP_SEQ 192 -#define TEGRA186_RESET_SIZE 193 - -#endif diff --git a/include/dt-bindings/reset/tegra194-reset.h b/include/dt-bindings/reset/tegra194-reset.h deleted file mode 100644 index 473afaa25bf..00000000000 --- a/include/dt-bindings/reset/tegra194-reset.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */ - -#ifndef __ABI_MACH_T194_RESET_H -#define __ABI_MACH_T194_RESET_H - -#define TEGRA194_RESET_ACTMON 1 -#define TEGRA194_RESET_ADSP_ALL 2 -#define TEGRA194_RESET_AFI 3 -#define TEGRA194_RESET_CAN1 4 -#define TEGRA194_RESET_CAN2 5 -#define TEGRA194_RESET_DLA0 6 -#define TEGRA194_RESET_DLA1 7 -#define TEGRA194_RESET_DPAUX 8 -#define TEGRA194_RESET_DPAUX1 9 -#define TEGRA194_RESET_DPAUX2 10 -#define TEGRA194_RESET_DPAUX3 11 -#define TEGRA194_RESET_EQOS 17 -#define TEGRA194_RESET_GPCDMA 18 -#define TEGRA194_RESET_GPU 19 -#define TEGRA194_RESET_HDA 20 -#define TEGRA194_RESET_HDA2CODEC_2X 21 -#define TEGRA194_RESET_HDA2HDMICODEC 22 -#define TEGRA194_RESET_HOST1X 23 -#define TEGRA194_RESET_I2C1 24 -#define TEGRA194_RESET_I2C10 25 -#define TEGRA194_RESET_RSVD_26 26 -#define TEGRA194_RESET_RSVD_27 27 -#define TEGRA194_RESET_RSVD_28 28 -#define TEGRA194_RESET_I2C2 29 -#define TEGRA194_RESET_I2C3 30 -#define TEGRA194_RESET_I2C4 31 -#define TEGRA194_RESET_I2C6 32 -#define TEGRA194_RESET_I2C7 33 -#define TEGRA194_RESET_I2C8 34 -#define TEGRA194_RESET_I2C9 35 -#define TEGRA194_RESET_ISP 36 -#define TEGRA194_RESET_MIPI_CAL 37 -#define TEGRA194_RESET_MPHY_CLK_CTL 38 -#define TEGRA194_RESET_MPHY_L0_RX 39 -#define TEGRA194_RESET_MPHY_L0_TX 40 -#define TEGRA194_RESET_MPHY_L1_RX 41 -#define TEGRA194_RESET_MPHY_L1_TX 42 -#define TEGRA194_RESET_NVCSI 43 -#define TEGRA194_RESET_NVDEC 44 -#define TEGRA194_RESET_NVDISPLAY0_HEAD0 45 -#define TEGRA194_RESET_NVDISPLAY0_HEAD1 46 -#define TEGRA194_RESET_NVDISPLAY0_HEAD2 47 -#define TEGRA194_RESET_NVDISPLAY0_HEAD3 48 -#define TEGRA194_RESET_NVDISPLAY0_MISC 49 -#define TEGRA194_RESET_NVDISPLAY0_WGRP0 50 -#define TEGRA194_RESET_NVDISPLAY0_WGRP1 51 -#define TEGRA194_RESET_NVDISPLAY0_WGRP2 52 -#define TEGRA194_RESET_NVDISPLAY0_WGRP3 53 -#define TEGRA194_RESET_NVDISPLAY0_WGRP4 54 -#define TEGRA194_RESET_NVDISPLAY0_WGRP5 55 -#define TEGRA194_RESET_RSVD_56 56 -#define TEGRA194_RESET_RSVD_57 57 -#define TEGRA194_RESET_RSVD_58 58 -#define TEGRA194_RESET_NVENC 59 -#define TEGRA194_RESET_NVENC1 60 -#define TEGRA194_RESET_NVJPG 61 -#define TEGRA194_RESET_PCIE 62 -#define TEGRA194_RESET_PCIEXCLK 63 -#define TEGRA194_RESET_RSVD_64 64 -#define TEGRA194_RESET_RSVD_65 65 -#define TEGRA194_RESET_PVA0_ALL 66 -#define TEGRA194_RESET_PVA1_ALL 67 -#define TEGRA194_RESET_PWM1 68 -#define TEGRA194_RESET_PWM2 69 -#define TEGRA194_RESET_PWM3 70 -#define TEGRA194_RESET_PWM4 71 -#define TEGRA194_RESET_PWM5 72 -#define TEGRA194_RESET_PWM6 73 -#define TEGRA194_RESET_PWM7 74 -#define TEGRA194_RESET_PWM8 75 -#define TEGRA194_RESET_QSPI0 76 -#define TEGRA194_RESET_QSPI1 77 -#define TEGRA194_RESET_SATA 78 -#define TEGRA194_RESET_SATACOLD 79 -#define TEGRA194_RESET_SCE_ALL 80 -#define TEGRA194_RESET_RCE_ALL 81 -#define TEGRA194_RESET_SDMMC1 82 -#define TEGRA194_RESET_RSVD_83 83 -#define TEGRA194_RESET_SDMMC3 84 -#define TEGRA194_RESET_SDMMC4 85 -#define TEGRA194_RESET_SE 86 -#define TEGRA194_RESET_SOR0 87 -#define TEGRA194_RESET_SOR1 88 -#define TEGRA194_RESET_SOR2 89 -#define TEGRA194_RESET_SOR3 90 -#define TEGRA194_RESET_SPI1 91 -#define TEGRA194_RESET_SPI2 92 -#define TEGRA194_RESET_SPI3 93 -#define TEGRA194_RESET_SPI4 94 -#define TEGRA194_RESET_TACH 95 -#define TEGRA194_RESET_RSVD_96 96 -#define TEGRA194_RESET_TSCTNVI 97 -#define TEGRA194_RESET_TSEC 98 -#define TEGRA194_RESET_TSECB 99 -#define TEGRA194_RESET_UARTA 100 -#define TEGRA194_RESET_UARTB 101 -#define TEGRA194_RESET_UARTC 102 -#define TEGRA194_RESET_UARTD 103 -#define TEGRA194_RESET_UARTE 104 -#define TEGRA194_RESET_UARTF 105 -#define TEGRA194_RESET_UARTG 106 -#define TEGRA194_RESET_UARTH 107 -#define TEGRA194_RESET_UFSHC 108 -#define TEGRA194_RESET_UFSHC_AXI_M 109 -#define TEGRA194_RESET_UFSHC_LP_SEQ 110 -#define TEGRA194_RESET_RSVD_111 111 -#define TEGRA194_RESET_VI 112 -#define TEGRA194_RESET_VIC 113 -#define TEGRA194_RESET_XUSB_PADCTL 114 -#define TEGRA194_RESET_NVDEC1 115 -#define TEGRA194_RESET_PEX0_CORE_0 116 -#define TEGRA194_RESET_PEX0_CORE_1 117 -#define TEGRA194_RESET_PEX0_CORE_2 118 -#define TEGRA194_RESET_PEX0_CORE_3 119 -#define TEGRA194_RESET_PEX0_CORE_4 120 -#define TEGRA194_RESET_PEX0_CORE_0_APB 121 -#define TEGRA194_RESET_PEX0_CORE_1_APB 122 -#define TEGRA194_RESET_PEX0_CORE_2_APB 123 -#define TEGRA194_RESET_PEX0_CORE_3_APB 124 -#define TEGRA194_RESET_PEX0_CORE_4_APB 125 -#define TEGRA194_RESET_PEX0_COMMON_APB 126 -#define TEGRA194_RESET_PEX1_CORE_5 129 -#define TEGRA194_RESET_PEX1_CORE_5_APB 130 -#define TEGRA194_RESET_CVNAS 131 -#define TEGRA194_RESET_CVNAS_FCM 132 -#define TEGRA194_RESET_DMIC5 144 -#define TEGRA194_RESET_APE 145 -#define TEGRA194_RESET_PEX_USB_UPHY 146 -#define TEGRA194_RESET_PEX_USB_UPHY_L0 147 -#define TEGRA194_RESET_PEX_USB_UPHY_L1 148 -#define TEGRA194_RESET_PEX_USB_UPHY_L2 149 -#define TEGRA194_RESET_PEX_USB_UPHY_L3 150 -#define TEGRA194_RESET_PEX_USB_UPHY_L4 151 -#define TEGRA194_RESET_PEX_USB_UPHY_L5 152 -#define TEGRA194_RESET_PEX_USB_UPHY_L6 153 -#define TEGRA194_RESET_PEX_USB_UPHY_L7 154 -#define TEGRA194_RESET_PEX_USB_UPHY_L8 155 -#define TEGRA194_RESET_PEX_USB_UPHY_L9 156 -#define TEGRA194_RESET_PEX_USB_UPHY_L10 157 -#define TEGRA194_RESET_PEX_USB_UPHY_L11 158 -#define TEGRA194_RESET_PEX_USB_UPHY_PLL0 159 -#define TEGRA194_RESET_PEX_USB_UPHY_PLL1 160 -#define TEGRA194_RESET_PEX_USB_UPHY_PLL2 161 -#define TEGRA194_RESET_PEX_USB_UPHY_PLL3 162 - -#endif diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h deleted file mode 100644 index 9dc84ec7630..00000000000 --- a/include/dt-bindings/reset/tegra210-car.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides Tegra210-specific constants for binding - * nvidia,tegra210-car. - */ - -#ifndef _DT_BINDINGS_RESET_TEGRA210_CAR_H -#define _DT_BINDINGS_RESET_TEGRA210_CAR_H - -#define TEGRA210_RESET(x) (7 * 32 + (x)) -#define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0) -#define TEGRA210_RST_ADSP TEGRA210_RESET(1) - -#endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */ diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h deleted file mode 100644 index 85cc423a7bd..00000000000 --- a/include/dt-bindings/reset/tegra234-reset.h +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ - -#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H -#define DT_BINDINGS_RESET_TEGRA234_RESET_H - -/** - * @file - * @defgroup bpmp_reset_ids Reset ID's - * @brief Identifiers for Resets controllable by firmware - * @{ - */ -#define TEGRA234_RESET_ACTMON 1U -#define TEGRA234_RESET_ADSP_ALL 2U -#define TEGRA234_RESET_DSI_CORE 3U -#define TEGRA234_RESET_CAN1 4U -#define TEGRA234_RESET_CAN2 5U -#define TEGRA234_RESET_DLA0 6U -#define TEGRA234_RESET_DLA1 7U -#define TEGRA234_RESET_DPAUX 8U -#define TEGRA234_RESET_OFA 9U -#define TEGRA234_RESET_NVJPG1 10U -#define TEGRA234_RESET_PEX1_CORE_6 11U -#define TEGRA234_RESET_PEX1_CORE_6_APB 12U -#define TEGRA234_RESET_PEX1_COMMON_APB 13U -#define TEGRA234_RESET_PEX2_CORE_7 14U -#define TEGRA234_RESET_PEX2_CORE_7_APB 15U -#define TEGRA234_RESET_NVDISPLAY 16U -#define TEGRA234_RESET_EQOS 17U -#define TEGRA234_RESET_GPCDMA 18U -#define TEGRA234_RESET_GPU 19U -#define TEGRA234_RESET_HDA 20U -#define TEGRA234_RESET_HDACODEC 21U -#define TEGRA234_RESET_EQOS_MACSEC 22U -#define TEGRA234_RESET_EQOS_MACSEC_SECURE 23U -#define TEGRA234_RESET_I2C1 24U -#define TEGRA234_RESET_PEX2_CORE_8 25U -#define TEGRA234_RESET_PEX2_CORE_8_APB 26U -#define TEGRA234_RESET_PEX2_CORE_9 27U -#define TEGRA234_RESET_PEX2_CORE_9_APB 28U -#define TEGRA234_RESET_I2C2 29U -#define TEGRA234_RESET_I2C3 30U -#define TEGRA234_RESET_I2C4 31U -#define TEGRA234_RESET_I2C6 32U -#define TEGRA234_RESET_I2C7 33U -#define TEGRA234_RESET_I2C8 34U -#define TEGRA234_RESET_I2C9 35U -#define TEGRA234_RESET_ISP 36U -#define TEGRA234_RESET_MIPI_CAL 37U -#define TEGRA234_RESET_MPHY_CLK_CTL 38U -#define TEGRA234_RESET_MPHY_L0_RX 39U -#define TEGRA234_RESET_MPHY_L0_TX 40U -#define TEGRA234_RESET_MPHY_L1_RX 41U -#define TEGRA234_RESET_MPHY_L1_TX 42U -#define TEGRA234_RESET_NVCSI 43U -#define TEGRA234_RESET_NVDEC 44U -#define TEGRA234_RESET_MGBE0_PCS 45U -#define TEGRA234_RESET_MGBE0_MAC 46U -#define TEGRA234_RESET_MGBE0_MACSEC 47U -#define TEGRA234_RESET_MGBE0_MACSEC_SECURE 48U -#define TEGRA234_RESET_MGBE1_PCS 49U -#define TEGRA234_RESET_MGBE1_MAC 50U -#define TEGRA234_RESET_MGBE1_MACSEC 51U -#define TEGRA234_RESET_MGBE1_MACSEC_SECURE 52U -#define TEGRA234_RESET_MGBE2_PCS 53U -#define TEGRA234_RESET_MGBE2_MAC 54U -#define TEGRA234_RESET_MGBE2_MACSEC 55U -#define TEGRA234_RESET_PEX2_CORE_10 56U -#define TEGRA234_RESET_PEX2_CORE_10_APB 57U -#define TEGRA234_RESET_PEX2_COMMON_APB 58U -#define TEGRA234_RESET_NVENC 59U -#define TEGRA234_RESET_MGBE2_MACSEC_SECURE 60U -#define TEGRA234_RESET_NVJPG 61U -#define TEGRA234_RESET_LA 64U -#define TEGRA234_RESET_HWPM 65U -#define TEGRA234_RESET_PVA0_ALL 66U -#define TEGRA234_RESET_CEC 67U -#define TEGRA234_RESET_PWM1 68U -#define TEGRA234_RESET_PWM2 69U -#define TEGRA234_RESET_PWM3 70U -#define TEGRA234_RESET_PWM4 71U -#define TEGRA234_RESET_PWM5 72U -#define TEGRA234_RESET_PWM6 73U -#define TEGRA234_RESET_PWM7 74U -#define TEGRA234_RESET_PWM8 75U -#define TEGRA234_RESET_QSPI0 76U -#define TEGRA234_RESET_QSPI1 77U -#define TEGRA234_RESET_I2S7 78U -#define TEGRA234_RESET_I2S8 79U -#define TEGRA234_RESET_SCE_ALL 80U -#define TEGRA234_RESET_RCE_ALL 81U -#define TEGRA234_RESET_SDMMC1 82U -#define TEGRA234_RESET_RSVD_83 83U -#define TEGRA234_RESET_RSVD_84 84U -#define TEGRA234_RESET_SDMMC4 85U -#define TEGRA234_RESET_MGBE3_PCS 87U -#define TEGRA234_RESET_MGBE3_MAC 88U -#define TEGRA234_RESET_MGBE3_MACSEC 89U -#define TEGRA234_RESET_MGBE3_MACSEC_SECURE 90U -#define TEGRA234_RESET_SPI1 91U -#define TEGRA234_RESET_SPI2 92U -#define TEGRA234_RESET_SPI3 93U -#define TEGRA234_RESET_SPI4 94U -#define TEGRA234_RESET_TACH0 95U -#define TEGRA234_RESET_TACH1 96U -#define TEGRA234_RESET_SPI5 97U -#define TEGRA234_RESET_TSEC 98U -#define TEGRA234_RESET_UARTI 99U -#define TEGRA234_RESET_UARTA 100U -#define TEGRA234_RESET_UARTB 101U -#define TEGRA234_RESET_UARTC 102U -#define TEGRA234_RESET_UARTD 103U -#define TEGRA234_RESET_UARTE 104U -#define TEGRA234_RESET_UARTF 105U -#define TEGRA234_RESET_UARTJ 106U -#define TEGRA234_RESET_UARTH 107U -#define TEGRA234_RESET_UFSHC 108U -#define TEGRA234_RESET_UFSHC_AXI_M 109U -#define TEGRA234_RESET_UFSHC_LP_SEQ 110U -#define TEGRA234_RESET_RSVD_111 111U -#define TEGRA234_RESET_VI 112U -#define TEGRA234_RESET_VIC 113U -#define TEGRA234_RESET_XUSB_PADCTL 114U -#define TEGRA234_RESET_VI2 115U -#define TEGRA234_RESET_PEX0_CORE_0 116U -#define TEGRA234_RESET_PEX0_CORE_1 117U -#define TEGRA234_RESET_PEX0_CORE_2 118U -#define TEGRA234_RESET_PEX0_CORE_3 119U -#define TEGRA234_RESET_PEX0_CORE_4 120U -#define TEGRA234_RESET_PEX0_CORE_0_APB 121U -#define TEGRA234_RESET_PEX0_CORE_1_APB 122U -#define TEGRA234_RESET_PEX0_CORE_2_APB 123U -#define TEGRA234_RESET_PEX0_CORE_3_APB 124U -#define TEGRA234_RESET_PEX0_CORE_4_APB 125U -#define TEGRA234_RESET_PEX0_COMMON_APB 126U -#define TEGRA234_RESET_RSVD_127 127U -#define TEGRA234_RESET_NVHS_UPHY_PLL1 128U -#define TEGRA234_RESET_PEX1_CORE_5 129U -#define TEGRA234_RESET_PEX1_CORE_5_APB 130U -#define TEGRA234_RESET_GBE_UPHY 131U -#define TEGRA234_RESET_GBE_UPHY_PM 132U -#define TEGRA234_RESET_NVHS_UPHY 133U -#define TEGRA234_RESET_NVHS_UPHY_PLL0 134U -#define TEGRA234_RESET_NVHS_UPHY_L0 135U -#define TEGRA234_RESET_NVHS_UPHY_L1 136U -#define TEGRA234_RESET_NVHS_UPHY_L2 137U -#define TEGRA234_RESET_NVHS_UPHY_L3 138U -#define TEGRA234_RESET_NVHS_UPHY_L4 139U -#define TEGRA234_RESET_NVHS_UPHY_L5 140U -#define TEGRA234_RESET_NVHS_UPHY_L6 141U -#define TEGRA234_RESET_NVHS_UPHY_L7 142U -#define TEGRA234_RESET_NVHS_UPHY_PM 143U -#define TEGRA234_RESET_DMIC5 144U -#define TEGRA234_RESET_APE 145U -#define TEGRA234_RESET_PEX_USB_UPHY 146U -#define TEGRA234_RESET_PEX_USB_UPHY_L0 147U -#define TEGRA234_RESET_PEX_USB_UPHY_L1 148U -#define TEGRA234_RESET_PEX_USB_UPHY_L2 149U -#define TEGRA234_RESET_PEX_USB_UPHY_L3 150U -#define TEGRA234_RESET_PEX_USB_UPHY_L4 151U -#define TEGRA234_RESET_PEX_USB_UPHY_L5 152U -#define TEGRA234_RESET_PEX_USB_UPHY_L6 153U -#define TEGRA234_RESET_PEX_USB_UPHY_L7 154U -#define TEGRA234_RESET_PEX_USB_UPHY_PLL0 159U -#define TEGRA234_RESET_PEX_USB_UPHY_PLL1 160U -#define TEGRA234_RESET_PEX_USB_UPHY_PLL2 161U -#define TEGRA234_RESET_PEX_USB_UPHY_PLL3 162U -#define TEGRA234_RESET_GBE_UPHY_L0 163U -#define TEGRA234_RESET_GBE_UPHY_L1 164U -#define TEGRA234_RESET_GBE_UPHY_L2 165U -#define TEGRA234_RESET_GBE_UPHY_L3 166U -#define TEGRA234_RESET_GBE_UPHY_L4 167U -#define TEGRA234_RESET_GBE_UPHY_L5 168U -#define TEGRA234_RESET_GBE_UPHY_L6 169U -#define TEGRA234_RESET_GBE_UPHY_L7 170U -#define TEGRA234_RESET_GBE_UPHY_PLL0 171U -#define TEGRA234_RESET_GBE_UPHY_PLL1 172U -#define TEGRA234_RESET_GBE_UPHY_PLL2 173U - -/** @} */ - -#endif diff --git a/include/dt-bindings/reset/thead,th1520-reset.h b/include/dt-bindings/reset/thead,th1520-reset.h deleted file mode 100644 index 00459f16048..00000000000 --- a/include/dt-bindings/reset/thead,th1520-reset.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2024 Samsung Electronics Co., Ltd. - * Author: Michal Wilczynski <m.wilczynski@samsung.com> - */ - -#ifndef _DT_BINDINGS_TH1520_RESET_H -#define _DT_BINDINGS_TH1520_RESET_H - -#define TH1520_RESET_ID_GPU 0 -#define TH1520_RESET_ID_GPU_CLKGEN 1 -#define TH1520_RESET_ID_NPU 2 -#define TH1520_RESET_ID_WDT0 3 -#define TH1520_RESET_ID_WDT1 4 - -#endif /* _DT_BINDINGS_TH1520_RESET_H */ diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h deleted file mode 100644 index eacc0f18083..00000000000 --- a/include/dt-bindings/reset/ti-syscon.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * TI Syscon Reset definitions - * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ - */ - -#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ -#define __DT_BINDINGS_RESET_TI_SYSCON_H__ - -/* - * The reset does not support the feature and corresponding - * values are not valid - */ -#define ASSERT_NONE (1 << 0) -#define DEASSERT_NONE (1 << 1) -#define STATUS_NONE (1 << 2) - -/* When set this function is activated by setting(vs clearing) this bit */ -#define ASSERT_SET (1 << 3) -#define DEASSERT_SET (1 << 4) -#define STATUS_SET (1 << 5) - -/* The following are the inverse of the above and are added for consistency */ -#define ASSERT_CLEAR (0 << 3) -#define DEASSERT_CLEAR (0 << 4) -#define STATUS_CLEAR (0 << 5) - -#endif diff --git a/include/dt-bindings/reset/toshiba,tmpv770x.h b/include/dt-bindings/reset/toshiba,tmpv770x.h deleted file mode 100644 index c1007acb194..00000000000 --- a/include/dt-bindings/reset/toshiba,tmpv770x.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef _DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ -#define _DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ - -/* Reset */ -#define TMPV770X_RESET_PIETHER_2P5M 0 -#define TMPV770X_RESET_PIETHER_25M 1 -#define TMPV770X_RESET_PIETHER_50M 2 -#define TMPV770X_RESET_PIETHER_125M 3 -#define TMPV770X_RESET_HOX 4 -#define TMPV770X_RESET_PCIE_MSTR 5 -#define TMPV770X_RESET_PCIE_AUX 6 -#define TMPV770X_RESET_PIINTC 7 -#define TMPV770X_RESET_PIETHER_BUS 8 -#define TMPV770X_RESET_PISPI0 9 -#define TMPV770X_RESET_PISPI1 10 -#define TMPV770X_RESET_PISPI2 11 -#define TMPV770X_RESET_PISPI3 12 -#define TMPV770X_RESET_PISPI4 13 -#define TMPV770X_RESET_PISPI5 14 -#define TMPV770X_RESET_PISPI6 15 -#define TMPV770X_RESET_PIUART0 16 -#define TMPV770X_RESET_PIUART1 17 -#define TMPV770X_RESET_PIUART2 18 -#define TMPV770X_RESET_PIUART3 19 -#define TMPV770X_RESET_PII2C0 20 -#define TMPV770X_RESET_PII2C1 21 -#define TMPV770X_RESET_PII2C2 22 -#define TMPV770X_RESET_PII2C3 23 -#define TMPV770X_RESET_PII2C4 24 -#define TMPV770X_RESET_PII2C5 25 -#define TMPV770X_RESET_PII2C6 26 -#define TMPV770X_RESET_PII2C7 27 -#define TMPV770X_RESET_PII2C8 28 -#define TMPV770X_RESET_PIPCMIF 29 -#define TMPV770X_RESET_PICKMON 30 -#define TMPV770X_RESET_SBUSCLK 31 -#define TMPV770X_NR_RESET 32 - -#endif /*_DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ */ diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h b/include/dt-bindings/reset/xlnx-versal-resets.h deleted file mode 100644 index 895424e9b0e..00000000000 --- a/include/dt-bindings/reset/xlnx-versal-resets.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_VERSAL_RESETS_H -#define _DT_BINDINGS_VERSAL_RESETS_H - -#define VERSAL_RST_PMC_POR (0xc30c001U) -#define VERSAL_RST_PMC (0xc410002U) -#define VERSAL_RST_PS_POR (0xc30c003U) -#define VERSAL_RST_PL_POR (0xc30c004U) -#define VERSAL_RST_NOC_POR (0xc30c005U) -#define VERSAL_RST_FPD_POR (0xc30c006U) -#define VERSAL_RST_ACPU_0_POR (0xc30c007U) -#define VERSAL_RST_ACPU_1_POR (0xc30c008U) -#define VERSAL_RST_OCM2_POR (0xc30c009U) -#define VERSAL_RST_PS_SRST (0xc41000aU) -#define VERSAL_RST_PL_SRST (0xc41000bU) -#define VERSAL_RST_NOC (0xc41000cU) -#define VERSAL_RST_NPI (0xc41000dU) -#define VERSAL_RST_SYS_RST_1 (0xc41000eU) -#define VERSAL_RST_SYS_RST_2 (0xc41000fU) -#define VERSAL_RST_SYS_RST_3 (0xc410010U) -#define VERSAL_RST_FPD (0xc410011U) -#define VERSAL_RST_PL0 (0xc410012U) -#define VERSAL_RST_PL1 (0xc410013U) -#define VERSAL_RST_PL2 (0xc410014U) -#define VERSAL_RST_PL3 (0xc410015U) -#define VERSAL_RST_APU (0xc410016U) -#define VERSAL_RST_ACPU_0 (0xc410017U) -#define VERSAL_RST_ACPU_1 (0xc410018U) -#define VERSAL_RST_ACPU_L2 (0xc410019U) -#define VERSAL_RST_ACPU_GIC (0xc41001aU) -#define VERSAL_RST_RPU_ISLAND (0xc41001bU) -#define VERSAL_RST_RPU_AMBA (0xc41001cU) -#define VERSAL_RST_R5_0 (0xc41001dU) -#define VERSAL_RST_R5_1 (0xc41001eU) -#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) -#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) -#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) -#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) -#define VERSAL_RST_SYSMON_LPD (0xc410023U) -#define VERSAL_RST_PDMA_RST1 (0xc410024U) -#define VERSAL_RST_PDMA_RST0 (0xc410025U) -#define VERSAL_RST_ADMA (0xc410026U) -#define VERSAL_RST_TIMESTAMP (0xc410027U) -#define VERSAL_RST_OCM (0xc410028U) -#define VERSAL_RST_OCM2_RST (0xc410029U) -#define VERSAL_RST_IPI (0xc41002aU) -#define VERSAL_RST_SBI (0xc41002bU) -#define VERSAL_RST_LPD (0xc41002cU) -#define VERSAL_RST_QSPI (0xc10402dU) -#define VERSAL_RST_OSPI (0xc10402eU) -#define VERSAL_RST_SDIO_0 (0xc10402fU) -#define VERSAL_RST_SDIO_1 (0xc104030U) -#define VERSAL_RST_I2C_PMC (0xc104031U) -#define VERSAL_RST_GPIO_PMC (0xc104032U) -#define VERSAL_RST_GEM_0 (0xc104033U) -#define VERSAL_RST_GEM_1 (0xc104034U) -#define VERSAL_RST_SPARE (0xc104035U) -#define VERSAL_RST_USB_0 (0xc104036U) -#define VERSAL_RST_UART_0 (0xc104037U) -#define VERSAL_RST_UART_1 (0xc104038U) -#define VERSAL_RST_SPI_0 (0xc104039U) -#define VERSAL_RST_SPI_1 (0xc10403aU) -#define VERSAL_RST_CAN_FD_0 (0xc10403bU) -#define VERSAL_RST_CAN_FD_1 (0xc10403cU) -#define VERSAL_RST_I2C_0 (0xc10403dU) -#define VERSAL_RST_I2C_1 (0xc10403eU) -#define VERSAL_RST_GPIO_LPD (0xc10403fU) -#define VERSAL_RST_TTC_0 (0xc104040U) -#define VERSAL_RST_TTC_1 (0xc104041U) -#define VERSAL_RST_TTC_2 (0xc104042U) -#define VERSAL_RST_TTC_3 (0xc104043U) -#define VERSAL_RST_SWDT_FPD (0xc104044U) -#define VERSAL_RST_SWDT_LPD (0xc104045U) -#define VERSAL_RST_USB (0xc104046U) -#define VERSAL_RST_DPC (0xc208047U) -#define VERSAL_RST_PMCDBG (0xc208048U) -#define VERSAL_RST_DBG_TRACE (0xc208049U) -#define VERSAL_RST_DBG_FPD (0xc20804aU) -#define VERSAL_RST_DBG_TSTMP (0xc20804bU) -#define VERSAL_RST_RPU0_DBG (0xc20804cU) -#define VERSAL_RST_RPU1_DBG (0xc20804dU) -#define VERSAL_RST_HSDP (0xc20804eU) -#define VERSAL_RST_DBG_LPD (0xc20804fU) -#define VERSAL_RST_CPM_POR (0xc30c050U) -#define VERSAL_RST_CPM (0xc410051U) -#define VERSAL_RST_CPMDBG (0xc208052U) -#define VERSAL_RST_PCIE_CFG (0xc410053U) -#define VERSAL_RST_PCIE_CORE0 (0xc410054U) -#define VERSAL_RST_PCIE_CORE1 (0xc410055U) -#define VERSAL_RST_PCIE_DMA (0xc410056U) -#define VERSAL_RST_CMN (0xc410057U) -#define VERSAL_RST_L2_0 (0xc410058U) -#define VERSAL_RST_L2_1 (0xc410059U) -#define VERSAL_RST_ADDR_REMAP (0xc41005aU) -#define VERSAL_RST_CPI0 (0xc41005bU) -#define VERSAL_RST_CPI1 (0xc41005cU) -#define VERSAL_RST_XRAM (0xc30c05dU) -#define VERSAL_RST_AIE_ARRAY (0xc10405eU) -#define VERSAL_RST_AIE_SHIM (0xc10405fU) - -#endif diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h deleted file mode 100644 index d44525b9f8d..00000000000 --- a/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H -#define _DT_BINDINGS_ZYNQMP_RESETS_H - -#define ZYNQMP_RESET_PCIE_CFG 0 -#define ZYNQMP_RESET_PCIE_BRIDGE 1 -#define ZYNQMP_RESET_PCIE_CTRL 2 -#define ZYNQMP_RESET_DP 3 -#define ZYNQMP_RESET_SWDT_CRF 4 -#define ZYNQMP_RESET_AFI_FM5 5 -#define ZYNQMP_RESET_AFI_FM4 6 -#define ZYNQMP_RESET_AFI_FM3 7 -#define ZYNQMP_RESET_AFI_FM2 8 -#define ZYNQMP_RESET_AFI_FM1 9 -#define ZYNQMP_RESET_AFI_FM0 10 -#define ZYNQMP_RESET_GDMA 11 -#define ZYNQMP_RESET_GPU_PP1 12 -#define ZYNQMP_RESET_GPU_PP0 13 -#define ZYNQMP_RESET_GPU 14 -#define ZYNQMP_RESET_GT 15 -#define ZYNQMP_RESET_SATA 16 -#define ZYNQMP_RESET_ACPU3_PWRON 17 -#define ZYNQMP_RESET_ACPU2_PWRON 18 -#define ZYNQMP_RESET_ACPU1_PWRON 19 -#define ZYNQMP_RESET_ACPU0_PWRON 20 -#define ZYNQMP_RESET_APU_L2 21 -#define ZYNQMP_RESET_ACPU3 22 -#define ZYNQMP_RESET_ACPU2 23 -#define ZYNQMP_RESET_ACPU1 24 -#define ZYNQMP_RESET_ACPU0 25 -#define ZYNQMP_RESET_DDR 26 -#define ZYNQMP_RESET_APM_FPD 27 -#define ZYNQMP_RESET_SOFT 28 -#define ZYNQMP_RESET_GEM0 29 -#define ZYNQMP_RESET_GEM1 30 -#define ZYNQMP_RESET_GEM2 31 -#define ZYNQMP_RESET_GEM3 32 -#define ZYNQMP_RESET_QSPI 33 -#define ZYNQMP_RESET_UART0 34 -#define ZYNQMP_RESET_UART1 35 -#define ZYNQMP_RESET_SPI0 36 -#define ZYNQMP_RESET_SPI1 37 -#define ZYNQMP_RESET_SDIO0 38 -#define ZYNQMP_RESET_SDIO1 39 -#define ZYNQMP_RESET_CAN0 40 -#define ZYNQMP_RESET_CAN1 41 -#define ZYNQMP_RESET_I2C0 42 -#define ZYNQMP_RESET_I2C1 43 -#define ZYNQMP_RESET_TTC0 44 -#define ZYNQMP_RESET_TTC1 45 -#define ZYNQMP_RESET_TTC2 46 -#define ZYNQMP_RESET_TTC3 47 -#define ZYNQMP_RESET_SWDT_CRL 48 -#define ZYNQMP_RESET_NAND 49 -#define ZYNQMP_RESET_ADMA 50 -#define ZYNQMP_RESET_GPIO 51 -#define ZYNQMP_RESET_IOU_CC 52 -#define ZYNQMP_RESET_TIMESTAMP 53 -#define ZYNQMP_RESET_RPU_R50 54 -#define ZYNQMP_RESET_RPU_R51 55 -#define ZYNQMP_RESET_RPU_AMBA 56 -#define ZYNQMP_RESET_OCM 57 -#define ZYNQMP_RESET_RPU_PGE 58 -#define ZYNQMP_RESET_USB0_CORERESET 59 -#define ZYNQMP_RESET_USB1_CORERESET 60 -#define ZYNQMP_RESET_USB0_HIBERRESET 61 -#define ZYNQMP_RESET_USB1_HIBERRESET 62 -#define ZYNQMP_RESET_USB0_APB 63 -#define ZYNQMP_RESET_USB1_APB 64 -#define ZYNQMP_RESET_IPI 65 -#define ZYNQMP_RESET_APM_LPD 66 -#define ZYNQMP_RESET_RTC 67 -#define ZYNQMP_RESET_SYSMON 68 -#define ZYNQMP_RESET_AFI_FM6 69 -#define ZYNQMP_RESET_LPD_SWDT 70 -#define ZYNQMP_RESET_FPD 71 -#define ZYNQMP_RESET_RPU_DBG1 72 -#define ZYNQMP_RESET_RPU_DBG0 73 -#define ZYNQMP_RESET_DBG_LPD 74 -#define ZYNQMP_RESET_DBG_FPD 75 -#define ZYNQMP_RESET_APLL 76 -#define ZYNQMP_RESET_DPLL 77 -#define ZYNQMP_RESET_VPLL 78 -#define ZYNQMP_RESET_IOPLL 79 -#define ZYNQMP_RESET_RPLL 80 -#define ZYNQMP_RESET_GPO3_PL_0 81 -#define ZYNQMP_RESET_GPO3_PL_1 82 -#define ZYNQMP_RESET_GPO3_PL_2 83 -#define ZYNQMP_RESET_GPO3_PL_3 84 -#define ZYNQMP_RESET_GPO3_PL_4 85 -#define ZYNQMP_RESET_GPO3_PL_5 86 -#define ZYNQMP_RESET_GPO3_PL_6 87 -#define ZYNQMP_RESET_GPO3_PL_7 88 -#define ZYNQMP_RESET_GPO3_PL_8 89 -#define ZYNQMP_RESET_GPO3_PL_9 90 -#define ZYNQMP_RESET_GPO3_PL_10 91 -#define ZYNQMP_RESET_GPO3_PL_11 92 -#define ZYNQMP_RESET_GPO3_PL_12 93 -#define ZYNQMP_RESET_GPO3_PL_13 94 -#define ZYNQMP_RESET_GPO3_PL_14 95 -#define ZYNQMP_RESET_GPO3_PL_15 96 -#define ZYNQMP_RESET_GPO3_PL_16 97 -#define ZYNQMP_RESET_GPO3_PL_17 98 -#define ZYNQMP_RESET_GPO3_PL_18 99 -#define ZYNQMP_RESET_GPO3_PL_19 100 -#define ZYNQMP_RESET_GPO3_PL_20 101 -#define ZYNQMP_RESET_GPO3_PL_21 102 -#define ZYNQMP_RESET_GPO3_PL_22 103 -#define ZYNQMP_RESET_GPO3_PL_23 104 -#define ZYNQMP_RESET_GPO3_PL_24 105 -#define ZYNQMP_RESET_GPO3_PL_25 106 -#define ZYNQMP_RESET_GPO3_PL_26 107 -#define ZYNQMP_RESET_GPO3_PL_27 108 -#define ZYNQMP_RESET_GPO3_PL_28 109 -#define ZYNQMP_RESET_GPO3_PL_29 110 -#define ZYNQMP_RESET_GPO3_PL_30 111 -#define ZYNQMP_RESET_GPO3_PL_31 112 -#define ZYNQMP_RESET_RPU_LS 113 -#define ZYNQMP_RESET_PS_ONLY 114 -#define ZYNQMP_RESET_PL 115 -#define ZYNQMP_RESET_PS_PL0 116 -#define ZYNQMP_RESET_PS_PL1 117 -#define ZYNQMP_RESET_PS_PL2 118 -#define ZYNQMP_RESET_PS_PL3 119 - -#endif |