5 files changed, 96 insertions, 3 deletions
diff --git a/include/configs/e850-96.h b/include/configs/e850-96.h
index 4607b3089b2..63e85332bd8 100644
--- a/include/configs/e850-96.h
+++ b/include/configs/e850-96.h
@@ -9,4 +9,25 @@
 #ifndef __E850_96_H
 #define __E850_96_H
 
+/* GUIDs for capsule updatable firmware images */
+#define E850_96_FWBL1_IMAGE_GUID \
+	EFI_GUID(0x181cd3f2, 0xe375, 0x44d2, 0x80, 0x78, \
+		 0x32, 0x21, 0xe1, 0xdf, 0xb9, 0x5e)
+
+#define E850_96_EPBL_IMAGE_GUID \
+	EFI_GUID(0x66c1a54d, 0xd149, 0x415d, 0xaa, 0xda, \
+		 0xb8, 0xae, 0xe4, 0x99, 0xb3, 0x70)
+
+#define E850_96_BL2_IMAGE_GUID \
+	EFI_GUID(0x89471c2a, 0x6c8d, 0x4158, 0xac, 0xad, \
+		 0x23, 0xd3, 0xb2, 0x87, 0x3d, 0x35)
+
+#define E850_96_BOOTLOADER_IMAGE_GUID \
+	EFI_GUID(0x629578c3, 0xffb3, 0x4a89, 0xac, 0x0c, \
+		 0x61, 0x18, 0x40, 0x72, 0x77, 0x79)
+
+#define E850_96_EL3_MON_IMAGE_GUID \
+	EFI_GUID(0xdf5718a2, 0x930a, 0x4916, 0xbb, 0x19, \
+		 0x32, 0x13, 0x21, 0x4d, 0x84, 0x86)
+
 #endif /* __E850_96_H */
diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h
index 94355cf61e4..e7db0161126 100644
--- a/include/configs/imx93_evk.h
+++ b/include/configs/imx93_evk.h
@@ -6,8 +6,6 @@
 #ifndef __IMX93_EVK_H
 #define __IMX93_EVK_H
 
-#include <linux/sizes.h>
-#include <linux/stringify.h>
 #include <asm/arch/imx-regs.h>
 
 #define CFG_SYS_UBOOT_BASE	\
diff --git a/include/configs/imx93_frdm.h b/include/configs/imx93_frdm.h
new file mode 100644
index 00000000000..987fcacb999
--- /dev/null
+++ b/include/configs/imx93_frdm.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __IMX93_FRDM_H
+#define __IMX93_FRDM_H
+
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_XPL_BUILD
+#define CFG_MALLOC_F_ADDR		0x204D0000
+#endif
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR		0x80000000
+#define CFG_SYS_INIT_RAM_SIZE		0x200000
+
+#define CFG_SYS_SDRAM_BASE		0x80000000
+#define PHYS_SDRAM			0x80000000
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR			WDG3_BASE_ADDR
+
+#endif
diff --git a/include/init.h b/include/init.h
index 2c10171359c..1e375da4893 100644
--- a/include/init.h
+++ b/include/init.h
@@ -18,7 +18,7 @@
  * In case of the EFI app the UEFI firmware provides the low-level
  * initialisation.
  */
-#ifdef CONFIG_EFI
+#ifdef CONFIG_EFI_CLIENT
 #define ll_boot_init()	false
 #else
 #include <asm/global_data.h>
diff --git a/include/k3_bist.h b/include/k3_bist.h
new file mode 100644
index 00000000000..cc650f5a8c4
--- /dev/null
+++ b/include/k3_bist.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments' BIST (Built-In Self-Test) driver
+ *
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *      Neha Malcom Francis <n-francis@ti.com>
+ *
+ */
+
+#ifndef _INCLUDE_BIST_H_
+#define _INCLUDE_BIST_H_
+
+#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT	0x00000001
+#define PROC_ID_MCU_R5FSS2_CORE0		0x0A
+#define PROC_ID_MCU_R5FSS2_CORE1		0x0B
+#define PROC_BOOT_CTRL_FLAG_R5_LPSC		0x00000002
+
+#define TISCI_DEV_PBIST14 237
+#define TISCI_DEV_R5FSS2_CORE0 343
+#define TISCI_DEV_R5FSS2_CORE1 344
+
+#define TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF 0
+#define TISCI_MSG_VALUE_DEVICE_SW_STATE_RETENTION 1
+#define TISCI_MSG_VALUE_DEVICE_SW_STATE_ON 2
+
+#define TISCI_BIT(n)  ((1) << (n))
+
+struct bist_ops {
+	int (*run_lbist)(void);
+	int (*run_lbist_post)(void);
+	int (*run_pbist_post)(void);
+	int (*run_pbist_neg)(void);
+	int (*run_pbist_rom)(void);
+	int (*run_pbist)(void);
+};
+
+void lbist_enable_isolation(void);
+void lbist_disable_isolation(void);
+int prepare_pbist(struct ti_sci_handle *handle);
+int deprepare_pbist(struct ti_sci_handle *handle);
+int prepare_lbist(struct ti_sci_handle *handle);
+int deprepare_lbist(struct ti_sci_handle *handle);
+
+#endif /* _INCLUDE_BIST_H_ */