diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/faraday/ftpmu010.h | 234 | ||||
| -rw-r--r-- | include/linux/mtd/fsl_upm.h | 44 | ||||
| -rw-r--r-- | include/linux/mtd/fsmc_nand.h | 84 | ||||
| -rw-r--r-- | include/netdev.h | 1 | ||||
| -rw-r--r-- | include/pca9698.h | 17 | ||||
| -rw-r--r-- | include/power/fg_battery_cell_params.h | 73 | ||||
| -rw-r--r-- | include/scf0403_lcd.h | 10 | ||||
| -rw-r--r-- | include/usb/fotg210.h | 362 | ||||
| -rw-r--r-- | include/usb/fusbh200.h | 59 |
9 files changed, 0 insertions, 884 deletions
diff --git a/include/faraday/ftpmu010.h b/include/faraday/ftpmu010.h deleted file mode 100644 index ccb7805375e..00000000000 --- a/include/faraday/ftpmu010.h +++ /dev/null @@ -1,234 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - */ - -/* - * Power Management Unit - */ -#ifndef __FTPMU010_H -#define __FTPMU010_H - -#ifndef __ASSEMBLY__ -struct ftpmu010 { - unsigned int IDNMBR0; /* 0x00 */ - unsigned int reserved0; /* 0x04 */ - unsigned int OSCC; /* 0x08 */ - unsigned int PMODE; /* 0x0C */ - unsigned int PMCR; /* 0x10 */ - unsigned int PED; /* 0x14 */ - unsigned int PEDSR; /* 0x18 */ - unsigned int reserved1; /* 0x1C */ - unsigned int PMSR; /* 0x20 */ - unsigned int PGSR; /* 0x24 */ - unsigned int MFPSR; /* 0x28 */ - unsigned int MISC; /* 0x2C */ - unsigned int PDLLCR0; /* 0x30 */ - unsigned int PDLLCR1; /* 0x34 */ - unsigned int AHBMCLKOFF; /* 0x38 */ - unsigned int APBMCLKOFF; /* 0x3C */ - unsigned int DCSRCR0; /* 0x40 */ - unsigned int DCSRCR1; /* 0x44 */ - unsigned int DCSRCR2; /* 0x48 */ - unsigned int SDRAMHTC; /* 0x4C */ - unsigned int PSPR0; /* 0x50 */ - unsigned int PSPR1; /* 0x54 */ - unsigned int PSPR2; /* 0x58 */ - unsigned int PSPR3; /* 0x5C */ - unsigned int PSPR4; /* 0x60 */ - unsigned int PSPR5; /* 0x64 */ - unsigned int PSPR6; /* 0x68 */ - unsigned int PSPR7; /* 0x6C */ - unsigned int PSPR8; /* 0x70 */ - unsigned int PSPR9; /* 0x74 */ - unsigned int PSPR10; /* 0x78 */ - unsigned int PSPR11; /* 0x7C */ - unsigned int PSPR12; /* 0x80 */ - unsigned int PSPR13; /* 0x84 */ - unsigned int PSPR14; /* 0x88 */ - unsigned int PSPR15; /* 0x8C */ - unsigned int AHBDMA_RACCS; /* 0x90 */ - unsigned int reserved2; /* 0x94 */ - unsigned int reserved3; /* 0x98 */ - unsigned int JSS; /* 0x9C */ - unsigned int CFC_RACC; /* 0xA0 */ - unsigned int SSP1_RACC; /* 0xA4 */ - unsigned int UART1TX_RACC; /* 0xA8 */ - unsigned int UART1RX_RACC; /* 0xAC */ - unsigned int UART2TX_RACC; /* 0xB0 */ - unsigned int UART2RX_RACC; /* 0xB4 */ - unsigned int SDC_RACC; /* 0xB8 */ - unsigned int I2SAC97_RACC; /* 0xBC */ - unsigned int IRDATX_RACC; /* 0xC0 */ - unsigned int reserved4; /* 0xC4 */ - unsigned int USBD_RACC; /* 0xC8 */ - unsigned int IRDARX_RACC; /* 0xCC */ - unsigned int IRDA_RACC; /* 0xD0 */ - unsigned int ED0_RACC; /* 0xD4 */ - unsigned int ED1_RACC; /* 0xD8 */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * ID Number 0 Register - */ -#define FTPMU010_ID_A320A 0x03200000 -#define FTPMU010_ID_A320C 0x03200010 -#define FTPMU010_ID_A320D 0x03200030 - -/* - * OSC Control Register - */ -#define FTPMU010_OSCC_OSCH_TRI (1 << 11) -#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) -#define FTPMU010_OSCC_OSCH_OFF (1 << 8) - -#define FTPMU010_OSCC_OSCL_TRI (1 << 3) -#define FTPMU010_OSCC_OSCL_RTCLSEL (1 << 2) -#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) -#define FTPMU010_OSCC_OSCL_OFF (1 << 0) - -/* - * Power Mode Register - */ -#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) -#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) -#define FTPMU010_PMODE_DIVAHBCLK(pmode) (((pmode) >> 4) & 0x7) -#define FTPMU010_PMODE_FCS (1 << 2) -#define FTPMU010_PMODE_TURBO (1 << 1) -#define FTPMU010_PMODE_SLEEP (1 << 0) - -/* - * Power Manager Status Register - */ -#define FTPMU010_PMSR_SMR (1 << 10) - -#define FTPMU010_PMSR_RDH (1 << 2) -#define FTPMU010_PMSR_PH (1 << 1) -#define FTPMU010_PMSR_CKEHLOW (1 << 0) - -/* - * Multi-Function Port Setting Register - */ -#define FTPMU010_MFPSR_DEBUGSEL (1 << 17) -#define FTPMU010_MFPSR_DMA0PINSEL (1 << 16) -#define FTPMU010_MFPSR_DMA1PINSEL (1 << 15) -#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) -#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) -#define FTPMU010_MFPSR_PWM1PINSEL (1 << 11) -#define FTPMU010_MFPSR_PWM0PINSEL (1 << 10) -#define FTPMU010_MFPSR_IRDACLKSEL (1 << 9) -#define FTPMU010_MFPSR_UARTCLKSEL (1 << 8) -#define FTPMU010_MFPSR_SSPCLKSEL (1 << 6) -#define FTPMU010_MFPSR_I2SCLKSEL (1 << 5) -#define FTPMU010_MFPSR_AC97CLKSEL (1 << 4) -#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) -#define FTPMU010_MFPSR_TRIAHBDIS (1 << 1) -#define FTPMU010_MFPSR_TRIAHBDBG (1 << 0) - -/* - * PLL/DLL Control Register 0 - * Note: - * 1. FTPMU010_PDLLCR0_HCLKOUTDIS: - * Datasheet indicated it starts at bit #21 which was wrong. - * 2. FTPMU010_PDLLCR0_DLLFRAG: - * Datasheet indicated it has 2 bit which was wrong. - */ -#define FTPMU010_PDLLCR0_HCLKOUTDIS(cr0) (((cr0) & 0xf) << 20) -#define FTPMU010_PDLLCR0_DLLFRAG(cr0) (1 << 19) -#define FTPMU010_PDLLCR0_DLLSTSEL (1 << 18) -#define FTPMU010_PDLLCR0_DLLSTABLE (1 << 17) -#define FTPMU010_PDLLCR0_DLLDIS (1 << 16) -#define FTPMU010_PDLLCR0_PLL1FRANG(cr0) (((cr0) & 0x3) << 12) -#define FTPMU010_PDLLCR0_PLL1NS(cr0) (((cr0) & 0x1ff) << 3) -#define FTPMU010_PDLLCR0_PLL1STSEL (1 << 2) -#define FTPMU010_PDLLCR0_PLL1STABLE (1 << 1) -#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) - -/* - * SDRAM Signal Hold Time Control Register - */ -#define FTPMU010_SDRAMHTC_RCLK_DLY(x) (((x) & 0xf) << 28) -#define FTPMU010_SDRAMHTC_CTL_WCLK_DLY(x) (((x) & 0xf) << 24) -#define FTPMU010_SDRAMHTC_DAT_WCLK_DLY(x) (((x) & 0xf) << 20) -#define FTPMU010_SDRAMHTC_EBICTRL_DCSR (1 << 18) -#define FTPMU010_SDRAMHTC_EBIDATA_DCSR (1 << 17) -#define FTPMU010_SDRAMHTC_SDRAMCS_DCSR (1 << 16) -#define FTPMU010_SDRAMHTC_SDRAMCTL_DCSR (1 << 15) -#define FTPMU010_SDRAMHTC_CKE_DCSR (1 << 14) -#define FTPMU010_SDRAMHTC_DQM_DCSR (1 << 13) -#define FTPMU010_SDRAMHTC_SDCLK_DCSR (1 << 12) - -#ifndef __ASSEMBLY__ -void ftpmu010_32768osc_enable(void); -void ftpmu010_dlldis_disable(void); -void ftpmu010_mfpsr_diselect_dev(unsigned int dev); -void ftpmu010_mfpsr_select_dev(unsigned int dev); -void ftpmu010_sdram_clk_disable(unsigned int cr0); -void ftpmu010_sdramhtc_set(unsigned int val); -#endif - -#ifdef __ASSEMBLY__ -#define FTPMU010_IDNMBR0 0x00 -#define FTPMU010_reserved0 0x04 -#define FTPMU010_OSCC 0x08 -#define FTPMU010_PMODE 0x0C -#define FTPMU010_PMCR 0x10 -#define FTPMU010_PED 0x14 -#define FTPMU010_PEDSR 0x18 -#define FTPMU010_reserved1 0x1C -#define FTPMU010_PMSR 0x20 -#define FTPMU010_PGSR 0x24 -#define FTPMU010_MFPSR 0x28 -#define FTPMU010_MISC 0x2C -#define FTPMU010_PDLLCR0 0x30 -#define FTPMU010_PDLLCR1 0x34 -#define FTPMU010_AHBMCLKOFF 0x38 -#define FTPMU010_APBMCLKOFF 0x3C -#define FTPMU010_DCSRCR0 0x40 -#define FTPMU010_DCSRCR1 0x44 -#define FTPMU010_DCSRCR2 0x48 -#define FTPMU010_SDRAMHTC 0x4C -#define FTPMU010_PSPR0 0x50 -#define FTPMU010_PSPR1 0x54 -#define FTPMU010_PSPR2 0x58 -#define FTPMU010_PSPR3 0x5C -#define FTPMU010_PSPR4 0x60 -#define FTPMU010_PSPR5 0x64 -#define FTPMU010_PSPR6 0x68 -#define FTPMU010_PSPR7 0x6C -#define FTPMU010_PSPR8 0x70 -#define FTPMU010_PSPR9 0x74 -#define FTPMU010_PSPR10 0x78 -#define FTPMU010_PSPR11 0x7C -#define FTPMU010_PSPR12 0x80 -#define FTPMU010_PSPR13 0x84 -#define FTPMU010_PSPR14 0x88 -#define FTPMU010_PSPR15 0x8C -#define FTPMU010_AHBDMA_RACCS 0x90 -#define FTPMU010_reserved2 0x94 -#define FTPMU010_reserved3 0x98 -#define FTPMU010_JSS 0x9C -#define FTPMU010_CFC_RACC 0xA0 -#define FTPMU010_SSP1_RACC 0xA4 -#define FTPMU010_UART1TX_RACC 0xA8 -#define FTPMU010_UART1RX_RACC 0xAC -#define FTPMU010_UART2TX_RACC 0xB0 -#define FTPMU010_UART2RX_RACC 0xB4 -#define FTPMU010_SDC_RACC 0xB8 -#define FTPMU010_I2SAC97_RACC 0xBC -#define FTPMU010_IRDATX_RACC 0xC0 -#define FTPMU010_reserved4 0xC4 -#define FTPMU010_USBD_RACC 0xC8 -#define FTPMU010_IRDARX_RACC 0xCC -#define FTPMU010_IRDA_RACC 0xD0 -#define FTPMU010_ED0_RACC 0xD4 -#define FTPMU010_ED1_RACC 0xD8 -#endif /* __ASSEMBLY__ */ - -#endif /* __FTPMU010_H */ diff --git a/include/linux/mtd/fsl_upm.h b/include/linux/mtd/fsl_upm.h deleted file mode 100644 index 9999993543b..00000000000 --- a/include/linux/mtd/fsl_upm.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * FSL UPM NAND driver - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - */ - -#ifndef __LINUX_MTD_NAND_FSL_UPM -#define __LINUX_MTD_NAND_FSL_UPM - -#include <linux/mtd/rawnand.h> - -#define FSL_UPM_WAIT_RUN_PATTERN 0x1 -#define FSL_UPM_WAIT_WRITE_BYTE 0x2 -#define FSL_UPM_WAIT_WRITE_BUFFER 0x4 - -struct fsl_upm { - void __iomem *mdr; - void __iomem *mxmr; - void __iomem *mar; - void __iomem *io_addr; -}; - -struct fsl_upm_nand { - struct fsl_upm upm; - - int width; - int upm_cmd_offset; - int upm_addr_offset; - int upm_mar_chip_offset; - int wait_flags; - int (*dev_ready)(int chip_nr); - int chip_delay; - int chip_offset; - int chip_nr; - - /* no need to fill */ - int last_ctrl; -}; - -extern int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun); - -#endif diff --git a/include/linux/mtd/fsmc_nand.h b/include/linux/mtd/fsmc_nand.h deleted file mode 100644 index 1d8a067f17e..00000000000 --- a/include/linux/mtd/fsmc_nand.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. - */ - -#ifndef __FSMC_NAND_H__ -#define __FSMC_NAND_H__ - -#include <linux/mtd/rawnand.h> - -struct fsmc_regs { - u32 ctrl; /* 0x00 */ - u8 reserved_1[0x40 - 0x04]; - u32 pc; /* 0x40 */ - u32 sts; /* 0x44 */ - u32 comm; /* 0x48 */ - u32 attrib; /* 0x4c */ - u32 ioata; /* 0x50 */ - u32 ecc1; /* 0x54 */ - u32 ecc2; /* 0x58 */ - u32 ecc3; /* 0x5c */ - u8 reserved_2[0xfe0 - 0x60]; - u32 peripid0; /* 0xfe0 */ - u32 peripid1; /* 0xfe4 */ - u32 peripid2; /* 0xfe8 */ - u32 peripid3; /* 0xfec */ - u32 pcellid0; /* 0xff0 */ - u32 pcellid1; /* 0xff4 */ - u32 pcellid2; /* 0xff8 */ - u32 pcellid3; /* 0xffc */ -}; - -/* ctrl register definitions */ -#define FSMC_WP (1 << 7) - -/* pc register definitions */ -#define FSMC_RESET (1 << 0) -#define FSMC_WAITON (1 << 1) -#define FSMC_ENABLE (1 << 2) -#define FSMC_DEVTYPE_NAND (1 << 3) -#define FSMC_DEVWID_8 (0 << 4) -#define FSMC_DEVWID_16 (1 << 4) -#define FSMC_ECCEN (1 << 6) -#define FSMC_ECCPLEN_512 (0 << 7) -#define FSMC_ECCPLEN_256 (1 << 7) -#define FSMC_TCLR_1 (1 << 9) -#define FSMC_TAR_1 (1 << 13) - -/* sts register definitions */ -#define FSMC_CODE_RDY (1 << 15) - -/* comm register definitions */ -#define FSMC_TSET_0 (0 << 0) -#define FSMC_TWAIT_6 (6 << 8) -#define FSMC_THOLD_4 (4 << 16) -#define FSMC_THIZ_1 (1 << 24) - -/* peripid2 register definitions */ -#define FSMC_REVISION_MSK (0xf) -#define FSMC_REVISION_SHFT (0x4) - -#define FSMC_VER8 0x8 - -/* - * There are 13 bytes of ecc for every 512 byte block and it has to be read - * consecutively and immediately after the 512 byte data block for hardware to - * generate the error bit offsets - * Managing the ecc bytes in the following way is easier. This way is similar to - * oobfree structure maintained already in u-boot nand driver - */ -#define FSMC_MAX_ECCPLACE_ENTRIES 32 - -struct fsmc_nand_eccplace { - u32 offset; - u32 length; -}; - -struct fsmc_eccplace { - struct fsmc_nand_eccplace eccplace[FSMC_MAX_ECCPLACE_ENTRIES]; -}; - -extern int fsmc_nand_init(struct nand_chip *nand); -#endif diff --git a/include/netdev.h b/include/netdev.h index 2b4e474ed08..2a7f40e5040 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -71,7 +71,6 @@ int skge_initialize(struct bd_info *bis); int smc91111_initialize(u8 dev_num, phys_addr_t base_addr); int smc911x_initialize(u8 dev_num, phys_addr_t base_addr); int uli526x_initialize(struct bd_info *bis); -int armada100_fec_register(unsigned long base_addr); /* Boards with PCI network controllers can call this from their board_eth_init() * function to initialize whatever's on board. diff --git a/include/pca9698.h b/include/pca9698.h deleted file mode 100644 index 48a5f756e28..00000000000 --- a/include/pca9698.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -#ifndef __PCA9698_H_ -#define __PCA9698_H_ - -int pca9698_request(unsigned gpio, const char *label); -void pca9698_free(unsigned gpio); -int pca9698_direction_input(u8 addr, unsigned gpio); -int pca9698_direction_output(u8 addr, unsigned gpio, int value); -int pca9698_get_value(u8 addr, unsigned gpio); -int pca9698_set_value(u8 addr, unsigned gpio, int value); - -#endif /* __PCA9698_H_ */ diff --git a/include/power/fg_battery_cell_params.h b/include/power/fg_battery_cell_params.h deleted file mode 100644 index 500c8ea7174..00000000000 --- a/include/power/fg_battery_cell_params.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#ifndef __FG_BATTERY_CELL_PARAMS_H_ -#define __FG_BATTERY_CELL_PARAMS_H_ - -#if defined(CONFIG_POWER_FG_MAX17042) && defined(CONFIG_TARGET_TRATS) - -/* Cell characteristics - Exynos4 TRATS development board */ -/* Shall be written to addr 0x80h */ -u16 cell_character0[16] = { - 0xA2A0, - 0xB6E0, - 0xB850, - 0xBAD0, - 0xBB20, - 0xBB70, - 0xBBC0, - 0xBC20, - 0xBC80, - 0xBCE0, - 0xBD80, - 0xBE20, - 0xC090, - 0xC420, - 0xC910, - 0xD070 -}; - -/* Shall be written to addr 0x90h */ -u16 cell_character1[16] = { - 0x0090, - 0x1A50, - 0x02F0, - 0x2060, - 0x2060, - 0x2E60, - 0x26A0, - 0x2DB0, - 0x2DB0, - 0x1870, - 0x2A20, - 0x16F0, - 0x08F0, - 0x0D40, - 0x08C0, - 0x08C0 -}; - -/* Shall be written to addr 0xA0h */ -u16 cell_character2[16] = { - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100, - 0x0100 -}; -#endif -#endif /* __FG_BATTERY_CELL_PARAMS_H_ */ diff --git a/include/scf0403_lcd.h b/include/scf0403_lcd.h deleted file mode 100644 index 07f8c643ba5..00000000000 --- a/include/scf0403_lcd.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013, Compulab Inc. - */ -#ifndef SCF0403_LCD_H_ -#define SCF0403_LCD_H_ - -int scf0403_init(int reset_gpio); - -#endif diff --git a/include/usb/fotg210.h b/include/usb/fotg210.h deleted file mode 100644 index 292ce54e0c4..00000000000 --- a/include/usb/fotg210.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday USB 2.0 OTG Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#ifndef _FOTG210_H -#define _FOTG210_H - -struct fotg210_regs { - /* USB Host Controller */ - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t rsvd1[3]; - uint32_t miscr; /* 0x40: Miscellaneous Register */ - uint32_t rsvd2[15]; - /* USB OTG Controller */ - uint32_t otgcsr;/* 0x80: OTG Control Status Register */ - uint32_t otgisr;/* 0x84: OTG Interrupt Status Register */ - uint32_t otgier;/* 0x88: OTG Interrupt Enable Register */ - uint32_t rsvd3[13]; - uint32_t isr; /* 0xC0: Global Interrupt Status Register */ - uint32_t imr; /* 0xC4: Global Interrupt Mask Register */ - uint32_t rsvd4[14]; - /* USB Device Controller */ - uint32_t dev_ctrl;/* 0x100: Device Control Register */ - uint32_t dev_addr;/* 0x104: Device Address Register */ - uint32_t dev_test;/* 0x108: Device Test Register */ - uint32_t sof_fnr; /* 0x10c: SOF Frame Number Register */ - uint32_t sof_mtr; /* 0x110: SOF Mask Timer Register */ - uint32_t phy_tmsr;/* 0x114: PHY Test Mode Selector Register */ - uint32_t rsvd5[2]; - uint32_t cxfifo;/* 0x120: CX FIFO Register */ - uint32_t idle; /* 0x124: IDLE Counter Register */ - uint32_t rsvd6[2]; - uint32_t gimr; /* 0x130: Group Interrupt Mask Register */ - uint32_t gimr0; /* 0x134: Group Interrupt Mask Register 0 */ - uint32_t gimr1; /* 0x138: Group Interrupt Mask Register 1 */ - uint32_t gimr2; /* 0x13c: Group Interrupt Mask Register 2 */ - uint32_t gisr; /* 0x140: Group Interrupt Status Register */ - uint32_t gisr0; /* 0x144: Group Interrupt Status Register 0 */ - uint32_t gisr1; /* 0x148: Group Interrupt Status Register 1 */ - uint32_t gisr2; /* 0x14c: Group Interrupt Status Register 2 */ - uint32_t rxzlp; /* 0x150: Receive Zero-Length-Packet Register */ - uint32_t txzlp; /* 0x154: Transfer Zero-Length-Packet Register */ - uint32_t isoeasr;/* 0x158: ISOC Error/Abort Status Register */ - uint32_t rsvd7[1]; - uint32_t iep[8]; /* 0x160 - 0x17f: IN Endpoint Register */ - uint32_t oep[8]; /* 0x180 - 0x19f: OUT Endpoint Register */ - uint32_t epmap14;/* 0x1a0: Endpoint Map Register (EP1 ~ 4) */ - uint32_t epmap58;/* 0x1a4: Endpoint Map Register (EP5 ~ 8) */ - uint32_t fifomap;/* 0x1a8: FIFO Map Register */ - uint32_t fifocfg; /* 0x1ac: FIFO Configuration Register */ - uint32_t fifocsr[4];/* 0x1b0 - 0x1bf: FIFO Control Status Register */ - uint32_t dma_fifo; /* 0x1c0: DMA Target FIFO Register */ - uint32_t rsvd8[1]; - uint32_t dma_ctrl; /* 0x1c8: DMA Control Register */ - uint32_t dma_addr; /* 0x1cc: DMA Address Register */ - uint32_t ep0_data; /* 0x1d0: EP0 Setup Packet PIO Register */ -}; - -/* Miscellaneous Register */ -#define MISCR_SUSPEND (1 << 6) /* Put transceiver in suspend mode */ -#define MISCR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define MISCR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define MISCR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* OTG Control Status Register */ -#define OTGCSR_SPD_HIGH (2 << 22) /* Speed of the attached device (host) */ -#define OTGCSR_SPD_LOW (1 << 22) -#define OTGCSR_SPD_FULL (0 << 22) -#define OTGCSR_SPD_MASK (3 << 22) -#define OTGCSR_SPD_SHIFT 22 -#define OTGCSR_SPD(x) (((x) >> 22) & 0x03) -#define OTGCSR_DEV_A (0 << 21) /* Acts as A-device */ -#define OTGCSR_DEV_B (1 << 21) /* Acts as B-device */ -#define OTGCSR_ROLE_H (0 << 20) /* Acts as Host */ -#define OTGCSR_ROLE_D (1 << 20) /* Acts as Device */ -#define OTGCSR_A_VBUS_VLD (1 << 19) /* A-device VBUS Valid */ -#define OTGCSR_A_SESS_VLD (1 << 18) /* A-device Session Valid */ -#define OTGCSR_B_SESS_VLD (1 << 17) /* B-device Session Valid */ -#define OTGCSR_B_SESS_END (1 << 16) /* B-device Session End */ -#define OTGCSR_HFT_LONG (1 << 11) /* HDISCON noise filter = 270 us*/ -#define OTGCSR_HFT (0 << 11) /* HDISCON noise filter = 135 us*/ -#define OTGCSR_VFT_LONG (1 << 10) /* VBUS noise filter = 472 us*/ -#define OTGCSR_VFT (0 << 10) /* VBUS noise filter = 135 us*/ -#define OTGCSR_IDFT_LONG (1 << 9) /* ID noise filter = 4 ms*/ -#define OTGCSR_IDFT (0 << 9) /* ID noise filter = 3 ms*/ -#define OTGCSR_A_SRPR_VBUS (0 << 8) /* A-device: SRP responds to VBUS */ -#define OTGCSR_A_SRPR_DATA (1 << 8) /* A-device: SRP responds to DATA-LINE */ -#define OTGCSR_A_SRP_EN (1 << 7) /* A-device SRP detection enabled */ -#define OTGCSR_A_HNP (1 << 6) /* Set role=A-device with HNP enabled */ -#define OTGCSR_A_BUSDROP (1 << 5) /* A-device drop bus (power-down) */ -#define OTGCSR_A_BUSREQ (1 << 4) /* A-device request bus */ -#define OTGCSR_B_VBUS_DISC (1 << 2) /* B-device discharges VBUS */ -#define OTGCSR_B_HNP (1 << 1) /* B-device enable HNP */ -#define OTGCSR_B_BUSREQ (1 << 0) /* B-device request bus */ - -/* OTG Interrupt Status Register */ -#define OTGISR_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGISR_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGISR_OVD (1 << 10) /* over-current detected */ -#define OTGISR_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGISR_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGISR_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGISR_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGISR_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGISR_BSRP (1 << 0) /* B-device SRP complete */ - -/* OTG Interrupt Enable Register */ -#define OTGIER_APRM (1 << 12) /* Mini-A plug removed */ -#define OTGIER_BPRM (1 << 11) /* Mini-B plug removed */ -#define OTGIER_OVD (1 << 10) /* over-current detected */ -#define OTGIER_IDCHG (1 << 9) /* ID(A/B) changed */ -#define OTGIER_RLCHG (1 << 8) /* Role(Host/Device) changed */ -#define OTGIER_BSESSEND (1 << 6) /* B-device Session End */ -#define OTGIER_AVBUSERR (1 << 5) /* A-device VBUS Error */ -#define OTGIER_ASRP (1 << 4) /* A-device SRP detected */ -#define OTGIER_BSRP (1 << 0) /* B-device SRP complete */ - -/* Global Interrupt Status Register (W1C) */ -#define ISR_HOST (1 << 2) /* USB Host interrupt */ -#define ISR_OTG (1 << 1) /* USB OTG interrupt */ -#define ISR_DEV (1 << 0) /* USB Device interrupt */ -#define ISR_MASK 0x07 - -/* Global Interrupt Mask Register */ -#define IMR_IRQLH (1 << 3) /* Interrupt triggered at level-high */ -#define IMR_IRQLL (0 << 3) /* Interrupt triggered at level-low */ -#define IMR_HOST (1 << 2) /* USB Host interrupt */ -#define IMR_OTG (1 << 1) /* USB OTG interrupt */ -#define IMR_DEV (1 << 0) /* USB Device interrupt */ -#define IMR_MASK 0x0f - -/* Device Control Register */ -#define DEVCTRL_FS_FORCED (1 << 9) /* Forced to be Full-Speed Mode */ -#define DEVCTRL_HS (1 << 6) /* High Speed Mode */ -#define DEVCTRL_FS (0 << 6) /* Full Speed Mode */ -#define DEVCTRL_EN (1 << 5) /* Chip Enable */ -#define DEVCTRL_RESET (1 << 4) /* Chip Software Reset */ -#define DEVCTRL_SUSPEND (1 << 3) /* Enter Suspend Mode */ -#define DEVCTRL_GIRQ_EN (1 << 2) /* Global Interrupt Enabled */ -#define DEVCTRL_HALFSPD (1 << 1) /* Half speed mode for FPGA test */ -#define DEVCTRL_RWAKEUP (1 << 0) /* Enable remote wake-up */ - -/* Device Address Register */ -#define DEVADDR_CONF (1 << 7) /* SET_CONFIGURATION has been executed */ -#define DEVADDR_ADDR(x) ((x) & 0x7f) -#define DEVADDR_ADDR_MASK 0x7f - -/* Device Test Register */ -#define DEVTEST_NOSOF (1 << 6) /* Do not generate SOF */ -#define DEVTEST_TST_MODE (1 << 5) /* Enter Test Mode */ -#define DEVTEST_TST_NOTS (1 << 4) /* Do not toggle sequence */ -#define DEVTEST_TST_NOCRC (1 << 3) /* Do not append CRC */ -#define DEVTEST_TST_CLREA (1 << 2) /* Clear External Side Address */ -#define DEVTEST_TST_CXLP (1 << 1) /* EP0 loopback test */ -#define DEVTEST_TST_CLRFF (1 << 0) /* Clear FIFO */ - -/* SOF Frame Number Register */ -#define SOFFNR_UFN(x) (((x) >> 11) & 0x7) /* SOF Micro-Frame Number */ -#define SOFFNR_FNR(x) ((x) & 0x7ff) /* SOF Frame Number */ - -/* SOF Mask Timer Register */ -#define SOFMTR_TMR(x) ((x) & 0xffff) - -/* PHY Test Mode Selector Register */ -#define PHYTMSR_TST_PKT (1 << 4) /* Packet send test */ -#define PHYTMSR_TST_SE0NAK (1 << 3) /* High-Speed quiescent state */ -#define PHYTMSR_TST_KSTA (1 << 2) /* High-Speed K state */ -#define PHYTMSR_TST_JSTA (1 << 1) /* High-Speed J state */ -#define PHYTMSR_UNPLUG (1 << 0) /* Enable soft-detachment */ - -/* CX FIFO Register */ -#define CXFIFO_BYTES(x) (((x) >> 24) & 0x7f) /* CX/EP0 FIFO byte count */ -#define CXFIFO_FIFOE(x) (1 << (((x) & 0x03) + 8)) /* EPx FIFO empty */ -#define CXFIFO_FIFOE_FIFO0 (1 << 8) -#define CXFIFO_FIFOE_FIFO1 (1 << 9) -#define CXFIFO_FIFOE_FIFO2 (1 << 10) -#define CXFIFO_FIFOE_FIFO3 (1 << 11) -#define CXFIFO_FIFOE_MASK (0x0f << 8) -#define CXFIFO_CXFIFOE (1 << 5) /* CX FIFO empty */ -#define CXFIFO_CXFIFOF (1 << 4) /* CX FIFO full */ -#define CXFIFO_CXFIFOCLR (1 << 3) /* CX FIFO clear */ -#define CXFIFO_CXSTALL (1 << 2) /* CX Stall */ -#define CXFIFO_TSTPKTFIN (1 << 1) /* Test packet data transfer finished */ -#define CXFIFO_CXFIN (1 << 0) /* CX data transfer finished */ - -/* IDLE Counter Register */ -#define IDLE_MS(x) ((x) & 0x07) /* PHY suspend delay = x ms */ - -/* Group Interrupt Mask(Disable) Register */ -#define GIMR_GRP2 (1 << 2) /* Disable interrupt group 2 */ -#define GIMR_GRP1 (1 << 1) /* Disable interrupt group 1 */ -#define GIMR_GRP0 (1 << 0) /* Disable interrupt group 0 */ -#define GIMR_MASK 0x07 - -/* Group Interrupt Mask(Disable) Register 0 (CX) */ -#define GIMR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GIMR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GIMR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GIMR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GIMR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GIMR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ -#define GIMR0_MASK 0x3f - -/* Group Interrupt Mask(Disable) Register 1 (FIFO) */ -#define GIMR1_FIFO_IN(x) (1 << (((x) & 3) + 16)) /* FIFOx IN */ -#define GIMR1_FIFO_TX(x) GIMR1_FIFO_IN(x) -#define GIMR1_FIFO_OUT(x) (1 << (((x) & 3) * 2)) /* FIFOx OUT */ -#define GIMR1_FIFO_SPK(x) (1 << (((x) & 3) * 2 + 1)) /* FIFOx SHORT PACKET */ -#define GIMR1_FIFO_RX(x) (GIMR1_FIFO_OUT(x) | GIMR1_FIFO_SPK(x)) -#define GIMR1_MASK 0xf00ff - -/* Group Interrupt Mask(Disable) Register 2 (Device) */ -#define GIMR2_WAKEUP (1 << 10) /* Device waked up */ -#define GIMR2_IDLE (1 << 9) /* Device idle */ -#define GIMR2_DMAERR (1 << 8) /* DMA error */ -#define GIMR2_DMAFIN (1 << 7) /* DMA finished */ -#define GIMR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GIMR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GIMR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GIMR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GIMR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GIMR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GIMR2_RESET (1 << 0) /* Reset Interrupt */ -#define GIMR2_MASK 0x7ff - -/* Group Interrupt Status Register */ -#define GISR_GRP2 (1 << 2) /* Interrupt group 2 */ -#define GISR_GRP1 (1 << 1) /* Interrupt group 1 */ -#define GISR_GRP0 (1 << 0) /* Interrupt group 0 */ - -/* Group Interrupt Status Register 0 (CX) */ -#define GISR0_CXABORT (1 << 5) /* CX command abort interrupt */ -#define GISR0_CXERR (1 << 4) /* CX command error interrupt */ -#define GISR0_CXEND (1 << 3) /* CX command end interrupt */ -#define GISR0_CXOUT (1 << 2) /* EP0-OUT packet interrupt */ -#define GISR0_CXIN (1 << 1) /* EP0-IN packet interrupt */ -#define GISR0_CXSETUP (1 << 0) /* EP0-SETUP packet interrupt */ - -/* Group Interrupt Status Register 1 (FIFO) */ -#define GISR1_IN_FIFO(x) (1 << (((x) & 0x03) + 16)) /* FIFOx IN */ -#define GISR1_OUT_FIFO(x) (1 << (((x) & 0x03) * 2)) /* FIFOx OUT */ -#define GISR1_SPK_FIFO(x) (1 << (((x) & 0x03) * 2 + 1)) /* FIFOx SPK */ -#define GISR1_RX_FIFO(x) (3 << (((x) & 0x03) * 2)) /* FIFOx OUT/SPK */ - -/* Group Interrupt Status Register 2 (Device) */ -#define GISR2_WAKEUP (1 << 10) /* Device waked up */ -#define GISR2_IDLE (1 << 9) /* Device idle */ -#define GISR2_DMAERR (1 << 8) /* DMA error */ -#define GISR2_DMAFIN (1 << 7) /* DMA finished */ -#define GISR2_ZLPRX (1 << 6) /* Zero-Length-Packet Rx Interrupt */ -#define GISR2_ZLPTX (1 << 5) /* Zero-Length-Packet Tx Interrupt */ -#define GISR2_ISOCABT (1 << 4) /* ISOC Abort Interrupt */ -#define GISR2_ISOCERR (1 << 3) /* ISOC Error Interrupt */ -#define GISR2_RESUME (1 << 2) /* Resume state change Interrupt */ -#define GISR2_SUSPEND (1 << 1) /* Suspend state change Interrupt */ -#define GISR2_RESET (1 << 0) /* Reset Interrupt */ - -/* Receive Zero-Length-Packet Register */ -#define RXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP rx interrupt */ - -/* Transfer Zero-Length-Packet Register */ -#define TXZLP_EP(x) (1 << ((x) - 1)) /* EPx ZLP tx interrupt */ - -/* ISOC Error/Abort Status Register */ -#define ISOEASR_EP(x) (0x10001 << ((x) - 1)) /* EPx ISOC Error/Abort */ - -/* IN Endpoint Register */ -#define IEP_SENDZLP (1 << 15) /* Send Zero-Length-Packet */ -#define IEP_TNRHB(x) (((x) & 0x03) << 13) \ - /* Transaction Number for High-Bandwidth EP(ISOC) */ -#define IEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define IEP_STALL (1 << 11) /* Stall */ -#define IEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ - -/* OUT Endpoint Register */ -#define OEP_RESET (1 << 12) /* Reset Toggle Sequence */ -#define OEP_STALL (1 << 11) /* Stall */ -#define OEP_MAXPS(x) ((x) & 0x7ff) /* Max. packet size */ - -/* Endpoint Map Register (EP1 ~ EP4) */ -#define EPMAP14_SET_IN(ep, fifo) \ - ((fifo) & 3) << (((ep) - 1) << 3 + 0) -#define EPMAP14_SET_OUT(ep, fifo) \ - ((fifo) & 3) << (((ep) - 1) << 3 + 4) -#define EPMAP14_SET(ep, in, out) \ - do { \ - EPMAP14_SET_IN(ep, in); \ - EPMAP14_SET_OUT(ep, out); \ - } while (0) - -#define EPMAP14_DEFAULT 0x33221100 /* EP1->FIFO0, EP2->FIFO1... */ - -/* Endpoint Map Register (EP5 ~ EP8) */ -#define EPMAP58_SET_IN(ep, fifo) \ - ((fifo) & 3) << (((ep) - 5) << 3 + 0) -#define EPMAP58_SET_OUT(ep, fifo) \ - ((fifo) & 3) << (((ep) - 5) << 3 + 4) -#define EPMAP58_SET(ep, in, out) \ - do { \ - EPMAP58_SET_IN(ep, in); \ - EPMAP58_SET_OUT(ep, out); \ - } while (0) - -#define EPMAP58_DEFAULT 0x00000000 /* All EPx->FIFO0 */ - -/* FIFO Map Register */ -#define FIFOMAP_BIDIR (2 << 4) -#define FIFOMAP_IN (1 << 4) -#define FIFOMAP_OUT (0 << 4) -#define FIFOMAP_DIR_MASK 0x30 -#define FIFOMAP_EP(x) ((x) & 0x0f) -#define FIFOMAP_EP_MASK 0x0f -#define FIFOMAP_CFG_MASK 0x3f -#define FIFOMAP_DEFAULT 0x04030201 /* FIFO0->EP1, FIFO1->EP2... */ -#define FIFOMAP(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) - -/* FIFO Configuration Register */ -#define FIFOCFG_EN (1 << 5) -#define FIFOCFG_BLKSZ_1024 (1 << 4) -#define FIFOCFG_BLKSZ_512 (0 << 4) -#define FIFOCFG_3BLK (2 << 2) -#define FIFOCFG_2BLK (1 << 2) -#define FIFOCFG_1BLK (0 << 2) -#define FIFOCFG_NBLK_MASK 3 -#define FIFOCFG_NBLK_SHIFT 2 -#define FIFOCFG_INTR (3 << 0) -#define FIFOCFG_BULK (2 << 0) -#define FIFOCFG_ISOC (1 << 0) -#define FIFOCFG_RSVD (0 << 0) /* Reserved */ -#define FIFOCFG_TYPE_MASK 3 -#define FIFOCFG_TYPE_SHIFT 0 -#define FIFOCFG_CFG_MASK 0x3f -#define FIFOCFG(fifo, cfg) (((cfg) & 0x3f) << (((fifo) & 3) << 3)) - -/* FIFO Control Status Register */ -#define FIFOCSR_RESET (1 << 12) /* FIFO Reset */ -#define FIFOCSR_BYTES(x) ((x) & 0x7ff) /* Length(bytes) for OUT-EP/FIFO */ - -/* DMA Target FIFO Register */ -#define DMAFIFO_CX (1 << 4) /* DMA FIFO = CX FIFO */ -#define DMAFIFO_FIFO(x) (1 << ((x) & 0x3)) /* DMA FIFO = FIFOx */ - -/* DMA Control Register */ -#define DMACTRL_LEN(x) (((x) & 0x1ffff) << 8) /* DMA length (Bytes) */ -#define DMACTRL_LEN_SHIFT 8 -#define DMACTRL_CLRFF (1 << 4) /* Clear FIFO upon DMA abort */ -#define DMACTRL_ABORT (1 << 3) /* DMA abort */ -#define DMACTRL_IO2IO (1 << 2) /* IO to IO */ -#define DMACTRL_FIFO2MEM (0 << 1) /* FIFO to Memory */ -#define DMACTRL_MEM2FIFO (1 << 1) /* Memory to FIFO */ -#define DMACTRL_START (1 << 0) /* DMA start */ - -#endif diff --git a/include/usb/fusbh200.h b/include/usb/fusbh200.h deleted file mode 100644 index 6ae1d848801..00000000000 --- a/include/usb/fusbh200.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday USB 2.0 EHCI Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#ifndef _FUSBH200_H -#define _FUSBH200_H - -struct fusbh200_regs { - struct { - uint32_t data[4]; - } hccr; /* 0x00 - 0x0f: hccr */ - struct { - uint32_t data[9]; - } hcor; /* 0x10 - 0x33: hcor */ - uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */ - uint32_t rsvd[2]; - uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */ - uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */ - uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */ -}; - -/* EOF & Async. Schedule Sleep Timer Register */ -#define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ -#define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ -#define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ -#define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ -#define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ - -/* Bus Monitor Control Status Register */ -#define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ -#define BMCSR_SPD_LOW (1 << 9) -#define BMCSR_SPD_FULL (0 << 9) -#define BMCSR_SPD_MASK (3 << 9) -#define BMCSR_SPD_SHIFT 9 -#define BMCSR_SPD(x) ((x >> 9) & 0x03) -#define BMCSR_VBUS (1 << 8) /* VBUS Valid */ -#define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ -#define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ -#define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ -#define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ -#define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ -#define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ -#define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ -#define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ -#define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ - -/* Bus Monitor Interrupt Status Register */ -/* Bus Monitor Interrupt Enable Register */ -#define BMISR_DMAERR (1 << 4) /* DMA error */ -#define BMISR_DMA (1 << 3) /* DMA complete */ -#define BMISR_DEVRM (1 << 2) /* device removed */ -#define BMISR_OVD (1 << 1) /* over-current detected */ -#define BMISR_VBUSERR (1 << 0) /* VBUS error */ - -#endif |