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2025-05-26Prepare v2025.07-rc3v2025.07-rc3Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-25Merge branch 'master' of git://source.denx.de/u-boot-usbTom Rini
2025-05-25Merge tag 'efi-2025-07-rc3-3' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request efi-2025-07-rc3-3 CI: * https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/26313 UEFI: * run dhcp if an http boot option is selected * separate device path into its own header and add it to the API docs * rename END to EFI_DP_END * make x86 SMBIOS tables usable in the EFI context
2025-05-25usb: ulpi: Clean up how we enable supportTom Rini
The way we enable ULPI support today isn't something that should work. The "optional" keyword in a choice statement is not a documented feature. To make this work in a supported way, make USB_ULPI something we ask about if USB_HOST is set. Next, we move the choice of what viewer to use to be after the framework portion and to depend on that. We then borrow a few words from the top-level README to make the help text here clearer. Finally we make the Qualcomm driver select ULPI as it's required and we make the tegra driver not duplicate a check that Kconfig now handles for us. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-25usb: ulpi: Remove unused omap-ulpi-viewport driverTom Rini
The last platform to enable this driver was removed in 2019. Remove this unused code and documentation now. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-25usb: dwc3: core: Fix timeout checkVaradarajan Narayanan
dwc3_core_init loops 'timeout' times to check if the IP block is out of reset using 'while (timeout--)'. If there is some issue and the block doesn't come out of reset, the loop will run till 'timeout' becomes zero and the post decrement operator would set timeout to 0xffffffff. Though the IP block is not out reset, the subsequent if check 'if !timeout' would fail as timeout is not equal to zero and the function proceeds with the initialization. Use poll API instead to resolve this. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-05-25efi_loader: Run dhcp if an http boot option is selectedIlias Apalodimas
The EFI boot manager relies on having an IP address before trying to boot an EFI HTTP(s) boot entry. However, defining it as a boot or pre-boot command is not always the right answer since it will unconditionally add delay to the board boot, even if we don't boot over the network. So let's do a DHCP request from the boot manager, if 'ipaddr' is empty and fail early if we don't have an address. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-by: Michal Simek <michal.simek@amd.com>
2025-05-25x86: efi_loader: Ensure the SMBIOS tables are sent via EFISimon Glass
The EFI-loader code has not been fully converted to use bloblist, so relies on the SMBIOS-table address being set in global_data. Set this up in write_tables() so that the SMBIOS tables are actually available. Enable the command for x86 QEMU so that the SMBIOS tests actually run. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 83ce35d6ebb ("emulation: Use bloblist to hold tables") Reported-by: Niklas Sombert <niklas.sombert@uni-duesseldorf.de> Tested-by: Niklas Sombert <niklas.sombert@uni-duesseldorf.de> Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-05-25efi: Rename END to EFI_DP_ENDSimon Glass
This exported symbol has a very generic name. Rename it to indicate that it relates to EFI and device-paths. Fix checkpatch warnings related to use of multiple assignments. Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-05-25efi: Include device-path functions in the EFI API docsSimon Glass
Include these function so they can be browsed in the API docs. Exclude END since it causes a warning, which becomes an error: ./include/efi_device_path.h:22: warning: cannot understand function prototype: 'const struct efi_device_path END; ' Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-05-25efi_loader: Separate device path into its own headerSimon Glass
These functions are useful for the EFI app. As a first step towards making these available outside lib/efi_loader, create a separate header file and include it where needed. Add proper comments to the functions, since many are missing at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-05-23ext4fs: Fix: Read outside partition errorTony Dinh
Use lbaint_t for blknr to avoid overflow in ext4fs_read_file(). Background: blknr (block number) used in ext4fs_read_file() could be increased to a very large value and causes a wrap around at 32 bit signed integer max, thus becomes negative. This results in an out-of-normal range for sector number (during the assignment delayed_start = blknr) where delayed_start sector is typed uint64 lbaint_t. This causes the "Read outside partition" error. This patch was tested on the Synology DS116 (Armada 385) board, and a 4TB Seagate HDD. Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2025-05-23fs: fs_devread should log error when read outside partitionTony Dinh
Log the error if fs_devread() fails when trying to reading outside partition. This will make bug reporting easier. Signed-off-by: Tony Dinh <mibodhi@gmail.com>
2025-05-23board: total_Compute: enable bloblist for SPL handoffJayanth Dodderi Chidanand
Add bloblist support to total_comput platform for passing data from TF-A using the firmware handoff framework. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
2025-05-23EXT4: add CRC16 dependencyMarius Dinu
CRC16 is used in ext4_common.c. Build fails without it. PS: This is my first patch sent to a mailing list. If there is anything wrong with it (email format, whitespace, etc.) please let me know. Signed-off-by: Marius Dinu <m95d+git@psihoexpert.ro>
2025-05-23env: mtd: fix usability with NAND flashesWeijie Gao
1. As this is for MTD-based devices, the Kconfig dependency should be MTD instead of only spi-nor flashes 2. Initialize saved_buf to avoid crash on free() 3. Remaining size should be set correctly to write_size Fixes: 03fb08d4aef (env: Introduce support for MTD) Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> Reviewed-by: Christian Marangi <ansuelsmth@gmail.com>
2025-05-22Merge tag 'u-boot-imx-master-20250522' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/26275 - Fix boot regression on imx8mn_bsh_smm_s2/s2pro. - Fix reset on imx6ulz_smm_m2. - Adjust DDR initialization on imx6ulz_smm_m2. - Fix CAAM startup error.
2025-05-22caam: Fix CAAM error on startupOlaf Baehring
In rare cases U-Boot returns an error message when intantiating the RNG of the CAAM device: “SEC0: RNG4 SH0 instantiation failed with error 0xffffffff” This means, that even when the CAAM device reports a finished descriptor, none is found in the output ring. This might be caused by a missing cache invalidation before reading the memory of the output ring This patch moves the cache invalidation of the output ring from start of the job to immediately after the notification from hardware where the output ring will be read. Signed-off-by: Olaf Baehring <olaf.baehring@draeger.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
2025-05-21Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/26259 - Initial SPL support for T-Head TH1520 SoC - Improve usability of TH1520 with mainline SPL - Support building RV32 & RV64 images - riscv: Improve jh7110 support
2025-05-21Merge tag 'net-20250520' of https://source.denx.de/u-boot/custodians/u-boot-netTom Rini
Pull request net-20250520. CI: https://source.denx.de/u-boot/custodians/u-boot-net/-/pipelines/26247 net, net-lwip: - Remove wget console output when called by EFI net-lwip: - Add 10 s timeout to TFTP - Add LMB buffer checks
2025-05-21board: bsh: imx6ulz_smm_m2: Add delay between DRAM read accessMichael Bode
A small delay between DRAM read access with wrong parameters and reconfiguration is necessary. Without a delay between DRAM read access and a following reconfiguration this reconfiguration fails for certain DRAM chips (Nanya). Signed-off-by: Michael Bode <michael.bode@bshg.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2025-05-21board: bsh: imx6ulz_smm_m2: Add support for 512 MiB DRAMMichael Bode
Calibration values were calculated using the NXP tool I.MX6ULL_DDR3_Script_Aid_V0.01.xlsx Signed-off-by: Michael Bode <michael.bode@bshg.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2025-05-21board: bsh: imx6ulz_smm_m2: Add support for 256 MiB DRAMSimon Holesch
Calibration values were calculated using the NXP tool I.MX6ULL_DDR3_Script_Aid_V0.01.xlsx Signed-off-by: Wolfgang Birkner <wolfgang.birkner@bshg.com> Signed-off-by: Simon Holesch <simon.holesch@bshg.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2025-05-21board: bsh: imx6ulz_smm_m2: Match SPL DDR settings to DCD tableMichael Trimarchi
When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code. As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case. The idea is simple: just use the DCD table and write directly to the DDR registers. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2025-05-21board: freescale: imx8mn_evk: let clock system enable UART clockMichael Trimarchi
Now that the UART driver can enable the required clocks, remove the hard-coded clock enable. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Tested-by: Fabio Estevam <festevam@gmail.com>
2025-05-21board: bsh: imx8mn_bsh_smm_s2/s2pro: let clock system enable UART clockDario Binacchi
Now that the UART driver can enable the required clocks, remove the hard-coded clock enable. Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2025-05-21board: bsh: imx8mn_bsh_smm_s2/s2pro: enlarge CONFIG_SPL_SYS_MALLOC_F_LENDario Binacchi
The commit dda454e933c6 ("serial: mxc: Support bulk enabling clocks") breaks the booting of the BSH SMM S2 board. The analysis of the issue revealed memory allocation failures during the registration of UART4 clocks as well as other peripherals. Increasing SYS_MALLOC_F_LEN to 0x10000 fixed the issue. Dropping this option allows it to be set to the default value of CONFIG_SYS_MALLOC_F_LEN, which is set by default to 0x10000 on i.MX8M platforms. Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2025-05-21configs: imx8mn_bsh_smm_s2: load U-Boot from raw NANDDario Binacchi
Commit 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") breaks the boot of the BSH SMM S2 board. Add options to load U-Boot from raw NAND sector. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2025-05-21imx: spl_imx_romapi: support raw NAND sectorDario Binacchi
Commit 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") breaks the boot of the BSH SMM S2 board. As stated in the dropped comment, "Some boards use this value even though MMC is not enabled in SPL, for example imx8mn_bsh_smm_s2". Support load of the U-Boot image from raw NAND sector. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2025-05-21spl: Kconfig: support U-Boot load from raw NANDDario Binacchi
Commit 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") breaks the boot of the BSH SMM S2 board. As stated in the commit itself, "Some boards use this value even though MMC is not enabled in SPL, for example imx8mn_bsh_smm_s2". Support load of the U-Boot image from raw NAND sector. This is equivalent to load from MMC raw sector. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2025-05-21ARM: dts: imx93-phycore: Migrate to OF_UPSTREAMPrimoz Fiser
Migrate to OF_UPSTREAM for phyCORE-i.MX93 since board can use upstream Linux kernel device-tree for phyBOARD-Segin-i.MX93. Signed-off-by: Primoz Fiser <primoz.fiser@norik.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
2025-05-21arm: dts: imx6ulz-bsh-smm-m2: Fix reset using wdt-reboot driverMichael Trimarchi
commit 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") introduced a regression that 'reset' command unable to reset imx6ulz based BSH module's modules in the u-boot. BSH module's imx6, imx6ulz-bsh-smm-m2.dts Fixes: 68dcbdd594d4 ("ARM: imx: Add weak default reset_cpu()") Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-21configs: imx6ulz_smm_m2: Add board watchdog reset configurationMichael Trimarchi
Add the configuration that allow to reset the board from reset cmd Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-21arm: dts: imx6ulz-bsh-smm-m2-u-boot: Drop soc nodeMichael Trimarchi
The node is specified on the parent architecture u-boot.dtsi file Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2025-05-21arm: imx: imx8m: soc: replace ifdef by IS_ENABLED()Dario Binacchi
Standardize on using the IS_ENABLED macro. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-21arm: imx: imx8m: soc: fix the macro nameMichael Trimarchi
The function arch_spl_mmc_get_uboot_raw_sector() was never compiled, even when the option CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION was enabled. So rename the macro SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION to CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION. Fixes: 2a00d73d081a ("spl: mmc: Try to clean up raw-mode options") Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-05-21riscv: dts: th1520: Complete clock treeYao Zi
Describe the newly-supported clock controller of TH1520 in SoC devicetree, replace dummy clocks with the controller-supplied ones and add correct clocks for GPIO controllers. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21riscv: cpu: th1520: Select clock driverYao Zi
The clock driver is essential for TH1520 SoCs to operate. Select the driver in SoC Kconfig entry. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21clk: thead: Port clock controller driver of TH1520 SoCYao Zi
The driver is adapted from Linux kernel's version of clk-th1520-ap.c, with only output clocks for external sensors, which are barely useful in bootloaders, removed. Same as the mainline driver, it currently lacks of ability to enable and reconfigure PLLs, which could be implemented later. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21riscv: cpu: th1520: Initialize IOPMPs in SPLYao Zi
TH1520 SoC ships several IOPMPs protecting various on-chip peripherals. They must be configured before accessing the peripherals. Let's initialize them in SPL harts_early_init(). Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21doc: thead: lpi4a: Update documentationYao Zi
Support for eMMC, SD card, GPIO and SPL have been available in LPi4A port. Update the documentation of support status and build instructions. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21board: thead: licheepi4a: Enable SPL supportYao Zi
Adjust Kconfig and defconfig and add SPL initialization code for Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC earlier. The board devicetree is changed to use TH1520 binman configuration to generate bootable images. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21riscv: dts: th1520: Add binman configurationYao Zi
Add binman configuration for TH1520 SoC, whose BROM loads the image combined into SRAM and directly jumps to it. The configuration creates u-boot-with-spl.bin where the SPL code locates at the start and the DDR firmware is shipped. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21riscv: dts: th1520: Add DRAM controllerYao Zi
Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL devicetree blob. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21riscv: dts: lichee-module-4a: Preserve memory node for SPLYao Zi
Memory node is necessary for TH1520 SPL to configure size and base address of DRAM. Let's preserve it in SPL devicetree blob. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21riscv: dts: th1520: Preserve necessary devices for SPLYao Zi
SPL for TH1520 requires CPU and boot UART nodes to function. Preserve them in SPL devicetree blob with bootph-pre-ram property. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21ram: thead: Add initial DDR controller support for TH1520Yao Zi
This patch cleans the vendor code of DDR initialization up, converts the driver to fit in DM framework and use a firmware[1] packaged by binman to ship PHY configuration. Currently the driver is only capable of initializing the controller to work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants of LicheePi 4A boards and I could test with. Support for other configurations could be easily added later. Link: https://github.com/ziyao233/th1520-firmware # [1] Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21riscv: cpu: Add TH1520 CPU supportYao Zi
Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21configs: th1520_lpi4a: Add UART clock frequencyYao Zi
The BROM of TH1520 always initializes UART0's parent clock and configures the baudrate to 115200. Describe the clock frequency to make UART function correctly in SPL without introducing CCF. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21riscv: lib: Split out support for T-Head cache management operationsYao Zi
Designed before a standard set of cache management operations defined in RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the customized extension XTheadCMO, which has been used in the CV1800B port of U-Boot. This patch splits XTheadCMO-related code into a generic module, allowing SoCs shipping T-Head cores to share the code. Link: https://github.com/XUANTIE-RV/thead-extension-spec Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-06 11:46:47 +0000