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12 daysMerge patch series "Update linker scripts to ensure appended device tree is ↵Tom Rini
correctly aligned" Tom Rini <trini@konsulko.com> says: This series builds on top of what Beleswar Padhi did in [1]. While there's still discussion about the mkimage related parts, the linker portion appears to the reliable path forward. An alternative that I had mentioned before, and was part of previous discussions on this topic[2] is in the end I believe not reliable enough. While we can take an output file and pad it to where we think it needs to be, ultimately the linker needs to place the symbol where we want it and if that isn't where we pad to, we have a different problem. So what this series does (but each commit message elaborates on the arch-specific linker scripts being inconsistent) is make sure the linker script will place the required symbol at 8-byte alignment, and then also use an ASSERT to fail the build if this would not be true due to some unforseen event. [1]: https://lore.kernel.org/u-boot/20260112101102.1417970-1-b-padhi@ti.com/ [2]: https://source.denx.de/u-boot/u-boot/-/issues/30 Link: https://lore.kernel.org/r/20260115222828.3931345-1-trini@konsulko.com
12 daysmicroblaze: Update linker scripts to ensure appended device tree is alignedTom Rini
With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c") it is now a fatal error to U-Boot if our device tree is not 8-byte aligned. In commit 85f586035d75 ("ARM: OMAP2+: Pad SPL binary to 8-byte alignment before DTB") Beleswar Padhi explains that we must have ALIGN(x) statements inside of a section to ensure that padding is included and not simply that the linker address counter is incremented. To that end, this patch: - Aligns the final section before _end (for U-Boot) or _image_binary_end (for xPL phases) by 8-bytes by adjusting the ALIGN(4) statement to be ALIGN(8) in the final section before the symbol. - Ensure that we do have alignment by adding an ASSERT so that when not aligned we fail to link (and explain why). Tested-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Tom Rini <trini@konsulko.com>
13 daysmicroblaze: Fix SPL device supportMichal Simek
Extend spl_boot_list[] only when SPL has support for it. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d1c1d677b2eb4266290d31dbdf2e6e44c77a75ff.1768557507.git.michal.simek@amd.com
2025-06-19dtc: Add Kconfig option to pad device tree blobEric Schikschneit
This will allow arch(s) that use device tree blobs to pad the end of the device tree so they can be modified by board files at run time. This will help prevent errors such as FDT_ERR_NOSPACE from occurring. Signed-off-by: Eric Schikschneit <eric.schikschneit@novatechautomation.com> [trini: Change default order so that X86 && EFI_APP works correctly]
2025-06-13microblaze: drop volatile qualifier from gd pointerRasmus Villemoes
Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
2024-10-14dts: Deduplicate dtbs targetMarek Vasut
The dtbs: target is almost identical in all architecture Makefiles. All architecture Makefiles include scripts/Makefile.dts . Deduplicate the dtbs: target into scripts/Makefile.dts . No functional change. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Caleb Connolly <caleb.connolly@linaro.org> #qcom, OF_UPSTREAM
2024-10-11arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
2024-09-03lmb: do away with arch_lmb_reserve()Sughosh Ganu
All of the current definitions of arch_lmb_reserve() are doing the same thing -- reserve the region of memory occupied by U-Boot, starting from the current stack address to the ram_top. Introduce a function lmb_reserve_uboot_region() which does this, and do away with the arch_lmb_reserve() function. Instead of using the current value of stack pointer for starting the reserved region, have a fixed value, considering the stack size config value. Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-09-03lmb: make LMB memory map persistent and globalSughosh Ganu
The current LMB API's for allocating and reserving memory use a per-caller based memory view. Memory allocated by a caller can then be overwritten by another caller. Make these allocations and reservations persistent using the alloced list data structure. Two alloced lists are declared -- one for the available(free) memory, and one for the used memory. Once full, the list can then be extended at runtime. [sjg: Use a stack to store pointer of lmb struct when running lmb tests] Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Signed-off-by: Simon Glass <sjg@chromium.org> [sjg: Optimise the logic to add a region in lmb_add_region_flags()]
2024-07-15microblaze: Remove duplicate newlinesMarek Vasut
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-06global: Make <asm/global_data.h> include <asm/u-boot.h>Tom Rini
This follows the example of RISC-V where <asm/global_data.h> includes <asm/u-boot.h> directly as "gd" includes a reference to bd_info already and so the first must include the second anyhow. We then remove <asm/u-boot.h> from all of the places which include references to "gd" an so have <asm/global_data.h> already. Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-18Revert "Merge patch series "pxe: Allow extlinux booting without CMDLINE ↵Tom Rini
enabled"" As reported by Jonas Karlman this series breaks booting on some AArch64 platforms with common use cases. For now the best path forward is to revert the series. This reverts commit 777c28460947371ada40868dc994dfe8537d7115, reversing changes made to ab3453e7b12daef47b9e91da2a2a3d48615dc6fc. Link: https://lore.kernel.org/u-boot/50dfa3d6-a1ca-4492-a3fc-8d8c56b40b43@kwiboo.se/ Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-10Merge patch series "pxe: Allow extlinux booting without CMDLINE enabled"Tom Rini
Simon Glass <sjg@chromium.org> says: This series is the culmanation of the current line of refactoring series. It adjusts pxe to call the booting functionality directly rather than going through the command-line interface. With this is is possible to boot using the extlinux bootmeth without the command line enabled. It also updates fastboot to do a similar thing.
2024-04-10treewide: Make arch-specific bootm code depend on BOOTMSimon Glass
Allow these functions to be compiled in when CONFIG_BOOTM is enabled, even if CONFIG_CMD_BOOTM is not. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Angelo Dureghello <angelo@kernel-space.org>
2024-01-22mtd: Make CONFIG_MTD be the gate symbol for the menuTom Rini
The help for CONFIG_MTD explains that it needs to be enabled for various things like NAND, etc to be available. It however then doesn't enforce this dependency and so if you have none of these systems present you still need to disable a number of options. Fix this by making places that select/imply one type of flash, but did not do the same, also do this for "MTD". Make boards which hadn't been enabling MTD already but need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it wasn't previously enabled but was now being implied. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21bootm: Adjust arguments of boot_os_fnSimon Glass
Adjust boot_os_fn to use struct bootm_info instead of the separate argc, argv and image parameters. Update the handlers accordingly. Few of the functions make use of the arguments, so this improves code size slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-10-24microblaze: Remove common.h usageTom Rini
We can remove common.h from most cases of the code here, and only a few places need an additional header instead. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Michal Simek <michal.simek@amd.com>
2023-08-09treewide: rework linker symbol declarations in sections headerShiji Yang
1. Convert all linker symbols to char[] type so that we can get the corresponding address by calling array name 'var' or its address '&var'. In this way, we can avoid some potential issues[1]. 2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has not been referenced by any source code. 3. Move '__data_end' to the arch x86's own sections header as it's only used by x86 arch. 4. Remove some duplicate declared linker symbols. Now we use the standard header file to declare them. [1] This patch fixes the boot failure on MIPS target. Error log: SPL: Image overlaps SPL Fixes: 1b8a1be1a1f1 ("spl: spl_legacy: Fix spl_end address") Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-07-21arm64: zynqmp: Switch to amd.com emailsMichal Simek
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-03microblaze: u-boot-spl.lds: Pass _image_binary_endFabio Estevam
Pass _image_binary_end to make a standard way to indicate the end of the text section in SPL. The motivation for this is to have a uniform way to handle the SPL boundary checks. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
2023-03-13microblaze: drop remnants of manual relocOvidiu Panait
Runtime relocation has been made the default for microblaze, so do the following cleanups: - drop all manual reloc codepaths in start.S - drop all STATIC_RELA ifdefs, as it is now enabled unconditionally in Kconfig Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20230311173838.521804-5-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-03-13microblaze: drop CONFIG_NEEDS_MANUAL_RELOCOvidiu Panait
Microblaze and m68k are the only remaining architectures that still enable CONFIG_NEEDS_MANUAL_RELOC by default. Microblaze has had runtime relocation support using CONFIG_STATIC_RELA for quite some time, since commit d58c007498 ("microblaze: Add support for run time relocation"). Drop support for CONFIG_NEEDS_MANUAL_RELOC and make runtime relocation the default, as the rest of the architectures do. Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20230311173838.521804-4-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-02-10Correct SPL uses of LMBSimon Glass
This converts 9 usages of this option to the non-SPL form, since there is no SPL_LMB defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09Correct SPL uses of CPU_MICROBLAZESimon Glass
This converts 2 usages of this option to the non-SPL form, since there is no SPL_CPU_MICROBLAZE defined in Kconfig Signed-off-by: Simon Glass <sjg@chromium.org>
2023-01-27microblaze: spl: drop boot_linuxOvidiu Panait
Drop boot_linux variable as it is not assigned anywhere. Now that there is no variable controlling linux boot in spl_start_uboot(), make this function always return false when falcon mode is enabled. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20230125164157.1638680-2-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-01-27microblaze: spl: wrap spl_start_uboot() in SPL_OS_BOOT ifdefsOvidiu Panait
Make spl_start_uboot() available only if CONFIG_SPL_OS_BOOT is enabled, since it is only used for falcon mode. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20230125164157.1638680-1-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-12-22Convert CONFIG_STANDALONE_LOAD_ADDR to KconfigTom Rini
This converts the following to Kconfig: CONFIG_STANDALONE_LOAD_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-10-31Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASESimon Glass
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29treewide: Drop bootm_headers_t typedefSimon Glass
This is not needed and we should avoid typedefs. Use the struct instead. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-13microblaze: add arch_print_bdinfo() implementationOvidiu Panait
Allow bdinfo command to print icache/dcache information: U-Boot-mONStR> bdinfo boot_params = 0x00000000 DRAM bank = 0x00000000 -> start = 0x04000000 -> size = 0x04000000 flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 baudrate = 9600 bps relocaddr = 0x07f76000 reloc off = 0x02f76000 Build = 32-bit current eth = unknown ethaddr = (not set) IP addr = <NULL> fdt_blob = 0x07fec7e0 new_fdt = 0x00000000 fdt_size = 0x00000000 lmb_dump_all: memory.cnt = 0x1 memory[0] [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0 reserved.cnt = 0x1 reserved[0] [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0 devicetree = embed icache = 32 KiB icache line = 4 Bytes dcache = 32 KiB dcache line = 4 Bytes Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-07-26zynqmp: Run board_get_usable_ram_top() only on main U-BootAshok Reddy Soma
With commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location"), the function board_get_usable_ram_top() is allocating MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this much memory in case of mini U-Boot. Keep these functions which use lmb under CONFIG_LMB so that they are compiled and used only when LMB is enabled. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
2022-07-07Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to KconfigTom Rini
This converts the following to Kconfig: CONFIG_SYS_BOOT_RAMDISK_HIGH Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-27Merge tag 'xilinx-for-v2022.10' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
2022-06-24microblaze: Remove interrupt handlerMichal Simek
The primary purpose for this code was timer. By converting it to CONFIG_TIMER there is no code which uses this implementation that's why remove it. If there is a need to handle interrupts this patch can be reverted in future. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/5f2decc5a30a5678490ebde26d8c6f5a5f873cda.1654684731.git.michal.simek@amd.com
2022-06-24microblaze: Convert axi timer to DM driverMichal Simek
Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com
2022-06-24cpu: add CPU driver for microblazeOvidiu Panait
Add a basic CPU driver that retrieves information about the microblaze CPU core. cpu_ops handlers are implemented so that the "cpu" command can work properly: U-Boot-mONStR> cpu list 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 U-Boot-mONStR> cpu detail 0: cpu@0 MicroBlaze @ 50MHz, Rev: 11.0, FPGA family: zynq7000 ID = 0, freq = 50 MHz: L1 cache, MMU Note: cpu_ver_lookup[] and family_string_lookup[] arrays were imported from linux. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-14-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: add support for handling PVR dataOvidiu Panait
Add helper code for PVR (Processor Version Register) data handling. It will be used by the UCLASS_CPU driver to populate cpuinfo fields at runtime. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-13-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce flush_dcache_range()Ovidiu Panait
Align microblaze with the other architectures and provide an implementation for flush_dcache_range(). Also, remove the microblaze exception in drivers/core/device.c. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-11-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce cpuinfo structureOvidiu Panait
Introduce a minimal cpuinfo structure to hold cache related info. The instruction/data cache size and cache line size are initialized early in the boot to default Kconfig values. They will be overwritten with data from PVR/dtb if the microblaze UCLASS_CPU driver is enabled. The cpuinfo struct was placed in global_data to allow the microblaze UCLASS_CPU driver to also run before relocation (initialized global data should be read-only before relocation). gd_cpuinfo() helper macro was added to avoid volatile "-Wdiscarded-qualifiers" warnings when using the pointer directly. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-10-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/)
2022-06-24microblaze: cache: introduce flush_cache_all()Ovidiu Panait
All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-9-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: introduce Kconfig options for icache/dcache sizesOvidiu Panait
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for instruction and data caches sizes, respectively: CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Also, get rid of the hardcoded value in icache_disable(). Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
2022-06-24microblaze: cache: split flush_cache() functionOvidiu Panait
Factor out icache/dcache components from flush_cache() function. Call the newly added __flush_icache()/__flush_dcache() functions inside icache_disable() and dcache_disable(), respectively. There is no need to flush both caches when disabling a particular cache type. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-7-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: improve icache Kconfig optionsOvidiu Panait
Replace CONFIG_ICACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WIC. It should be enabled if the processor supports the "wic" (Write to Instruction Cache) instruction. It will be used to guard "wic" invocations in microblaze cache code. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-6-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: improve dcache Kconfig optionsOvidiu Panait
Replace CONFIG_DCACHE with a Kconfig option more limited in scope - XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports the "wdc" (Write to Data Cache) instruction. It will be used to guard "wdc" invocations in microblaze cache code. Also, drop all ifdefs around flush_cache() calls and only keep one CONFIG_IS_ENABLED() guard within flush_cache() itself. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: cache: replace XILINX_USE_DCACHE -> CONFIG_DCACHEOvidiu Panait
XILINX_USE_DCACHE macro was removed in 7556fa09e0e ("microblaze: Simplify cache handling"), but it was still used in a couple of places. Replace those occurences with CONFIG_DCACHE. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-4-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: start.S: remove unused codeOvidiu Panait
in16/out16 routines seem to not be used anywhere in microblaze code, so remove them. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Link: https://lore.kernel.org/r/20220531181435.3473549-3-ovpanait@gmail.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-06-24microblaze: Add support for run time relocationMichal Simek
Microblaze is using NEEDS_MANUAL_RELOC from the beginnging. This is causing issues with function pointer arrays which need to be updated manually after relocation. Building code with -fPIC and linking with -pic will remove this limitation and there is no longer need to run manual update. By default still old option is enabled but by disabling NEEDS_MANUAL_RELOC code will be compiled for full relocation. The patch does couple of things which are connected to each other. - Define STATIC_RELA dependency to call relocate-rela to fill sections. - REMAKE_ELF was already enabled but u-boot file can't be used because sections are empty. relocate-rela will fill them and output file is u-boot.elf which should be used. - Add support for full relocation (u-boot.elf) - Add support for early relocation when u-boot.bin is loaded to different address then CONFIG_SYS_TEXT_BASE - Add rela.dyn and dynsym sections Disabling NEEDS_MANUAL_RELOC U-Boot size increased by 10% of it's original size (550kB to 608kB). Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/a845670b34925859b2e321875f7588a29f6655f9.1655299267.git.michal.simek@amd.com
2022-06-24microblaze: Create SYM_ADDR macro to deal with symbolsMichal Simek
Symbol handling depends on compilation flags. Right now manual relocation is used that's why symbols can be referenced just by name and there is no need to find them out. But when position independent code (PIC) is used symbols need to be described differently. That's why having one macro change is easier than changing the whole code. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/d704e9a267c8b536452fb999111dbfbc9d652be5.1655299267.git.michal.simek@amd.com
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