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path: root/arch/riscv/cpu/fu740/spl.c
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2024-05-02board: sifive: Rename spl_soc_init() to spl_dram_init()Lukas Funke
Rename spl_soc_init() to spl_dram_init() because the generic function name does not reflect what the function actually does. Also spl_dram_init() is commonly used for dram initialization and should be called from board_init_f(). Signed-off-by: Lukas Funke <lukas.funke@weidmueller.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-08-17riscv: cpu: fu740: Fix typo of dateZong Li
Fixed the typo of date of copyright declaration. Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-31riscv: cpu: fu740: clear feature disable CSRGreen Wan
Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-05-31riscv: cpu: fu740: Add support for cpu fu740Green Wan
Add SiFive fu740 cpu to support RISC-V arch Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>