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C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.
This patch sets them up for efficient operation and satisfying
requirements of an SMP system.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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TH1520 SoC ships several IOPMPs protecting various on-chip peripherals.
They must be configured before accessing the peripherals. Let's
initialize them in SPL harts_early_init().
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Introduce the SoC-specific code and corresponding Kconfig entries for
TH1520 SoC. Following features are implemented for TH1520,
- Cache enable/disable through customized CSR
- Invalidation of customized PMP entries
- DRAM driver probing for SPL
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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