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A redundant comparison (jtag_usercode >= 0) was removed from the
condition checking jtag_usercode. Since jtag_usercode is an unsigned
integer, the check for non-negativity was always true. The code was
simplified to resolve the Coverity warning.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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Enable nand as one of the bootable media in SPL.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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This configuration is not valid for N5X; removing it.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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All the source code of secure_vab.c and secure_vab.h are from Intel
and Altera. Updating the license to use either GPL-2.0 or
BSD-3-Clause because this copy of code may be used for open source
and internal project.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Appropriate header files are included according to U-Boot
coding style.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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This patch is to set spi-max-freq to 50Mhz. This will add support to the
driver to set the operation speed according to the slave device up to
50Mhz. Without this node, the driver just can adjust the operation speed
to the default speed which is far below the best
operation speed of the SPI slave device.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Fix STMicroelectronics spelling in comments.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Since SYS_MALLOC_F_LEN increasing to 0x2100000 on STM32MP13, the
pre-console buffer is overlapped by stack (0xC0400000 + 0x2100000),
so the this buffer must be moved just before the bootstage to avoid issue.
After this patch the pre-relocation memory mapping for STM32MP13x is:
C3000000 = Bootstage CONFIG_BOOTSTAGE_STASH_ADDR
C2FFF000 = PreConsole CONFIG_PRE_CON_BUF_ADDR
with size CONFIG_PRE_CON_BUF_SZ = 4096
C0400000 = start for stack with CONFIG_CUSTOM_SYS_INIT_SP_ADDR
including CONFIG_SYS_MALLOC_F_LEN
C0000000 = Load Address of U-Boot with CONFIG_TEXT_BASE
Fixes: 93c962c7af7e ("configs: stm32mp13: increase SYS_MALLOC_F_LEN to 0x210000")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Cosmetic update to replace space by tab in sys_proto.h
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Add U-Boot specific file for stm32mp235f-dk board
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Add STM32MP23 support which is a cost optimized of STM32MP25.
More details available at:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Add SPL specific DT additions to DH STM32MP13xx DHCOR DHSBC . These
include I2C3 configuration which is required to access the PMIC,
PMIC regulator and QSPI NOR bootph-all properties to allow SPL to
configure PMIC buck regulators and load from QSPI NOR respectively,
etzpc bus switch to simple-bus to prevent interference from TFABOOT
specific configuration, and RCC configuration to define clock tree
configuration used by this platform.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Add DT additions required by U-Boot SPL to bring up the hardware.
This includes binman node to generate STM32 Image v2.0 which can be
booted by the BootROM, clock entries used by the SPL clock driver
during clock tree initialization, and syscon-reboot node so U-Boot
can reset the system without having to rely on PSCI call.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Add DRAM settings for 512 MiB of DRAM variant of DH STM32MP13xx DHCOR DHSBC.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Factor out common parts of STM32MP15xx DRAM controller configuration DT
description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
describes STM32MP13xx DRAM controller configuration in DT.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Add hardware initialization for the STM32MP13xx in SPL. This is
similar to STM32MP15xx except the code has to enable MCE to bring
DRAM controller up later.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Introduce Kconfig options used by SPL on STM32MP13xx and isolate
the Kconfig options only used in case TFA BL2 is used as a SPL
behind CONFIG_TFABOOT dependency.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
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Add support for STM32MP25 SoC.
Identification and hardware configuration registers allow to read the
timer version and capabilities (counter width, ...).
So, rework the probe to avoid touching ARR register by simply read the
counter width when available. This may avoid messing with a possibly
running timer.
Also add useful bit fields to stm32-timers header file.
Signed-off-by: Cheick Traore <cheick.traore@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
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https://source.denx.de/u-boot/custodians/u-boot-at91
Second set of u-boot-at91 features for the 2025.10 cycle:
This feature set includes the addition of new sama7d65 SoC and a new
board named sama7d65-curiosity.
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Signed-off-by: Andrew Davis <afd@ti.com>
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I updated the mailmap a while back but it's nice to have authorship
comments adjusted too.
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Add the basic Kconfig options, addresses and other values for the
existing Kconfig settings for the new Allwinner A523/T527/H728 SoC.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Add reverse engineered code to add support for DDR3 DRAM chips on the
Allwinner A523 DRAM controller.
The timings are copying what boot0 set up on the X96QPro+ TV box, though
they seem quite suboptimal, with longer latencies that would be required
for DDR3-1600. The chips are also actually capable of DDR3-1833, so
there is room for future improvement.
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
[Andre: rework to copy from H616 DDR3 driver, calculate timings]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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DRAM init code, as per reverse engineering and matching against
previous SoCs. As usual no real documentation, and the DRAM controller
is the usual mixture of close-to-previous IP and new inventions.
This version supports LPDDR4 for now only, as seen on the early boards.
This needs improvements, but it can be done later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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This adds the early A523 clock setup code, for the basic peripheral PLL
and the basic bus clocks (APB/AHB). This is quite close to the existing
H6 and H616 clock code, so this shares the same file. A few bits and bobs
are different, though, so filter for the A523 in a few occasions.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The cpu_sunxi_ncat2.h header file contains addresses of some peripherals
that are needed for the SPL, for chips that belong to the "NCAT2"
generation.
The Allwinner A523 is a member of this group, but a few addresses
differ, and we need a few more addresses, for playing with the core
reset, for instance.
Add the new addresses needed for the A523 and guard existing definitions
that conflict with that new chip.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The watchdog in the Allwinner A523 SoC differs a bit from the one in the
previous SoCs: it lives in a separate register frame, so no longer
inside some timer device, and it manages to shuffle around some
registers a bit. But it also conveniently adds a direct reset
functionality, so we don't need to use a dummy timeout period.
Avoid introducing a new MMIO register frame C struct, but just define
the one needed register offset as a macro. Then just trigger this new
direct reset functionality in the A523 specific reset_cpu()
implementation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner A523 features 8 CPU cores, organised in two clusters, both
driven by separate PLLs. Also there is the DSU PLL, which clocks the
hardware that connects the cores to the rest of the system.
And while the PLL registers itself are very similar, they are located in
a separate register frame, outside the main CCU, and also the register
controlling the CPU clock source (mux) is different.
Provide a separate function that reparents the two clusters and the DSU,
while their PLLs are programmed. For the actual PLL programming, we rely
on the existing shared routine.
The selection between the new A523 routine and the existing code is made
with C if statements, but since the choice is effectively made at compile
time already, the compiler optimises away the other code paths, leaving
just the one required function in.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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When we program the CPU PLL, we need to switch the CPU clock source away
from the PLL temporarily, then switch it back, once the PLL has
stabilised.
The CPU CLK register will be different on the A523, so move the current
code into a separate function, to allow using a different version of
that later for the A523.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The SPL initial clock setup code for the Allwinner H6 and H616 SoCs uses
a simple CPU PLL setup routine, which programs all register bits at once,
then waits for the LOCK bit to clear.
The manual suggests to follow a certain procedure for bringing up any
PLLs, which involves several register writes, one at a time, and some
delays. Also the H616 and the new A523 require some tiny changes in this
sequence, and the different SoCs also feature some extra bits here and
there, which we should not just clear.
So factor out the PLL setup routine, and make it follow the manual's
suggestion. This will read the PLL register at the beginning, then tweak
the bits we need to manipulate, and writes the register several times on
the way. This allows to cover the specific bits for different SoCs.
Besides improving the reliability of the PLL setup, this helps with the
A523, which requires *three* CPU PLLs to be programmed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The Allwinner PLLs share most of their control bits, they differ mostly
in the factors and dividers.
Drop the PLL specific definition of those common bits, and use one
shared macro, for all PLLs.
This requires changing the users in the SPL clock and DRAM code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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The generic name 'EFI' would be more useful for common EFI features. At
present it just refers to the EFI app and stub, which is confusing.
Rename it to EFI_CLIENT
Signed-off-by: Simon Glass <sjg@chromium.org>
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Add board specific functions for sama7d65_curiosity.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
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Add u-boot device tree and tweaks for sama7d65-curiosity board on top of
the upstream DTS files in dts/upstream.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
[varshini.rajendran@microchip.com: align with Linux DT and add tweaks]
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
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Add support for new SoC sama7d65.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27149
- Add support for the NXP imx93 frdm board.
- imx93_evk and phycore-imx93 cleanups.
- Convert imx6dl-sielaff to OF_UPSTREAM and fix serial download mode boot.
- Fix crash in imx power-domain.
- Migrate Phytec imx8mm boards to standard boot.
- Fix smatch warnings.
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Neha Malcom Francis <n-francis@ti.com> says:
This series implements a driver for the BIST (Built-In Self Test) module
for K3 devices. The BIST driver must ideally support triggering of BIST
tests, both PBIST (Memory BIST) and LBIST (Logic BIST) on a core. Both
tests are destructive in nature. Please see links [1] and [2] for
further information regarding the two.
At boot up, BIST is executed by hardware for the MCU domain
automatically as part of HW POST. So BIST has been checked only for the
MCU domain when U-Boot comes up in the usual U-Boot to Linux boot flow.
To facilitate the use-case where some safe firmware is intended to be
run on a safe core, it is best to have triggered the BIST tests on that
core. As an example, we take triggering the BIST tests on the MAIN R52_x
cores. The triggering patch is kept as DONOTMERGE.
The general procedure for triggering BIST on a core is:
1. Power on the core under test following a sequence
2. Trigger the BIST test
3. Reset the core under test following a sequence
BIST tests are triggered from A72 SPL where the DM (Device Manager
firmware that handles power management) is already up and can perform
these power sequences for us.
Boot logs (with LOG_DEBUG and CONFIG_K3_BIST enabled) and DT node kept (already
merged to ti-k3-dts-next [3]):
https://gist.github.com/nehamalcom/3fed504d038b54e3e05ba3874d73d603
[1] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/pbist.html#introduction
[2] https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/sdl/sdl_docs/userguide/j721e/modules/lbist.html#introduction
[3] https://lore.kernel.org/all/175205725858.918402.3771835070085533874.b4-ty@ti.com/
Link: https://lore.kernel.org/r/20250716062156.2564297-1-n-francis@ti.com
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The load address for the R5's SPL is defined in Kconfig by
SPL_TEXT_BASE. Rather than hard coding the load address which could
lead to hard to debug issues if this value is changed, just use the
SPL_TEXT_BASE value.
Reviewed-by: Andrew Davis <afd@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
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The uart11 reg address was a copy of the value for uart10.
Update it to the correct value.
Signed-off-by: Rebecca Cran <rebecca@os.amperecomputing.com>
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Trigger all tests of PBIST and LBIST using appropriate calls to set the
core under test (MAIN R5 2_0) to it's required state.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
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Add the initial board support for the NXP i.MX93 FRDM board:
https://www.nxp.com/design/design-center/development-boards-and-designs/frdm-i-mx-93-development-board:FRDM-IMX93
Based on the NXP U-Boot code.
There were attempts to upstream the board devicetree, but it has not been
accepted upstream yet:
https://lore.kernel.org/linux-arm-kernel/20250526-fpg-nxp-imx93-frdm-v2-2-e5ad0efaec33@pengutronix.de/
Once it reaches upstream, we can switch to OF_UPSTREAM.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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Switch to OF_UPSTREAM to make use of the upstream devicetree.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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There is a value to generate fit-dtb.blob even for cases without SPL
because flows with FSBL also require it.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2952da3c064d67821cd166d2392db39c1d23b2c.1752822270.git.michal.simek@amd.com
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Aristo Chen <jj251510319013@gmail.com> says:
This patch series introduces a validation step in `mkimage` to ensure that
the `default` property under the `/configurations` node in a FIT image
references a valid subnode. If the referenced node does not exist, mkimage
now prints an error and fails early. This helps prevent runtime failures
when U-Boot attempts to boot using an undefined configuration.
The first patch implements the validation logic in `fit_image.c`. The second
patch fixes an invalid default configuration reference exposed by this new
check in the `k3-am65-iot2050-boot-image.dtsi`. The final patch adds a test
case to verify that mkimage correctly fails when an invalid default
configuration is present in the ITS file.
This series improves the robustness of FIT image generation and helps
catch malformed image trees during build time.
Link: https://lore.kernel.org/r/20250715130317.3886-1-aristo.chen@canonical.com
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mkimage introduced a validation step to ensure that the 'default'
property under the /configurations node in a FIT image refers to a
valid subnode. This exposed an issue in the
k3-am65-iot2050-boot-image.dtsi, where the 'default' property was set to
"ti/k3-am6528-iot2050-basic" and "ti/k3-am6528-iot2050-basic-pg2", which
do not correspond to actual configuration node names.
This patch updates both /configurations nodes to reference the correct
subnode.
Without this fix, mkimage will fail with an error:
"ERROR: Default configuration 'ti/k3-am6528-iot2050-basic' not found
under /configurations"
An upcoming commit will validate the if the default configuration exists
Signed-off-by: Aristo Chen <aristo.chen@canonical.com>
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We are now using the DM code for the i2c mux and to read out the
inventory eeprom. Therefore we need to add the nodes to the specific DTS
files.
Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
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KASLR, or Kernel Address Space Layout Randomization, is a security
feature in the Linux kernel that randomizes the memory location
where the kernel is loaded during boot.
OP-TEE RNG is a Random Number Generator (RNG) component within the
Open Portable Trusted Execution Environment (OP-TEE) which provides
a random number to U-BOOT and U-BOOT provides this random number
as seed value to the LINUX kernel for KASLR.
Add KASLR OPTEE RNG support across K3 devices by enabling the required
configs.
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
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In order to compile more drivers, add an empty sync() function.
Signed-off-by: Tom Rini <trini@konsulko.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-imx
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27088
- Add support for the i.MX95 B0 version.
- Enable standard boot for phycore-imx8mp.
- Kconfig fixes for i.MX MMC and FSL_SEC_MON.
- Support 4Gb single die variant of the i.MX8MM Venice board.
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