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path: root/drivers/clk/imx/clk-imx8mp.c
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2025-04-10clk: imx8mp: Add media related clocksMiquel Raynal
These are all the clocks needed to get an LCD panel working, going through one of the LCDIF and the LDB. The media AXI and APB clocks are also described. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-03-24clk: imx: Pass struct udevice into imx_clk_fixed_factor*()Marek Vasut
Pass struct udevice * into imx_clk_fixed_factor*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <marex@denx.de>
2025-03-24clk: imx: Pass struct udevice into imx_clk_divider*()Marek Vasut
Pass struct udevice * into imx_clk_divider*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <marex@denx.de>
2025-03-24clk: imx: Convert clock-osc-* back to osc_*Marek Vasut
Convert clock-osc-24m back to osc_24m and clock-osc-32k back to osc_32k. These are the clock which match clock tables in Linux. This is now possible because the clock drivers now resolve clock names based on clock-names DT property in the CCM DT node. Signed-off-by: Marek Vasut <marex@denx.de>
2025-03-24clk: imx: Pass struct udevice into imx_clk_composite*()Marek Vasut
Pass struct udevice * into imx_clk_composite*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <marex@denx.de>
2025-03-24clk: imx: Pass struct udevice into imx_clk_gate*()Marek Vasut
Pass struct udevice * into imx_clk_gate*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <marex@denx.de>
2025-03-24clk: imx: Pass struct udevice into imx_clk_mux*()Marek Vasut
Pass struct udevice * into imx_clk_mux*() functions, so the clock core would have access to parent struct udevice *. Signed-off-by: Marek Vasut <marex@denx.de>
2024-10-13clk: imx8mp: Add i.MX8MP Dummy clkPeng Fan
i.MX8MP SDHC use CLK_IMX8MP_DUMMY clk entry. Without the clk, the bulk api will return failure. The correct entry should be replaced with IMX8MP_IPG_ROOT clk in device tree. This will be done in Kernel device tree and sync to U-Boot in future: https://lore.kernel.org/all/20241012025221.1728438-1-peng.fan@oss.nxp.com/ Fixes: 76332fae769 ("mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk API") Reported-by: Gilles Talis <gilles.talis@nxp.com> Tested-by: Gilles TALIS <gilles.talis@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-08-02clk: imx8m: register ARM A53 core clockHou Zhiqiang
Register ARM A53 core clock for i.MX 8M Mini, Nano and Plus, preparing for enabling the 'cpu' command, which depends on this to print CPU core frequency. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2024-07-22clk: imx8mp: Make parent names arrays const pointersMichael Trimarchi
The arrays containing the mux selectors need to be of const pointer to const char. Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07clk: Remove <common.h> and add needed includesTom Rini
Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-24clk: imx8mp: Add support for PCIe clocksSumit Garg
Add support for PCIe clocks required to enable PCIe support on iMX8MP SoC. Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-07-13clk: imx8mp: Update clocks based on kernel 6.4-RC4Adam Ford
There are some newer clocks added to the kernel recently, so to fix prepare for resycing the device trees, update the clock list. Since there are some minor changes to the USB clocks, update which USB clocks are enabled to match with the upstream kernel as well. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
2023-03-30clk: imx8mp: add pwm clocks supportTommaso Merciai
Add clocks support for the PWM controllers. This is ported from Linux v6.3.0-rc1 Signed-off-by: Tommaso Merciai <tomm.merciai@gmail.com>
2023-03-30clk: imx8mp: Add EQoS MAC clockMarek Vasut
Add clock for the DWMAC EQoS block. This is used among other things to configure the MII clock via DM CLK. Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de>
2022-06-14clk: imx8mp: use usb_core_ref for usb_root_clkAndrey Zhizhikin
Upstream commit 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") added usb_core_ref for USB Controller but never set it to be used as a clock source, using rather "osc_32k" instead. This produces following boot log message: "clk_register: failed to get osc_32k device (parent of usb_root_clk)" Fix the USB controller clock source by using usb_core_ref instead of osc_32k. Fixes: 7a2c3be95a50 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-14clk: imx8mp: fix root clock names for ecspiAndrey Zhizhikin
Root clock name contained underscore, which does not match to the actual clock name. Correct the name to match what is present in the FDT. Fixes: 87f958810fcb ("clk: imx8mp: Add ECSPI clocks") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-04-13clk: imx8mp: Fix 24M and 32k clockMarek Vasut
Fix registration of 24M and 32k clock, those got applied or rebased incorrectly, so fill in the correct code. Fixes: 7a2c3be95a5 ("clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clock") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com>
2022-04-12clk: imx8mp: Add ECSPI clocksElmar Albert
Add clock tables required for bing up ECSPI interfaces Signed-off-by: Elmar Albert <ealbert@data-modul.com> Cc: Fabio Estevam <festevam@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: uboot-imx <uboot-imx@nxp.com> Signed-off-by: Elmar Albert <ealbert@data-modul.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-04-12clk: imx8mp: Fill in DWC3 USB, USB PHY, HSIOMIX clockMarek Vasut
Add clock tables required to bring up DWC3 USB, USB PHY and HSIOMIX domain. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
2022-04-12clk: imx8m: reduce rate table duplicationAngus Ainslie
Re-factor the imx8m[nmpq] rate tables into the common pll1416x clock driver. 43cdaa1567ad3 ("clk: imx8mm: Move 1443X/1416X PLL clock structure to common place") Signed-off-by: Angus Ainslie <angus@akkea.ca> Tested-by: Adam Ford <aford173@gmail.com> #imx8mm-beacon
2022-03-30clk: Use generic CCF ops where possibleSean Anderson
This converts most CCF drivers to use generic ops. imx6q is the only outlier, where we retain the existing functionality by moving the check to request(). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com [ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-07-14clk: imx8mp: Update imx8mp ccf clock driverYe Li
Add clocks for FEC and flexspi, and add set parent clock callback, so DTS can assign clocks Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-01dm: Fix error handling for dev_read_addr_ptrSean Anderson
dev_read_addr_ptr had different semantics depending on whether OF_LIVE was enabled. This patch converts both implementations to return NULL on error, and converts all call sites which check for FDT_ADDR_T_NONE to check for NULL instead. This patch also removes the call to map_physmem, since we have dev_remap_addr* for those semantics. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop log.h from common headerSimon Glass
Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-08clk: imx: add i.MX8MP clk driverPeng Fan
Add i.MX8MP clk driver for i.MX8MP CLK driver model usage Signed-off-by: Peng Fan <peng.fan@nxp.com>