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Add GCC_AHB2PHY_WEST_CLK gate clock definition to the QCS615
clock driver. This clock is required for proper PHY operation
and eliminates clock-related warnings during USB initialization.
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-2-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Add support for GCC_USB3_PRIM_CLKREF_CLK to the QCS615 clock driver.
This clock is referenced in the device tree USB node but was not
implemented in U-Boot, causing "Clock 152 not found" warnings during
fastboot run.
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20260213-talos_usb-v1-1-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Correct USB30 primary clock RCG configuration and add missing
USB3_PRIM_PHY_AUX_CMD_RCGR RCG configuration.
Above taken from Linux commit 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Add missing USB3_PRIM_PHY_PIPE_CLK gate clock definition.
Extend reset map with USB-related BCR entries and video BCR
for comprehensive reset control support.
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260113065856.3287772-1-balaji.selvanathan@oss.qualcomm.com
[casey: indentation fix]
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Add clock gate definitions and entries for QUP (Qualcomm Universal
Peripheral) serial engine clocks across all four wrappers on SA8775P.
This enables proper clock management for I2C, SPI, and UART
peripherals connected to the QUP blocks.
This resolves the "unknown clock ID 133" error for UART10 and
provides complete QUP clock infrastructure for the platform.
Signed-off-by: Swathi Tamilselvan <swathi.tamilselvan@oss.qualcomm.com>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260113042213.3107106-1-balaji.selvanathan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Add more clocks for UART2, i2c9 and a few others. This is enough to get
the rubikpi 3 working.
Link: https://patch.msgid.link/20260108195007.3156604-1-casey.connolly@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Add support for configuring the SDCC1 apps clock on QCM2290 by introducing
a frequency table and enabling dynamic rate setting. Previously, the clock
was assumed to be fixed at 384 MHz by firmware, which limited flexibility
and correctness when selecting optimal rates for SD/MMC operations.
Suggested-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://patch.msgid.link/20251210155454.1561611-2-loic.poulain@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Allow us to power up UART7 so we can load the QUP firmware, this is used
for bluetooth on RB3 Gen 2 and possibly other boards.
Additionally add the UART5 clocks so we can adjust baud rate for UART
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://patch.msgid.link/20250714-geni-load-fw-v5-5-5abbc0d29838@linaro.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
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Add a clock driver for the SM7150 SoC. This driver can enable necessary
clocks for UART, UFS, USB, and MMC.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Co-developed-by: Jens Reidel <adrian@mainlining.org>
Signed-off-by: Jens Reidel <adrian@mainlining.org>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250831004602.699953-2-adrian@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
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Add Clock driver for the GCC block found in the SM6350 SoC.
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
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Clean up some defines which are not used in the driver.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250924-2025-10-misc-v1-2-7e75842ca714@fairphone.com
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
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The global clock controller on SDM670 is similar to SDM845, so let's add
support here.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: David Wronek <david.wronek@mainlining.org>
Link: https://lore.kernel.org/r/20251003-sdm670-v2-2-52c0fa481286@mainlining.org
Signed-off-by: Casey Connolly <kcxt@postmarketos.org>
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Commit [0] introduced, correctly, the bubble of qcom clock errors to
make it easy to spot missing clocks in the platforms, and this is a case
of that, add the GCC_CFG_NOC_USB3_PRIM_AXI_CLK clock to sm8650 clock
pool.
0: 7c5460afec3f ("clk/qcom: bubble up qcom_gate_clk_en() errors")
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250618093253.225929-1-rui.silva@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Update the variable name to sm8250_gcc_data as it's in the sm8250
driver.
Fixes: dcd688229cb ("clk/qcom: add driver for sm8250 GCC")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250611-qcom-clk-variable-names-v1-2-37615b74daad@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Update the variable name to sc7280_gcc_data as it's in the sc7280
driver.
Fixes: f50e7be6bb1 ("clk/qcom: add initial clock driver for sc7280")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250611-qcom-clk-variable-names-v1-1-37615b74daad@fairphone.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Port Linux's gcc-qcs615.c driver to U-Boot for basic bring-up.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250521035324.1182833-4-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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* Port Linux's gcc-qcs8300.c driver to U-Boot for basic bring-up.
* Enable QCS8300 clocks in qcom_defconfig.
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-4-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Add initial set of clocks and resets for enabling U-Boot on ipq5424
based RDP platforms.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250304110105.2762124-5-quic_varada@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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As of commit dc8754e8e408 ("clk/qcom: apq8016: improve clk_enable logging")
there are now warnings in the U-Boot console on DragonBoard 410c:
apq8016_clk_enable: unknown clk id 122
apq8016_clk_enable: unknown clk id 123
apq8016_clk_enable: unknown clk id 124
apq8016_clk_enable: unknown clk id 125
This is because we don't implement enable() properly for the SDCC clocks.
Currently they are being enabled as part of set_rate().
Fix this by moving the enable calls out of the apq8016_clk_init_sdc()
function and convert them to the equivalent GATE_CLK_POLLED() definitions.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-6-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Convert the usages of GATE_CLK() in clock-apq8016 to GATE_CLK_POLLED() to
make sure that we poll the status when enabling clocks:
- PRNG_AHB_CLK is a vote clock, so we poll a different register address.
- The USB clocks are simple branches, so enable/poll is the same register.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-5-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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GATE_CLK() in its current state is unsafe: A simple write to the clock
enable register does not guarantee that the clock is immediately running.
Without polling the clock status, we may issue writes to registers before
the necessary clocks start running. This doesn't seem to cause issues in
U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A
for the SMMU clocks on DB410c reliably triggers an exception during boot.
Make it possible to poll the branch clock status register, by adding a new
GATE_CLK_POLLED() macro that takes the extra register address. Existing
usages work just as before, without polling the clock status. Ideally all
usages should be updated to specify the correct poll address in the future.
The Qualcomm naming for these clocks is "branch" and not "gate", but let's
keep the existing naming for now to avoid confusion until all others
drivers have been converted.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-4-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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This avoids having to inline it separately into every single clock driver,
when U-Boot is built with support for multiple SoCs.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses:
- SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018
Should be 0x42018, this is an invalid register close to the USB clocks.
- SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018
Should be 0x43018, this is the SDCC1 clock.
When we try to enable SDCC2, we actually end up enabling SDCC1. When we try
to enable SDCC1, we just issue some broken register writes.
This hasn't caused any trouble so far, because the boot firmware is keeping
both SDCC clocks running. However, if these clocks are disabled when
entering U-Boot, MMC initialization is failing.
Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was
already correct, but change it the same way for consistency.
Fixes: 085921368b7d ("arm: Add support for Qualcomm Snapdragon family")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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The device name is always clk_qcom... Not very useful.
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Tested-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Select the right clock for sdhci.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250407175617.3494506-3-jorge.ramirez@oss.qualcomm.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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The function should return a valid rate.
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by:
Link: https://lore.kernel.org/r/20250407175617.3494506-2-jorge.ramirez@oss.qualcomm.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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These are all usually enabled, hence we don't (yet) bother configuring
their RCG src clocks.
Add them to remove the errors about missing clocks when the UFS and MMC
drivers probe.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250317-sc7280-mmc-ufs-clocks-v1-2-38e05c16511b@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Missing for UFS.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250324-sdm845-fixes-fastboot-v1-2-d177a10f336d@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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These are necessary for USB gadget to come up properly, now that
qcom_gate_clk_en fails on unknown clocks.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250319-sdm845-usb-clocks-v1-1-ddea854f62ec@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add support for a bunch of new clocks, including PCIe, GENI (for all
peripherals used on the RB3 Gen 2), and some missing USB clocks.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-3-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Dump a few PCIe and USB clocks
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-2-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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If we try to enable a gate clock that doesn't exist, we used to just
fail silently. This may make sense for early bringup of some core
peripherals that we know are already enabled, but it only makes
debugging missing clocks more difficult.
Bubble up errors now that qcom_gate_clk_en() can return an error code to
catch any still-missing clocks and make it easier to find missing ones
as more complicated peripherals are enabled.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-1-ead54487c38e@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Properly warn when an unknown clock is enabled.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-4-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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This clock needs to be enabled for the msm-rng driver to work on
MSM8916, otherwise accessing the PRNG register block causes a data
abort.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-2-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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This reads a little bit nicer (IMO), and is consistent with the kernel.
Signed-off-by: Sam Day <me@samcday.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250212-msm-rng-fixes-v2-1-645cf8d3fd3c@samcday.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add initial set of clocks and resets for enabling U-Boot on ipq9574
based RDP platforms.
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250226064505.1178054-4-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add the PCIe clocks for the x1e80100 GCC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-4-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add the PCIe clocks for the SM8650 GCC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-3-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add the PCIe clocks for the SM8550 GCC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-2-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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The PCIe PIPE clock requires a special setup function to
mux & enable the clock from the PCIe PHY before the PHY
has enabled the clock.
Import the clk_phy_mux_enable() from the Linux driver to
use the same implementation regarding the PIPE clock.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-clk-v1-1-4315d1e4e164@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add Clock driver for the GCC block found in the X1E80100 SoC.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # Yoga Slim 7x
Link: https://lore.kernel.org/r/20241118-topic-x1e80100-clk-v1-1-8841e87ad81f@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add initial set of clocks and resets for enabling U-Boot on QCS9100
based Ride platforms.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250110050817.3819282-4-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Drop in the RCG and GPLL data for debugging these clocks.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add "clk dump" support for SM6115.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add debug data to dump PLL and RCG clocks.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add support for dumping a few of the clocks used on Qualcomm platforms.
Naming the Global PLL's, Root Clock Generators, and gate clocks.
This helps a lot with platform bringup and feature enablement by making
it easy to sanity check that the clocks are programmed correctly.
== Usage ==
Enable CONFIG_CMD_CLK and "#define LOG_DEBUG" at the top of
qcom-<soc>.c.
The "clk dump" command should print the states of all the gates, GPLLs
and RCGs for your SoC.
== Glossary ==
RCG: Root Clock Generator
* Takes in some fairly arbitrary high freq clock (configurable clock
source and options for taking just even pulses and other things)
* Output frequency = input_freq * (m/n) * (1/d) where m/n are arbitrary
8 or 16-bit values (depending on the RCG), and d is a number (with
support for .5 offsets).
GPLL: Global Phase Locked Loop
* Crystal as input
* integer multiplier + exponent part (2^-40)
Gate: Simple on/off clock
* Put between RCGs and the peripherals they power
* Required to allow for correct power sequencing
If you do the maths manually using the equations from "clk dump", the
numbers should roughly line up by they're likely to be out by a handful
of MHz. They output is formatted so that it can be pasted directly into
the python interpreter.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add clock, reset and power domain driver for SM8150. Driver code is
based on the similar U-Boot drivers. All constants are taken from the
corresponding Linux driver.
This driver supports clock rate setting only debug UART,
RGMII/Ethernet modules and USB controller.
Co-authored-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Julius Lehmann <lehmanju@devpi.de>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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We don't actually need any clocks to get UFS up and running, resets are
useful though.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.
This syncs the driver with Linux.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
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ESS clock is the Ethernet Subsystem clock, so lets add it as its
already configured by SBL1.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
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