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2025-06-14drivers: use lowercase hex prefix styleE Shattow
Use consistent lowercase hex prefix style in drivers/* Does not change hex prefix case in allcaps uppercase style error messages Signed-off-by: E Shattow <e@freeshell.de>
2025-04-22ddr: altera: iossm: Enhance debug information for ECC errorsTingting Meng
ECC debug information was enhanced to improve the readability of error messages. Signed-off-by: Tingting Meng <tingting.meng@altera.com>
2025-04-22ddr: altera: agilex5: LPDDRs in-line ECC supportTingting Meng
In-line ECC support was added for LPDDR by reserving the last one-eighth of the memory space for ECC data. Full memory initialization using the BIST MEM INIT mailbox command, based on address and size, is required to correctly generate ECC data and enable proper ECC logic verification. Signed-off-by: Tingting Meng <tingting.meng@altera.com>
2025-04-22drivers: ddr: altera: Fix integer overflow during size calculationNaresh Kumar Ravulapalli
Data structure, dramaddrw, is defined as u32. Compiler performs 32-bit arithmetic and logic operations on this data structure. Fix is provided to avoid integer overflow while performing shifting operations greater than 32-bit. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-04-11Kbuild: Always use $(PHASE_)Tom Rini
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our Makefiles as part of the macros to determine when to do something in our Makefiles based on what phase of the build we are in. For consistency, bring this down to a single macro and use "$(PHASE_)" only. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-02-25ddr: altera: Add DDR driver for Agilex5 seriesTingting Meng
Adding DDR driver support for Agilex5 series. Signed-off-by: Tingting Meng <tingting.meng@altera.com>
2024-12-23imx: Use per board ddrphy_trained_csrPeng Fan
Drop global ddrphy_trained_csr which maybe different with per board ddrphy_trained_csr. DDR TOOL generates ddrphy_trained_csr for each board, using the global ddrphy_trained_csr has risk that values may be not up to date. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-12-07ddr: imx: Add new rates for i.MX91Ye Li
iMX91 reuses iMX93 controller and PHY, but with lower speed, so add new DDR rates for i.MX91. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-10-25imx: Support i.MX93 9X9 QSB boardPeng Fan
Add i.MX93 9x9 Quick Start Board support. - Two ddr scripts included w/o inline ecc feature. - SDHC/NETWORK/I2C/UART supported - PCA9450 supported, default over drive mode - Documentation added. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-10-23ddr: altera: include u-boot/schedule.hRasmus Villemoes
These TUs currently rely on getting a declaration of schedule() through some nested include. Include the proper header directly. Signed-off-by: Rasmus Villemoes <ravi@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
2024-10-11global: Rename SPL_ to XPL_Simon Glass
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is no-longer set. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11drivers: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
2024-09-19imx9: Add 233Mhz DDR PLL frequencyYe Li
To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq to DDR PLL for second mission point at 933MTS. Otherwise DDR training will fail. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-08-13fsl: mxc: Drop legacy I2cSimon Glass
Drop some old code from the mxc_i2c and ddr/fsl drivers. This will allow removal of very old common I2C code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2024-07-22drivers: ddr: Remove duplicate newlinesMarek Vasut
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-07-08arm: mvebu: a38x: Add optional support for using old DDR3 training codeMarek Behún
Add optional support for using old DDR3 training code from 2017. The code lives in drivers/ddr/marvell/a38x/old/. To prevent symbol clashing with new DDR3 training code, a special header which renames all clashing symbols via macros is included and the symbols are prefixed with 'old_'. If old DDR3 training support is selected for a board, then the SPL initialization code calls a new function board_use_old_ddr3_training() to check whether it should use old DDR3 training code. The default weak implementation returns false, defaulting to new DDR3 training code. Boards that wish to support this need to select the ARMADA_38X_SUPPORT_OLD_DDR3_TRAINING config option and implement the old version of DDR topology provider, ddr3_get_topology_map(). Signed-off-by: Marek Behún <kabel@kernel.org>
2024-07-08ddr: marvell: a38x: old: Backport immutable debug settingsMarek Behún
Backport the option to compile with immutable debug settings also to the old implementation of the DDR3 training code. The original PR for mv-ddr-marvell can be seen at https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/45/ Signed-off-by: Marek Behún <kabel@kernel.org>
2024-07-08ddr: marvell: a38x: old: Fix some compiler warning of the old codeMarek Behún
Fix some compilation warning in the old DDR training code. Signed-off-by: Marek Behún <kabel@kernel.org>
2024-07-08ddr: marvell: a38x: Import old DDR training code from 2017 version of U-BootMarek Behún
Import DDR training code from commit 1b69ce2fc0ec ("arm: mvebu: ddr3_debug: remove self assignments") into drivers/ddr/marvell/a38x/old/. The code is not used yet. Explanation: Since 2019, on some Turris Omnia boards we have been having problems with newer versions of Marvell's DDR3 training code for Armada 38x, which is ported from mv-ddr-marvell [1] to U-Boot into the drivers/ddr/marvell/a38x/ directory: - sometimes the DDR3 training fails on some older boards, sometime it fails on some newer boards - other times it succeeds, but some boards experience crashes of the operating system after running for some time. Using the stock version of Turris Omnia's U-Boot from solved these issues, but this solution was not satisfactory, since we wanted features from new U-Boot. Back in 2020-2022 we have spent several months trying to debug the issues, working with Marvell, on our own, and also with U-Boot community, but these issues persist still. One solution we used back in 2019 was a "hybrid U-Boot": the SPL part (containing the DDR3 training code) was taken from the stock version, while the proper part was current U-Boot at the time. This solution also has its drawbacks, of which the main one is the need to glue binaries from two separate builds. Since then there have been some more changes to the DDR3 training code in upstream mv-ddr-marvell that have been ported to U-Boot. We have provided our users experimental builds of U-Boot in the TurrisOS so that they could try upgrading the firmware and let us know if those problems still exist. And they do. We do not have the time nor manpower to debug this problem and fix it properly. Marvell was also no able to provide a solution to this, probably because they do not have the manpower as well. I have therefore come up with this "not that pretty" solution: take the DDR3 training code from an older version of U-Boot that is known to work, put it into current U-Boot under old/ subdirectory within drivers/ddr/marvell/a38x/, build into the SPL binary both the old and new versions and make it possible to select the old version via an env variable. [1] https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell Signed-off-by: Marek Behún <kabel@kernel.org>
2024-07-08ddr: marvell: a38x: debug: Allow compiling with immutable debug settings to ↵Marek Behún
reduce binary size Allow compiling with immutable debug settings: - DEBUG_LEVEL is always set to DEBUG_LEVEL_ERROR - register dumps are disabled This can save around 10 KiB of space in the resulting binary, which is a lot in U-Boot SPL. Signed-off-by: Marek Behún <kabel@kernel.org>
2024-07-08ddr: marvell: a38x: debug: Define DDR_VIEWER_TOOL variables only if needed, ↵Marek Behún
and make them static The variables is_validate_window_per_if, is_validate_window_per_pup, sweep_cnt and is_run_leveling_sweep_tests are only used if DDR_VIEWER_TOOL macro is defined, so define them only in that case. Make them static since they are only used in ddr3_debug.c. Signed-off-by: Marek Behún <kabel@kernel.org>
2024-07-08ddr: marvell: a38x: debug: Remove unused variablesMarek Behún
The variables is_default_centralization, is_tune_result and is_bist_reset_bit are never used. Signed-off-by: Marek Behún <kabel@kernel.org>
2024-07-08ddr: marvell: a38x: debug: return from ddr3_tip_print_log() early if we ↵Marek Behún
won't print anything Return from ddr3_tip_print_log() early if we won't print anything anyway. This way the compiler can optimize away the VALIDATE_IF_ACTIVE() calls in the for-loop, so if the SILENT_LIB macro is defined, no code is generated for the rest of the function, which saves some space. Signed-off-by: Marek Behún <kabel@kernel.org>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07ddr: Remove <common.h> and add needed includesTom Rini
Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-22Kconfig: Remove trailing whitespace in its promptMichal Simek
All errors are generated by ./tools/qconfig.py -b -j8 -i whatever. Error look like this: warning: SPL_CLK_CCF (defined at drivers/clk/Kconfig:59) has leading or trailing whitespace in its prompt Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-12-21global: Drop common.h inclusionTom Rini
In order to make it easier to move on to dropping common.h from code directly, remove common.h inclusion from the rest of the header file which had been including it. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-21arm: Partial cleanup and audit usage of <config.h>Tom Rini
We need to include <config.h> directly when a file needs to have something such as CFG_SYS_SDRAM_SIZE referenced as this file is not automatically globally included and is most commonly indirectly included via common.h. Remove most cases of arm including config.h directly, but add it where needed. This includes a few board-specific fixes. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-12-18Merge tag 'v2024.01-rc5' into nextTom Rini
Prepare v2024.01-rc5
2023-12-14ddr: imx: Add 3600 MTps rate supportMarek Vasut
Add PLL settings for DDR 3600 MTps . This is very similar to 3200 MTps PLL setting, except the divider is not 9 but 8 . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-14ddr: imx: Handle 3734 in addition to 3733 and 3732 MTps ratesMarek Vasut
The new MX8M DDR tool 3.31 now generates a programming file which uses data rate 3734 instead of 3733 or 3732 . Handle another rounding option . Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2023-12-13ddr: imx: Save the FW loading if it hasn't changedShawn Guo
Function ddr_load_train_firmware() is called 4 times in a loop by ddr_cfg_phy(). The first 3 calls are all '1D' type and just loading the same FWs. Let's add a type check and save 2 of them. This helps to reduce DDRPHY training time from 269 ms down to 212 ms, and thus speed up boot time ~ 50 ms. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-08-09treewide: unify the linker symbol reference formatShiji Yang
Now all linker symbols are declared as type char[]. Though we can reference the address via both the array name 'var' and its address '&var'. It's better to unify them to avoid confusing developers. This patch converts all '&var' linker symbol refrences to the most commonly used format 'var'. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2023-05-21ddr: imx9: update the rank setting for multi fsp supportJacky Bai
The rank setting flow should be updated to support multi fsp config. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: update the ddr init to support mult setpointsJacky Bai
Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: Add 625M bypass clock supportJacky Bai
Add 625M bypass clock that may be used DRAM 625M bypass mode support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Change the saved ddr data base to 0x2051c000Jacky Bai
change the ddr saved info to the last 16KB of the OCRAM. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2023-05-06drivers: use devfdt_get_addr_index_ptr when cast to pointerJohan Jonker
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_index_ptr instead of the devfdt_get_addr_index function in the various files in the drivers directory that cast to a pointer. As we are there also streamline the error response to -EINVAL on return. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2023-04-13ddr: marvell: a38x: Perform DDR training sequence again for 2nd bootTony Dinh
- DDR Training sequence happens very fast. The speedup in boot time is negligible by skipping the training sequence during 2nd boot or after. So remove the check and skip. - This change improves the robustness of DDR training. If u-boot crashed during DDR training, the training could be left in a limbo state, where the BootROM has recorded that it is already in a 2nd boot. The training must be repeated in this scenario to get out of this limbo state, but due to the check it cannot be performed. Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
2023-03-29ddr: imx: Update the ddr init flow on imx8ulpJacky Bai
Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2023-03-29ddr: imx8ulp: Change DRAM timing save area to 0x20055000Ye Li
To align with ARM trusted firmware's change, adjust DRAM timing save area to new position 0x20055000. So we can release the space since 0x2006c000 for the NOBITS region of ARM trusted firmware Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2023-03-24ddr: marvell: a38x: Remove unused file seq_exec.hPali Rohár
DDR code does not use seq_exec.h, so remove it. Signed-off-by: Pali Rohár <pali@kernel.org>
2023-01-30ddr: imx: Handle both 3733 and 3732 MTps ratesMarek Vasut
The DDR calibration tool for i.MX8M currently produces 3732 MTps rate in lpddr4_timing.c , while the PHY code expects 3733 MTps rate. Support both variants to avoid surprises where the system fails to boot. Signed-off-by: Marek Vasut <marex@denx.de>
2023-01-26ddr: marvell: a38x: Add support for DDR4 from Marvell mv-ddr-marvell repositoryTony Dinh
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow" d5acc10c287e40cc2feeb28710b92e45c93c702c This patch was created by following steps: 1. Replace all a38x files in U-Boot tree by files from upstream github Marvell mv-ddr-marvell repository. 2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4: files=drivers/ddr/marvell/a38x/* unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \ -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \ -UCONFIG_64BIT $files 3. Manually change license to SPDX-License-Identifier (upstream license in upstream github repository contains long license texts and U-Boot is using just SPDX-License-Identifier. After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github repository and in U-Boot would be fully identical. So in future applying above steps could be used to sync code again. The only change in this patch are: 1. Some fixes with include files. 2. Some function return and basic type defines changes in mv_ddr_plat.c (to correct Marvell bug). 3. Remove of dead code in newly copied files (as a result of the filter script stripping out everything other than a38x, dd3, and ddr4). Reference: "ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository" https://source.denx.de/u-boot/u-boot/-/commit/107c3391b95bcc2ba09a876da4fa0c31b6c1e460 Signed-off-by: Tony Dinh <mibodhi@gmail.com> Reviewed-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2023-01-20global: Finish CONFIG -> CFG migrationTom Rini
At this point, the remaining places where we have a symbol that is defined as CONFIG_... are in fairly odd locations. While as much dead code has been removed as possible, some of these locations are simply less obvious at first. In other cases, this code is used, but was defined in such a way as to have been missed by earlier checks. Perform a rename of all such remaining symbols to be CFG_... rather than CONFIG_... Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-23global: Migrate CONFIG_MAX_MEM_MAPPED to CFGTom Rini
Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-23global: Remove undef CONFIG_... for unused valuesTom Rini
We have a number of places that undef CONFIG_... while we never reference CONFIG_... in the first place. Remove these lines. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22ddr: fsl: Remove CONFIG_MEM_INIT_VALUETom Rini
The way all of the memory init code here works is that we pass 0xDEADBEEF around for the initial value (as it's a well known 'poison' value and so easily recognized in debuggers, etc). The only point of this CONFIG symbol was to pass in a different value for that purpose. Drop this symbol and cleanup the code slightly. Signed-off-by: Tom Rini <trini@konsulko.com>
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