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Adding support for:
GD5F1GQ4RExxG
GD5F2GQ4UExxG
GD5F2GQ4RExxG
GD5F1GQ5RExxG
GD5F2GQ5UExxG
GD5F2GQ5RExxG
GD5F4GQ6UExxG
GD5F4GQ6RExxG
GD5F1GM7UExxG
GD5F1GM7RExxG
GD5F2GM7UExxG
GD5F2GM7RExxG
GD5F4GM8UExxG
GD5F4GM8RExxG
GD5F2GQ5xExxH
GD5F1GQ5RExxH
GD5F1GQ4RExxH
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
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6.15 + winbond"
Christian Marangi <ansuelsmth@gmail.com> says:
This small series sync linux/bitfield.h from Linux 6.15 and fix all
the compilation error due to a change in the header include.
The sync is needed to make it easier to support the winbond changes.
The changes are CI test with [1]
[1] https://github.com/u-boot/u-boot/pull/777
Link: https://lore.kernel.org/r/20250607211133.2005-1-ansuelsmth@gmail.com
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Add Winbond W25N04KV flash support that use a different value to detect
ECC bitflip.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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E Shattow <e@freeshell.de> says:
Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot.
There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix
or placeholder in documentation and error messages.
External devicetree-rebasing dts/upstream and the generated code of
xilinx/zynq are ignored for the series.
Link: https://lore.kernel.org/r/20250606224558.1117422-1-e@freeshell.de
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Use consistent lowercase hex prefix style in drivers/*
Does not change hex prefix case in allcaps uppercase style error messages
Signed-off-by: E Shattow <e@freeshell.de>
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Tom Rini <trini@konsulko.com> says:
Hey all,
Related to my other series I've posted recently on cleaning up some
headers, this series here is the result of at least lightly auditing the
#includes used in include/[a-m]*.h. This ignores subdirectories, as at
least in part I think the top-level includes we've constructed are the
most likely places to have some extra transitive include paths. I'm sure
there's exceptions and I'll likely audit deeper once this first pass is
done. This only gets as far as "include/m*.h" because I didn't want this
to get too big. This also sets aside <miiphy.h> and <phy.h>. While
miiphy.h does not directly need <phy.h> there are *so* many users and I
think I had half of the tree just about not building when I first tried.
It might be worth further investigation, but it might just be OK as-is.
Link: https://lore.kernel.org/r/20250521230119.2084088-1-trini@konsulko.com
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There are only a few things found in <mtd.h> today. Go through and audit
the C files which include <mtd.h> and remove it when not required. Then,
add it to the files which had either missed it or had an indirect
inclusion of it.
Signed-off-by: Tom Rini <trini@konsulko.com>
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The clock driver allows to boost the NAND performance
controller. Make changes to let it use the new clock driver
=> time nand read ${loadaddr} kernel
NAND read: device 0 offset 0x500000, size 0x800000
8388608 bytes read: OK
time: 0.488 seconds
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Make simple the clock registration and enable and allow later
to add support for other platforms
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
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Write enable(06h) command will be sent to a flash device to
set the write enable latch bit before every program, erase,
write command. After that write disable command (04h) needs
to be sent to clear the write enable latch.
This write_disable() is missing at the majority of the places
in the driver, add it to clear write enable latch.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://gist.github.com/PrasanthBabuMantena/c12f39744de188a9d08cd5ca51dc2a7b
Tested-by: Prasanth Babu Mantena <p-mantena@ti.com>
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MT35XU512ABA has only BFPT and 4-Byte Address Instruction Table
in SFDP. commit bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map")
added checks in spi_nor_octal_dtr_enable() to bail out if the 22nd DWORD
in SCCR does not indicate DTR Octal Mode Enable, since MT35XU512ABA device
supports octal DTR mode, add this property in SFDP fixup.
Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
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The MTD device reference is dropped via put_mtd_device, however its
field ->index is read and passed to ubi_msg. To fix this, the patch
moves the reference dropping after calling ubi_msg.
Signed-off-by: Pan Bian <bianpan2016@163.com>
Reviewed-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
Upstream Linux commit: b95f83ab762dd6211351b9140f99f43644076ca8
Signed-off-by: Alexander Vickberg <wickbergster@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
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Flash partitions may specify MTDPART_SIZ_FULL (=0) as the size of the
partition to indicate "the remainder of the flash". Make this work with
device-tree "fixed-partitions" as well.
This makes MTD partitioning compatible with the Linux kernel, see:
https://github.com/torvalds/linux/blob/master/include/linux/mtd/partitions.h#L29
https://github.com/torvalds/linux/blob/master/drivers/mtd/mtdpart.c#L123
Previously, this could only be done through MTDPARTS so this change allows
boards like topic_miami to migrate from `mtdparts`/`mtdids` to devicetree
partitions.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
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SST(sst26wf016) flashes have multiple erase block sizes, including
8 KB, 32 KB, and 64 KB. Since a 64 KB sector erase cannot be performed
on all blocks, the 4 KB sector erase command should be used instead.
Enabling the SPI_FLASH_USE_4K_SECTORS configuration allows the use of
4 KB sector erases, but it may increase the erase operation time for large
memory flashes.
This reverts commit 34cd4a72fb2d113e2754c0d643618a8e3fa549ab
MEMORY ORGANIZATION:
The SST26WF016B/016BA SQI memory array is organized
in uniform, 4 KByte erasable sectors with the following
erasable blocks: eight 8 KByte parameter, two
32 KByte overlay, and thirty 64 KByte overlay blocks.
See Figure 3-1.
Top of Memory Block
┌──────────┐
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 32 KByte │
├──────────┤
│ 64 KByte │
├──────────┤
│ 64 KByte │
├──────────┤
│ 64 KByte │
├──────────┤
│ 32 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
├──────────┤
│ 8 KByte │
└──────────┘
Bottom of Memory Block
┌────────────────────────────────┐
│ 64 KByte │
├────────────────────────────────┤
│ 64 KByte │
└────────────────────────────────┘
Expanded View:
┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
│ 4 KB │ │ 4 KB │ │ 4 KB │ │ 4 KB │
├──────┤ ├──────┤ ├──────┤ ├──────┤
│ . . . (continues) . . . │
└──────┘ └──────┘ └──────┘ └──────┘
2 Sectors for 8 KByte blocks
8 Sectors for 32 KByte blocks
16 Sectors for 64 KByte blocks
Link: https://ww1.microchip.com/downloads/en/DeviceDoc/20005013D.pdf
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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Takahiro Kuwano <Takahiro.Kuwano@infineon.com> says:
Those are 3.0V, 256Mb/2Gb NOR Flash devices with Octal interface.
Same fanctionalities with 1.8V version that are already supported.
Link: https://lore.kernel.org/r/cover.1743575001.git.Takahiro.Kuwano@infineon.com
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Infineon S28HL02GT is 3.0V, 2Gb Flash device with Octal interface.
It has the same functionalities with S28HS02GT.
Link: https://www.infineon.com/dgdl/Infineon-S28HS02GT_S28HS04GT_S28HL02GT_S28HL04GT_2Gb_4Gb_SEMPER_Flash_Octal_interface_1.8V_3.0V-DataSheet-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017f0631e33714d9
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
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Infineon S28HL256T is 3.0V, 256Mb Flash device with Octal interface.
It has the same functionalities with S28HS256T.
Link:https://www.infineon.com/dgdl/Infineon-S28HS256T_S28HL256T_256Mb_SEMPER_Flash_Octal_interface_1_8V_3-DataSheet-v02_00-EN.pdf?fileId=8ac78c8c8fc2dd9c018fc66787aa0657
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
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At the moment a mixture of ifdef(CONFIG_IS_ENABLED) and
CONFIG_IS_ENABLED(SPI_FLASH_BAR) is used in the spi-nor framework.
This leads to misbehaviour in the SPL as there is no Kconfig option
CONFIG_SPL_SPI_FLASH_BAR. This commit standardizes the use of
CONFIG_SPI_FLASH to get SPLs that load U-Boot proper from the
SPI flash to work again.
Fixes: 9bb02f7 (mtd: spi-nor: Fix the spi_nor_read() when config SPI_STACKED_PARALLEL is enabled)
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
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Since the opcode SPINOR_OP_CHIP_ERASE (0xc7) is not supported
for the mt35xu01g/2g flashes, the NO_CHIP_ERASE flag has been added
to enable sector erase functionality instead.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
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The mtd partition offset must be calculated first as it will be
referenced when calculating the mtd partition size.
Change-Id: Iccfd101b0a9597ac240c25670da638a82af28980
Fixes: 1ca97ee9039 (mtd: mtdpart: Support MTD_SIZE_REMAINING with unallocated memory area)
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Reported-by: Francesco Dolcini <francesco@dolcini.it>
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Call SPI setup_for_spinand() if supported and defined to configure the
SPI slave for the attached NAND. This is needed to configure the SPI
with the NAND page size and spare size for correct configuration of the
device.
Call it as soon as the NAND is detected to correctly handle SPI
controller with select_op_variant detection.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Andre Przywara <andre.przywara@arm.com> says:
C's implicit fallthrough behaviour in switch/case statements can lead to
subtle bugs. Quite some while ago many compilers introduced warnings in
those cases, requiring intentional fallthrough's to be annotated.
So far we were not enabling that compiler option, so many ambiguities
and some bugs in the code went unnoticed.
This series adds the required annotations in code paths that the first
stage of the U-Boot CI covers. There is a large number of cases left
in the libbz2 code. The usage of switch/case is borderline insane there,
labels are hidden in macros, and there are no breaks, but just goto's.
Upstream still uses very similar code, without any annotations. I still
am not 100% sure those are meant to fall through or not, and plan to do
further investigations, but didn't want to hold the rest of the patches
back. You can see for yourself by applying patch 18/18 and building for
sandbox64, for instance.
Because of this we cannot quite enable the warning in the Makefile yet,
but those fixes are worth regardless, and be it to increase readability.
Please note that those patches do not fix anything, really, they just add
those fallthrough annotations, so the series is not really critical.
Link: https://lore.kernel.org/r/20250327153313.2105227-1-andre.przywara@arm.com
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The raw NAND flash code uses an implicit switch/case fallthrough to
share code when dealing with different ECC modes, and also when handling
some read command.
Add our "fallthrough;" statement-like macro before the respective labels
in the NAND code, to avoid a warning when GCC's -Wimplicit-fallthrough
warning option is enabled.
This copies the fallthrough annotations that the original kernel code
gained, before this function got refactored there.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Michael Trimrachi <michael@amarulasolutions.com>
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The SPI NOR code uses an implicit switch/case fallthrough when checking
different vendors to determine how to deal with extended addressig modes.
Add our "fallthrough;" statement-like macro before some label in the
4-byte addressing mode code, to avoid a warning when GCC's
-Wimplicit-fallthrough warning option is enabled.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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The UBI code uses an implicit switch/case fallthrough when handling two
related cases of bad header errors. Also there is a switch/case for unit
prefix handling (G/M/K), which accumulates multiplications.
Add our "fallthrough;" statement-like macro before the respective labels
in both cases, to avoid a warning when GCC's -Wimplicit-fallthrough
warning option is enabled.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
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https://source.denx.de/u-boot/custodians/u-boot-ubi
ubi fixes for v2025.07-rc1
- ubi: fix bug creating partitions for non-existent volumes
from Oskar Nilsson
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The part_get_info_ubi() function was incorrectly returning 0 (success)
when a UBI volume was not found for a given partition index. This caused
the part_create_block_devices() function in blk-uclass.c to continue
creating devices for non-existent partitions up to MAX_SEARCH_PARTITIONS
Fix the issue by returning -1 when a volume is not found, signaling to
the part_create_block_devices() function that no more valid volumes
exist.
Before patch, 128 blk_partition are created:
Class Index Probed Driver Name
-------------------------------------------------
root 0 [ + ] root_driver root_driver
thermal 0 [ ] imx_thermal |-- imx_thermal
simple_bus 0 [ + ] simple_bus |-- soc
mtd 0 [ + ] mxs-nand-dt | |-- nand-controller@1806000
blk 0 [ ] ubi_blk | | `-- nand-controller@1806000.blk
partition 0 [ ] blk_partition | | |-- nand-controller@1806000.blk:1
...
partition 127 [ ] blk_partition | | `-- nand-controller@1806000.blk:128
After patch, the expected blk_partition are created:
Class Index Probed Driver Name
-------------------------------------------------
root 0 [ + ] root_driver root_driver
thermal 0 [ ] imx_thermal |-- imx_thermal
simple_bus 0 [ + ] simple_bus |-- soc
mtd 0 [ + ] mxs-nand-dt | |-- nand-controller@1806000
blk 0 [ ] ubi_blk | | `-- nand-controller@1806000.blk
partition 0 [ ] blk_partition | | |-- nand-controller@1806000.blk:1
partition 1 [ ] blk_partition | | |-- nand-controller@1806000.blk:2
partition 2 [ ] blk_partition | | |-- nand-controller@1806000.blk:3
partition 3 [ ] blk_partition | | `-- nand-controller@1806000.blk:4
simple_bus 1 [ + ] simple_bus | |-- bus@2000000
Signed-off-by: Oskar Nilsson <onilsson@rums.se>
Cc: Kyungmin Park <kmpark@infradead.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Alexey Romanov <avromanov@salutedevices.com>
Changed in v2:
- Change return from -1 to -ENOENT
Reviewed-by: Heiko Schocher <hs@denx.de>
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https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next
CI: https://source.denx.de/u-boot/custodians/u-boot-nand-flash/-/pipelines/25178
This merge request add support for cadence raw nand driver for agilex
board and add a fix to meson driver.
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If 'oob_required' is not set by the caller (for example 'oobbuf' is NULL),
then driver doesn't copy OOB data from 'oob_poi' to special controller
structures, so zeroes will be written as OOB. But, generic raw NAND logic
in 'nand_base.c' already handles case when OOB is not required to write by
filling 'oob_poi' with 0xFF's. So let's remove 'oob_required' check to
always read 'oob_poi' data for OOB.
Kernel driver (drivers/mtd/nand/raw/meson_nand.c) works in the same way,
so need to keep same behaviour here.
Fixes: c2e8c4d09a7a ("mtd: rawnand: Meson NAND controller support")
Signed-off-by: Arseniy Krasnov <avkrasnov@salutedevices.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
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Add SYS_NAND_PAGE_SIZE dependency for cadence NAND.
This config is needed as the SPL driver will use this parameter
to read uboot-proper image in NAND during booting.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Enable the Kconfig and Makefile for the Cadence-Nand
SPL support in agilex5 family device.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Add support for spl nand to load binary image from NAND
to RAM. Leverage the existing nand_spl_load_image from nand_spl_loaders.c
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Leverage linux code to support hardware ECC interface
to verify nand bad block.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Enable the Kconfig and Makefile for the
Cadence NAND driver for the agilex5 family device.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Enable nand to use bounce buffer. In bounce buffer,
read/write buf will use cadence->buf which has been allocated
using malloc. This will align the memory and avoid memory to be
allocated in different addresses.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Poll for thread complete status to ensure the
descriptor processing is complete. If complete then can ensure
controller already update the descriptor status.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Ensure ddr memory is updated with the data from dcache.
This would help to ensure cdma always reading the latest dma descriptor
from ddr memory.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Support NAND_CMD_SET_FEATURES & NAND_CMD_GET_FEATURES.
These commands is one of the basic commands of NAND. The parameters get
from these commands will be used to set timing mode
of NAND data interface.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Support nand reset command for Cadence Nand Driver.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Add support for reading param page of NAND device.
These paramaters are unique and used for identification purpose.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Add support for readid command in Cadence NAND driver.
The id is unique and used for flash identification.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Add support for read status command
in Cadence NAND driver. This status bit is important to check
whether the flash is write-protected.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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Enable driver for Cadence NAND for the family
device agilex5. This driver is leveraged from the path
/drivers/mtd/nand/raw/cadence-nand-controller.c from the
stable version 6.11.2.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
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If there is an unallocated memory area before the last, filling parting
the size calculation for MTD_SIZE_REMAINING does not take this hole
into account.
Fix this by calculating the remaining size just based on total size
and partition offset.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
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From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems
like we have to wait tREA after rising RE# before sampling the data.
Thus pulse time must be at least tREA.
Without this fix we got PMECC errors when reading, after switching to
ONFI timing mode 3 on SAM9X60 SoC with S34ML02G1 raw NAND flash chip.
The approach to set timings used before worked on sam9g20 and sama5d2
with the same flash (S34ML02G1), probably because those have a slower
mck clock rate and thus the resolution of the timings setup is not as
tight as with sam9x60.
The approach to fix the issue was carried over from at91bootstrap, and
has been successfully tested in at91bootstrap, U-Boot and Linux.
Link: https://github.com/linux4sam/at91bootstrap/issues/174
Cc: Li Bin <bin.li@microchip.com>
Signed-off-by: Alexander Dahl <ada@thorsis.com>
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Replace Maximumm with Maximum in Kconfig symbol description, fix a typo.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Michal Simek <michal.simek@amd.com>
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In the case of MTD_BLOCK and UBI_BLOCK they should be select'ing BLK as
they provide block device functionality and not depending on some other
block device already being enabled too (as is the typical case).
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Prepare v2025.01-rc6
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Update the spi_nor_read() function based on the config SPI_FLASH_BAR
and update the length and bank calculation by spliting the memory of
16MB size banks only when the address width is 3byte.
Fix the read issue for 4byte address width by passing the entire
length to the read function.
Fixes: 5d40b3d384 ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
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Prepare v2025.01-rc5
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