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path: root/drivers/net
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17 hoursnet: phy: mscc: add support for the VSC8572Charles Perry
This is similar to the VSC8574 according to the Linux commit that adds support for it [1]. This was tested on an HX1000 board with SGMII (PIC64-HX SoC which has a GEM MAC). [1]: https://lore.kernel.org/all/dfabe39a52efcd2cfff9358f271b8673143503b8.1480497966.git.neill.whillans@codethink.co.uk/ Signed-off-by: Charles Perry <charles.perry@microchip.com> Reviewed-by: Manikandan Muralidharan <manikandan.m@microchip.com>
17 hoursnet: macb: add gigabit implementation for fixed-linkChristian DREHER
A fixed gigabit link on a non-gigabit controller is only rejected during PHY init (even though there is no PHY to init), because, on device-tree parsing, the controller is not probed, and it is still unknown whether it is gigabit-capable. This code was only tested on emulator with a full-duplex RGMII interface, but is expected to work in GMII or half-duplex as well. Signed-off-by: Christian DREHER <christian.dreher@nanoxplore.com>
17 hoursnet: macb: do not set user_io when it does not existChristian DREHER
Cadence Ethernet MAC has a feature named user_io, which provides some input and some output signals for arbitrary purpose in the SoC. From the driver code, I understand that, on Atmel SoC, it is used to drive the PHY mode. At least on Cadence IP7014 r1p12, this feature is optional, and I am working on a SoC that does not instantiate it. The presence of this feature is advertised in DCFG1, this patch merely disables the access to the user_io register based on this information. I did not apply this change to the non-gigabit capable versions of the IP, as I do not have documentation for them, and a new non-gigabit instance is unlikely to appear. I prefer avoiding regressions on old systems. Signed-off-by: Christian DREHER <christian.dreher@nanoxplore.com>
17 hoursnet: macb: use SA1 for MAC filtering on GEMChristian DREHER
The MACB uses specific address registers (SA Top and Bottom) to filter source or destination MAC addresses. On the Gigabit Ethernet version, SA1B is @0x88. On the non-GEM version, SA1B is @0x98. Before this commit, the code was always writing 0x98. By chance, on GEM, this is the address of SA3B, allowing the driver to work anyway. The motivation for this change is to be able to use the driver on an instance of the GEM with less than 4 SA registers. Signed-off-by: Christian DREHER <christian.dreher@nanoxplore.com>
17 hoursnet: macb: include arch/clk.h only when necessaryChristian DREHER
It does not exist in my setup (an on-going arm64 SoC), and removing it does not cause any missing declaration, but some code called when CONFIG_CLK is missing calls get_macb_pclk_rate, which is only defined in arch/arm/mach-at91/include/mach/clk.h Signed-off-by: Christian DREHER <christian.dreher@nanoxplore.com>
17 hoursnet: phy: adin: add support for the ADIN1200 phyRasmus Villemoes
The ADIN1200 chip is register compatible with the ADIN1300, but only supports 10/100 Mbit. Signed-off-by: Rasmus Villemoes <ravi@prevas.dk>
17 hoursnet: phy: airoha: air_en8811: use standard rx-polarity/tx-polarity propertiesLucien.Jheng
Replace the proprietary airoha,pnswap-rx / airoha,pnswap-tx boolean device tree properties with the standard rx-polarity and tx-polarity properties defined in phy-common-props.yaml. Backward compatibility is maintained by reading the legacy boolean properties first and passing them as the default_pol argument to phy_get_rx/tx_polarity(). If the standard properties are absent the legacy values are used transparently, so existing device trees remain functional without modification. Link: https://git.kernel.org/linus/66d8a334b57e64e43810623b3d88f0ce9745270b Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com>
17 hoursnet: cpsw: Support new cpsw-switch DT bindingsMarkus Schneider-Pargmann (TI)
Upstream devicetrees use a newer DT binding using cpsw-switch compatibles. The bindings are a bit different, so two functions are introduced to capture the differences, cpsw_eth_of_to_plat_switch() and cpsw_eth_of_to_plat_legacy(). Signed-off-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>
17 hoursnet: cpsw: Use driver data for phy_selMarkus Schneider-Pargmann (TI)
Use driver data to pass the correct gmii_sel function. This way new compatibles don't need manual compatible matching as is done in cpsw_phy_sel(). Signed-off-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>
17 hoursnet: cpsw: Remove compat string argumentMarkus Schneider-Pargmann (TI)
The string is already in the priv struct, remove it from the argument list. Signed-off-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>
17 hoursnet: cpsw: Fix error messageMarkus Schneider-Pargmann (TI)
It should complain about mac_control here. Signed-off-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>
17 hoursnet: phy: dp83867: default to 2ns delay if unspecified in device-treeSiddharth Vadapalli
Since Linux commit c360eb0c3ccb ("dt-bindings: net: ethernet-controller: Add informative text about RGMII delays"), the interpretation of RGMII delays has changed. Prior to the commit, the RGMII Variant among "rgmii", "rgmii-id", "rgmii-rxid" and "rgmii-txid" clearly specified whether it is the MAC or the PHY that "should" add the delay. However, post that commit, the RGMII Variant only specifies whether or not there is a delay on the PCB traces between the MAC and the PHY, leaving it open as to who adds the delay. Hence, instead of enforcing the existence of the device-tree properties "ti,rx-internal-delay" and "ti,tx-internal-delay", default to a delay of 2ns, while continuing to override this delay with the aforementioned properties, if they exist in the device-tree. This is in line with the Linux driver implementation updated by commit 6bf78849371d ("net: phy: dp83867: use 2ns delay if not specified in DTB"). Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Anshul Dalal <anshuld@ti.com>
9 daysMerge patch series "net: migrate NO_NET out of the networking stack choice"Tom Rini
Quentin Schulz <foss+uboot@0leil.net> says: This migrates the net options away from the main Kconfig to net/Kconfig, rename the current NET option to NET_LEGACY to really highlight what it is and hopefully encourage more people to use lwIP, add a new NET menuconfig (but keep NO_NET as an alias to NET=n for now) which then allows us to replace all the "if legacy_stack || lwip_stack" checks with "if net_support" which is easier to read and maintain. The only doubt I have is wrt SYS_RX_ETH_BUFFER which seems to be needed for now even when no network is configured? Likely due to include/net-common.h with PKTBUFSRX? No change in behavior is intended. Only change in defconfig including other defconfigs where NO_NET=y or NET is not set, in which case NO_NET is not set or NET=y should be set in the top defconfig. Similar change required for config fragments. See commit log in patch adding NET menuconfig for details. This was tested based on 70fd0c3bb7c2 ("x86: there is no CONFIG_UBOOT_ROMSIZE_KB_12288"), from within the GitLab CI container trini/u-boot-gitlab-ci-runner:noble-20251013-23Jan2026 and set up similarly as in "build all platforms in a single job" GitLab CI job. #!/usr/bin/env bash set -o pipefail set -eux ARGS="-BvelPEWM --reproducible-builds --step 0" ./tools/buildman/buildman -o ${O} --force-build $ARGS -CE $* ./tools/buildman/buildman -o ${O} $ARGS -Ssd $* O=../build/u-boot/ ../u-boot.sh -b master^..b4/net-kconfig |& tee ../log.txt I can't really decipher the log.txt, but there's no line starting with + which would be an error according to tools/buildman/builder.py help text. Additionally, because I started the script with set -e set and because buildman has an exit code != 0 when it fails to build a board, and I have the summary printed (which is the second buildman call), I believe it means all builds passed. The summary is the following: aarch64: (for 537/537 boards) all +0.0 rodata +0.0 uniphier_v8 : all +1 rodata +1 u-boot: add: 0/0, grow: 1/0 bytes: 1/0 (1) function old new delta data_gz 10640 10641 +1 arm: (for 733/733 boards) all -0.0 rodata -0.0 uniphier_v7 : all -1 rodata -1 u-boot: add: 0/0, grow: 0/-1 bytes: 0/-1 (-1) function old new delta data_gz 11919 11918 -1 opos6uldev : all -3 rodata -3 u-boot: add: 0/0, grow: 0/-1 bytes: 0/-3 (-3) function old new delta data_gz 18778 18775 -3 uniphier_ld4_sld8: all -3 rodata -3 u-boot: add: 0/0, grow: 0/-1 bytes: 0/-3 (-3) function old new delta data_gz 11276 11273 -3 stemmy : all -20 rodata -20 u-boot: add: 0/0, grow: 0/-1 bytes: 0/-20 (-20) function old new delta data_gz 15783 15763 -20 As far as I could tell this data_gz is an automatically generated array when CONFIG_CMD_CONFIG is enabled. It is the compressed .config stored in binary form. Because I'm changing the name of symbols, replacing a menu with a menuconfig, additional text makes it to .config and the "# Networking" section in .config disappears. Here is the diff for the 5 defconfigs listed above, generated with: for f in build/*-m; do diff --unified=0 $f/.config $(dirname $f)/$(basename -a -s '-m' $f)/.config done (-m is the build directory for master, and without the suffix, it's the top commit of this series) """ --- build/opos6uldev-m/.config 2026-04-20 10:53:49.804528526 +0200 +++ build/opos6uldev/.config 2026-04-20 11:03:37.430242767 +0200 @@ -970,4 +969,0 @@ - -# -# Networking -# @@ -975,0 +972 @@ +CONFIG_NET_LEGACY=y --- build/stemmy-m/.config 2026-04-20 11:01:33.653698123 +0200 +++ build/stemmy/.config 2026-04-20 11:04:53.452577311 +0200 @@ -733,4 +732,0 @@ - -# -# Networking -# @@ -738,2 +733,0 @@ -# CONFIG_NET is not set -# CONFIG_NET_LWIP is not set --- build/uniphier_ld4_sld8-m/.config 2026-04-20 11:00:41.605469071 +0200 +++ build/uniphier_ld4_sld8/.config 2026-04-20 11:04:22.226439899 +0200 @@ -997,4 +996,0 @@ - -# -# Networking -# @@ -1002,0 +999 @@ +CONFIG_NET_LEGACY=y --- build/uniphier_v7-m/.config 2026-04-20 10:53:04.019307319 +0200 +++ build/uniphier_v7/.config 2026-04-20 11:03:01.688085486 +0200 @@ -1004,4 +1003,0 @@ - -# -# Networking -# @@ -1009,0 +1006 @@ +CONFIG_NET_LEGACY=y --- build/uniphier_v8-m/.config 2026-04-20 10:43:05.614441175 +0200 +++ build/uniphier_v8/.config 2026-04-20 10:41:03.214852130 +0200 @@ -875,4 +874,0 @@ - -# -# Networking -# @@ -880,0 +877 @@ +CONFIG_NET_LEGACY=y """ This is fine: - Networking menu doesn't exist anymore so "#\n# Networking\n#\n" won't be in .config anymore. - opos6uldev, uniphier_ld4_sld8, uniphier_v7 and uniphier_v8 all have (old) CONFIG_NET enabled, (new) CONFIG_NET will still be set but CONFIG_NET_LEGACY also needs to be defined now to reflect the stack choice (even if default), - stemmy has CONFIG_NO_NET set, which means CONFIG_NET and CONFIG_NET_LWIP are not reachable anymore hence why they don't need to be part of .config, GitLab CI was run on this series (well, not exactly, but it's only changes to the git logs that were made): https://source.denx.de/u-boot/contributors/qschulz/u-boot/-/pipelines/29849 It passes. Link: https://lore.kernel.org/r/20260420-net-kconfig-v1-0-9900002d8e72@cherry.de
9 dayssimplify NET_LEGACY || NET_LWIP condition with NET conditionQuentin Schulz
Since the move to make NET a menuconfig and NO_NET a synonym of NET=n, when NET is enabled, NET_LEGACY || NET_LWIP is necessarily true, so let's simplify the various checks across the codebase. SPL_NET_LWIP doesn't exist but SPL_NET_LEGACY is an alias for SPL_NET so the proper symbol is still defined in SPL whenever needed. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
9 daysrename NET to NET_LEGACYQuentin Schulz
Highlight that NET really is the legacy networking stack by renaming the option to NET_LEGACY. This requires us to add an SPL_NET_LEGACY alias to SPL_NET as otherwise CONFIG_IS_ENABLED(NET_LEGACY) will not work for SPL. The "depends on !NET_LWIP" for SPL_NET clearly highlights that it is using the legacy networking app so this seems fine to do. This also has the benefit of removing potential confusion on NET being a specific networking stack instead of "any" network stack. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
14 daysnet: zynq_gem: Clear stale speed bits in NWCFG before setting new onesRafał Hibner
Commit ecba4380ad26 ("net: zynq_gem: Update the MDC clock divisor in the probe function") changed zynq_gem_init() from a direct register write to a read-modify-write pattern in order to preserve MDC clock divider bits. However, the old speed selection bits (SPEED100/SPEED1000) are never cleared before OR-ing in the new value. When the PHY renegotiates at a different speed between successive calls to zynq_gem_init() (e.g. link flapping from 1 Gbps to 100 Mbps on a marginal cable), both SPEED100 and SPEED1000 end up set simultaneously in NWCFG. This confuses the GEM hardware and no frames are received. Fix by explicitly clearing both speed bits before merging the new configuration, so only the currently negotiated speed is ever active. Fixes: ecba4380ad26 ("net: zynq_gem: Update the MDC clock divisor in the probe function") Signed-off-by: Rafał Hibner <rafal.hibner@secom.com.pl> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20260420074640.4036119-1-rafal.hibner@secom.com.pl
14 daysnet: zynq_gem: reinitialize RX BDs on every initPranav Tilak
Reinitialize RX BDs and rewrite rxqbase on every init instead of only on the first init. This ensures a clean BD state on every init for all GEM configurations. For AMD Versal Gen 2 10GBE this is required since the USX block resets the RX DMA pointer to rxqbase on each init, so BDs must be rebuilt each time to stay in sync with hardware. Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20260410093018.1461732-4-pranav.vinaytilak@amd.com
14 daysnet: zynq_gem: set 128-bit AXI bus width for 10GBEPranav Tilak
Set 128-bit AXI bus width in network config for 10GBE. The default 64-bit setting causes DMA data corruption. Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20260410093018.1461732-3-pranav.vinaytilak@amd.com
14 daysnet: zynq_gem: add SPEED_10000 case in clock rate selectionPranav Tilak
Add SPEED_10000 case in the speed switch with the fixed 150 MHz tx_clk rate. Without this, clk_rate stays 0 for 10000 Mbps and clk_set_rate(0) on a fixed clock aborts initialization. Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20260410093018.1461732-2-pranav.vinaytilak@amd.com
14 daysnet: xilinx: Reject broadcast and multicast packets in AXI Ethernet MACMichal Simek
Set the XAE_RAF_BCSTREJ_MASK bit in the Reset and Address Filter (RAF) register during hardware initialization to make the MAC drop incoming frames with broadcast destination address. This avoids unnecessary broadcast traffic processing by the CPU. Additionally, when IPv6 is not enabled (CONFIG_IPV6), also set the XAE_RAF_MCSTREJ_MASK bit to reject multicast frames. Multicast rejection is skipped when IPv6 is configured because IPv6 Neighbor Discovery and DHCPv6 rely on multicast. Expose the RAF register (offset 0x0) in struct axi_regs which was previously hidden in a reserved array. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/07ad94eb8a3a9d80273a16a7ac8c7caaba607fe2.1774282153.git.michal.simek@amd.com
2026-04-21net: fsl_enetc: Add iMX95 enetc4 10Gbps port supportYe Li
1. Add optional serdes-supply regulator property support. 2. Enable 10Gbps feature for the controller, configure netc blkctrl CFG_LINK_PCS_PROT_2 to 10G SXGMII. 3. Add internal xpcs phy initialization to 10G XGMII Mode without auto-negotiation interface. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com>
2026-04-21net: phy: aquantia: Increase timeout for out of resetYe Li
Current timeout for PHY out of reset is 50ms which is too short. Increase it to 2s to align with kernel. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
2026-04-09drivers: net: fsl-mc: add the nowait option when applying the DPLIoana Ciornei
The process through which the MC firmware parses the DPL and initializes all the requested DPAA2 objects is a complex one which can take quite a bit of time. For the those circumstances in which a fast boot is required on DPAA2 based SoCs, add the 'nowait' optional parameter for the fsl_mc [lazy]apply dpl command. When this option is used, the Linux kernel fsl-mc bus must wait for the firmware to finish parsing the DPL before proceeding with probing all the DPAA2 objects. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-04-09drivers: net: fsl-mc: cleanup the fsl_mc command help textIoana Ciornei
All the parameters that can be currently passed to the fsl_mc command are positional arguments which are mandatory. This is not perfectly clear when reading the help text because of the use of square brackets. Fix this by changing the square brackets, which are commonly used for optional parameters, with < .. >. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-04-09drivers: net: fsl-mc: remove unused parameter from the wait_for_mc() functionIoana Ciornei
The first parameter of the wait_for_mc() function - booting_mc - is not used. Remove it. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2026-04-07arm: mach-sc5xx: Align header paths with SYS_SOC conventionPhilip Molloy
Define CONFIG_SYS_SOC in the mach-sc5xx Kconfig. Follow the standard U-Boot include path convention by moving the SC5xx SoC headers from arch/arm/include/asm/arch-adi/sc5xx/ to the conventional arch/arm/include/asm/arch-sc5xx/ location. Update includes from <asm/arch-adi/sc5xx/*.h> to <asm/arch/*.h> across mach-sc5xx and board files. Signed-off-by: Philip Molloy <philip.molloy@analog.com>
2026-04-07global: Correct duplicate U_BOOT_DRIVER entry namesTom Rini
The U_BOOT_DRIVER macro creates a list of drivers used at link time, and all entries here must be unique. This in turn means that all entries in the code should also be unique in order to not lead to build failures later with unexpected build combinations. Typically, the problem we have here is when a driver is obviously based on another driver and didn't update this particular field and so while the name field reflects something unique the linker entry itself is not. In a few places this provides a more suitable string name as well, however. Reviewed-by: Marek Vasut <marek.vasut+usb@mailbox.org> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # Tegra Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Heiko Schocher <hs@nabladev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-31net: rswitch: Remap CPU to bus addresses using dev_phys_to_bus()Marek Vasut
Use dev_phys_to_bus() to convert CPU addresses of DMA descriptors into bus addresses of DMA descriptors. This is necessary on hardware which does not have 1:1 mapping between CPU and memory addressed by the DMA. This has no impact on other hardware which does not need this conversion. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-03-31net: phy: dp83867: reset PHY on init to ensure clean statePranav Tilak
After a warm reboot, the PHY is left in power-down state (BMCR_PDOWN set) causing auto-negotiation to timeout when running the dhcp command. Fix this by calling phy_reset() in dp83867_config() which brings the PHY to a known clean state. The existing DP83867_SW_RESTART is removed as it is redundant after phy_reset(). Fixes: 721aed79126b ("net: phy: Add support for Texas Instruments DP83867") Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
2026-03-31net: rswitch: Avoid NULL pointer dereference during PHY accessMarek Vasut
At the very early stage when PHY ID is being auto-detected, the PHY device is not yet instantiated and rswitch_etha .phydev is still NULL. Add missing check for this condition and perform C22 fallback access in this PHY ID auto-detection case. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2026-03-31net: Correct dependencies for HIFEMAC_ETHTom Rini
The HIFEMAC_ETH functionality can only work with both DM_ETH_PHY and DM_MDIO enabled (it calls one of the functions that requires both), so express this dependency in Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-31rtl8169: add support for RTL8125dJaven Xu
This patch adds support for RTL8125d. Its chip version is 0x6a. Signed-off-by: Javen Xu <javen_xu@realsil.com.cn> [jf: add missing comma] Signed-off-by: Jerome Forissier <jerome.forissier@arm.com>
2026-03-31net: Rework dependencies around NET/NET_LWIP and NETDEVICESTom Rini
Functionally, both networking stacks require DM_ETH. This is because they both also require some networking devices to be enabled. Express this more correctly by having both NET and NET_LWIP select NETDEVICES. In turn NETDEVICES no longer depends on NET or NET_LWIP as it's not prompted anymore. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jerome Forissier <jerome.forissier@arm.com>
2026-03-31phy: micrel: ksz90x1: Issue PHY soft reset during configurationBoon Khai Ng
- Add a call to phy_reset() in ksz9031_config() to ensure the PHY is properly reset during initialization. - This clears the power-down bit and ensures the PHY recovers correctly after Linux reboot. Tested on Agilex5 hardware with KSZ90X1 PHY. Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
2026-03-31net: dwc_eth_xgmac: Move DMA reset and pad calibration after PHY initBoon Khai Ng
- Move DMA software reset and pad calibration in xgmac_start() to occur after the PHY is initialized and connected. - This ensures the PHY is ready before performing these operations, which is necessary for proper recovery after reboot. This change fixes issues where the PHY did not recover from power-down state after a Linux reboot, for the board using Micrel KSZ90x1 PHY. Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
2026-03-31net: Rework some symbol dependenciesTom Rini
As exposed by "make randconfig", we have a few dependency issues with some network drivers: - Both HIFEMAC_ETH and HIGMACV300_ETH functionally require both DM and OF_CONTROL. Further, HIFEMAC_ETH needs DM_CLK not just CLK to be selected. - BNXT_ETH deals with it's PCI requirement in a backwards way. The symbol PCI_INIT_R is board specific, PCI alone is required to build. Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-31net: pcs-airoha: fix allyesconfig buildingMikhail Kshevetskiy
Airoha PCS driver depends on ARCH_AIROHA, so it should not be built by allyesconfig configuration. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-31net: pcs-airoha: unify code using SCU regmap helperMikhail Kshevetskiy
Use common code to get CHIP_SCU registers instead of driver one. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-31net: airoha: probe airoha switch mdio on airoha_eth probingMikhail Kshevetskiy
Airoha switch mdio maybe used not only by GDM1, but also by other GDM ports (ex: as21xxx phy connected to GDM2 port). So it's better probe airoha switch mdio a bit early in the airoha_eth_probe() code. Also remove useless eth_phy_set_mdio_bus() call and related code. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-27Merge tag 'xilinx-for-v2026.07-rc1-v2' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze into next AMD/Xilinx/FPGA changes for v2026.07-rc1 v2 Kconfig: - Correct XILINX_TIMER entry - Rework TARGET_MICROBLAZE_GENERIC - Fix CPU_MICROBLAZE PVR logic - Remove non existing SPL_BINMAN_FDT i2c: - Wire pca9848 support spi/cadence-qspi: - Disable DAC mode - Do reset pulse net/gem: - Disable broadcast packets - Clear TXSR transfer complete - Add support for dma-coherent versal2: - Enable GIC600 support - Fix UFS distro boot wiring
2026-03-25fw_loader: Introduce SUPPORTS_FW_LOADER symbolTom Rini
The implementation of FW_LOADER requires CMDLINE to be enabled, and expressses this. In order to not have to have every users also depends on CMDLINE introduce SUPPORTS_FW_LOADER. This depends on CMDLINE and ENV_SUPPORT and then we have all users depends on SUPPORTS_FW_LOADER. Signed-off-by: Tom Rini <trini@konsulko.com>
2026-03-23net: zynq_gem: Add support for dma-coherent flagMichal Simek
When dma-coherent DT property is passed there is no need to do any cache operations. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/10c7a40364162cc8d3c82cb3e64e043f49a5153e.1772437409.git.michal.simek@amd.com
2026-03-23net: zynq_gem: clear TXSR transfer completePadmarao Begari
The Zynq GEM TX status register retains the transfer‑complete bit until it is explicitly cleared. The current flow waits for transfer‑complete but never clears it, so on the next send the wait loop returns immediately because transfer‑complete is already high. This causes the driver to report TX completion before the new DMA transfer has actually finished, which breaks back‑to‑back transmissions. This issue causes timeouts during LWIP TFTP transfers when cache coherency is enabled. Fix this by explicitly clearing transfer‑complete (write‑to‑clear) after the wait completes, so each transmit starts with a clean TXSR. Co-developed-by: Harini Katakam <harini.katakam@amd.com> Signed-off-by: Harini Katakam <harini.katakam@amd.com> Co-developed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Padmarao Begari <padmarao.begari@amd.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/f354680d43fba0f590a6fae693848e5bf7114ba5.1772437409.git.michal.simek@amd.com
2026-03-23net: zynq_gem: Disable broadcast packetsMichal Simek
There is no reason to react on broadcast packets that's why just ignore them not to waste cycles on packets which are not for the platform. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/6e10793b7d72668343756edb66221f1415570250.1772437409.git.michal.simek@amd.com
2026-03-13Merge tag 'net-20260312' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-net into next Pull request net-20260312. net: - Move network PHY under NETDEVICES - s/DM_CLK/CLK/ in HIFEMAC_{ETH,MDIO} - Add support for Airoha AN8811HB PHY - airoha: PCS and MDIO support for Airoha AN7581 SoC net-lwip: - Fix issue when TFTP blocksize is >8192 - Adjust PBUF_POOL_SIZE/IP_REASS_MAX_PBUFS for better performance and resource usage. - Enable mii command for NET_LWIP
2026-03-13net: Move network PHY under NETDEVICESTom Rini
A number of network PHY drivers have Kconfig dependencies on various network drivers under NETDEVICES. This is in addition to logical dependencies of network PHYs needing network drivers. Resolve the Kconfig problems by moving the network PHY lines to be after the network devices, within the overall NETDEVICES guard. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Jerome Forissier <jerome.forissier@arm.com>
2026-03-13net: do not use non-existent CONFIG_DM_CLKHeinrich Schuchardt
For enabling the clock driver we use symbol CONFIG_CLK. Select this symbol for the HiSilicon Fast Ethernet Controller driver. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2026-03-13net: phy: air_en8811: add support for Airoha AN8811HB PHYTommy Shih
Add support for the Airoha AN8811HB 2.5 Gigabit PHY to the existing en8811h driver. This PHY supports 10/100/1000/2500 Mbps speeds. Update the driver to recognize the AN8811HB PHY ID and handle its specific firmware loading requirements. The firmware loading mechanism remains consistent with the existing implementation. This driver is based on: - Linux upstream PHY subsystem (v7.0-rc1) - air_an8811hb v0.0.4 out-of-tree uboot driver written by "Lucien.Jheng <lucien.jheng@airoha.com>" Tested on MT7987 RFB board. Link: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=6f1769ec5892ac41d82e820d94dcdc68e904aa99 Link: https://patchwork.kernel.org/project/netdevbpf/patch/20260122071601.1057083-3-bjorn@mork.no/ Signed-off-by: Tommy Shih <tommy.shih@airoha.com> Reviewed-by: Lucien.Jheng <lucienzx159@gmail.com>
2026-03-12net: airoha: use mt7531 mdio for GDM1Mikhail Kshevetskiy
Current code just bind mt7531 mdio with it's driver, so mdio device may not be probed and hense not usable. This patch: * Forces probing of mt7531 mdio for GDM1 port * Renames the mt7531 mdio bus interface to 'mt7531-mdio'. We may have multiple available MDIO, so the name 'mdio' isn't descriptive enough. * Sets mdio bus for the GDM port device Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
2026-03-12net: airoha: makes PCS support optionalMikhail Kshevetskiy
It's not possible to disable PCS support just now, an7581 u-boot will not compile. This patch fixes an issue. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
generated by cgit v1.2.3 (git 2.0.4) at 2026-05-07 02:05:23 +0000