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After years of developing the ADI ADSP platform, Timesys was purchased
by another company and is no longer contracted to maintain the platform.
Signed-off-by: Philip Molloy <philip.molloy@analog.com>
Reviewed-by: Greg Malysa <malysagreg@gmail.com>
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Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.
Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.
This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20260129081054.1703479-1-pranav.vinaytilak@amd.com
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Pull request net-20260209.
net:
- airoha: mdio support for the switch
- phy: mscc: allow RGMII with internal delay for the VSC8541
- dwc_eth_qos: Update tail pointer handling
net-legacy:
- Stop conflating return value with file size in net_loop()
net-lwip:
- wget: rework the '#' printing
- tftp: add support of tsize option to client
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The i.MX91 SoC reuses the ENET FEC from i.MX93. Add all required driver
checks to make it work also on the i.MX91 based platforms.
Signed-off-by: Primoz Fiser <primoz.fiser@norik.com>
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Add the missing RGMII modes with internal delay for the VSC8541.
Fixes: a5fd13ad1913 ("net: phy: MSCC Add Support for VSC8530-VSC8531-VSC8540-VSC8541")
Signed-off-by: Charles Perry <charles.perry@microchip.com>
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mdio is a child node of the switch, so to get switch base address
we need to lookup for a parent node
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
uses "airoha,en7581-switch" dts node for finding MDIO childs. This is wrong
for EN7523 SoC. The correct node name should be used instead.
Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Commit d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
refers to non-present CONFIG_MDIO_MT7531 and non-present "mt7531-mdio"
driver. It should use CONFIG_MDIO_MT7531_MMIO and "mt7531-mdio-mmio"
instead.
Fixes: d2145a89bcf6 ("net: airoha: bind MDIO controller on Ethernet load")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Multicast and Broadcast Queue Enable and Promiscuous Mode Enable bits
are currently written to "unused" registers using magic values.
Define more of the "unused" MAC regs based on information in the
DesignWare Cores Ethernet Quality-of-Service databook.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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The DesignWare Cores Ethernet Quality-of-Service databook state that
receive and transmit descriptor list address and also transmit and
receive tail pointer registers should be initialized before the receive
and transmit DMAs are started.
It also state to enable the MAC receiver only after the DMA is active.
Otherwise, received frames can fill the Rx FIFO and overflow.
Move the activation of receive and transmit DMA and MAC receiver until
after tail pointer registers have been initialized.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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The DesignWare Cores Ethernet Quality-of-Service databook state that
descriptors up to one location less than the one indicated by the
descriptor tail pointer are owned by the DMA. The DMA continues to
process the descriptors until the following condition occurs:
Current Descriptor Pointer == Descriptor Tail Pointer
The DMA goes into suspend mode when this condition occurs, and updating
the tail pointer resume the DMA processing.
Configure the transmit tail pointer to the first (current) descriptor
pointer so that the tail pointer is a valid address instead of being
initialized to NULL when transmit DMA is started.
Also update the receive tail pointer comment to state that by pointing
to the last descriptor we are actually implying that all receive
descriptors are owned by and can be processed by the DMA.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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The DesignWare Cores Ethernet Quality-of-Service databook state that the
descriptor address from the start to the end of the ring must not cross
the 4GB boundary.
Use lower_32_bits() to write the lower 32 bits of descriptor addresses,
including the 32-bit tail pointers, consistently. No functional change
is intended.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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The CUX3410 is similar to AQR113C. The main difference is CUX3410 does not
support MACSEC.
Signed-off-by: Bo-Cun Chen <bc-bocun.chen@mediatek.com>
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With commit 5663b137e682 ("arm: Remove edminiv2 board") the last
ARCH_ORION5X platform was removed. Remove the rest of the architecture
code which is now unused.
Reviewed-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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The micrel KSZ9031 phy has a optional clock pin (CLK125_NDO) which can be
used as reference clock for the MAC unit. The clock signal must meet the
RGMII requirements to ensure the correct data transmission between the
MAC and the PHY. The KSZ9031 phy does not fulfill the duty cycle
requirement if the phy is configured as slave. For a complete
describtion look at the errata sheets: DS80000691D or DS80000692D.
The errata sheet recommends to force the phy into master mode whenever
there is a 1000Base-T link-up as work around. Only set the
"micrel,force-master" property if you use the phy reference clock provided
by CLK125_NDO pin as MAC reference clock in your application.
Attention: this workaround is only usable if the link partner can
be configured to slave mode for 1000Base-T.
This follows linux implementation in commit
e1b505a60366 ("net: phy: micrel: add 125MHz reference clock workaround")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
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Disable the support due to chip errata and call genphy_config_aneg
instead of genphy_config. For a complete describtion look at the
KSZ9031 errata sheets: DS80000691D or DS80000692D.
Micrel KSZ9021 has no errata, but has the same issue with Asymmetric Pause.
This patch apply the same workaround as the one for KSZ9031.
This follows linux implementation in commits
3aed3e2a143c ("net: phy: micrel: add Asym Pause workaround")
407d8098cb1a ("net: phy: micrel: add Asym Pause workaround for KSZ9021")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Max Merchel <Max.Merchel@ew.tq-group.com>
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Replace PHY interface mode bitmap handling with comparison test to match
U-Boot PHY subsystem behavior. U-Boot currently implements only single PHY
interface mode for each PHY. Linux currently uses bitmap of PHY interface
modes for each PHY.
The reason why in Linux uses bitmap of supported interface modes is so
that Linux can select the best serdes mode switching behavior for the PHY.
For example if the host only supports 10gbase-r serdes mode, then the PHY
must always talk to the host in 10gbase-r mode, even if the RJ-45 copper
speed was autonegotiated to lower speed (i.e. 1Gbps).
If the host supports both 10gbase-r and sgmii serdes modes, we want the
PHY to switch to sgmii if the RJ-45 speed is 1000/100/10, and to switch
to 10gbase-r if the RJ-45 speed is 10000.
U-Boot does not implement this functionality yet, therefore remove modes
which cannot be currently supported and switch mv_test_bit() to plain
mode comparison.
Fixes: b6fcab0728cb ("net: phy: marvell10g: Adapt Marvell 10G PHY driver from Linux")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Add Microsemi/Microchip MDIO driver for interfaces found in their network
switches.
Driver is based on the Linux version.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Jerome Forissier <jerome@forissier.org>
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Tom Rini <trini@konsulko.com> says:
As seen by a number of patches fixing memory leaks, U-Boot has a problem
with developer expectations around devm_kmalloc and friends. Namely,
whereas in Linux these memory allocations will be freed automatically in
most cases, in U-Boot this is only true if DEVRES is enabled. Now,
intentionally, in xPL phases, we do not (and do not offer as an option)
enabling DEVRES. However in full U-Boot this is left either to the user,
or some drivers have select'd DEVRES on their own. This inconsistency is
a problem. This series goes and deals with two small issues that were
shown by having all drivers that use devm_.alloc to allocate memory also
select DEVRES and then we make DEVRES no longer be a prompted option and
instead select'd as needed. We do not make this unconditional as it
would result in growing the resulting binary on the many platforms which
have no users of the devm_.alloc family of functions.
Link: https://lore.kernel.org/r/20251227223833.3019311-1-trini@konsulko.com
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The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).
This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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As in Linux with d78c0ced60 ("net: ravb: Make write access to CXR35 first
before accessing other EMAC register"), configure CXR31 and CXR35 correctly
on rzg2. MII mode does not work correctly unless those registers are
properly configured.
Signed-off-by: Mathieu Othacehe <othacehe@gnu.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Prepare v2026.01-rc4
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https://source.denx.de/u-boot/custodians/u-boot-socfpga
This pull request delivers a broad set of improvements across the
SoCFPGA family, including Agilex5, Cyclone V, SoC64, and common code.
Key updates include refined boot flows, new driver enablement, handoff
tooling enhancements, and several stability fixes.
Highlights:
* Agilex5:
- Enable FAT-based environment storage
- MMC driver restores legacy clkmgr-based clock lookup
- Cleanup of MMC raw mode enablement logic
* Cyclone V:
- SPL FAT boot support and updated bootcmd sequence
- Disable SPL SPI to prevent contention with FAT-based boot
- New board handoff script and BSP generator tooling
- Optimized Makefile support for SoCFPGA handoff workflows* New drivers:
- Cadence xSPI driver with full protocol and command support
- SPL enablement for DW APB GPIO controller
* Networking:
- xgmac MDIO now supports Clause 45 read/write operations
* NAND / SoC64:
- Enable ONFI detection in Denali NAND controller for SoC64 devices
* DTS and board updates:
- Sync common SoCFPGA U-Boot DTS with kernel sources
- Fixes for FPGA2SDRAM configuration and SoCFPGA boot stall behavior
- Vining_FPGA migrated to the modern LED framework
- Device tree relocation no longer forced off for Vining FPGA
* Tooling:
- Introduces a new Python-based Cyclone V BSP generator
covering EMIF, IOCSR, HPS, XML parsing, rendering, and documentation
to simplify board enablement and handoff regeneration workflows
Overall, this series improves boot robustness, enhances xSPI and MDIO
capabilities, modernizes board support, and introduces new tooling to
streamline SoCFPGA handoff generation.
Pipelines test passing
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/28569
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Aquantia PHYs are being used w/o SPI flash in some routers recently.
Current firmware loader only attempts to load from FS on top of MMC,
limiting the use on many devices.
Removed the old firmware loader, migrate to generic script based firmware
loader to allow a wider range and runtime override of firmware source.
(e.g., MMC, USB, UBIFS).
Tested on Buffalo WXR18000BE10P with UBIFS.
Signed-off-by: Beiyan Yun <root@infi.wang>
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Split `aquantia_upload_firmware` into `aquantia_upload_firmware`
and `aquantia_do_upload_firmware` to prepare for fwloader change.
Signed-off-by: Beiyan Yun <root@infi.wang>
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These two PHY drivers have some overlap of supported PHYs. A longer term
effort is needed to both remove duplication and enhance support by
dealing with some issues that downstream vendor drivers address. For
now, make both of these depend on !COMPILE_TEST so that we can enable
"allyesconfig".
Signed-off-by: Tom Rini <trini@konsulko.com>
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Bind MDIO controller on Ethernet Controller load. The Airoha AN7581 SoC
have an integrated Switch based on MT7531 (or more saying MT7988).
Attach it to the mdio node in the switch node to support scanning for
MDIO devices on the BUS with DM API.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Add the driver for the Airoha EN8811H 2.5 Gigabit PHY. The PHY supports
100/1000/2500 Mbps with auto negotiation only.
The driver uses two firmware files, for which updated versions are added to
linux-firmware already.
Locating the AIROHA FW within the filesystem at the designated partition
and path will trigger its automatic loading and writing to the PHY via MDIO.
If need board specific loading override,
please override the en8811h_read_fw function on board or architecture level.
Based on the Linux upstream AIROHA EN8811H driver code(air_en8811h.c),
I have modified the relevant process to align with the U-Boot boot sequence.
and have validated this on Banana Pi BPI-R3 Mini.
Signed-off-by: Lucien.Jheng <lucienzx159@gmail.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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bcm54210e_config() configures the RGMII delays and then calls
bcm5461_config(). But the latter will do a PHY soft reset and thus
resets the delay settings again. Call bcm5461_config() first to fix it.
Fixes: cba79a1b2e11 ("net: phy: broadcom: add support for BCM54210E")
Signed-off-by: Michael Walle <mwalle@kernel.org>
Reviewed-by: Rafał Miłecki <rafal@milecki.pl>
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According to the TI DP83869HM datasheet Revision D (June 2025), section
7.6.1.41 STRAP_STS Register, the STRAP_OPMODE bitmask is bit [11:9].
Fix this.
In case the PHY is auto-detected via PHY ID registers, or not described
in DT, or, in case the PHY is described in DT but the optional DT property
"ti,op-mode" is not present, then the driver reads out the PHY functional
mode (RGMII, SGMII, ...) from hardware straps.
Currently, all upstream users of this PHY specify both DT compatible string
"ethernet-phy-id2000.a0f1" and ti,op-mode = <DP83869_RGMII_COPPER_ETHERNET>
property, therefore it seems no upstream users are affected by this bug.
The driver currently interprets bits [2:0] of STRAP_STS register as PHY
functional mode. Those bits are controlled by ANEG_DIS, ANEGSEL_0 straps
and an always-zero reserved bit. Systems that use RGMII-to-Copper functional
mode are unlikely to disable auto-negotiation via ANEG_DIS strap, or change
auto-negotiation behavior via ANEGSEL_0 strap. Therefore, even with this bug
in place, the STRAP_STS register content is likely going to be interpreted
by the driver as RGMII-to-Copper mode.
However, for a system with PHY functional mode strapping set to other mode
than RGMII-to-Copper, the driver is likely to misinterpret the strapping
as RGMII-to-Copper and misconfigure the PHY.
For example, on a system with SGMII-to-Copper strapping, the STRAP_STS
register reads as 0x0c20, but the PHY ends up being configured for
incompatible RGMII-to-Copper mode.
Fixes: f3e22eea815d ("net: phy: add TI DP83869HM ethernet driver")
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Use FIELD_GET()
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Currently, clause-22 format is supported. This change adds
support for clause-45 format.
Signed-off-by: Nikunj Kela <nikunj.kela@sima.ai>
Reviewed-by: Boon Khai Ng <boon.khai.ng@altera.com>
Tested-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Boon Khai Ng <boon.khai.ng@altera.com>
Tested-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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The last parameter to device_bind_driver_to_node is optional.
Since the returned information is not used and overwritten by
uclass_get_device_by_ofnode just provide NULL as parameter.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>
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When using DM_MDIO on SOC with more than one FEC and not sharing the MDIO
bus the name of the driver and the bus needs to be unique. Since name
used in device_bind_driver_to_node needs to be a static string, add the
string to the fec_priv struct and reuse fec_set_dev_name to generate the
name with the device sequence number.
Fixes: 3b8f99a3e762 ("net: fec: add support for DM_MDIO")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>
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If DM_ETH_PHY is used and the FEC instance owns the shared MDIO bus,
eth_phy_get_mdio_bus returns NULL. If DM_MDIO bus is used, the
mdio_register API is called from dm_mdio_post_probe. Therefore the
bus should must be queried by name in this case.
For DM_MDIO case fec_mii_setspeed has already being called in
dm_fec_mdio_probe(), so skip setting this again.
Fixes: 3b8f99a3e762 ("net: fec: add support for DM_MDIO")
Fixes: e75d08821574 ("net: fec-mxc: prevent crash if no MAC address is set")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>
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The code should only be executed if MDIO bus is not assigned.
Otherwise the already assigned / allocated bus will be overwritten.
Add condition check and simplify the code to make it more readable.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>
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If DM_MDIO is used and the FEC device is removed the mdio API
must not be used to remove the bus structure. Store pointer the
the udevice for MDIO bus created by dm_fec_bind_mdio and use DM
functions to cleanup the device in fecmxc_remove.
Fixes: 3b8f99a3e762 ("net: fec: add support for DM_MDIO")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>
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When initializing the MDIO bus the MDC signal needs to be configured.
Otherwise the communication over the bus may fail. Add the call to
fec_mii_setspeed to the DM_MDIO probe handler.
Fixes: 3b8f99a3e762 ("net: fec: add support for DM_MDIO")
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>
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If no MAC address can be found (either in ROM, device tree or env),
the post_probe of an ethernet device will fail and therefore
the device cannot be instantiated.
The DM_ETH_PHY (eth-phy-uclass) use case must not be mixed with
using CONFIG_FEC_MXC_MDIO_BASE.
This prevents following error for MAC not fused, no eth[1]addr
env is present and providing a random MAC is disabled:
Net:
Error: ethernet@5b040000 address not set.
Error: ethernet@5b040000 address not set.
FEC: can't find phy-handle
"Error" handler, esr 0xbf000002
elr: 000000008004e4b8 lr : 000000008004e4b4 (reloc)
elr: 00000000bfe984b8 lr : 00000000bfe984b4
x0 : 0000000000000000 x1 : 0000000000000020
x2 : 00000000bbe61e50 x3 : 00000000bbe6e1a0
x4 : 0000000000000020 x5 : 0000000000000020
x6 : 000000000000000a x7 : 0000000000000000
x8 : 0000000000000000 x9 : 0000000000000008
x10: 00000000ffffffd8 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000002c50
x14: 0000000000000000 x15: 00000000ffffffff
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000bbe61d98 x19: 00000000bbe4fa68
x20: 00000000bbe78c10 x21: 00000000bbe6e460
x22: 00000000bbe78c10 x23: 00000000bbe91780
x24: 00000000bbe6e510 x25: 00000000000001f8
x26: 00000000ffff8000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000bbe4fa10
Code: f900003f 9100a3a1 97ffff6e 35000100 (f94017a1)
Resetting CPU ...
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>
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phy_config may fail - for instance in parsing device tree.
This should be handled correctly. So return errors from
phy_config to caller.
Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>
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Currently, the bind callback of the driver namely am65_cpsw_nuss_bind()
registers all ethernet ports including the ones that have been disabled
in the device-tree. Since the ports that have been disabled are ought to
be ignored, fix the implementation to register only the enabled ports as
indicated by their 'status' in their respective device-tree node.
Fixes: 3943531a5468 ("net: ti: am65-cpsw-nuss: Define bind method for CPSW driver")
Reported-by: Wadim Egorov <w.egorov@phytec.de>
Closes: https://patch.msgid.link/8b4ac072-125c-493b-b12a-f0a4e9d56e7e@phytec.de
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
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Fix compiler warnings about casting integers to pointers of different
sizes by using uintptr_t as intermediate type. This ensures proper
type conversion across 32-bit and 64-bit architectures.
Signed-off-by: Sai Varun Venkatapuram <saivarun.venkatapuram@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/11b1d9b1a5589d06cff724e807832f366794c075.1762510401.git.michal.simek@amd.com
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Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:
This patch series adds basic support for the boards based on Airoha
EN7523/EN7529/EN7562 SoCs. Due to ATF restrictions these boards are
able to run 32-bit OS only.
This patch series adds support for the following hardware:
* console UART
* ethernet controller/switch
* spinand flash (in non-dma mode)
The following issues may be expected:
* Extra slow UBI attaching in U-Boot (up to 20 sec with fastmap enabled).
This is caused by the lack of DMA support in the U-Boot airoha-snfi driver.
* Linux airoha-snfi driver in some cases might damage you flash data
(see: https://lore.kernel.org/lkml/20251012121707.2296160-15-mikhail.kshevetskiy@iopsys.eu/)
* Latest linux kernel is recommended to properly support flashes
with more than one plane per lun
(see: https://lore.kernel.org/lkml/20251012121707.2296160-7-mikhail.kshevetskiy@iopsys.eu/)
* It's NOT recommended to use flashes working in continuous mode because
U-Boot airoha-snfi driver does not support such flashes properly.
The patches was tested on the board:
- SoC: Airoha EN7562
- RAM: 512 MB
- SPI NAND: 4 Gbit, made by Toshiba
- Linux boot: was NOT tested
The U-Boot was chain-loaded from the running U-Boot. Airoha ATF-2.3 does
not allow easily chain-loading of U-Boot from U-Boot, so a special FIT
image (mimic linux kernel) was created
1) Create u-boot.its file with the following contents:
=== cut here ===
/dts-v1/;
/ {
description = "ARM OpenWrt FIT (Flattened Image Tree)";
#address-cells = <1>;
images {
u-boot-ram {
description = "OpenWrt U-Boot RAM image";
data = /incbin/("u-boot.bin.lzma");
type = "kernel";
arch = "arm";
os = "linux";
compression = "lzma";
load = <0x81e00000>;
entry = <0x81e00000>;
hash@1 {
algo = "crc32";
};
hash@2 {
algo = "sha1";
};
};
fdt-1 {
description = "OpenWrt device tree blob";
data = /incbin/("dts/upstream/src/arm/airoha/en7523-evb.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
hash@1 {
algo = "crc32";
};
hash@2 {
algo = "sha1";
};
};
};
configurations {
default = "config-ram-uboot";
config-ram-uboot {
description = "OpenWrt RAM U-Boot";
kernel = "u-boot-ram";
fdt = "fdt-1";
};
};
};
==================
2) Create u-boot.itb image to chain-load new u-boot from the old one
lzma_alone e u-boot.bin u-boot.bin.lzma
mkimage -f u-boot.its u-boot.itb
3) Load new u-boot from the old one
U-Boot> tftpboot u-boot.itb && bootm
Link: https://lore.kernel.org/r/20251101004503.2379529-1-mikhail.kshevetskiy@iopsys.eu
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Add support for Ethernet controller present in Airoha en7523/en7529/en7562.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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This allow us remove some an7581/an7583 specific code and use a common
code instead.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Add support for the Renesas Ethernet Switch3 (RSW3) controller,
present in R-Car Gen5 SoCs such as R-Car X5H (R8A78000). The
hardware offset differences are handled via driver match data.
The driver newly detects whether the switch prot is connected
to xPCS or not, and if so, turns on MIOC bit 3. This is new on
R-Car X5H. GWCKSC register is also programmed only on X5H. The
rest of the operation is identical to RSwitch2.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
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The MPIC_MDC_CLK clock setting value differs between R-Car S4
and R-Car X5H. Parametrize the value in preparation for R-Car
X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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The GWDCBAC0, GWDCBAC1, FWPBFCSDC, CABPIRM register offsets changed
between R-Car S4 and R-Car X5H. Parametrize their offsets in preparation
for R-Car X5H addition into this driver. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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Inline FWRO, CARO, GWRO, TARO, RMRO macros directly into the
follow up register macros. FWRO, CARO, GWRO, TARO are already
zero, drop them. RMRO is 0x1000, increment all registers which
add RMRO by 0x1000 directly. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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The forwarding engine CSD register offset changed between the
R-Car S4 and R-Car X5H. Parametrize this offset in preparation
for R-Car X5H addition into this driver. Clean up the macro
parameter names and make them more obvious. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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