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Add STM32MP23 OSPI support.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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A large number of drivers "depends on" SPI_MEM but this is library type
functionality and so must be select'd instead in order to ensure that
drivers will build. Correct this usage and hide the symbol normally.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Add new driver to support NXP XSPI controller for NOR and NAND flash.
XSPI controller also uses a programmable sequence engine to provide
flexibility to support existing and future memory devices. It supports
single, dual, quad, octal modes of operation.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
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Tom Rini <trini@konsulko.com> says:
As seen by a number of patches fixing memory leaks, U-Boot has a problem
with developer expectations around devm_kmalloc and friends. Namely,
whereas in Linux these memory allocations will be freed automatically in
most cases, in U-Boot this is only true if DEVRES is enabled. Now,
intentionally, in xPL phases, we do not (and do not offer as an option)
enabling DEVRES. However in full U-Boot this is left either to the user,
or some drivers have select'd DEVRES on their own. This inconsistency is
a problem. This series goes and deals with two small issues that were
shown by having all drivers that use devm_.alloc to allocate memory also
select DEVRES and then we make DEVRES no longer be a prompted option and
instead select'd as needed. We do not make this unconditional as it
would result in growing the resulting binary on the many platforms which
have no users of the devm_.alloc family of functions.
Link: https://lore.kernel.org/r/20251227223833.3019311-1-trini@konsulko.com
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The devm alloc functions that we have may follow the Linux kernel model
where allocations are (almost always) automatically free()'d. However,
quite often we don't enable, in full U-Boot, the tracking and free()'ing
functionality. This in turn leads to memory leaks because the driver
author expects that since the functions have the same name as in the
Linux Kernel they have the same behavior. In turn we then get
functionally correct commits such as commit 00e1fed93c8c ("firmware:
ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually
add these calls. Rather than manually tracking allocations and
implementing free()s, rework things so that we follow expectations by
enabling the DEVRES functionality (outside of xPL phases).
This turns DEVRES from a prompted symbol to a symbol that must be
select'd, and we now remove our non-managed alloc/free functions from
outside of xPL builds.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
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This driver is only possible to build on ARCH_AIROHA, so update the
dependencies.
Fixes: 6134e4efd432 ("spi: airoha: Add Airoha SPI NAND driver")
Signed-off-by: Tom Rini <trini@konsulko.com>
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To reduce SPL size, make it possible to exclude designware driver,
while keeping it enabled in the main u-boot.
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
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This patch ports the Cadence xSPI controller driver from
the Linux kernel. The controller supports three operating modes:
1. ACMD (Auto Command) mode
- Includes PIO and CDMA submodes.
- CDMA mode uses linked descriptors for high-performance,
low-overhead operation.
- PIO mode is suitable for simple, single-command transactions.
2. STIG (Software Triggered Instruction Generator) mode
- Issues low-level 128-bit instructions to memory.
- Uses the Slave DMA interface for data transfers.
3. Direct mode
- Enables direct data access through the slave interface
without commands.
Currently, only the STIG work mode is enabled. Additional modes will be
supported in future updates.
At the same time, also enabling the kconfig option for xSPI driver.
This driver has been ported and functionally verified on the Intel Simics
platform. It is intended for evaluation and experimental use at this stage.
Link: https://lore.kernel.org/all/1632038734-23999-1-git-send-email-pthombar@cadence.com/
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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A few spi drivers cannot build without access to some platform
specific header files. Express those requirements in Kconfig as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
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Add STM32 OSPI driver, it supports :
- support sNOR / sNAND devices.
- Two functional modes: indirect (read/write) and memory-mapped (read).
- Single-, dual-, quad-, and octal-SPI communication.
- Single data rate (SDR).
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
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A dependency exposed by "make allyesconfig" is that the logic around
this symbol was not quite correct. It needs to depend on ARCH_MVEBU and
ARM64 and then select CLK_MVEBU.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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Add Airoha SPI NAND driver to permit usage of attached SNAND on the
Airoha AN7581 SoC. While SPI controller supports DMA transation, due to
U-Boot limitation we currently limit it to single command in Manual
mode.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Greg Malysa <malysagreg@gmail.com> says:
This series adds all of the supported peripheral drivers for the sc5xx
series of SoCs from Analog Devices and other drivers that are used by
the evaluation kits, such as a GPIO expander used by the EZLITE carrier
boards. This series passes gitlab CI tests.
Link: https://lore.kernel.org/r/20250226173150.13198-1-malysagreg@gmail.com
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This adds support for the ADI-specific SPI driver present in the ADI
SC5xx line of SoCs. This IP block is distinct from the QSPI/OSPI block
that uses the Cadence driver. Both may be used at once with appropriate
pin muxing configuration.
Co-developed-by: Greg Malysa <malysagreg@gmail.com>
Signed-off-by: Greg Malysa <malysagreg@gmail.com>
Co-developed-by: Angelo Dureghello <angelo.dureghello@timesys.com>
Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com>
Co-developed-by: Ian Roberts <ian.roberts@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
Co-developed-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
Signed-off-by: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>
Signed-off-by: Vasileios Bimpikas <vasileios.bimpikas@analog.com>
Signed-off-by: Utsav Agarwal <utsav.agarwal@analog.com>
Signed-off-by: Arturs Artamonovs <arturs.artamonovs@analog.com>
Signed-off-by: Oliver Gaskell <Oliver.Gaskell@analog.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
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Most other spi-mem drivers also depend on SPI_MEM. Fixes this build
error:
arm-v5te-linux-gnueabi-ld.bfd: drivers/spi/atmel-quadspi.o: in function `atmel_qspi_supports_op':
/mnt/data/adahl/src/u-boot/drivers/spi/atmel-quadspi.c:460: undefined reference to `spi_mem_default_supports_op'
make[1]: *** [/mnt/data/adahl/src/u-boot/Makefile:1821: u-boot] Error 1
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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This is inside of an 'if DM_SPI' block, and thus always true.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
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The correct spelling is R-Car, including the dash, update the usage.
Kconfig strings and comment changes only, no functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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The SPI_ADVANCE description does not explain what the switch does.
It does not have anything to do with any advanced functionality, it
only gates off support for stacked and parallel SPI NORs. Rename the
Kconfig symbol, update description, and move it right next to Xilinx
hardware as it seems to be specific to this hardware. Make sure the
symbol is also protected by if DM_SPI in Kconfig.
Fixes: 5d40b3d384dc ("mtd: spi-nor: Add parallel and stacked memories support")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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John Watts <contact@jookia.org> says:
I'm doing some SPI work so I tried to compile all the drivers on my
sunxi board to try and avoid some regressions. This failed, so here are
some fixes for this.
Link: https://lore.kernel.org/r/20240427-spikconfig-v1-0-8a54772522f4@jookia.org
Signed-off-by: Tom Rini <trini@konsulko.com>
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This is required for compiling.
Signed-off-by: John Watts <contact@jookia.org>
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These dependencies are required for building the drivers and create
compile errors if not enabled.
Signed-off-by: John Watts <contact@jookia.org>
[trini: Add ARCH_MVEBU to KIRKWOOD_SPI]
Signed-off-by: Tom Rini <trini@konsulko.com>
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In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.
In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical
Spi-nor will pass on the appropriate flash select flag to low level
driver, and it will select pass all the data to that particular flash.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling
the address space each operation is performed at addr/2 flash offset,
where addr is the address specified by the user.
Similarly for read and erase operations it will read from both flashes,
so size and offset are divided by 2 and send to flash.
Adding the config option SPI_ADVANCE for non SPL code.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
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Enable and update OSPI/QSPI/GQSPI drivers to support Versal Gen 2 SoCs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/691782470f56f7d49a3204f6757296f2752d4156.1716994063.git.michal.simek@amd.com
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Add spi nor flash controller driver for cv1800b SoC
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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Since commit 773ad4ebb1d6 ("spi, mpc8xx: Add support for chipselect via
GPIO and fixups"), DM_GPIO is required for 8xx SPI.
Add the missing dependency to avoid build failures.
Fixes: 773ad4ebb1d6 ("spi, mpc8xx: Add support for chipselect via GPIO and fixups")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
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Similar change was done by commit b4c2c151b14b ("Kconfig: Remove all
default n/no options") and again sync is required.
default n/no doesn't need to be specified. It is default option anyway.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com> # tegra
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Angelo Dureghello <angelo@kernel-space.org>
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Add A1 SPIFC driver from Linux. Slightly modified to use u-boot driver
framework and accommodate to lack of ioread32_rep/iowrite32_rep.
Based on Linux version 6.6-rc4
Signed-off-by: Igor Prusov <IVPrusov@sberdevices.ru>
Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20231024225140.366571-2-ivprusov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
[trini: Drop <common.h> as it's not needed]
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The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an
updated SPI controller that add the capability to allow the driver to
control chip select explicitly. Driver can control and keep cs low
between the transfers natively. Hence the dummy cs workaround or prepend
mode found in the bcm63xx-hsspi driver are no longer needed and this new
driver is much cleaner.
Port from linux patch:
Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zhang@broadcom.com
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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ARCH_BCMBCA was introduced to cover individual Broadcom broadband SoC
for common features and IP blocks. Use this config instead of each chip
config as the Kconfig dependency for Broadcom HSSPI driver.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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Enable support for parsing and auto discovery of parameters for
SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP)
tables as per JESD216 standard.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Make SFDP the default unconditionally
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https://source.denx.de/u-boot/custodians/u-boot-sh
- Initial R-Car Generation 4 support
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Use CONFIG_RCAR_64 to make the driver available on both
R-Car Gen3 and R-Car Gen4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
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The Freescale ESPI driver (CONFIG_FSL_ESPI) relies to the MPC85xx platform
(PowerPC) through arch/powerpc/include/asm/immap_85xx.h. The driver can't
compile on another architecture/platform.
Signed-off-by: Corentin Guillevic <corentin.guillevic@smile.fr>
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Introduce Socionext F_OSPI controller driver. This controller is used to
communicate with slave devices such as SPI flash memories. It supports
4 slave devices and up to 8-bit wide bus, but supports master mode only.
This driver uses spi-mem framework for SPI flash memory access, and
can only operate indirect access mode and single data rate mode.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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Stop using CONFIG_SANDBOX_ARCH and use CONFIG_SANDBOX instead. For the
SPI related defines, set them directly in Kconfig. This now empties
arch/sandbox/include/asm/config.h.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.
Co-developed-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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- NPCM PSPI controller (Jim)
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As CONFIG_ARCH_BCM6858 is replaced with CONFIG_BCM6858, update the
driver Kconfig to use the new config symbol.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
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As CONFIG_ARCH_BCM68360 is replaced with CONFIG_BCM6856, update the
driver Kconfig to use the new config symbol.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
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As CONFIG_ARCH_BCM63158 is replaced with CONFIG_BCM63158, update the
Kconfig to use the new config symbol.
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
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Add Nuvoton NPCM BMC Peripheral SPI controller driver.
NPCM750 include two general-purpose SPI interface.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2023.01-rc1 (round 2)
xilinx:
- Add support for new Versal NET SOC
zynqmp:
- Use mdio bus for ethernet phy description
- Wire ethernet phy reset via i2c-gpio
versal:
- Config cleanup
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Trivial changes to support cadence ospi driver for Versal NET platform.
Also avoid ospi flash reset for now.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0789141f432189aab69bc496fe33e0218d1d7510.1663589964.git.michal.simek@amd.com
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This patch adds support for spi-mem controller found on newer MediaTek SoCs
This controller supports Single/Dual/Quad SPI mode.
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
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This adds the dirmap API originally introduced in
Linux commit aa167f3fed0c
("spi: spi-mem: Add a new API to support direct mapping").
This also includes several follow-up patches and fixes.
Changes from Linux include:
* Added Kconfig option
* Changed struct device to struct udevice
* Changed struct spi_mem to struct spi_slave
This patch is obtained from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-seanga2@gmail.com/
The corresponding Linux kernel SHA1 is aa167f3fed0c.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
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Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.
There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
fetches initial device boot image from FMC chip select(CS) 0.
- SPI1: Play the role of a SPI Master controller. Or, there is a
dedicated path for HOST(X86) to access its BIOS flash mounted
under BMC. spi-aspeed-smc.c implements the control sequence when
SPI1 is a SPI master.
- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
mounted under it are for pure storage purpose.
ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
13h is used to fetch boot image from SPI flash.
- AST2500: Only 03h command can be used after power on
or reset.
- AST2600: If FMC04[6:4] is set, 13h command is used,
otherwise, 03h command.
The address length is decided by FMC04[2:0].
- Command mode: SPI controller can send command and address
automatically when CPU read/write the related remapped
or decoded address area. The command used by this mode
can be configured by FMC10/14/18[23:16]. Also, the
address length is decided by FMC04[2:0]. This mode will
be implemented in the following patch series.
- User mode: It is a traditional and pure SPI operation, where
SPI transmission is controlled by CPU. It is the main
mode in this patch.
Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.
This patch only implements user mode initially. Command read/write
mode will be implemented in the following patches.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
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This patch makes mt7621_spi driver available for MediaTek MT7621 SoC
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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Add support for cadence ospi driver for Versal platform. This driver
provides support for DMA read operation which utilizes cadence qspi
driver.
If "cdns,is-dma" DT property is specified use dma for read operation
from cadence_qspi driver. As cadence_qspi_apb_dma_read() is defined in
cadence_ospi_versal driver add a weak function defination in
cadence_qspi driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220512100535.16364-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
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The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
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