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path: root/drivers/spi/spi-synquacer.c
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2024-10-09spi: spi-uclass: Read chipselect and restrict capabilitiesVenkatesh Yadav Abbarapu
Read chipselect properties from DT which are populated using 'reg' property and save it in plat->cs[] array for later use. Also read multi chipselect capability which is used for parallel-memories and return errors if they are passed on using DT but driver is not capable of handling it. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07spi: Remove <common.h> and add needed includesTom Rini
Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: William Zhang <william.zhang@broadcom.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-13spi: synquacer: remove SPI_TX_BYTE handlingMasahisa Kojima
Current code expects that SPI_TX_BYTE is single bit mode but it is wrong. It indicates byte program mode, not single bit mode. If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set, the default transfer bus width is single bit. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2023-04-25spi: synquacer: Silence uninitialized variable warningsIlias Apalodimas
When building with clang, the compiler compains with drivers/spi/spi-synquacer.c:212:11: warning: variable 'bus_width' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:276:11: note: uninitialized use occurs here val |= ((bus_width >> 1) << BUS_WIDTH); ^~~~~~~~~ drivers/spi/spi-synquacer.c:212:7: note: remove the 'if' if its condition is always true else if (priv->mode & SPI_TX_OCTAL) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/spi/spi-synquacer.c:189:25: note: initialize the variable 'bus_width' to silence this warning So initialize bus_width to 1 and add a warning if none of the configured modes matches Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2022-06-10spi: synquacer: simplify tx completion checkingMasahisa Kojima
There is a TX-FIFO and Shift Register empty(TFES) status bit in spi controller. This commit checks the TFES bit to wait the TX transfer completes. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10spi: synquacer: DMSTART bit must not be set while transferringMasahisa Kojima
DMSTART bit must not be set while there is active transfer. This commit sets the DMSTART bit only when the transfer begins. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10spi: synquacer: wait until slave is deselectedMasahisa Kojima
synquacer_cs_set() function does not wait the chip select is deasserted when the driver sets the DMSTOP to deselect the slave. This commit checks the Slave Select Released(SRS) bit to wait until the slave is deselected. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2022-06-10spi: synquacer: busy variable must be initialized before useMasahisa Kojima
"busy" variable is ORed without being initialized, must be zeroed before use. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
2021-07-06spi: synquacer: Add HSSPI SPI controller driver for SynQuacerJassi Brar
This is a driver for the HSSPI SPI controller on SynQuacer SoC. The HSSPI has command sequence mode (memory mapped) and direct mode (FIFO access). The driver will operate it under the direct mode. And before booting OS, it switch back to the command sequence mode since that is compatible with default EDK2 behavior. Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>