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2025-06-06ram: rockchip: Fix dependency of RAM_ROCKCHIP_DEBUGLukasz Czechowski
The RAM_ROCKCHIP_DEBUG can be used only if DEBUG_UART is available. The next commit introduces changes in definition of debug uart functions, so that DEBUG_UART is required to be defined in order to initialize uart and use print functions. Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
2025-06-05Merge tag 'xilinx-for-v2025.07-rc4' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-microblaze AMD/Xilinx/FPGA changes for v2025.07-rc4 usb: - Fix regulator handling net: - Fix MII clock handling phy: - Fix GTR line logic for sgmii pci: - Fix pcireg_base logic fpga: - Fix change handling in intel_sdm_mb driver
2025-06-04mmc: am654_sdhci: Clear UHS_MODE_SELECT when <= MMC_HS_52Judith Mendez
This clears UHS_MODE_SELECT for timing modes <= MMC_HS_52. When initializing to HS400 mode, the host controller downgrades to non-uhs modes so clear UHS_MODE_SELECT at modes <= MMC_HS_52. This fixes eMMC writes on j7200 EVM. Fixes: 6067aa66b3bb ("mmc: am654_sdhci: Add am654_sdhci_set_control_reg") Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-06-03Merge tag 'qcom-more-for-2025.07' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-snapdragon More Qualcomm fixes for 2025.07 * Adjust fdtfile logic to support more boards * Support linux,code variable in qcom-pmic button driver * Minor CLK API adjustments and apq8096/msm8916 fixes * vbus regulator register fixes * dragonboard410c KASLR support and other fixes
2025-06-02button: qcom-pmic: allow to specify code in devicetreeAlexey Minnekhanov
Most device vendors put "Volume Down" button onto PMIC RESIN. But Sony is special: see dts/upstream/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi or [1]. They put "Volume Down" on PMIC GPIO 7 where others usually put "Volume Up", and KEY_VOLUMEUP is inside &pon_resin. Currently if you boot U-Boot on such Sony device, you end up with 2 "Volume Down" buttons, and no "Volume Up", which makes navigating menu problematic. Support reading devicetree "linux,code" property and override statically defined button code & label based on that. [1] https://elixir.bootlin.com/linux/v6.15-rc3/source/arch/ arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi#L263 Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org> Signed-off-by: Alexey Minnekhanov <alexeymin@minlexx.ru> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424014811.3809818-1-alexeymin@minlexx.ru Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02clk: qcom: apq8016: Fix SDCC clock warningsStephan Gerhold
As of commit dc8754e8e408 ("clk/qcom: apq8016: improve clk_enable logging") there are now warnings in the U-Boot console on DragonBoard 410c: apq8016_clk_enable: unknown clk id 122 apq8016_clk_enable: unknown clk id 123 apq8016_clk_enable: unknown clk id 124 apq8016_clk_enable: unknown clk id 125 This is because we don't implement enable() properly for the SDCC clocks. Currently they are being enabled as part of set_rate(). Fix this by moving the enable calls out of the apq8016_clk_init_sdc() function and convert them to the equivalent GATE_CLK_POLLED() definitions. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-6-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02clk: qcom: apq8016: Convert GATE_CLK() to GATE_CLK_POLLED()Stephan Gerhold
Convert the usages of GATE_CLK() in clock-apq8016 to GATE_CLK_POLLED() to make sure that we poll the status when enabling clocks: - PRNG_AHB_CLK is a vote clock, so we poll a different register address. - The USB clocks are simple branches, so enable/poll is the same register. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-5-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02clk: qcom: Allow polling for clock status in qcom_gate_clk_en()Stephan Gerhold
GATE_CLK() in its current state is unsafe: A simple write to the clock enable register does not guarantee that the clock is immediately running. Without polling the clock status, we may issue writes to registers before the necessary clocks start running. This doesn't seem to cause issues in U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A for the SMMU clocks on DB410c reliably triggers an exception during boot. Make it possible to poll the branch clock status register, by adding a new GATE_CLK_POLLED() macro that takes the extra register address. Existing usages work just as before, without polling the clock status. Ideally all usages should be updated to specify the correct poll address in the future. The Qualcomm naming for these clocks is "branch" and not "gate", but let's keep the existing naming for now to avoid confusion until all others drivers have been converted. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-4-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02clk: qcom: Use setbits_le32() for qcom_gate_clk_en()Stephan Gerhold
The other clock enable functions in clock-qcom.c use setbits_le32() to read/modify/write the enable registers. Use the same for qcom_gate_clk_en() to simplify the code a bit. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02clk: qcom: Move qcom_gate_clk_en() to C fileStephan Gerhold
This avoids having to inline it separately into every single clock driver, when U-Boot is built with support for multiple SoCs. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-2-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02clk: qcom: apq8016: Fix SDCC clock addressesStephan Gerhold
The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses: - SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018 Should be 0x42018, this is an invalid register close to the USB clocks. - SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018 Should be 0x43018, this is the SDCC1 clock. When we try to enable SDCC2, we actually end up enabling SDCC1. When we try to enable SDCC1, we just issue some broken register writes. This hasn't caused any trouble so far, because the boot firmware is keeping both SDCC clocks running. However, if these clocks are disabled when entering U-Boot, MMC initialization is failing. Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was already correct, but change it the same way for consistency. Fixes: 085921368b7d ("arm: Add support for Qualcomm Snapdragon family") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02power: qcom_vbus_regulator: add and fix support for pmic variantsRui Miguel Silva
Fix and add support for different pmic variants pm8x50b to handle the vbus regulator. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Link: https://lore.kernel.org/r/20250412174157.104419-1-rui.silva@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-06-02i2c: designware_i2c Return -ETIMEDOUT for timeout errorsWojciech Szamocki
Change the return value for timeout errors in i2c-designware from 1 to -ETIMEDOUT. Returning errors as negative values is standard practice in the u-boot, which enhances error handling consistency across the codebase. The current behavior can lead to silent errors when functions check for negative return values to identify errors. For example, in `dm_i2c_reg_read` from i2c-uclass.c, a timeout results in an uninitialized value being returned, potentially causing unexpected behavior. Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Wojciech Szamocki <wojciech.szamocki@nokia.com> Signed-off-by: Wojciech Szamocki <wojciech.szamocki@nokia.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2025-06-02net: gem: ignore tx_clk if MII is usedMartin Kaistra
If the MII interface is used, the PHY is the clock master, thus don't set the clock rate. On Zynq-7000, this will prevent the following error: zynq_gem ethernet@e000b000: failed to set tx clock rate 25000000 Signed-off-by: Martin Kaistra <martin.kaistra@linutronix.de> Link: https://lore.kernel.org/r/20250415150400.136723-1-martin.kaistra@linutronix.de Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-06-02phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shiftFrantisek Bohacek
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are four bits for each GEM, and one bit reserved in between. This has caused that using more than one GEM is impossible, additionally corrupting the GEM0's configuration, leaving GEM0 unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is going to write to GEM0's registers wrong value, leaving GEM0 unusable) Signed-off-by: Frantisek Bohacek <rutherther@ditigal.xyz> Link: https://lore.kernel.org/r/20250522060703.4863-1-rutherther@ditigal.xyz Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-06-02drivers: fpga: intel_sdm_mb: Flush cache before FPGA configurationNaresh Kumar Ravulapalli
FPGA configuration encounters failure when the cache is not flushed. Add cache flushing to the memory region that holds the FPGA configuration bitstream. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Link: https://lore.kernel.org/r/20250506012851.30039-1-nareshkumar.ravulapalli@altera.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-06-02pci: zynqmp: Fix the pcireg baseVenkatesh Yadav Abbarapu
The pcireg base is not assigned to any address, reading the pcireg base with PS_LINKUP_OFFSET which is incorrect and giving random values. So update the pcireg base from devicetree so that we can read the valid PCIE link status and PHY ready status. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Stefan Roese <sr@denx.de> Link: https://lore.kernel.org/r/20250516092314.939424-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-05-25usb: ulpi: Clean up how we enable supportTom Rini
The way we enable ULPI support today isn't something that should work. The "optional" keyword in a choice statement is not a documented feature. To make this work in a supported way, make USB_ULPI something we ask about if USB_HOST is set. Next, we move the choice of what viewer to use to be after the framework portion and to depend on that. We then borrow a few words from the top-level README to make the help text here clearer. Finally we make the Qualcomm driver select ULPI as it's required and we make the tegra driver not duplicate a check that Kconfig now handles for us. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-25usb: ulpi: Remove unused omap-ulpi-viewport driverTom Rini
The last platform to enable this driver was removed in 2019. Remove this unused code and documentation now. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-25usb: dwc3: core: Fix timeout checkVaradarajan Narayanan
dwc3_core_init loops 'timeout' times to check if the IP block is out of reset using 'while (timeout--)'. If there is some issue and the block doesn't come out of reset, the loop will run till 'timeout' becomes zero and the post decrement operator would set timeout to 0xffffffff. Though the IP block is not out reset, the subsequent if check 'if !timeout' would fail as timeout is not equal to zero and the function proceeds with the initialization. Use poll API instead to resolve this. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
2025-05-22Merge tag 'u-boot-imx-master-20250522' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/26275 - Fix boot regression on imx8mn_bsh_smm_s2/s2pro. - Fix reset on imx6ulz_smm_m2. - Adjust DDR initialization on imx6ulz_smm_m2. - Fix CAAM startup error.
2025-05-22caam: Fix CAAM error on startupOlaf Baehring
In rare cases U-Boot returns an error message when intantiating the RNG of the CAAM device: “SEC0: RNG4 SH0 instantiation failed with error 0xffffffff” This means, that even when the CAAM device reports a finished descriptor, none is found in the output ring. This might be caused by a missing cache invalidation before reading the memory of the output ring This patch moves the cache invalidation of the output ring from start of the job to immediately after the notification from hardware where the output ring will be read. Signed-off-by: Olaf Baehring <olaf.baehring@draeger.com> Signed-off-by: Fabio Estevam <festevam@gmail.com>
2025-05-21clk: thead: Port clock controller driver of TH1520 SoCYao Zi
The driver is adapted from Linux kernel's version of clk-th1520-ap.c, with only output clocks for external sensors, which are barely useful in bootloaders, removed. Same as the mainline driver, it currently lacks of ability to enable and reconfigure PLLs, which could be implemented later. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-21ram: thead: Add initial DDR controller support for TH1520Yao Zi
This patch cleans the vendor code of DDR initialization up, converts the driver to fit in DM framework and use a firmware[1] packaged by binman to ship PHY configuration. Currently the driver is only capable of initializing the controller to work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants of LicheePi 4A boards and I could test with. Support for other configurations could be easily added later. Link: https://github.com/ziyao233/th1520-firmware # [1] Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2025-05-20mmc: cv1800b: Fix build without MMC_SUPPORTS_TUNINGAlexander Sverdlin
That's how it looks like without CONFIG_MMC_SUPPORTS_TUNING before the patch: aarch64-buildroot-linux-gnu-ld.bfd: drivers/mmc/cv1800b_sdhci.o: in function `cv1800b_execute_tuning': drivers/mmc/cv1800b_sdhci.c:47:(.text.cv1800b_execute_tuning+0x50): undefined reference to `mmc_send_tuning' Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-05-12net: fsl_enetc: fix imdio register calculationThomas Schaefer
With commit cc4e8af2c552, fsl_enetc register accessors have been split to handle different register offsets on different SoCs. However, for internal MDIO register calculation, only ENETC_PM_IMDIO_BASE was fixed without adding the SoC specific MAC register offset. As a result, the network support for the Kontron SMARC-sAL28 and probably other boards based on the LS1028A CPU is broken. Add the SoC specific MAC register offset to calculation of imdio.priv to fix this. Fixes: cc4e8af2c552 ("net: fsl_enetc: Split register accessors") Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # LS1028A Tested-by: Tim Harvey <tharvey@gateworks.com> # imx95_19x19_evk Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Alice Guo <alice.guo@nxp.com>
2025-05-12spi: fspi: dev_dbg() call assumes fdt_addr_t always a long longJonathan Currier
On 32-bit systems, e.g. i.mxrt-1170 fdt_addr_t may only be 32-bit. Cast to a "long long" for garbage avoidance. Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
2025-05-12spi: fspi: Add imxrt1170 device dataJonathan Currier
Add the device specific driver data, and the clock configuration. Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
2025-05-12spi: fspi: involve lut_num for struct nxp_fspi_devtype_dataJonathan Currier
The flexspi on different SoCs may have different number of LUTs. So involve lut_num in nxp_fspi_devtype_data to make distinguish. This patch prepare for the adding of imx8ulp. Fixes: ef89fd56bdfc ("arm64: dts: imx8ulp: add flexspi node") Cc: stable@kernel.org Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20240905094338.1986871-3-haibo.chen@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org> (Picked from linux 190b7e2efb1ed8435fc7431d9c7a2447d05d5066) Signed-off-by: Jonathan Currier <dullfire@yahoo.com>
2025-05-12clk: Fix clk_set_parent() regressionJonas Karlman
The commit ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") add a call to clk_enable() for the parent clock. For clock drivers that do not implement the enable() ops, like most Rockchip clock drivers, this now cause the set_parent() ops to never be called when CLK_CCF=n (default for Rockchip). clk_enable() typically return -ENOSYS when the enable() ops is not implemented by the clock driver, with CLK_CCF=y clk_enable() instead return 0 when the enable() ops is unimplemented. Change to ignore -ENOSYS from the newly introduced clk_enable() call to fix this regression and restore the old behavior of set_parent() ops being called regardless of if enable() ops is implemented or not. Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Dang Huynh <danct12@riseup.net> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-05-09net: dwc: xgmac: Allow DMA buffers above 4GBNikunj Kela
Currently, Synopsis xgmac driver only works if DMA region is under 4GB. This change enables the DMA buffers allocations above 4GB memory regions. Signed-off-by: Nikunj Kela <nikunj.kela@sima.ai>
2025-05-09x86: apl: Correct usage of IS_ENABLED() macro in acpi-pmc-uclass.cTom Rini
This file was using IS_ENABLED() to test for CONFIG flags but omitted the CONFIG_ prefix and so did not work as expected. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-08Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegraTom Rini
2025-05-08Merge tag 'u-boot-rockchip-20250508' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/26117 - New Board support: rk3566 LCKFB TaishanPi, rk3588 Xunlong Orange Pi 5 Max; - Add rk3288 rmii support; - pinctrl driver fix; - binman description update;
2025-05-08video: backlight: add Skyworks/Analogictech AAT2870 led controller driverSvyatoslav Ryhel
Add support for Skyworks AAT2870 LED Backlight Driver and Multiple LDO Lighting Management Unit. Only backlight is supported as for now. Supported backlight level range is from 2 to 255 with step of 1. Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-05-08video: panel: add LG LH400WV3-SD04 MIPI DSI panel driverSvyatoslav Ryhel
LG LH400WV3-SD04 is a color active matrix TFT (Thin Film Transistor) liquid crystal display (LCD). The resolution of a 4" contains 480 x 800 pixels. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-05-08video: panel: add Hitachi TX10D07VM0BAA MIPI DSI panel driverSvyatoslav Ryhel
Hitachi TX10D07VM0BAA is a color active matrix TFT (Thin Film Transistor) liquid crystal display (LCD). The resolution of a 4" contains 480 x 800 pixels. Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-05-08video: tegra: add 8-bit CPU driven protocolSvyatoslav Ryhel
Add support for 8-bit CPU driven (primary and secondary) display signal interface found in Tegra 2 and Tegra 3 SoC. Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-05-08sysreset: implement MAX9807 sysreset functionsSvyatoslav Ryhel
MAX8907 PMIC has embedded poweroff function used by some device to initiane device power off. Implement it as optional sysreset driver guarded by kconfig option and system-power-controller device tree property. Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-05-08power: regulator: max9807: add regulator supportSvyatoslav Ryhel
Added a new regulator driver for the MAXIM MAX8907 PMIC, providing essential regulator functionalities and incorporated the necessary binding framework within the core PMIC driver. Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-05-08power: pmic: add the base MAX8907 PMIC supportSvyatoslav Ryhel
Add basic i2c based read/write functions to access PMIC registers. Tested-by: Ion Agorria <ion@agorria.com> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-05-08gpio: tegra_gpio: implement rfree operationSvyatoslav Ryhel
Releasing a GPIO on Tegra necessitates changing its configuration to SFIO to activate its special function. Without this reconfiguration, the special function will be unavailable. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
2025-05-08net: gmac_rockchip: Add RMII support for rk3288Christoph Fritz
Add RMII-specific handling to rk3288_gmac_fix_mac_speed() so that it properly sets the RMII clock (2.5 MHz vs. 25 MHz) and speed bits (10 Mbps vs. 100 Mbps). Also define a new rk3288_gmac_set_to_rmii() function to set the PHY interface field and RMII_MODE bit. Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-05-06mtd: spi-nor: Send write disable cmd after every write enableVenkatesh Yadav Abbarapu
Write enable(06h) command will be sent to a flash device to set the write enable latch bit before every program, erase, write command. After that write disable command (04h) needs to be sent to clear the write enable latch. This write_disable() is missing at the majority of the places in the driver, add it to clear write enable latch. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://gist.github.com/PrasanthBabuMantena/c12f39744de188a9d08cd5ca51dc2a7b Tested-by: Prasanth Babu Mantena <p-mantena@ti.com>
2025-05-06mtd: spi-nor-core: Fixup SNOR_F_IO_MODE_EN_VOLATILE for MT35XVaishnav Achath
MT35XU512ABA has only BFPT and 4-Byte Address Instruction Table in SFDP. commit bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map") added checks in spi_nor_octal_dtr_enable() to bail out if the 22nd DWORD in SCCR does not indicate DTR Octal Mode Enable, since MT35XU512ABA device supports octal DTR mode, add this property in SFDP fixup. Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com>
2025-05-06rockchip: io-domain: Enable by default for all supported SoCsChen-Yu Tsai
The IO domain driver controls the I/O voltage for various pins, MMC included. Enable it by default for all supported Rockchip SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Paul Kocialkowski <paulk@sys-base.io> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Anand Moon <linux.amoon@gmail.com>
2025-05-06pinctrl: rockchip: constify rockchip_pin_ctrl for RV1108Quentin Schulz
There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-05-06pinctrl: rockchip: constify rockchip_pin_ctrl for RK3399Quentin Schulz
There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-05-06pinctrl: rockchip: constify rockchip_pin_ctrl for RK3368Quentin Schulz
There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-05-06pinctrl: rockchip: constify rockchip_pin_ctrl for RK3328Quentin Schulz
There's no need to modify private data from the controller, so let's make that struct const. Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-07 00:08:10 +0000