Added the OS files

4 files changed, 128 insertions, 0 deletions

diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h
new file mode 100644
index 0000000..d10ccc2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+#endif
+
+
+#define CYGMEM_REGION_sram_l (0x1f800000)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCML)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x1f000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_OCRAM)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x3f800000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCMU)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi
new file mode 100644
index 0000000..d634d52
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_ocram.ldi
@@ -0,0 +1,37 @@
+// eCos memory layout
+// modified for VYBRID
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+//------------CM4 OCRAM code
+
+MEMORY
+{
+	OCRAM : ORIGIN = 0x1f000000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_OCRAM-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCML  : ORIGIN = 0x1f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCML-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCMU  : ORIGIN = 0x3f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCMU-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+}
+
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (OCRAM, 0x1f000400, LMA_EQ_VMA)
+    SECTION_RELOCS (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_bss (OCRAM, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_sram (OCRAM, ALIGN (0x8),LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x1f000000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x1f000000 + CYGHWR_HAL_CORTEXM_VYBRID_OCRAM);
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h
new file mode 100644
index 0000000..d10ccc2
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.h
@@ -0,0 +1,26 @@
+// eCos memory layout
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+#endif
+
+
+#define CYGMEM_REGION_sram_l (0x1f800000)
+#define CYGMEM_REGION_sram_l_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCML)
+#define CYGMEM_REGION_sram_l_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_sram (0x1f000000)
+#define CYGMEM_REGION_sram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_OCRAM)
+#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+#define CYGMEM_REGION_ram (0x3f800000)
+#define CYGMEM_REGION_ram_SIZE (CYGHWR_HAL_CORTEXM_VYBRID_TCMU)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+
+
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_sram+CYGMEM_REGION_sram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi
new file mode 100644
index 0000000..01086a8
--- /dev/null
+++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/pkgconf/mlt_vybrid_tcml.ldi
@@ -0,0 +1,39 @@
+// eCos memory layout
+// modified for VYBRID
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.inc>
+
+//------------CM4 TCML code
+
+MEMORY
+{
+	OCRAM : ORIGIN = 0x1f000000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_OCRAM-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCML  : ORIGIN = 0x1f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCML-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+    TCMU  : ORIGIN = 0x3f800000, LENGTH = CYGHWR_HAL_CORTEXM_VYBRID_TCMU-(CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE)
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (TCML, 0x1f800400, LMA_EQ_VMA)
+    SECTION_RELOCS (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_text (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fini (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_rodata1 (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_fixup (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_gcc_except_table (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_eh_frame (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_got (TCML, ALIGN (0x8), LMA_EQ_VMA)
+    SECTION_data (TCML, ALIGN(0x8), LMA_EQ_VMA)
+    SECTION_sram (TCMU, 0x3f800000, LMA_EQ_VMA)
+    SECTION_bss (TCMU, ALIGN (0x8), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
+
+hal_vsr_table = 0x1f800000;
+hal_virtual_vector_table = hal_vsr_table + 128*4;
+hal_startup_stack = (0x3f800000 + 0x00007ff0);
+
+