diff options
Diffstat (limited to 'Documentation/devicetree/bindings')
929 files changed, 30730 insertions, 5591 deletions
diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index 7b668f7fd400..6b4b4f51c371 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -6,7 +6,7 @@ DT_MK_SCHEMA ?= dt-mk-schema DT_SCHEMA_LINT = $(shell which yamllint || \ echo "warning: python package 'yamllint' not installed, skipping" >&2) -DT_SCHEMA_MIN_VERSION = 2023.9 +DT_SCHEMA_MIN_VERSION = 2024.4 PHONY += check_dtschema_version check_dtschema_version: @@ -46,6 +46,18 @@ quiet_cmd_chk_bindings = CHKDT $(src) xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(src)) \ && touch $@ || true +DT_CHK_STYLE = $(srctree)/scripts/dtc/dt-check-style + +# Feed the file list to the checker via @argfile in a single Python +# process so the ruamel.yaml import is paid once. scripts/jobserver-exec +# claims slots from the GNU make jobserver and exposes the count via +# $PARALLELISM, which dt-check-style picks up to size its worker pool. +quiet_cmd_chk_style = STYLE $(src) + cmd_chk_style = f=$$(mktemp) && $(find_cmd) > $$f && \ + $(PYTHON3) $(srctree)/scripts/jobserver-exec \ + $(PYTHON3) $(DT_CHK_STYLE) @$$f \ + && touch $@ || true; rm -f $$f + quiet_cmd_mk_schema = SCHEMA $@ cmd_mk_schema = f=$$(mktemp) ; \ $(find_all_cmd) > $$f ; \ @@ -62,13 +74,16 @@ override DTC_FLAGS := \ $(obj)/processed-schema.json: $(DT_DOCS) check_dtschema_version FORCE $(call if_changed,mk_schema) -targets += .dt-binding.checked .yamllint.checked +targets += .dt-binding.checked .yamllint.checked .dt-style.checked $(obj)/.yamllint.checked: $(DT_DOCS) $(src)/.yamllint FORCE $(if $(DT_SCHEMA_LINT),$(call if_changed,yamllint),) $(obj)/.dt-binding.checked: $(DT_DOCS) FORCE $(call if_changed,chk_bindings) +$(obj)/.dt-style.checked: $(DT_DOCS) FORCE + $(call if_changed,chk_style) + always-y += processed-schema.json targets += $(patsubst $(obj)/%,%, $(CHK_DT_EXAMPLES)) targets += $(patsubst $(obj)/%.dtb,%.dts, $(CHK_DT_EXAMPLES)) @@ -82,7 +97,7 @@ dt_compatible_check: $(obj)/processed-schema.json $(Q)$(srctree)/scripts/dtc/dt-extract-compatibles $(srctree) | xargs dt-check-compatible -v -s $< PHONY += dt_binding_check_one -dt_binding_check_one: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked +dt_binding_check_one: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked $(obj)/.dt-style.checked PHONY += dt_binding_check dt_binding_check: dt_binding_check_one $(CHK_DT_EXAMPLES) diff --git a/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml index 67c449d804c2..cc564dc7b414 100644 --- a/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml +++ b/Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml @@ -19,15 +19,29 @@ properties: items: - enum: - airoha,en7581-chip-scu + - airoha,an7583-chip-scu - const: syscon reg: maxItems: 1 + '#thermal-sensor-cells': + const: 0 + required: - compatible - reg +if: + properties: + compatible: + contains: + const: airoha,en7581-chip-scu + +then: + properties: + '#thermal-sensor-cells': false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 206686f3eebc..3030cf46fe74 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -111,10 +111,23 @@ properties: - enum: - intel,socfpga-agilex5-socdk - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-debug - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 + - description: Agilex72 boards + items: + - enum: + - intel,socfpga-agilex72-socdk + - const: intel,socfpga-agilex72 + + - description: Agilex7m boards + items: + - enum: + - altr,socfpga-agilex7m-socdk + - const: altr,socfpga-agilex7m + - description: SoCFPGA VT items: - const: altr,socfpga-vt diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index a885278bc4e2..9f73a0054fb2 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -234,6 +234,12 @@ properties: - amlogic,av400 - const: amlogic,a5 + - description: Boards with the Amlogic A9 A311Y3 SoC + items: + - enum: + - amlogic,by401 + - const: amlogic,a9 + - description: Boards with the Amlogic C3 C302X/C308L SoC items: - enum: diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 5c2629ec3d4c..fb277c96f341 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -96,6 +96,13 @@ description: | - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) + Devices based on the "M3" SoC: + + - MacBook Air (13-inch, M3, 2024) + - MacBook Air (15-inch, M3, 2024) + - MacBook Pro (14-inch, M3, 2023) + - iMac (24-inch, M3, 2023) + Devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: - MacBook Pro (14-inch, M1 Pro, 2021) @@ -116,6 +123,14 @@ description: | - Mac Studio (M2 Ultra, 2023) - Mac Pro (M2 Ultra, 2023) + Devices based on the "M3 Pro", "M3 Max" and "M3 Ultra" SoCs: + + - MacBook Pro (14-inch, M3 Pro, 2023) + - MacBook Pro (14-inch, M3 Max, 2023) + - MacBook Pro (16-inch, M3 Pro, 2023) + - MacBook Pro (16-inch, M3 Max, 2023) + - Mac Studio (M3 Ultra, 2025) + The compatible property should follow this format: compatible = "apple,<targettype>", "apple,<socid>", "apple,arm-platform"; @@ -297,6 +312,17 @@ properties: - const: apple,t8112 - const: apple,arm-platform + - description: Apple M3 SoC based platforms + items: + - enum: + - apple,j433 # iMac (24-inch, 2x USB-C, M3, 2023) + - apple,j434 # iMac (24-inch, 4x USB-C, M3, 2023) + - apple,j504 # MacBook Pro (14-inch, M3, 2023) + - apple,j613 # MacBook Air (13-inch, M3, 2024) + - apple,j615 # MacBook Air (15-inch, M3, 2024) + - const: apple,t8122 + - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms items: - enum: @@ -347,6 +373,35 @@ properties: - const: apple,t6022 - const: apple,arm-platform + - description: Apple M3 Pro SoC based platforms + items: + - enum: + - apple,j514s # MacBook Pro (14-inch, M3 Pro, 2023) + - apple,j516s # MacBook Pro (16-inch, M3 Pro, 2023) + - const: apple,t6030 + - const: apple,arm-platform + + - description: Apple M3 Max SoC based platforms + oneOf: + - items: + - enum: + - apple,j514c # MacBook Pro (14-inch, M3 Max, 16 cores, 2023) + - apple,j516c # MacBook Pro (16-inch, M3 Max, 16 cores, 2023) + - const: apple,t6031 + - const: apple,arm-platform + - items: + - enum: + - apple,j514m # MacBook Pro (14-inch, M3 Max, 14 cores, 2023) + - apple,j516m # MacBook Pro (16-inch, M3 Max, 14 cores, 2023) + - const: apple,t6034 + - const: apple,arm-platform + + - description: Apple M3 Ultra SoC based platforms + items: + - const: apple,j575d # Mac Studio (M3 Ultra, 2025) + - const: apple,t6032 + - const: apple,arm-platform + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index b88f41a225a3..1d2001836eb4 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -36,7 +36,11 @@ properties: - const: syscon - const: simple-mfd - items: - - const: apple,t6020-pmgr + - enum: + - apple,t6020-pmgr + - apple,t6030-pmgr + - apple,t6031-pmgr + - apple,t8122-pmgr - const: apple,t8103-pmgr - const: syscon - const: simple-mfd diff --git a/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml b/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml index ce5f2e1ec1ea..4ae7dc706b84 100644 --- a/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml +++ b/Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Juno FPGA APB Registers maintainers: - - Sudeep Holla <sudeep.holla@arm.com> + - Sudeep Holla <sudeep.holla@kernel.org> properties: compatible: diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 95d4baa85506..30cc534a91ee 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM Versatile Express and Juno Boards maintainers: - - Sudeep Holla <sudeep.holla@arm.com> + - Sudeep Holla <sudeep.holla@kernel.org> - Linus Walleij <linusw@kernel.org> description: |+ diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-scc.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-scc.yaml index 9b8f7e0c4ea0..060c0bc58a15 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-scc.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-scc.yaml @@ -8,7 +8,7 @@ title: ARM Versatile Express Serial Configuration Controller maintainers: - Liviu Dudau <liviu.dudau@arm.com> - - Sudeep Holla <sudeep.holla@arm.com> + - Sudeep Holla <sudeep.holla@kernel.org> description: | Test chips for ARM Versatile Express platform implement SCC (Serial diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 8ec7a3e74a21..dd7996960de3 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -95,6 +95,8 @@ properties: - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc + - facebook,rainiera6-bmc + - facebook,sanmiguel-bmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc - facebook,yosemite5-bmc @@ -117,4 +119,10 @@ properties: - ufispace,ncplite-bmc - const: aspeed,ast2600 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + - const: aspeed,ast2700 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5f5ff5e51e51..5be89c584026 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -223,6 +223,7 @@ properties: - qcom,oryon-1-2 - qcom,oryon-1-3 - qcom,oryon-1-4 + - qcom,oryon-1-5 - qcom,oryon-2-1 - qcom,oryon-2-2 - qcom,oryon-2-3 diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml index 5d033570b57b..26ebcf4565f3 100644 --- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml +++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml @@ -50,8 +50,8 @@ additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - firmware { - optee { + firmware { + optee { compatible = "linaro,optee-tz"; method = "smc"; interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>; @@ -59,8 +59,8 @@ examples: }; - | - firmware { - optee { + firmware { + optee { compatible = "linaro,optee-tz"; method = "hvc"; }; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0023cd126807..656f2596e1d5 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -688,7 +688,7 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul - - description: i.MX6UL Variscite VAR-SOM-MX6 Boards + - description: i.MX6UL Variscite VAR-SOM-6UL Boards items: - const: variscite,mx6ulconcerto - const: variscite,var-som-imx6ul @@ -797,6 +797,12 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL Variscite VAR-SOM-6UL Boards + items: + - const: variscite,mx6ullconcerto # Variscite VAR-SOM-6UL dev kit board + - const: variscite,var-som-imx6ull # Variscite VAR-SOM-6UL SoM (6ULL variant) + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: @@ -1025,6 +1031,7 @@ properties: - toradex,verdin-imx8mm-nonwifi-ivy # Verdin iMX8M Mini Module on Ivy - toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow - toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia + - toradex,verdin-imx8mm-nonwifi-zinnia # Verdin iMX8M Mini Module on Zinnia - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -1037,6 +1044,7 @@ properties: - toradex,verdin-imx8mm-wifi-ivy # Verdin iMX8M Mini Wi-Fi / BT Module on Ivy - toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow - toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia + - toradex,verdin-imx8mm-wifi-zinnia # Verdin iMX8M Mini Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -1056,6 +1064,12 @@ properties: - const: solidrun,imx8mm-sr-som - const: fsl,imx8mm + - description: Variscite DART-MX8MM based boards + items: + - const: variscite,var-dart-mx8mm-sonata # Variscite DART-MX8MM on Sonata Development Board + - const: variscite,var-dart-mx8mm # Variscite DART-MX8M-MINI SOM + - const: fsl,imx8mm + - description: Variscite VAR-SOM-MX8MM based boards items: - const: variscite,var-som-mx8mm-symphony @@ -1271,6 +1285,7 @@ properties: - toradex,verdin-imx8mp-nonwifi-ivy # Verdin iMX8M Plus Module on Ivy - toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow - toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia + - toradex,verdin-imx8mp-nonwifi-zinnia # Verdin iMX8M Plus Module on Zinnia - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -1283,6 +1298,7 @@ properties: - toradex,verdin-imx8mp-wifi-ivy # Verdin iMX8M Plus Wi-Fi / BT Module on Ivy - toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow - toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia + - toradex,verdin-imx8mp-wifi-zinnia # Verdin iMX8M Plus Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -1300,6 +1316,24 @@ properties: - const: tq,imx8mp-tqma8mpql # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM - const: fsl,imx8mp + - description: + TQMa8MPxS is a series of SOM featuring NXP i.MX8MP system-on-chip + variants. It has the SMARC-2.0 form factor and is designed to be + placed on different carrier boards. All CPU variants use the same + device tree hence only one compatible is needed. MB-SMARC-2 is a + carrier reference design. + items: + - enum: + - tq,imx8mp-tqma8mpqs-mb-smarc-2 # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM on MB-SMARC-2 + - const: tq,imx8mp-tqma8mpqs # TQ-Systems GmbH i.MX8MP TQMa8MPQS SOM + - const: fsl,imx8mp + + - description: Variscite DART-MX8M Plus based boards + items: + - const: variscite,var-dart-mx8mp-sonata # Variscite DART-MX8MP on Sonata Development Board + - const: variscite,var-dart-mx8mp # Variscite DART-MX8MP SOM + - const: fsl,imx8mp + - description: Variscite VAR-SOM-MX8M Plus based boards items: - const: variscite,var-som-mx8mp-symphony @@ -1359,6 +1393,12 @@ properties: - fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board - const: fsl,imx8qm + - description: i.MX8QM Variscite VAR-SOM-MX8 based Boards + items: + - const: variscite,var-som-imx8qm-symphony + - const: variscite,var-som-imx8qm + - const: fsl,imx8qm + - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules items: - enum: @@ -1394,6 +1434,13 @@ properties: - fsl,imx8dxl-evk # i.MX8DXL EVK Board - const: fsl,imx8dxl + - description: SolidRun i.MX8DXL SoM based boards + items: + - enum: + - solidrun,imx8dxl-hummingboard-telematics # SolidRun i.MX8DXL SoM EVK Board + - const: solidrun,imx8dxl-sr-som + - const: fsl,imx8dxl + - description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules items: - enum: @@ -1458,6 +1505,7 @@ properties: - description: i.MX91 based Boards items: - enum: + - fsl,imx91-9x9-qsb # i.MX91 9x9 QSB Board - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board - fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board - fsl,imx91-11x11-frdm-s # FRDM i.MX91S Development Board @@ -1482,9 +1530,11 @@ properties: - description: i.MX95 based Boards items: - enum: + - fsl,imx95-15x15-ab2 # i.MX95 15x15 Audio Board V2 - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - fsl,imx95-19x19-frdm-pro # i.MX95 19x19 FRDM PRO Board - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 @@ -1501,6 +1551,14 @@ properties: - const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC - const: fsl,imx95 + - description: Toradex Boards with Aquila iMX95 Modules + items: + - enum: + - toradex,aquila-imx95-clover # Aquila iMX95 Module on Clover Board + - toradex,aquila-imx95-dev # Aquila iMX95 Module on Aquila Development Board + - const: toradex,aquila-imx95 # Aquila iMX95 Module + - const: fsl,imx95 + - description: Toradex Boards with SMARC iMX95 Modules items: - const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board @@ -1515,6 +1573,7 @@ properties: - toradex,verdin-imx95-nonwifi-ivy # Verdin iMX95 Module on Ivy - toradex,verdin-imx95-nonwifi-mallow # Verdin iMX95 Module on Mallow - toradex,verdin-imx95-nonwifi-yavia # Verdin iMX95 Module on Yavia + - toradex,verdin-imx95-nonwifi-zinnia # Verdin iMX95 Module on Zinnia - const: toradex,verdin-imx95-nonwifi # Verdin iMX95 Module without Wi-Fi / BT - const: toradex,verdin-imx95 # Verdin iMX95 Module - const: fsl,imx95 @@ -1527,6 +1586,7 @@ properties: - toradex,verdin-imx95-wifi-ivy # Verdin iMX95 Wi-Fi / BT Module on Ivy - toradex,verdin-imx95-wifi-mallow # Verdin iMX95 Wi-Fi / BT Module on Mallow - toradex,verdin-imx95-wifi-yavia # Verdin iMX95 Wi-Fi / BT Module on Yavia + - toradex,verdin-imx95-wifi-zinnia # Verdin iMX95 Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx95-wifi # Verdin iMX95 Wi-Fi / BT Module - const: toradex,verdin-imx95 # Verdin iMX95 Module - const: fsl,imx95 @@ -1559,11 +1619,13 @@ properties: in the assembled SOC. MBa91xxCA mainboard can be used as starterkit for the SOM soldered on an adapter board or for the connector variant - MBa91xxLA mainboard is a single board computer using the solderable - SOM variant + to demonstrate parallel display and majority of interfaces while + MBa93xxCA starterkit mainboard is focused on communication + interfaces without display support. items: - enum: - tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa91xxCA + - tq,imx91-tqma9131-mba93xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa93xxCA - const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM - const: fsl,imx91 @@ -1614,6 +1676,18 @@ properties: - const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM - const: fsl,imx91 + - description: Variscite VAR-SOM-MX91 based boards + items: + - const: variscite,var-som-mx91-symphony # Variscite VAR-SOM-MX91 on Symphony + - const: variscite,var-som-mx91 # Variscite VAR-SOM-MX91 + - const: fsl,imx91 + + - description: Variscite DART-MX93 based boards + items: + - const: variscite,var-dart-mx93-sonata # Variscite DART-MX93 on Sonata Development Board + - const: variscite,var-dart-mx93 # Variscite DART-MX93 SOM + - const: fsl,imx93 + - description: Variscite VAR-SOM-MX93 based boards items: - const: variscite,var-som-mx93-symphony @@ -1868,6 +1942,7 @@ properties: - enum: - solidrun,clearfog-cx - solidrun,honeycomb + - solidrun,twins-single - const: solidrun,lx2160a-cex7 - const: fsl,lx2160a diff --git a/Documentation/devicetree/bindings/arm/gemini.yaml b/Documentation/devicetree/bindings/arm/gemini.yaml index fc092962ab56..dfb11244b57e 100644 --- a/Documentation/devicetree/bindings/arm/gemini.yaml +++ b/Documentation/devicetree/bindings/arm/gemini.yaml @@ -55,6 +55,11 @@ properties: - const: itian,sq201 - const: cortina,gemini + - description: Raidsonic NAS IB-4210-B + items: + - const: raidsonic,ib-4210-b + - const: cortina,gemini + - description: Raidsonic NAS IB-4220-B items: - const: raidsonic,ib-4220-b @@ -70,6 +75,11 @@ properties: - const: teltonika,rut1xx - const: cortina,gemini + - description: Verbatim S08V1901-D1 NAS + items: + - const: verbatim,s08v1901-d1 + - const: cortina,gemini + - description: Wiligear Wiliboard WBD-111 items: - const: wiligear,wiliboard-wbd111 diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 382d0eb4d0af..cd4040ad3437 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -314,7 +314,7 @@ properties: - const: google,steelix-sku196608 - const: google,steelix - const: mediatek,mt8186 - - description: Google Squirtle (Acer Chromebook Spin 311 (R724T) + - description: Google Squirtle (Acer Chromebook Spin 311 (R724T)) items: - const: google,squirtle - const: mediatek,mt8186 diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt deleted file mode 100644 index a43e4c7aba3d..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ /dev/null @@ -1,55 +0,0 @@ -Some socs have a large number of interrupts requests to service -the needs of its many peripherals and subsystems. All of the -interrupt lines from the subsystems are not needed at the same -time, so they have to be muxed to the irq-controller appropriately. -In such places a interrupt controllers are preceded by an CROSSBAR -that provides flexibility in muxing the device requests to the controller -inputs. - -Required properties: -- compatible : Should be "ti,irq-crossbar" -- reg: Base address and the size of the crossbar registers. -- interrupt-controller: indicates that this block is an interrupt controller. -- ti,max-irqs: Total number of irqs available at the parent interrupt controller. -- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. -- ti,reg-size: Size of a individual register in bytes. Every individual - register is assumed to be of same size. Valid sizes are 1, 2, 4. -- ti,irqs-reserved: List of the reserved irq lines that are not muxed using - crossbar. These interrupt lines are reserved in the soc, - so crossbar bar driver should not consider them as free - lines. - -Optional properties: -- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for - SOC-specific hard-wiring of those irqs which unexpectedly bypasses the - crossbar. These irqs have a crossbar register, but still cannot be used. - -- ti,irqs-safe-map: integer which maps to a safe configuration to use - when the interrupt controller irq is unused (when not provided, default is 0) - -Examples: - crossbar_mpu: crossbar@4a002a48 { - compatible = "ti,irq-crossbar"; - reg = <0x4a002a48 0x130>; - ti,max-irqs = <160>; - ti,max-crossbar-sources = <400>; - ti,reg-size = <2>; - ti,irqs-reserved = <0 1 2 3 5 6 131 132>; - ti,irqs-skip = <10 133 139 140>; - }; - -Consumer: -======== -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and -Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for -further details. - -An interrupt consumer on an SoC using crossbar will use: - interrupts = <GIC_SPI request_number interrupt_level> - -Example: - device_x@4a023000 { - /* Crossbar 8 used */ - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - ... - }; diff --git a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt deleted file mode 100644 index 8bd6d0a238a8..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/dmm.txt +++ /dev/null @@ -1,22 +0,0 @@ -OMAP Dynamic Memory Manager (DMM) bindings - -The dynamic memory manager (DMM) is a module located immediately in front of the -SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory -accesses such as priority generation amongst initiators, configuration of SDRAM -interleaving, optimizing transfer of 2D block objects, and provide MMU-like page -translation for initiators which need contiguous dma bus addresses. - -Required properties: -- compatible: Should contain "ti,omap4-dmm" for OMAP4 family - Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family -- reg: Contains DMM register address range (base address and length) -- interrupts: Should contain an interrupt-specifier for DMM_IRQ. -- ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm" - -Example: - -dmm@4e000000 { - compatible = "ti,omap4-dmm"; - reg = <0x4e000000 0x800>; - ti,hwmods = "dmm"; -}; diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt deleted file mode 100644 index 6816adcdc15f..000000000000 --- a/Documentation/devicetree/bindings/arm/omap/l4.txt +++ /dev/null @@ -1,37 +0,0 @@ -L4 interconnect bindings - -These bindings describe the OMAP SoCs L4 interconnect bus. - -Required properties: -- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus - Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus - Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus - Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus - Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus - Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus - Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus - Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus - Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus - Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus - Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus - Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus -- ranges : contains the IO map range for the bus -- reg : registers link agent and interconnect agent and access protection -- reg-names : "la" for link agent, "ia0" to "ia3" for one to three - interconnect agent instances, "ap" for access if it exists - -Examples: - -l4: interconnect@48000000 { - compatible "ti,omap4-l4-per", "simple-bus"; - reg = <0x48000000 0x800>, - <0x48000800 0x800>, - <0x48001000 0x400>, - <0x48001400 0x400>, - <0x48001800 0x400>, - <0x48001c00 0x400>; - reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48000000 0x100000>; -}; diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 6e2e0c551841..0d04389c81fa 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -146,12 +146,12 @@ examples: // Case 1: PSCI v0.1 only. psci { - compatible = "arm,psci"; - method = "smc"; - cpu_suspend = <0x95c10000>; - cpu_off = <0x95c10001>; - cpu_on = <0x95c10002>; - migrate = <0x95c10003>; + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x95c10000>; + cpu_off = <0x95c10001>; + cpu_on = <0x95c10002>; + migrate = <0x95c10003>; }; - |+ @@ -159,8 +159,8 @@ examples: // Case 2: PSCI v0.2 only psci { - compatible = "arm,psci-0.2"; - method = "smc"; + compatible = "arm,psci-0.2"; + method = "smc"; }; - |+ @@ -251,7 +251,7 @@ examples: cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; - domain-idle-states = <&cpu_pwrdn>; + domain-idle-states = <&cpu_pwrdn>; power-domains = <&cluster_pd>; }; diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index e002f87361ad..f3f3feac4ce2 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -29,7 +29,11 @@ properties: oneOf: - items: - enum: + - qcom,glymur-ctcu + - qcom,kaanapali-ctcu - qcom,qcs8300-ctcu + - qcom,sm8750-ctcu + - qcom,x1e80100-ctcu - const: qcom,sa8775p-ctcu - enum: - qcom,sa8775p-ctcu diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml index ef648a15b806..37147124449e 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml @@ -82,7 +82,7 @@ additionalProperties: false examples: - | - tn@109ab000 { + tn@109ab000 { compatible = "qcom,coresight-tnoc", "arm,primecell"; reg = <0x109ab000 0x4200>; diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index 152403f548c3..c7301f1b28c1 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -9,7 +9,7 @@ title: Trace, Profiling and Diagnostics Monitor - TPDM description: | The TPDM or Monitor serves as data collection component for various dataset - types specified in the QPMDA spec. It covers Implementation defined ((ImplDef), + types specified in the QPMDA spec. It covers Implementation defined (ImplDef), Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete Single Bit (DSB). It performs data collection in the data producing clock domain and transfers it to the data collection time domain, generally ATB diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index 27261039d56f..e7160b63d814 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -11,10 +11,10 @@ maintainers: description: | Guidelines for new compatibles for SoC blocks/components. - When adding new compatibles in new bindings, use the format:: + When adding new compatibles in new bindings, use the format: qcom,SoC-IP - For example:: + For example: qcom,sdm845-llcc-bwmon When adding new compatibles to existing bindings, use the format in the @@ -22,49 +22,69 @@ description: | select: properties: + # Select all nodes which have SoC-based compatibles, but not the root + # "/" node, because its front compatibles do not follow any SoC patterns + $nodename: + pattern: "[^/]" compatible: - oneOf: - - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,.*(glymur|milos).*$" + contains: + oneOf: + - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,.*(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra).*$" required: - compatible properties: compatible: - oneOf: - # Preferred naming style for compatibles of SoC components: - - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" - - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" - - pattern: "^qcom,(glymur|milos)-.*$" + contains: + anyOf: + # Preferred naming style for compatibles of SoC components: + - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" + - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" + - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" + - pattern: "^qcom,(eliza|kaanapali|glymur|hawi|mahua|maili|milos|nord|shikra)-.+$" - # Legacy namings - variations of existing patterns/compatibles are OK, - # but do not add completely new entries to these: - - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" - - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" - - enum: - - qcom,dsi-ctrl-6g-qcm2290 - - qcom,gpucc-sdm630 - - qcom,gpucc-sdm660 - - qcom,lcc-apq8064 - - qcom,lcc-ipq8064 - - qcom,lcc-mdm9615 - - qcom,lcc-msm8960 - - qcom,lpass-cpu-apq8016 - - qcom,usb-ss-ipq4019-phy - - qcom,usb-hs-ipq4019-phy - - qcom,vqmmc-ipq4019-regulator + # Legacy namings - variations of existing patterns/compatibles are OK, + # but do not add completely new entries to these: + - pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,apss-wdt-[a-z]+$" # Codenames variant + - pattern: "^qcom,kpss-gcc-(apq|ipq|mdm|msm)[0-9]+.*$" + - pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,rpmcc-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm)[0-9]+.*$" + - pattern: "^qcom,rpm(cc)?-[a-z]+$" # Codenames variant + - pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sar?|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,scm-[a-z]+$" # Codenames variant + - pattern: "^qcom,tcsr-(apq|ipq|mdm|msm)[0-9]+.*$" + - pattern: "^qcom,usb-hs-phy-(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - enum: + - qcom,dsi-ctrl-6g-qcm2290 + - qcom,gpucc-sdm630 + - qcom,gpucc-sdm660 + - qcom,lcc-apq8064 + - qcom,lcc-ipq8064 + - qcom,lcc-mdm9615 + - qcom,lcc-msm8960 + - qcom,lpass-cpu-apq8016 + - qcom,usb-hs-ipq4019-phy + - qcom,usb-hsic-phy-mdm9615 + - qcom,usb-hsic-phy-msm8974 + - qcom,usb-ss-ipq4019-phy + - qcom,vqmmc-ipq4019-regulator - # Legacy compatibles with wild-cards - list cannot grow with new bindings: - - enum: - - qcom,ipq806x-gmac - - qcom,ipq806x-nand - - qcom,ipq806x-sata-phy - - qcom,ipq806x-usb-phy-ss - - qcom,ipq806x-usb-phy-hs + # Legacy compatibles with wild-cards - list cannot grow with new bindings: + - enum: + - qcom,ipq806x-ahci + - qcom,ipq806x-gmac + - qcom,ipq806x-nand + - qcom,ipq806x-sata-phy + - qcom,ipq806x-usb-phy-ss + - qcom,ipq806x-usb-phy-hs + + # In general non-SoC Qualcomm devices do not need to be listed here, + # however in a few cases they got selected by patterns in "select": + - pattern: "^qcom,wsa[0-9]+$" additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b4943123d2e4..ff8a35df7862 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -51,123 +51,174 @@ properties: - items: - enum: - - qcom,apq8060-dragonboard - - qcom,msm8660-surf - - const: qcom,msm8660 - - - items: - - enum: - qcom,apq8084-mtp - qcom,apq8084-sbc - const: qcom,apq8084 - items: + - const: qcom,eliza-cqs-evk + - const: qcom,eliza-cqs-som + - const: qcom,eliza + + - items: + - enum: + - sony,karin_windy + - const: qcom,apq8094 + + - items: + - enum: + - arrow,apq8096-db820c + - inforce,ifc6640 + - const: qcom,apq8096-sbc + - const: qcom,apq8096 + + - items: + - const: arrow,apq8096sg-db820c + - const: arrow,apq8096-db820c + - const: qcom,apq8096-sbc + - const: qcom,apq8096sg + - const: qcom,apq8096 + + - items: - enum: - qcom,eliza-mtp - const: qcom,eliza - items: - enum: + - asus,zenbook-a16-ux3607oa - qcom,glymur-crd - const: qcom,glymur - items: - enum: - - qcom,mahua-crd - - const: qcom,mahua + - 8dev,jalapeno + - alfa-network,ap120c-ac + - const: qcom,ipq4018 - items: - enum: - - fairphone,fp6 - - const: qcom,milos + - qcom,ipq4019-ap-dk01.1-c1 + - qcom,ipq4019-ap-dk04.1-c3 + - qcom,ipq4019-ap-dk07.1-c1 + - qcom,ipq4019-ap-dk07.1-c2 + - qcom,ipq4019-dk04.1-c1 + - const: qcom,ipq4019 - items: - enum: - - microsoft,dempsey - - microsoft,makepeace - - microsoft,moneypenny - - motorola,falcon - - samsung,ms013g - - samsung,s3ve3g - - const: qcom,msm8226 + - qcom,ipq5018-rdp432-c2 + - tplink,archer-ax55-v1 + - const: qcom,ipq5018 - items: - enum: - - htc,memul - - microsoft,superman-lte - - microsoft,tesla - - motorola,peregrine - - samsung,matisselte - - const: qcom,msm8926 - - const: qcom,msm8226 + - qcom,ipq5210-rdp504 + - const: qcom,ipq5210 - items: - enum: - - wingtech,wt82918hd - - const: qcom,msm8929 + - qcom,ipq5332-ap-mi01.2 + - qcom,ipq5332-ap-mi01.3 + - qcom,ipq5332-ap-mi01.6 + - qcom,ipq5332-ap-mi01.9 + - const: qcom,ipq5332 - items: - enum: - - asus,z00t - - huawei,kiwi - - longcheer,l9100 - - samsung,a7 - - sony,kanuti-tulip - - square,apq8039-t2 - - wingtech,wt82918 - - wingtech,wt82918hdhw39 - - const: qcom,msm8939 + - qcom,ipq5424-rdp466 + - const: qcom,ipq5424 - items: - enum: - - sony,kugo-row - - sony,suzu-row - - const: qcom,msm8956 + - qcom,ipq6018-cp01 + - qcom,ipq6018-cp01-c1 + - const: qcom,ipq6018 - items: - enum: - - qcom,msm8960-cdp - - samsung,expressatt - - const: qcom,msm8960 + - mikrotik,rb3011 + - qcom,ipq8064-ap148 + - const: qcom,ipq8064 - items: - enum: - - sony,huashan - - const: qcom,msm8960t - - const: qcom,msm8960 + - qcom,ipq8074-hk01 + - qcom,ipq8074-hk10-c1 + - qcom,ipq8074-hk10-c2 + - const: qcom,ipq8074 - items: - enum: - - lge,hammerhead - - samsung,hlte - - sony,xperia-amami - - sony,xperia-honami - - sony,xperia-togari - - const: qcom,msm8974 + - qcom,ipq9574-ap-al02-c2 + - qcom,ipq9574-ap-al02-c2-emmc + - qcom,ipq9574-ap-al02-c6 + - qcom,ipq9574-ap-al02-c7 + - qcom,ipq9574-ap-al02-c7-emmc + - qcom,ipq9574-ap-al02-c8 + - qcom,ipq9574-ap-al02-c9 + - const: qcom,ipq9574 - items: - enum: - - fairphone,fp2 - - htc,m8 - - oneplus,bacon - - samsung,klte - - sony,xperia-aries - - sony,xperia-castor - - sony,xperia-leo - - const: qcom,msm8974pro - - const: qcom,msm8974 + - qcom,ipq9650-rdp488 + - const: qcom,ipq9650 - items: - enum: - - samsung,kltechn - - const: samsung,klte - - const: qcom,msm8974pro - - const: qcom,msm8974 + - qcom,hawi-mtp + - const: qcom,hawi - items: - enum: - - longcheer,l9360 - - const: qcom,msm8976 + - qcom,kaanapali-mtp + - qcom,kaanapali-qrd + - const: qcom,kaanapali + + - items: + - enum: + - qcom,mahua-crd + - const: qcom,mahua + + - description: Sierra Wireless MangOH Green with WP8548 Module + items: + - const: swir,mangoh-green-wp8548 + - const: swir,wp8548 + - const: qcom,mdm9615 + + - items: + - enum: + - fairphone,fp6 + - nothing,asteroids + - const: qcom,milos + + - items: + - enum: + - microsoft,dempsey + - microsoft,makepeace + - microsoft,moneypenny + - motorola,falcon + - motorola,titan + - samsung,ms013g + - samsung,s3ve3g + - const: qcom,msm8226 + + - items: + - enum: + - htc,memul + - microsoft,superman-lte + - microsoft,tesla + - motorola,peregrine + - samsung,matisselte + - sony,eagle + - const: qcom,msm8926 + - const: qcom,msm8226 + + - items: + - enum: + - qcom,apq8060-dragonboard + - qcom,msm8660-surf + - const: qcom,msm8660 - items: - enum: @@ -218,11 +269,28 @@ properties: - items: - enum: + - wingtech,wt82918hd + - const: qcom,msm8929 + + - items: + - enum: - xiaomi,land - const: qcom,msm8937 - items: - enum: + - asus,z00t + - huawei,kiwi + - longcheer,l9100 + - samsung,a7 + - sony,kanuti-tulip + - square,apq8039-t2 + - wingtech,wt82918 + - wingtech,wt82918hdhw39 + - const: qcom,msm8939 + + - items: + - enum: - flipkart,rimob - motorola,potter - xiaomi,daisy @@ -233,6 +301,57 @@ properties: - items: - enum: + - sony,kugo-row + - sony,suzu-row + - const: qcom,msm8956 + + - items: + - enum: + - qcom,msm8960-cdp + - samsung,expressatt + - const: qcom,msm8960 + + - items: + - enum: + - sony,huashan + - const: qcom,msm8960t + - const: qcom,msm8960 + + - items: + - enum: + - lge,hammerhead + - samsung,hlte + - sony,xperia-amami + - sony,xperia-honami + - sony,xperia-togari + - const: qcom,msm8974 + + - items: + - enum: + - fairphone,fp2 + - htc,m8 + - oneplus,bacon + - samsung,klte + - sony,xperia-aries + - sony,xperia-castor + - sony,xperia-leo + - const: qcom,msm8974pro + - const: qcom,msm8974 + + - items: + - enum: + - samsung,kltechn + - const: samsung,klte + - const: qcom,msm8974pro + - const: qcom,msm8974 + + - items: + - enum: + - longcheer,l9360 + - const: qcom,msm8976 + + - items: + - enum: - lg,bullhead - lg,h815 - microsoft,talkman @@ -241,11 +360,6 @@ properties: - items: - enum: - - sony,karin_windy - - const: qcom,apq8094 - - - items: - - enum: - huawei,angler - microsoft,cityman - sony,ivy-row @@ -257,20 +371,6 @@ properties: - items: - enum: - - arrow,apq8096-db820c - - inforce,ifc6640 - - const: qcom,apq8096-sbc - - const: qcom,apq8096 - - - items: - - const: arrow,apq8096sg-db820c - - const: arrow,apq8096-db820c - - const: qcom,apq8096-sbc - - const: qcom,apq8096sg - - const: qcom,apq8096 - - - items: - - enum: - oneplus,oneplus3 - oneplus,oneplus3t - qcom,msm8996-mtp @@ -302,81 +402,6 @@ properties: - xiaomi,sagit - const: qcom,msm8998 - - items: - - enum: - - 8dev,jalapeno - - alfa-network,ap120c-ac - - const: qcom,ipq4018 - - - items: - - enum: - - qcom,ipq4019-ap-dk01.1-c1 - - qcom,ipq4019-ap-dk04.1-c3 - - qcom,ipq4019-ap-dk07.1-c1 - - qcom,ipq4019-ap-dk07.1-c2 - - qcom,ipq4019-dk04.1-c1 - - const: qcom,ipq4019 - - - items: - - enum: - - qcom,ipq5018-rdp432-c2 - - tplink,archer-ax55-v1 - - const: qcom,ipq5018 - - - items: - - enum: - - qcom,ipq5210-rdp504 - - const: qcom,ipq5210 - - - items: - - enum: - - qcom,ipq5332-ap-mi01.2 - - qcom,ipq5332-ap-mi01.3 - - qcom,ipq5332-ap-mi01.6 - - qcom,ipq5332-ap-mi01.9 - - const: qcom,ipq5332 - - - items: - - enum: - - qcom,ipq5424-rdp466 - - const: qcom,ipq5424 - - - items: - - enum: - - mikrotik,rb3011 - - qcom,ipq8064-ap148 - - const: qcom,ipq8064 - - - items: - - enum: - - qcom,ipq8074-hk01 - - qcom,ipq8074-hk10-c1 - - qcom,ipq8074-hk10-c2 - - const: qcom,ipq8074 - - - items: - - enum: - - qcom,ipq9574-ap-al02-c2 - - qcom,ipq9574-ap-al02-c2-emmc - - qcom,ipq9574-ap-al02-c6 - - qcom,ipq9574-ap-al02-c7 - - qcom,ipq9574-ap-al02-c7-emmc - - qcom,ipq9574-ap-al02-c8 - - qcom,ipq9574-ap-al02-c9 - - const: qcom,ipq9574 - - - items: - - enum: - - qcom,kaanapali-mtp - - qcom,kaanapali-qrd - - const: qcom,kaanapali - - - description: Sierra Wireless MangOH Green with WP8548 Module - items: - - const: swir,mangoh-green-wp8548 - - const: swir,wp8548 - - const: qcom,mdm9615 - - description: Qualcomm Technologies, Inc. Robotics RB1 items: - enum: @@ -395,8 +420,23 @@ properties: - shift,otter - thundercomm,minipc-g1iot - thundercomm,rubikpi3 + - vicharak,axon-mini - const: qcom,qcm6490 + - items: + - enum: + - qcom,qcs404-evb-1000 + - qcom,qcs404-evb-4000 + - const: qcom,qcs404-evb + - const: qcom,qcs404 + + - items: + - enum: + - arduino,monza + - qcom,monaco-evk + - qcom,qcs8300-ride + - const: qcom,qcs8300 + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform items: - enum: @@ -410,6 +450,31 @@ properties: - qcom,qru1000-idp - const: qcom,qru1000 + - items: + - enum: + - qcom,sa8155p-adp + - const: qcom,sa8155p + + - items: + - enum: + - qcom,sa8295p-adp + - qcom,sa8540p-ride + - const: qcom,sa8540p + + - items: + - enum: + - qcom,sa8775p-ride + - qcom,sa8775p-ride-r3 + - const: qcom,sa8775p + + - items: + - enum: + - qcom,lemans-evk + - qcom,qcs9100-ride + - qcom,qcs9100-ride-r3 + - const: qcom,qcs9100 + - const: qcom,sa8775p + - description: Qualcomm AR2 Gen1 platform items: - enum: @@ -841,6 +906,11 @@ properties: - items: - enum: + - inforce,ifc6560 + - const: qcom,sda660 + + - items: + - enum: - lenovo,tbx605f - motorola,ali - const: qcom,sdm450 @@ -855,11 +925,6 @@ properties: - items: - enum: - - inforce,ifc6560 - - const: qcom,sda660 - - - items: - - enum: - fairphone,fp3 - motorola,ocean - const: qcom,sdm632 @@ -885,74 +950,13 @@ properties: - const: google,bonito - const: qcom,sdm670 - - items: - - enum: - - qcom,sdx55-mtp - - qcom,sdx55-telit-fn980-tlb - - qcom,sdx55-t55 - - const: qcom,sdx55 - - - items: - - enum: - - qcom,sdx65-mtp - - const: qcom,sdx65 - - - items: - - enum: - - qcom,sdx75-idp - - const: qcom,sdx75 - - - items: - - enum: - - qcom,ipq6018-cp01 - - qcom,ipq6018-cp01-c1 - - const: qcom,ipq6018 - - - items: - - enum: - - qcom,qcs404-evb-1000 - - qcom,qcs404-evb-4000 - - const: qcom,qcs404-evb - - const: qcom,qcs404 - - - items: - - enum: - - arduino,monza - - qcom,monaco-evk - - qcom,qcs8300-ride - - const: qcom,qcs8300 - - - items: - - enum: - - qcom,qcs615-ride - - qcom,talos-evk - - const: qcom,qcs615 - - const: qcom,sm6150 - - - items: - - enum: - - qcom,sa8155p-adp - - const: qcom,sa8155p - - - items: - - enum: - - qcom,sa8295p-adp - - qcom,sa8540p-ride - - const: qcom,sa8540p - - - items: - - enum: - - qcom,sa8775p-ride - - qcom,sa8775p-ride-r3 - - const: qcom,sa8775p - - - items: + - description: Xiaomi Poco F1 + items: - enum: - - qcom,lemans-evk - - qcom,qcs9100-ride - - qcom,qcs9100-ride-r3 - - const: qcom,qcs9100 - - const: qcom,sa8775p + - xiaomi,beryllium-ebbg + - xiaomi,beryllium-tianma + - const: xiaomi,beryllium + - const: qcom,sdm845 - items: - enum: @@ -972,13 +976,46 @@ properties: - sony,akatsuki-row - sony,apollo-row - thundercomm,db845c - - xiaomi,beryllium - - xiaomi,beryllium-ebbg - xiaomi,polaris - const: qcom,sdm845 - items: - enum: + - qcom,shikra-cqm-evk + - const: qcom,shikra-cqm-som + - const: qcom,shikra + + - items: + - enum: + - qcom,shikra-cqs-evk + - const: qcom,shikra-cqs-som + - const: qcom,shikra + + - items: + - enum: + - qcom,shikra-iqs-evk + - const: qcom,shikra-iqs-som + - const: qcom,shikra + + - items: + - enum: + - qcom,sdx55-mtp + - qcom,sdx55-telit-fn980-tlb + - qcom,sdx55-t55 + - const: qcom,sdx55 + + - items: + - enum: + - qcom,sdx65-mtp + - const: qcom,sdx65 + + - items: + - enum: + - qcom,sdx75-idp + - const: qcom,sdx75 + + - items: + - enum: - oneplus,billie2 - const: qcom,sm4250 @@ -1014,6 +1051,13 @@ properties: - items: - enum: + - qcom,qcs615-ride + - qcom,talos-evk + - const: qcom,qcs615 + - const: qcom,sm6150 + + - items: + - enum: - sony,pdx213 - const: qcom,sm6350 @@ -1040,7 +1084,9 @@ properties: - items: - enum: + - motorola,dubai - nothing,spacewar + - xiaomi,taoyao - const: qcom,sm7325 - items: @@ -1094,6 +1140,13 @@ properties: - items: - enum: + - imdt,qcs8550-sbc + - const: imdt,qcs8550-som + - const: qcom,qcs8550 + - const: qcom,sm8550 + + - items: + - enum: - qcom,qcs8550-aim300-aiot - const: qcom,qcs8550-aim300 - const: qcom,qcs8550 @@ -1101,6 +1154,12 @@ properties: - items: - enum: + - qcom,qcs8550-rb5gen2 + - const: qcom,qcs8550 + - const: qcom,sm8550 + + - items: + - enum: - ayaneo,pocket-s2 - qcom,sm8650-hdk - qcom,sm8650-mtp @@ -1147,6 +1206,7 @@ properties: - dell,inspiron-14-plus-7441 - dell,latitude-7455 - dell,xps13-9345 + - honor,magicbook-art-14-snapdragon - hp,elitebook-ultra-g1q - hp,omnibook-x14 - lenovo,ideacentre-mini-01q8x10 @@ -1169,6 +1229,10 @@ properties: - const: qcom,x1e80100 - items: + - const: microsoft,surface-pro-12in + - const: qcom,x1p42100 + + - items: - enum: - qcom,purwa-iot-evk - const: qcom,purwa-iot-som @@ -1198,7 +1262,7 @@ properties: items: items: - description: | - MSM chipset ID - an exact match value consisting of two bitfields:: + MSM chipset ID - an exact match value consisting of two bitfields: - bits 0-15 - The unique MSM chipset ID - bits 16-31 - Reserved; should be 0 - description: | @@ -1224,7 +1288,7 @@ properties: - items: - items: - description: | - Board ID consisting of three bitfields:: + Board ID consisting of three bitfields: - bits 31-24 - Unused - bits 23-16 - Platform Version Major - bits 15-8 - Platform Version Minor diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 1a9dde18626d..a799bb843f74 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -66,11 +66,24 @@ properties: - anbernic,rg-ds - const: rockchip,rk3568 + - description: Anbernic RK3576 Handheld Gaming Console + items: + - enum: + - anbernic,rg-vita-pro + - const: rockchip,rk3576 + - description: Ariaboard Photonicat items: - const: ariaboard,photonicat - const: rockchip,rk3568 + - description: ArmSoM CM5 Module based boards + items: + - enum: + - armsom,cm5-io + - const: armsom,cm5 + - const: rockchip,rk3576 + - description: ArmSoM Sige1 board items: - const: armsom,sige1 @@ -162,6 +175,13 @@ properties: - const: coolpi,pi-4b - const: rockchip,rk3588s + - description: Alientek CLRV1126F SoM based boards + items: + - enum: + - alientek,dlrv1126 + - const: alientek,clrv1126f + - const: rockchip,rv1126 + - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards items: - const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board @@ -191,6 +211,11 @@ properties: - const: embedfire,lubancat-2 - const: rockchip,rk3568 + - description: EmbedFire LubanCat 4 + items: + - const: embedfire,lubancat-4 + - const: rockchip,rk3588s + - description: Engicam PX30.Core C.TOUCH 2.0 items: - const: engicam,px30-core-ctouch2 @@ -684,6 +709,12 @@ properties: - const: google,veyron - const: rockchip,rk3288 + - description: Graperain G3568 series board + items: + - enum: + - graperain,g3568-v2 + - const: rockchip,rk3568 + - description: H96 Max V58 TV Box items: - const: haochuangyi,h96-max-v58 @@ -724,6 +755,11 @@ properties: - const: hardkernel,odroid-m2 - const: rockchip,rk3588s + - description: HINLINK H28K + items: + - const: hinlink,h28k + - const: rockchip,rk3528 + - description: HINLINK H66K / H68K items: - enum: @@ -779,6 +815,16 @@ properties: - const: lckfb,tspi-rk3566 - const: rockchip,rk3566 + - description: LCKFB Taishan Pi 3M RK3576 + items: + - const: lckfb,tspi-3m-rk3576 + - const: rockchip,rk3576 + + - description: LincPlus LincStation E1 + items: + - const: techvision,tvd8322r + - const: rockchip,rk3568 + - description: LinkEase EasePi R1 items: - const: linkease,easepi-r1 @@ -1306,6 +1352,21 @@ properties: - const: turing,rk1 - const: rockchip,rk3588 + - description: Vicharak Axon + items: + - const: vicharak,axon + - const: rockchip,rk3588 + + - description: Vicharak Vaaman + items: + - const: vicharak,vaaman + - const: rockchip,rk3399 + + - description: Vicharak Vaaman2 + items: + - const: vicharak,vaaman2 + - const: rockchip,rk3588 + - description: WolfVision PF5 mainboard items: - const: wolfvision,rk3568-pf5 @@ -1338,6 +1399,7 @@ properties: items: - enum: - xunlong,orangepi-5 + - xunlong,orangepi-5-pro - xunlong,orangepi-5b - const: rockchip,rk3588s @@ -1347,6 +1409,11 @@ properties: - const: xunlong,orangepi-cm5 - const: rockchip,rk3588s + - description: Youyeetoo YY3588 + items: + - const: youyeetoo,yy3588 + - const: rockchip,rk3588 + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml index 55b2200d6e75..1cff2328cd01 100644 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -61,7 +61,13 @@ properties: type: object reboot-mode: - type: object + $ref: /schemas/power/reset/syscon-reboot-mode.yaml + unevaluatedProperties: false + + patternProperties: + # Negative look-ahead to disallow unsupported modes. The '$' has to be + # part of lookahead group to work, instead of trailing outside of (). + "^mode-(?!(bootloader$|loader$|normal$|recovery$))": false required: - compatible diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 753b3ba1b607..273464400477 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -235,6 +235,12 @@ properties: - winlink,e850-96 # WinLink E850-96 - const: samsung,exynos850 + - description: Exynos8855 based boards + items: + - enum: + - samsung,exynos8855-smdk # Samsung SMDK + - const: samsung,exynos8855 + - description: Exynos8895 based boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml index 653f85997643..ab000befe76d 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml @@ -11,10 +11,10 @@ maintainers: description: | Guidelines for new compatibles for SoC blocks/components. - When adding new compatibles in new bindings, use the format:: + When adding new compatibles in new bindings, use the format: samsung,SoC-IP - For example:: + For example: samsung,exynos5433-cmu-isp select: diff --git a/Documentation/devicetree/bindings/arm/st,nomadik.yaml b/Documentation/devicetree/bindings/arm/st,nomadik.yaml new file mode 100644 index 000000000000..d2167908ff60 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/st,nomadik.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/st,nomadik.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST Nomadik SoC based Boards + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: + Boards using the Nomadik SoC platform + +properties: + $nodename: + const: '/' + compatible: + enum: + - st,nomadik-nhk-15 + - calaosystems,usb-s8815 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt deleted file mode 100644 index 2fdff5a806cf..000000000000 --- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt +++ /dev/null @@ -1,38 +0,0 @@ -ST-Ericsson Nomadik Device Tree Bindings - -For various board the "board" node may contain specific properties -that pertain to this particular board, such as board-specific GPIOs. - -Required root node property: src -- Nomadik System and reset controller used for basic chip control, clock - and reset line control. -- compatible: must be "stericsson,nomadik,src" - -Boards with the Nomadik SoC include: - -Nomadik NHK-15 board manufactured by ST Microelectronics: - -Required root node property: - -compatible="st,nomadik-nhk-15"; - -S8815 "MiniKit" manufactured by Calao Systems: - -Required root node property: - -compatible="calaosystems,usb-s8815"; - -Required node: usb-s8815 - -Example: - -usb-s8815 { - ethernet-gpio { - gpios = <&gpio3 19 0x1>; - interrupts = <19 0x1>; - interrupt-parent = <&gpio3>; - }; - mmcsd-gpio { - gpios = <&gpio3 16 0x1>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index e6443c266fa1..f04db28c630a 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -96,6 +96,12 @@ properties: - const: allwinner,ba10-tvbox - const: allwinner,sun4i-a10 + - description: Baijie A133 HelperBoard + items: + - const: baijie,helperboard-a133 + - const: baijie,helperboard-a133-core + - const: allwinner,sun50i-a100 + - description: BananaPi items: - const: lemaker,bananapi @@ -598,6 +604,7 @@ properties: - description: NetCube Systems Nagami SoM based boards items: - enum: + - netcube,dobermann - netcube,nagami-basic-carrier - netcube,nagami-keypad-carrier - const: netcube,nagami diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 033a63f6c068..a54d0024e636 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -268,6 +268,11 @@ properties: items: - const: nvidia,p3509-0000+p3668-0001 - const: nvidia,tegra194 + - description: Lenovo ThinkEdge SE70 + items: + - const: lenovo,thinkedge-se70 + - const: nvidia,p3668-0001 + - const: nvidia,tegra194 - items: - const: nvidia,tegra234-vdk - const: nvidia,tegra234 diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml index dcd1c5376507..dd1f637e4175 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -16,6 +16,7 @@ properties: - nvidia,tegra186-pmc - nvidia,tegra194-pmc - nvidia,tegra234-pmc + - nvidia,tegra238-pmc - nvidia,tegra264-pmc reg: @@ -76,6 +77,7 @@ allOf: contains: enum: - nvidia,tegra234-pmc + - nvidia,tegra238-pmc - nvidia,tegra264-pmc then: properties: diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 2a6a9441c23d..eebb3523303c 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -40,6 +40,7 @@ properties: - description: K3 AM62L3 SoC and Boards items: - enum: + - beagle,am62l3-beaglebadge - ti,am62l3-evm - const: ti,am62l3 @@ -97,6 +98,19 @@ properties: - const: toradex,verdin-am62 # Verdin AM62 Module - const: ti,am625 + - description: K3 AM625 SoC on TQ-Systems TQMa62xx SoM + items: + - enum: + - tq,am625-tqma6254-mba62xx # MBa62xx base board + - const: tq,am625-tqma6254 + - const: ti,am625 + + - description: K3 AM625 SoC Variscite SOM and Carrier Boards + items: + - const: variscite,var-som-am62-symphony + - const: variscite,var-som-am62 + - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/xen.txt b/Documentation/devicetree/bindings/arm/xen.txt deleted file mode 100644 index f925290d4641..000000000000 --- a/Documentation/devicetree/bindings/arm/xen.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Xen hypervisor device tree bindings - -Xen ARM virtual platforms shall have a top-level "hypervisor" node with -the following properties: - -- compatible: - compatible = "xen,xen-<version>", "xen,xen"; - where <version> is the version of the Xen ABI of the platform. - -- reg: specifies the base physical address and size of the regions in memory - where the special resources should be mapped to, using an HYPERVISOR_memory_op - hypercall. - Region 0 is reserved for mapping grant table, it must be always present. - The memory region is large enough to map the whole grant table (it is larger - or equal to gnttab_max_grant_frames()). - Regions 1...N are extended regions (unused address space) for mapping foreign - GFNs and grants, they might be absent if there is nothing to expose. - -- interrupts: the interrupt used by Xen to inject event notifications. - A GIC node is also required. - -To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node -under /hypervisor with following parameters: - -________________________________________________________________________________ -Name | Size | Description -================================================================================ -xen,uefi-system-table | 64-bit | Guest physical address of the UEFI System - | | Table. --------------------------------------------------------------------------------- -xen,uefi-mmap-start | 64-bit | Guest physical address of the UEFI memory - | | map. --------------------------------------------------------------------------------- -xen,uefi-mmap-size | 32-bit | Size in bytes of the UEFI memory map - | | pointed to in previous entry. --------------------------------------------------------------------------------- -xen,uefi-mmap-desc-size | 32-bit | Size in bytes of each entry in the UEFI - | | memory map. --------------------------------------------------------------------------------- -xen,uefi-mmap-desc-ver | 32-bit | Version of the mmap descriptor format. --------------------------------------------------------------------------------- - -Example (assuming #address-cells = <2> and #size-cells = <2>): - -hypervisor { - compatible = "xen,xen-4.3", "xen,xen"; - reg = <0 0xb0000000 0 0x20000>; - interrupts = <1 15 0xf08>; - uefi { - xen,uefi-system-table = <0xXXXXXXXX>; - xen,uefi-mmap-start = <0xXXXXXXXX>; - xen,uefi-mmap-size = <0xXXXXXXXX>; - xen,uefi-mmap-desc-size = <0xXXXXXXXX>; - xen,uefi-mmap-desc-ver = <0xXXXXXXXX>; - }; -}; - -The format and meaning of the "xen,uefi-*" parameters are similar to those in -Documentation/arch/arm/uefi.rst, which are provided by the regular UEFI stub. However -they differ because they are provided by the Xen hypervisor, together with a set -of UEFI runtime services implemented via hypercalls, see -http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html. diff --git a/Documentation/devicetree/bindings/arm/xen.yaml b/Documentation/devicetree/bindings/arm/xen.yaml new file mode 100644 index 000000000000..bad077a112c9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/xen.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/xen.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xen hypervisor + +maintainers: + - Stefano Stabellini <sstabellini@kernel.org> + +description: + Xen ARM virtual platforms shall have a top-level "hypervisor" node with + the properties defined below. + +properties: + $nodename: + pattern: '^hypervisor(@[0-9a-f]+)?$' + + compatible: + description: + Specifies the Xen hypervisor. The version of the Xen ABI is encoded + in the first item as "xen,xen-<version>", followed by the generic + "xen,xen" string. + items: + - pattern: '^xen,xen-[0-9]+\.[0-9]+$' + - const: xen,xen + + reg: + description: | + Base physical address and size of the regions in memory where special + resources should be mapped to, using a HYPERVISOR_memory_op hypercall. + + Region 0 is reserved for mapping the grant table and must always be + present. The memory region must be large enough to map the whole grant + table (it is larger or equal to gnttab_max_grant_frames()). + + Regions 1...N are extended regions (unused address space) for mapping + foreign GFNs and grants. They might be absent if there is nothing to + expose. + minItems: 1 + + interrupts: + description: + The interrupt used by Xen to inject event notifications. + A GIC node is also required. + maxItems: 1 + + uefi: + type: object + description: + Node populated by Xen to support UEFI on Xen ARM virtual platforms. + The format and meaning of the "xen,uefi-*" parameters are similar to + those in Documentation/arch/arm/uefi.rst, but are provided by the Xen + hypervisor together with a set of UEFI runtime services implemented via + hypercalls. + + properties: + xen,uefi-system-table: + description: Guest physical address of the UEFI System Table. + $ref: /schemas/types.yaml#/definitions/uint64 + + xen,uefi-mmap-start: + description: Guest physical address of the UEFI memory map. + $ref: /schemas/types.yaml#/definitions/uint64 + + xen,uefi-mmap-size: + description: Size in bytes of the UEFI memory map pointed to by xen,uefi-mmap-start. + $ref: /schemas/types.yaml#/definitions/uint32 + + xen,uefi-mmap-desc-size: + description: Size in bytes of each entry in the UEFI memory map. + $ref: /schemas/types.yaml#/definitions/uint32 + + xen,uefi-mmap-desc-ver: + description: Version of the mmap descriptor format. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - xen,uefi-system-table + - xen,uefi-mmap-start + - xen,uefi-mmap-size + - xen,uefi-mmap-desc-size + - xen,uefi-mmap-desc-ver + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + hypervisor@b0000000 { + compatible = "xen,xen-4.3", "xen,xen"; + reg = <0xb0000000 0x20000>; + interrupts = <1 15 0xf08>; + + uefi { + xen,uefi-system-table = /bits/ 64 <0x1301415>; + xen,uefi-mmap-start = /bits/ 64 <0x7591400>; + xen,uefi-mmap-size = <0x1800>; + xen,uefi-mmap-desc-size = <0x30>; + xen,uefi-mmap-desc-ver = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/arm/zte.yaml b/Documentation/devicetree/bindings/arm/zte.yaml new file mode 100644 index 000000000000..f028d2cec7ab --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/zte.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx platforms + +maintainers: + - Stefan Dösinger <stefandoesinger@gmail.com> + +description: | + ARM platforms using SoCs designed by ZTE. Currently this supports devices + based on the zx297520v3 SoC which is found in LTE routers. + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - dlink,dwr932m + - const: zte,zx297520v3 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/ata/st,ahci.yaml b/Documentation/devicetree/bindings/ata/st,ahci.yaml index 6e8e4b4f3d6c..d82c5a65b60c 100644 --- a/Documentation/devicetree/bindings/ata/st,ahci.yaml +++ b/Documentation/devicetree/bindings/ata/st,ahci.yaml @@ -57,16 +57,16 @@ examples: #include <dt-bindings/clock/stih407-clks.h> sata@9b20000 { - compatible = "st,ahci"; - reg = <0x9b20000 0x1000>; - interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; interrupt-names = "hostc"; - phys = <&phy_port0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - resets = <&powerdown STIH407_SATA0_POWERDOWN>, - <&softreset STIH407_SATA0_SOFTRESET>, - <&softreset STIH407_SATA0_PWR_SOFTRESET>; - reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; - clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; - clock-names = "ahci_clk"; + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + clock-names = "ahci_clk"; }; diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml index 2eacb581b9fd..ea1e3fbca202 100644 --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis.yaml @@ -24,6 +24,7 @@ properties: - const: fsl,fpga-qixis - items: - enum: + - fsl,ls1021aqds-fpga - fsl,ls1043aqds-fpga - fsl,ls1043ardb-fpga - fsl,ls1046aqds-fpga diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml index 00bbde203f59..5e872ddacaab 100644 --- a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -26,21 +26,27 @@ select: compatible: contains: enum: + - fsl,aipi-bus - fsl,aips + - fsl,eim-bus - fsl,emi + - fsl,emi-bus - fsl,spba-bus required: - compatible properties: $nodename: - pattern: "^((spba|emi)-bus|bus)(@[0-9a-f]+)?$" + pattern: "^((spba|emi|eim)-bus|bus)(@[0-9a-f]+)?$" compatible: items: - enum: + - fsl,aipi-bus - fsl,aips + - fsl,eim-bus - fsl,emi + - fsl,emi-bus - fsl,spba-bus - const: simple-bus diff --git a/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt b/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt deleted file mode 100644 index 72daefc6b4a1..000000000000 --- a/Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Device tree bindings for Texas Instruments da8xx master peripheral - priority driver - -DA8XX SoCs feature a set of registers allowing to change the priority of all -peripherals classified as masters. - -Documentation: -OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf - -Required properties: - -- compatible: "ti,da850-mstpri" - for da850 based boards -- reg: offset and length of the mstpri registers - -Example for da850-lcdk is shown below. - -mstpri { - compatible = "ti,da850-mstpri"; - reg = <0x14110 0x0c>; -}; diff --git a/Documentation/devicetree/bindings/bus/ti,da850-mstpri.yaml b/Documentation/devicetree/bindings/bus/ti,da850-mstpri.yaml new file mode 100644 index 000000000000..5b03abd3fc3b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti,da850-mstpri.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/ti,da850-mstpri.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DA8XX Master Peripheral Priority Registers + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +description: | + DA8XX SoCs feature a set of registers allowing to change the priority of all + peripherals classified as masters. + + Documentation: + OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf + +properties: + compatible: + const: ti,da850-mstpri + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + mstpri@14110 { + compatible = "ti,da850-mstpri"; + reg = <0x14110 0x0c>; + }; diff --git a/Documentation/devicetree/bindings/bus/ti,omap-l4.yaml b/Documentation/devicetree/bindings/bus/ti,omap-l4.yaml new file mode 100644 index 000000000000..0b09fb91934a --- /dev/null +++ b/Documentation/devicetree/bindings/bus/ti,omap-l4.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/ti,omap-l4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI OMAP SoCs L4 interconnect bus + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +description: + These bindings describe the OMAP SoCs L4 interconnect bus. + +select: + properties: + compatible: + contains: + enum: + - ti,omap2-l4 + - ti,omap2-l4-wkup + - ti,omap3-l4-core + - ti,omap4-l4-abe + - ti,omap4-l4-cfg + - ti,omap4-l4-per + - ti,omap4-l4-wkup + - ti,omap5-l4-abe + - ti,omap5-l4-cfg + - ti,omap5-l4-per + - ti,omap5-l4-wkup + - ti,dra7-l4-cfg + - ti,dra7-l4-per1 + - ti,dra7-l4-per2 + - ti,dra7-l4-per3 + - ti,dra7-l4-wkup + - ti,am33xx-l4-fast + - ti,am33xx-l4-fw + - ti,am33xx-l4-mpuss + - ti,am33xx-l4-per + - ti,am33xx-l4-wkup + - ti,am4-l4-fast + - ti,am4-l4-per + - ti,am4-l4-wkup + - ti,dm814-l4hs + - ti,dm814-l4ls + required: + - compatible + +properties: + compatible: + items: + - enum: + - ti,omap2-l4 + - ti,omap2-l4-wkup + - ti,omap3-l4-core + - ti,omap4-l4-abe + - ti,omap4-l4-cfg + - ti,omap4-l4-per + - ti,omap4-l4-wkup + - ti,omap5-l4-abe + - ti,omap5-l4-cfg + - ti,omap5-l4-per + - ti,omap5-l4-wkup + - ti,dra7-l4-cfg + - ti,dra7-l4-per1 + - ti,dra7-l4-per2 + - ti,dra7-l4-per3 + - ti,dra7-l4-wkup + - ti,am33xx-l4-fast + - ti,am33xx-l4-fw + - ti,am33xx-l4-mpuss + - ti,am33xx-l4-per + - ti,am33xx-l4-wkup + - ti,am4-l4-fast + - ti,am4-l4-per + - ti,am4-l4-wkup + - ti,dm814-l4hs + - ti,dm814-l4ls + - enum: + - simple-bus + - simple-pm-bus + + reg: + minItems: 1 + maxItems: 6 + + reg-names: + minItems: 1 + maxItems: 6 + items: + enum: + - ap + - la + - ia0 + - ia1 + - ia2 + - ia3 + + ranges: true + + dma-ranges: true + + clocks: + maxItems: 1 + + clock-names: + items: + - const: fck + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + +required: + - compatible + - ranges + +additionalProperties: + type: object + +examples: + - | + bus@48000000 { + compatible = "ti,omap4-l4-per", "simple-bus"; + reg = <0x48000000 0x800>, + <0x48000800 0x800>, + <0x48001000 0x400>, + <0x48001400 0x400>, + <0x48001800 0x400>, + <0x48001c00 0x400>; + reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; + }; diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml index 10c1a900202f..ee604117ffb3 100644 --- a/Documentation/devicetree/bindings/cache/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml @@ -66,6 +66,9 @@ properties: reg: maxItems: 1 + power-domains: + maxItems: 1 + arm,data-latency: description: Cycles of latency for Data RAM accesses. Specifies 3 cells of read, write and setup latencies. Minimum valid values are 1. Controllers diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 995d57815781..a1340226a0d0 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -19,32 +19,40 @@ description: | properties: compatible: - enum: - - qcom,glymur-llcc - - qcom,ipq5424-llcc - - qcom,kaanapali-llcc - - qcom,qcs615-llcc - - qcom,qcs8300-llcc - - qcom,qdu1000-llcc - - qcom,sa8775p-llcc - - qcom,sar1130p-llcc - - qcom,sar2130p-llcc - - qcom,sc7180-llcc - - qcom,sc7280-llcc - - qcom,sc8180x-llcc - - qcom,sc8280xp-llcc - - qcom,sdm670-llcc - - qcom,sdm845-llcc - - qcom,sm6350-llcc - - qcom,sm7150-llcc - - qcom,sm8150-llcc - - qcom,sm8250-llcc - - qcom,sm8350-llcc - - qcom,sm8450-llcc - - qcom,sm8550-llcc - - qcom,sm8650-llcc - - qcom,sm8750-llcc - - qcom,x1e80100-llcc + oneOf: + - enum: + - qcom,eliza-llcc + - qcom,glymur-llcc + - qcom,hawi-llcc + - qcom,ipq5424-llcc + - qcom,kaanapali-llcc + - qcom,qcs615-llcc + - qcom,qcs8300-llcc + - qcom,qdu1000-llcc + - qcom,sa8775p-llcc + - qcom,sar1130p-llcc + - qcom,sar2130p-llcc + - qcom,sc7180-llcc + - qcom,sc7280-llcc + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + - qcom,sdm670-llcc + - qcom,sdm845-llcc + - qcom,shikra-llcc + - qcom,sm6350-llcc + - qcom,sm7150-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + - qcom,sm8550-llcc + - qcom,sm8650-llcc + - qcom,sm8750-llcc + - qcom,x1e80100-llcc + - items: + - enum: + - qcom,maili-llcc + - const: qcom,hawi-llcc reg: minItems: 1 @@ -57,6 +65,11 @@ properties: interrupts: maxItems: 1 + memory-region: + maxItems: 1 + description: handle to a reserved-memory node used for firmware-populated + SLC/SCT shared memory. + nvmem-cells: items: - description: Reference to an nvmem node for multi channel DDR @@ -206,6 +219,7 @@ allOf: enum: - qcom,sc7280-llcc - qcom,sdm670-llcc + - qcom,shikra-llcc then: properties: reg: @@ -318,6 +332,7 @@ allOf: contains: enum: - qcom,kaanapali-llcc + - qcom,hawi-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc @@ -340,6 +355,39 @@ allOf: - const: llcc3_base - const: llcc_broadcast_base - const: llcc_broadcast_and_base + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-llcc + then: + required: + - memory-region + else: + properties: + memory-region: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC2 base register region + - description: LLCC broadcast OR register region + - description: LLCC broadcast AND register region + reg-names: + items: + - const: llcc0_base + - const: llcc2_base + - const: llcc_broadcast_base + - const: llcc_broadcast_and_base additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-aoclkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-aoclkc.yaml new file mode 100644 index 000000000000..1fa9b3a32fbb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-aoclkc.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a9-aoclkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A9 Series Always-On Clock Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Jian Hu <jian.hu@amlogic.com> + - Xianwei Zhao <xianwei.zhao@amlogic.com> + +properties: + compatible: + const: amlogic,a9-aoclkc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 5 + items: + - description: input oscillator + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input sys clk + - description: external fixed 32k (optional) + + clock-names: + minItems: 5 + items: + - const: xtal + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: sys + - const: ext_32k + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@0 { + compatible = "amlogic,a9-aoclkc"; + reg = <0x0 0x0 0x0 0x58>; + #clock-cells = <1>; + clocks = <&xtal>, + <&scmi_clk 14>, + <&scmi_clk 16>, + <&scmi_clk 18>, + <&scmi_clk 21>; + clock-names = "xtal", + "fdiv3", + "fdiv4", + "fdiv5", + "sys"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml new file mode 100644 index 000000000000..f0aef005ecf3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml @@ -0,0 +1,164 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A9 Series Peripherals Clock Controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + - Jerome Brunet <jbrunet@baylibre.com> + - Jian Hu <jian.hu@amlogic.com> + - Xianwei Zhao <xianwei.zhao@amlogic.com> + +properties: + compatible: + const: amlogic,a9-peripherals-clkc + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + clocks: + minItems: 27 + items: + - description: input oscillator + - description: input fclk div 2 + - description: input fclk div 3 + - description: input fclk div 4 + - description: input fclk div 5 + - description: input fclk div 7 + - description: input fclk div 2p5 + - description: input sys clk + - description: input gp1 pll + - description: input gp2 pll + - description: input sys pll div 16 + - description: input cpu clk div 16 + - description: input a78 clk div 16 + - description: input dsu clk div 16 + - description: input rtc clk + - description: input gp0 pll + - description: input hifi0 pll + - description: input hifi1 pll + - description: input mclk0 pll + - description: input mclk1 pll + - description: input video1 pll + - description: input video2 pll + - description: input hdmi out2 clk + - description: input hdmi pixel clk + - description: input pixel0 pll + - description: input pixel1 pll + - description: input ddr pll test clk + - description: external input rmii oscillator (optional) + + clock-names: + minItems: 27 + items: + - const: xtal + - const: fdiv2 + - const: fdiv3 + - const: fdiv4 + - const: fdiv5 + - const: fdiv7 + - const: fdiv2p5 + - const: sys + - const: gp1 + - const: gp2 + - const: sysplldiv16 + - const: cpudiv16 + - const: a78div16 + - const: dsudiv16 + - const: rtc + - const: gp0 + - const: hifi0 + - const: hifi1 + - const: mclk0 + - const: mclk1 + - const: vid1 + - const: vid2 + - const: hdmiout2 + - const: hdmipix + - const: pix0 + - const: pix1 + - const: ddr_test + - const: ext_rmii + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@200 { + compatible = "amlogic,a9-peripherals-clkc"; + reg = <0x0 0x200 0x0 0x2f8>; + #clock-cells = <1>; + clocks = <&xtal>, + <&scmi_clk 10>, + <&scmi_clk 12>, + <&scmi_clk 14>, + <&scmi_clk 16>, + <&scmi_clk 18>, + <&scmi_clk 20>, + <&scmi_clk 21>, + <&scmi_clk 33>, + <&scmi_clk 34>, + <&scmi_clk 35>, + <&scmi_clk 36>, + <&scmi_clk 37>, + <&scmi_clk 38>, + <&scmi_clk 40>, + <&gp0 3>, + <&hifi0 3>, + <&hifi1 3>, + <&mclk0 3>, + <&mclk1 3>, + <&vid1>, + <&vid2>, + <&hdmitx 10>, + <&hdmitx 11>, + <&pix0>, + <&pix1>, + <&ddr 3>; + clock-names = "xtal", + "fdiv2", + "fdiv3", + "fdiv4", + "fdiv5", + "fdiv7", + "fdiv2p5", + "sys", + "gp1", + "gp2", + "sysplldiv16", + "cpudiv16", + "a78div16", + "dsudiv16", + "rtc", + "gp0", + "hifi0", + "hifi1", + "mclk0", + "mclk1", + "vid1", + "vid2", + "hdmiout2", + "hdmipix", + "pix0", + "pix1", + "ddr_test"; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml index 55bb73707d58..a4b214a941ea 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml @@ -24,7 +24,7 @@ properties: const: 1 clocks: - minItems: 14 + minItems: 15 items: - description: input oscillator - description: input sys clk @@ -40,12 +40,13 @@ properties: - description: input gp1 pll - description: input mpll1 - description: input mpll2 + - description: input mpll3 - description: external input rmii oscillator (optional) - description: input video pll0 (optional) - description: external pad input for rtc (optional) clock-names: - minItems: 14 + minItems: 15 items: - const: xtal - const: sys @@ -61,6 +62,7 @@ properties: - const: gp1 - const: mpll1 - const: mpll2 + - const: mpll3 - const: ext_rmii - const: vid_pll0 - const: ext_rtc @@ -97,7 +99,8 @@ examples: <&gp0 1>, <&gp1 1>, <&mpll 4>, - <&mpll 6>; + <&mpll 6>, + <&mpll 8>; clock-names = "xtal", "sys", "fix", @@ -111,6 +114,7 @@ examples: "gp0", "gp1", "mpll1", - "mpll2"; + "mpll2", + "mpll3"; }; }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml index 49c61f65deff..b488d92b7984 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml @@ -72,7 +72,7 @@ allOf: contains: enum: - amlogic,t7-gp0-pll - - amlogic,t7-gp1--pll + - amlogic,t7-gp1-pll - amlogic,t7-hifi-pll - amlogic,t7-pcie-pll - amlogic,t7-mpll diff --git a/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml new file mode 100644 index 000000000000..34c93cb5db40 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Clock + +maintainers: + - Xukai Wang <kingxukai@zohomail.com> + +description: + The Canaan K230 clock controller generates various clocks for SoC + peripherals. See include/dt-bindings/clock/canaan,k230-clk.h for + valid clock IDs. + +properties: + compatible: + const: canaan,k230-clk + + reg: + items: + - description: PLL control registers + - description: Sysclk control registers + + clocks: + items: + - description: Main external reference clock + - description: + External clock which used as the pulse input + for the timer to provide timing signals. + + clock-names: + items: + - const: osc24m + - const: timer-pulse-in + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@91102000 { + compatible = "canaan,k230-clk"; + reg = <0x91102000 0x40>, + <0x91100000 0x108>; + clocks = <&osc24m>, <&timerx_pulse_in>; + clock-names = "osc24m", "timer-pulse-in"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml index d416c374e853..ceeaa8f9fb08 100644 --- a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml +++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml @@ -11,14 +11,19 @@ maintainers: description: | The CS2000-CP is an extremely versatile system clocking device that - utilizes a programmable phase lock loop. + utilizes a programmable phase lock loop. CS2500 is a compatible + drop-in replacement for CS2000-CP. Link: https://www.cirrus.com/products/cs2000/ + Link: https://www.cirrus.com/products/cs2500/ properties: compatible: - enum: - - cirrus,cs2000-cp + oneOf: + - items: + - const: cirrus,cs2500 + - const: cirrus,cs2000-cp + - const: cirrus,cs2000-cp clocks: description: diff --git a/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml new file mode 100644 index 000000000000..43df689ae647 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/eswin,eic7700-hspcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN EIC7700 HSP Clock and Reset Generator + +maintainers: + - Xuyang Dong <dongxuyang@eswincomputing.com> + +description: + Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals). + +properties: + compatible: + const: eswin,eic7700-hspcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: HSP configuration top clock + - description: MMC top clock + - description: SATA top clock + + clock-names: + items: + - const: cfg + - const: mmc + - const: sata + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/eswin,eic7700-hspcrg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/eswin,eic7700-hspcrg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@50440000 { + compatible = "eswin,eic7700-hspcrg"; + reg = <0x50440000 0x2000>; + clocks = <&clock 171>, <&clock 254>, <&clock 187>; + clock-names = "cfg", "mmc", "sata"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/keystone-gate.txt b/Documentation/devicetree/bindings/clock/keystone-gate.txt deleted file mode 100644 index 43f6fb6c9392..000000000000 --- a/Documentation/devicetree/bindings/clock/keystone-gate.txt +++ /dev/null @@ -1,27 +0,0 @@ -Binding for Keystone gate control driver which uses PSC controller IP. - -This binding uses the common clock binding[1]. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,keystone,psc-clock". -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : parent clock phandle -- reg : psc control and domain address address space -- reg-names : psc control and domain registers -- domain-id : psc domain id needed to check the transition state register - -Optional properties: -- clock-output-names : From common clock binding to override the - default output clock name -Example: - clkusb: clkusb { - #clock-cells = <0>; - compatible = "ti,keystone,psc-clock"; - clocks = <&chipclk16>; - clock-output-names = "usb"; - reg = <0x02350008 0xb00>, <0x02350000 0x400>; - reg-names = "control", "domain"; - domain-id = <0>; - }; diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml index 6f3a8578fe2a..0db5504013d5 100644 --- a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -37,6 +37,9 @@ properties: '#power-domain-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg @@ -44,16 +47,27 @@ required: additionalProperties: false -if: - not: - properties: - compatible: - contains: - const: marvell,pxa1908-apmu - -then: - properties: - '#power-domain-cells': false +allOf: + - if: + not: + properties: + compatible: + contains: + const: marvell,pxa1908-apmu + then: + properties: + '#power-domain-cells': false + - if: + not: + properties: + compatible: + contains: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + then: + properties: + '#reset-cells': false examples: # APMU block: diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml new file mode 100644 index 000000000000..03db1ee9e594 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8173 MFG TOP controller + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: + The MFG TOP glue layer controls various signals going to the MFG (GPU) + block on the MT8173. + +properties: + compatible: + const: mediatek,mt8173-mfgtop + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: sys + - const: mem + - const: core + - const: clk26m + + power-domains: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/power/mt8173-power.h> + + clock-controller@13fff000 { + compatible = "mediatek,mt8173-mfgtop"; + reg = <0x13fff000 0x1000>; + clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>, + <&topckgen CLK_TOP_MEM_MFG_IN_SEL>, + <&topckgen CLK_TOP_MFG_SEL>, + <&clk26m>; + clock-names = "sys", "mem", "core", "clk26m"; + power-domains = <&spm MT8173_POWER_DOMAIN_MFG>; + #clock-cells = <1>; + #power-domain-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml index b98cf45efe2f..f0c8df4d10c8 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml @@ -65,7 +65,7 @@ examples: - | pericfg@10003000 { - compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"; + compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon"; reg = <0x10003000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml index 47ceab641a4c..1eec77e75a0a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,ipq5018-a53pll + - qcom,ipq5210-a53pll - qcom,ipq5332-a53pll - qcom,ipq6018-a53pll - qcom,ipq8074-a53pll diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index ef2b1e204430..a177a1934b19 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -42,12 +42,6 @@ properties: - const: cfg_ahb_clk - const: gcc_disp_gpll0_div_clk_src - '#clock-cells': - const: 1 - - '#power-domain-cells': - const: 1 - power-domains: description: A phandle and PM domain specifier for the CX power domain. @@ -58,18 +52,16 @@ properties: A phandle to an OPP node describing the power domain's performance point. maxItems: 1 - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | @@ -101,6 +93,7 @@ examples: power-domains = <&rpmpd SM6125_VDDCX>; #clock-cells = <1>; + #reset-cells = <1>; #power-domain-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 53a5ab319159..6863db9bd092 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -13,7 +13,7 @@ description: | Qualcomm display clock control module provides the clocks, resets and power domains on SM8150/SM8250/SM8350. - See also:: + See also: include/dt-bindings/clock/qcom,dispcc-sm8150.h include/dt-bindings/clock/qcom,dispcc-sm8250.h include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml index 27df7e3e5bf3..68532244901e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on APQ8064. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-msm8960.h include/dt-bindings/reset/qcom,gcc-msm8960.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml index 0a0a26d9beab..1c022e75fd71 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on APQ8084. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-apq8084.h include/dt-bindings/reset/qcom,gcc-apq8084.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml index 4d2614d4f368..c7fb84438db7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml @@ -15,7 +15,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on IPQ6018. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-ipq6018.h include/dt-bindings/reset/qcom,gcc-ipq6018.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml index a71557395c01..b4d3175780bc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on IPQ8064. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml index d7da30b0e7ee..d4dd51fb4b8a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-mdm9607.h allOf: @@ -25,19 +25,33 @@ properties: enum: - qcom,gcc-mdm9607 + clocks: + items: + - description: XO source + - description: Sleep clock source + + clock-names: + items: + - const: xo + - const: sleep_clk + required: - compatible + - clocks + - clock-names - '#power-domain-cells' unevaluatedProperties: false examples: - | - clock-controller@900000 { + clock-controller@1800000 { compatible = "qcom,gcc-mdm9607"; - reg = <0x900000 0x4000>; + reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + clocks = <&xo_board>, <&sleep_clk>; + clock-names = "xo", "sleep_clk"; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml index 418dea31eb62..0656d5ee448d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-mdm9615.h allOf: diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml index e03b6d0acdb6..70c9da1f35c2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks and resets on MSM8660 - See also:: + See also: include/dt-bindings/clock/qcom,gcc-msm8660.h include/dt-bindings/reset/qcom,gcc-msm8660.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml index ce1f5a60bd8c..2edb6c251d99 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on MSM8909, MSM8917 or QM215. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-msm8909.h include/dt-bindings/clock/qcom,gcc-msm8917.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml index 258b6b93deca..af4b639ea8c3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on MSM8916 or MSM8939. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-msm8916.h include/dt-bindings/clock/qcom,gcc-msm8939.h include/dt-bindings/reset/qcom,gcc-msm8916.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml index ced3118c8580..9f2b970bfb48 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml @@ -7,15 +7,13 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439 maintainers: - - Adam Skladowski <a_skl39@protonmail.com> - - Sireesh Kodali <sireeshkodali@protonmail.com> - Barnabas Czeman <barnabas.czeman@mainlining.org> description: | Qualcomm global clock control module provides the clocks, resets and power domains on MSM8937, MSM8940, MSM8953 or SDM439. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-msm8917.h include/dt-bindings/clock/qcom,gcc-msm8953.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml index 929fafc84c19..378dfe7854ac 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml @@ -15,7 +15,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on MSM8974 (all variants) and MSM8226. - See also:: + See also: include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml index 724ce0491118..72aaf699cf70 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml @@ -14,7 +14,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on SDM630, SDM636 and SDM660 - See also:: + See also: include/dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660) $ref: qcom,gcc.yaml# diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml new file mode 100644 index 000000000000..fb0bc1acc920 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-evacc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-evacc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm EVA Clock & Reset Controller on Glymur SoC + +maintainers: + - Taniya Das <taniya.das@oss.qualcomm.com> + +description: | + Qualcomm EVA clock control module which supports the clocks, resets and + power domains for the EVA instances on Glymur SoC. + + See also: + - include/dt-bindings/clock/qcom,glymur-evacc.h + +properties: + compatible: + const: qcom,glymur-evacc + + clocks: + items: + - description: Interface clock from GCC + - description: Board XO source + - description: Sleep clock source + + power-domains: + items: + - description: MMCX power domain + - description: MXC power domain + + required-opps: + description: + Required OPP nodes for the MMCX and MXC power domains. + items: + - description: MMCX performance point + - description: MXC performance point + +required: + - compatible + - clocks + - power-domains + - required-opps + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,glymur-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@ab00000 { + compatible = "qcom,glymur-evacc"; + reg = <0x0ab00000 0x10000>; + clocks = <&gcc GCC_EVA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + power-domains = <&rpmhpd RPMHPD_MMCX>, + <&rpmhpd RPMHPD_MXC>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml index b05b0e6c4483..7a4054c9f215 100644 --- a/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml @@ -65,9 +65,15 @@ properties: - description: USB4 PHY 2 pcie pipe clock source - description: USB4 PHY 2 Max pipe clock source + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + required: - compatible - clocks + - power-domains - '#power-domain-cells' allOf: @@ -78,6 +84,7 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> clock-controller@100000 { compatible = "qcom,glymur-gcc"; reg = <0x100000 0x1f9000>; @@ -113,6 +120,7 @@ examples: <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>, <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>, <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>; + power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml new file mode 100644 index 000000000000..2b6422627165 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on Glymur + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Taniya Das <taniya.das@oss.qualcomm.com> + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on Glymur + + See also: + - include/dt-bindings/clock/qcom,glymur-tcsr.h + +properties: + compatible: + items: + - enum: + - qcom,glymur-tcsr + - qcom,mahua-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + vdda-qrefrpt0-0p9-supply: true + vdda-qrefrpt1-0p9-supply: true + vdda-qrefrpt2-0p9-supply: true + vdda-qrefrpt3-0p9-supply: true + vdda-qrefrpt4-0p9-supply: true + vdda-qrefrpt5-0p9-supply: true + vdda-qrefrx0-0p9-supply: true + vdda-qrefrx1-0p9-supply: true + vdda-qrefrx2-0p9-supply: true + vdda-qrefrx3-0p9-supply: true + vdda-qrefrx4-0p9-supply: true + vdda-qrefrx5-0p9-supply: true + vdda-qreftx0-0p9-supply: true + vdda-qreftx0-1p2-supply: true + vdda-qreftx1-0p9-supply: true + vdda-refgen3-0p9-supply: true + vdda-refgen3-1p2-supply: true + vdda-refgen4-0p9-supply: true + vdda-refgen4-1p2-supply: true + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,glymur-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrx0-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx4-0p9-supply + - vdda-qrefrx5-0p9-supply + - vdda-qreftx0-0p9-supply + - vdda-qreftx0-1p2-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply + - vdda-refgen4-0p9-supply + - vdda-refgen4-1p2-supply + - if: + properties: + compatible: + contains: + const: qcom,mahua-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrpt5-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx3-0p9-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@1fd5000 { + compatible = "qcom,glymur-tcsr", "syscon"; + reg = <0x0 0x1fd5000 0x0 0x21000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + vdda-qrefrpt0-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt1-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt2-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt3-0p9-supply = <&vreg_l1a>; + vdda-qrefrpt4-0p9-supply = <&vreg_l1a>; + vdda-qrefrx0-0p9-supply = <&vreg_l1a>; + vdda-qrefrx1-0p9-supply = <&vreg_l1a>; + vdda-qrefrx2-0p9-supply = <&vreg_l1a>; + vdda-qrefrx4-0p9-supply = <&vreg_l1a>; + vdda-qrefrx5-0p9-supply = <&vreg_l1a>; + vdda-qreftx0-0p9-supply = <&vreg_l1a>; + vdda-qreftx0-1p2-supply = <&vreg_l2a>; + vdda-qreftx1-0p9-supply = <&vreg_l1a>; + vdda-refgen3-0p9-supply = <&vreg_l1a>; + vdda-refgen3-1p2-supply = <&vreg_l2a>; + vdda-refgen4-0p9-supply = <&vreg_l1a>; + vdda-refgen4-1p2-supply = <&vreg_l2a>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 4cdff6161bf0..3ac4419009a9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -14,7 +14,7 @@ description: | Qualcomm graphics clock control module provides the clocks, resets and power domains on Qualcomm SoCs. - See also:: + See also: include/dt-bindings/clock/qcom,gpucc-sdm845.h include/dt-bindings/clock/qcom,gpucc-sa8775p.h include/dt-bindings/clock/qcom,gpucc-sc7180.h diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml new file mode 100644 index 000000000000..2101f4e4bb0d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,hawi-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on Hawi + +maintainers: + - Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> + - Taniya Das <taniya.das@oss.qualcomm.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on Hawi and Maili. + + See also: + include/dt-bindings/clock/qcom,hawi-gcc.h + include/dt-bindings/clock/qcom,maili-gcc.h + +properties: + compatible: + enum: + - qcom,hawi-gcc + - qcom,maili-gcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + - description: UFS PHY RX symbol 0 clock + - description: UFS PHY RX symbol 1 clock + - description: UFS PHY TX symbol 0 clock + - description: USB3 PHY wrapper pipe clock + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,hawi-gcc"; + reg = <0x00100000 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml index 489d0fc5607c..9925b931ecad 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm global clock control module provides the clocks, resets and power domains on IPQ5018 - See also:: + See also: include/dt-bindings/clock/qcom,ipq5018-gcc.h include/dt-bindings/reset/qcom,ipq5018-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index de338c05190f..a4f9af8fa187 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -8,7 +8,7 @@ title: Qualcomm CMN PLL Clock Controller on IPQ SoC maintainers: - Bjorn Andersson <andersson@kernel.org> - - Luo Jie <quic_luoj@quicinc.com> + - Luo Jie <jie.luo@oss.qualcomm.com> description: The CMN (or common) PLL clock controller expects a reference @@ -25,6 +25,7 @@ properties: compatible: enum: - qcom,ipq5018-cmn-pll + - qcom,ipq5332-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq6018-cmn-pll - qcom,ipq8074-cmn-pll diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 27ae9938febc..1337bd87fddd 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -8,13 +8,12 @@ title: Qualcomm Global Clock & Reset Controller on IPQ9574 maintainers: - Bjorn Andersson <andersson@kernel.org> - - Anusha Rao <quic_anusha@quicinc.com> description: | Qualcomm global clock control module provides the clocks, resets and power domains on IPQ9574 - See also:: + See also: include/dt-bindings/clock/qcom,ipq9574-gcc.h include/dt-bindings/reset/qcom,ipq9574-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml index 7ff4ff3587ca..a35bbc7b1924 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -8,7 +8,6 @@ title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IP maintainers: - Bjorn Andersson <andersson@kernel.org> - - Anusha Rao <quic_anusha@quicinc.com> description: | Qualcomm networking sub system clock control module provides the clocks, diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml new file mode 100644 index 000000000000..f33105217a06 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9650 + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ9650 + + See also: + include/dt-bindings/clock/qcom,ipq9650-gcc.h + include/dt-bindings/reset/qcom,ipq9650-gcc.h + +properties: + compatible: + const: qcom,ipq9650-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: PCIE30 PHY4 pipe clock source + - description: USB PCIE wrapper pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq9650-gcc"; + reg = <0x01800000 0x40000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&pcie30_phy4_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml index 466c884aa2ba..e868963f659b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -44,7 +44,7 @@ required: - power-domains - '#power-domain-cells' -unevaluatedProperties: false +additionalProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml index f63149ecf3e1..707b25d2c11e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml @@ -25,6 +25,10 @@ properties: - description: Sleep clock source - description: Camera AHB clock from GCC + interconnects: + items: + - description: Interconnect path to enable the MultiMedia NoC + required: - compatible - clocks @@ -37,12 +41,16 @@ unevaluatedProperties: false examples: - | #include <dt-bindings/clock/qcom,milos-gcc.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,milos-rpmh.h> clock-controller@adb0000 { compatible = "qcom,milos-camcc"; reg = <0x0adb0000 0x40000>; clocks = <&bi_tcxo_div2>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml new file mode 100644 index 000000000000..fbcb5d3f3e3d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,milos-gxclkctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Power Domain Controller on Milos + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: | + Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and + Power domains (GDSC). This module provides the power domains control + of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem. + + See also: + include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h + +properties: + compatible: + enum: + - qcom,milos-gxclkctl + + reg: + maxItems: 1 + + power-domains: + description: + Power domains required for the clock controller to operate + items: + - description: GFX power domain + - description: GPUCC(CX) power domain + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/power/qcom,rpmhpd.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d64000 { + compatible = "qcom,milos-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + power-domains = <&rpmhpd RPMHPD_GFX>, + <&gpucc 0>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml index 61473385da2d..8d7a58609372 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml @@ -8,13 +8,13 @@ title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084 maintainers: - Bjorn Andersson <andersson@kernel.org> - - Luo Jie <quic_luoj@quicinc.com> + - Luo Jie <jie.luo@oss.qualcomm.com> description: | Qualcomm NSS clock control module provides the clocks and resets on QCA8386(switch mode)/QCA8084(PHY mode) - See also:: + See also: include/dt-bindings/clock/qcom,qca8k-nsscc.h include/dt-bindings/reset/qcom,qca8k-nsscc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml index 4a533b45eec2..8d4f53c8a6cb 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml @@ -17,7 +17,13 @@ description: | properties: compatible: - const: qcom,qcm2290-dispcc + oneOf: + - items: + - enum: + - qcom,shikra-dispcc + - const: qcom,qcm2290-dispcc + - enum: + - qcom,qcm2290-dispcc clocks: items: @@ -37,10 +43,15 @@ properties: - const: dsi0_phy_pll_out_byteclk - const: dsi0_phy_pll_out_dsiclk + power-domains: + items: + - description: CX domain + required: - compatible - clocks - clock-names + - power-domains - '#power-domain-cells' allOf: @@ -53,6 +64,7 @@ examples: #include <dt-bindings/clock/qcom,dispcc-qcm2290.h> #include <dt-bindings/clock/qcom,gcc-qcm2290.h> #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> clock-controller@5f00000 { compatible = "qcom,qcm2290-dispcc"; reg = <0x5f00000 0x20000>; @@ -68,6 +80,7 @@ examples: "gcc_disp_gpll0_div_clk_src", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk"; + power-domains = <&rpmpd RPMPD_VDDCX>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml index 734880805c1b..ad2386190346 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml @@ -13,12 +13,14 @@ description: | Qualcomm graphics clock control module provides the clocks, resets and power domains on Qualcomm SoCs. - See also:: + See also: include/dt-bindings/clock/qcom,qcm2290-gpucc.h properties: compatible: - const: qcom,qcm2290-gpucc + enum: + - qcom,qcm2290-gpucc + - qcom,shikra-gpucc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml index ab97d4b7dba8..17332aa55886 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml @@ -12,7 +12,7 @@ maintainers: description: | The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and - come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is + come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock is an "active" clock, which means that the consumer only care that the clock is available when the apps CPU subsystem is active, i.e. not suspended or in deep idle. If it is important that the clock keeps running during system @@ -21,35 +21,41 @@ description: | properties: compatible: - items: - - enum: - - qcom,rpmcc-apq8060 - - qcom,rpmcc-apq8064 - - qcom,rpmcc-ipq806x - - qcom,rpmcc-mdm9607 - - qcom,rpmcc-msm8226 - - qcom,rpmcc-msm8660 - - qcom,rpmcc-msm8909 - - qcom,rpmcc-msm8916 - - qcom,rpmcc-msm8917 - - qcom,rpmcc-msm8936 - - qcom,rpmcc-msm8937 - - qcom,rpmcc-msm8940 - - qcom,rpmcc-msm8953 - - qcom,rpmcc-msm8974 - - qcom,rpmcc-msm8976 - - qcom,rpmcc-msm8992 - - qcom,rpmcc-msm8994 - - qcom,rpmcc-msm8996 - - qcom,rpmcc-msm8998 - - qcom,rpmcc-qcm2290 - - qcom,rpmcc-qcs404 - - qcom,rpmcc-sdm429 - - qcom,rpmcc-sdm660 - - qcom,rpmcc-sm6115 - - qcom,rpmcc-sm6125 - - qcom,rpmcc-sm6375 - - const: qcom,rpmcc + oneOf: + - items: + - enum: + - qcom,rpmcc-apq8060 + - qcom,rpmcc-apq8064 + - qcom,rpmcc-ipq806x + - qcom,rpmcc-mdm9607 + - qcom,rpmcc-msm8226 + - qcom,rpmcc-msm8660 + - qcom,rpmcc-msm8909 + - qcom,rpmcc-msm8916 + - qcom,rpmcc-msm8917 + - qcom,rpmcc-msm8936 + - qcom,rpmcc-msm8937 + - qcom,rpmcc-msm8940 + - qcom,rpmcc-msm8953 + - qcom,rpmcc-msm8974 + - qcom,rpmcc-msm8976 + - qcom,rpmcc-msm8992 + - qcom,rpmcc-msm8994 + - qcom,rpmcc-msm8996 + - qcom,rpmcc-msm8998 + - qcom,rpmcc-qcm2290 + - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm429 + - qcom,rpmcc-sdm660 + - qcom,rpmcc-sm6115 + - qcom,rpmcc-sm6125 + - qcom,rpmcc-sm6375 + - const: qcom,rpmcc + - items: + - enum: + - qcom,rpmcc-shikra + - const: qcom,rpmcc-qcm2290 + - const: qcom,rpmcc '#clock-cells': const: 1 @@ -126,6 +132,7 @@ allOf: - qcom,rpmcc-qcs404 - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 + - qcom,rpmcc-shikra - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index a2c404a57981..2b446aca5207 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -16,35 +16,41 @@ description: | properties: compatible: - enum: - - qcom,eliza-rpmh-clk - - qcom,glymur-rpmh-clk - - qcom,kaanapali-rpmh-clk - - qcom,milos-rpmh-clk - - qcom,nord-rpmh-clk - - qcom,qcs615-rpmh-clk - - qcom,qdu1000-rpmh-clk - - qcom,sa8775p-rpmh-clk - - qcom,sar2130p-rpmh-clk - - qcom,sc7180-rpmh-clk - - qcom,sc7280-rpmh-clk - - qcom,sc8180x-rpmh-clk - - qcom,sc8280xp-rpmh-clk - - qcom,sdm670-rpmh-clk - - qcom,sdm845-rpmh-clk - - qcom,sdx55-rpmh-clk - - qcom,sdx65-rpmh-clk - - qcom,sdx75-rpmh-clk - - qcom,sm4450-rpmh-clk - - qcom,sm6350-rpmh-clk - - qcom,sm8150-rpmh-clk - - qcom,sm8250-rpmh-clk - - qcom,sm8350-rpmh-clk - - qcom,sm8450-rpmh-clk - - qcom,sm8550-rpmh-clk - - qcom,sm8650-rpmh-clk - - qcom,sm8750-rpmh-clk - - qcom,x1e80100-rpmh-clk + oneOf: + - enum: + - qcom,eliza-rpmh-clk + - qcom,glymur-rpmh-clk + - qcom,hawi-rpmh-clk + - qcom,kaanapali-rpmh-clk + - qcom,milos-rpmh-clk + - qcom,nord-rpmh-clk + - qcom,qcs615-rpmh-clk + - qcom,qdu1000-rpmh-clk + - qcom,sa8775p-rpmh-clk + - qcom,sar2130p-rpmh-clk + - qcom,sc7180-rpmh-clk + - qcom,sc7280-rpmh-clk + - qcom,sc8180x-rpmh-clk + - qcom,sc8280xp-rpmh-clk + - qcom,sdm670-rpmh-clk + - qcom,sdm845-rpmh-clk + - qcom,sdx55-rpmh-clk + - qcom,sdx65-rpmh-clk + - qcom,sdx75-rpmh-clk + - qcom,sm4450-rpmh-clk + - qcom,sm6350-rpmh-clk + - qcom,sm8150-rpmh-clk + - qcom,sm8250-rpmh-clk + - qcom,sm8350-rpmh-clk + - qcom,sm8450-rpmh-clk + - qcom,sm8550-rpmh-clk + - qcom,sm8650-rpmh-clk + - qcom,sm8750-rpmh-clk + - qcom,x1e80100-rpmh-clk + - items: + - enum: + - qcom,maili-rpmh-clk + - const: qcom,hawi-rpmh-clk clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml index 99ab9106009f..fd06ac9bceb9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm LPASS core and audio clock control module provides the clocks and power domains on SC7280. - See also:: + See also: include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 273d66e245c5..f235b4e24cc7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm LPASS core and audio clock control module provides the clocks, and reset on SC8280XP. - See also:: + See also: include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h properties: diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml new file mode 100644 index 000000000000..d59f7e47a0d7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-audiocorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio Core Clock Controller for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik <imran.shaik@oss.qualcomm.com> + +description: | + Audio core clock control module provides the clocks on Qualcomm Shikra + SoC platform. + + See also: + - include/dt-bindings/clock/qcom,shikra-audiocorecc.h + +properties: + compatible: + const: qcom,shikra-audiocorecc + + clocks: + items: + - description: Board XO source + - description: Board sleep clock + - description: Audio ref clock source + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/clock/qcom,shikra-gcc.h> + clock-controller@a0a0000 { + compatible = "qcom,shikra-audiocorecc"; + reg = <0x0a0a0000 0x10000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&aud_ref_clk_src>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml new file mode 100644 index 000000000000..da6eebfa84c2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,shikra-gcc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,shikra-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Global Clock & Reset Controller on Qualcomm Shikra SoC + +maintainers: + - Imran Shaik <imran.shaik@oss.qualcomm.com> + - Taniya Das <taniya.das@oss.qualcomm.com> + +description: | + Global clock control module provides the clocks, resets and power + domains on Qualcomm Shikra SoC platform. + + See also: include/dt-bindings/clock/qcom,shikra-gcc.h + +properties: + compatible: + const: qcom,shikra-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: EMAC0 sgmiiphy mac rclk source + - description: EMAC0 sgmiiphy mac tclk source + - description: EMAC1 sgmiiphy mac rclk source + - description: EMAC1 sgmiiphy mac tclk source + - description: PCIE Pipe clock source + - description: USB3 phy wrapper pipe clock source + + power-domains: + items: + - description: CX domain + +required: + - compatible + - clocks + - power-domains + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + clock-controller@1400000 { + compatible = "qcom,shikra-gcc"; + reg = <0x01400000 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <&emac0_sgmiiphy_rclk>, + <&emac0_sgmiiphy_tclk>, + <&emac1_sgmiiphy_rclk>, + <&emac1_sgmiiphy_tclk>, + <&pcie_pipe_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml index 8cbab3fbb660..d7e1938b5e1b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml @@ -14,7 +14,7 @@ description: | Qualcomm LPASS core and audio clock controllers provide audio-related resets on SM6115 and its derivatives. - See also:: + See also: include/dt-bindings/clock/qcom,sm6115-lpasscc.h properties: diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml index 5c2ecec0624e..a986ab4ce7c7 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm video clock control module provides the clocks, resets and power domains on Qualcomm SoCs. - See also:: + See also: include/dt-bindings/clock/qcom,videocc-sm8350.h include/dt-bindings/reset/qcom,videocc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 8492a7ef7324..b41247b257b1 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -70,13 +70,11 @@ allOf: - if: properties: compatible: - contains: - enum: - - qcom,kaanapali-cambistmclkcc - - qcom,kaanapali-camcc - - qcom,sc8280xp-camcc - - qcom,sm8450-camcc - - qcom,sm8550-camcc + not: + contains: + enum: + - qcom,sm8475-camcc + - qcom,sm8650-camcc then: required: - required-opps diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml index fdbdf605ee69..2a2d37c59442 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml @@ -18,6 +18,8 @@ description: | include/dt-bindings/clock/qcom,glymur-gpucc.h include/dt-bindings/clock/qcom,kaanapali-gpucc.h include/dt-bindings/clock/qcom,milos-gpucc.h + include/dt-bindings/clock/qcom,nord-gpu2cc.h + include/dt-bindings/clock/qcom,nord-gpucc.h include/dt-bindings/clock/qcom,sar2130p-gpucc.h include/dt-bindings/clock/qcom,sm4450-gpucc.h include/dt-bindings/clock/qcom,sm8450-gpucc.h @@ -33,6 +35,8 @@ properties: - qcom,glymur-gpucc - qcom,kaanapali-gpucc - qcom,milos-gpucc + - qcom,nord-gpu2cc + - qcom,nord-gpucc - qcom,sar2130p-gpucc - qcom,sm4450-gpucc - qcom,sm8450-gpucc diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 7bbf120d928c..910c6d5672b8 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -16,22 +16,28 @@ description: | See also: include/dt-bindings/clock/qcom,glymur-videocc.h + include/dt-bindings/clock/qcom,hawi-videocc.h include/dt-bindings/clock/qcom,kaanapali-videocc.h + include/dt-bindings/clock/qcom,maili-videocc.h include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h include/dt-bindings/clock/qcom,sm8750-videocc.h + include/dt-bindings/clock/qcom,x1p42100-videocc.h properties: compatible: enum: - qcom,glymur-videocc + - qcom,hawi-videocc - qcom,kaanapali-videocc + - qcom,maili-videocc - qcom,sm8450-videocc - qcom,sm8475-videocc - qcom,sm8550-videocc - qcom,sm8650-videocc - qcom,sm8750-videocc - qcom,x1e80100-videocc + - qcom,x1p42100-videocc clocks: items: @@ -63,13 +69,11 @@ allOf: - if: properties: compatible: - contains: - enum: - - qcom,glymur-videocc - - qcom,kaanapali-videocc - - qcom,sm8450-videocc - - qcom,sm8550-videocc - - qcom,sm8750-videocc + not: + contains: + enum: + - qcom,sm8475-videocc + - qcom,sm8650-videocc then: required: - required-opps diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index 591ce91b8d54..61f58fbd5bd2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -16,6 +16,7 @@ description: | See also: - include/dt-bindings/clock/qcom,kaanapali-dispcc.h + - include/dt-bindings/clock/qcom,nord-dispcc.h - include/dt-bindings/clock/qcom,sm8550-dispcc.h - include/dt-bindings/clock/qcom,sm8650-dispcc.h - include/dt-bindings/clock/qcom,sm8750-dispcc.h @@ -25,6 +26,8 @@ properties: compatible: enum: - qcom,kaanapali-dispcc + - qcom,nord-dispcc0 + - qcom,nord-dispcc1 - qcom,sar2130p-dispcc - qcom,sm8550-dispcc - qcom,sm8650-dispcc diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 1ccdf4b0f5dd..1f3332275c17 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -16,7 +16,7 @@ description: | See also: - include/dt-bindings/clock/qcom,eliza-tcsr.h - - include/dt-bindings/clock/qcom,glymur-tcsr.h + - include/dt-bindings/clock/qcom,hawi-tcsrcc.h - include/dt-bindings/clock/qcom,nord-tcsrcc.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h @@ -24,19 +24,25 @@ description: | properties: compatible: - items: - - enum: - - qcom,eliza-tcsr - - qcom,glymur-tcsr - - qcom,kaanapali-tcsr - - qcom,milos-tcsr - - qcom,nord-tcsrcc - - qcom,sar2130p-tcsr - - qcom,sm8550-tcsr - - qcom,sm8650-tcsr - - qcom,sm8750-tcsr - - qcom,x1e80100-tcsr - - const: syscon + oneOf: + - items: + - enum: + - qcom,eliza-tcsr + - qcom,hawi-tcsrcc + - qcom,kaanapali-tcsr + - qcom,milos-tcsr + - qcom,nord-tcsrcc + - qcom,sar2130p-tcsr + - qcom,sm8550-tcsr + - qcom,sm8650-tcsr + - qcom,sm8750-tcsr + - qcom,x1e80100-tcsr + - const: syscon + - items: + - enum: + - qcom,maili-tcsrcc + - const: qcom,hawi-tcsrcc + - const: syscon clocks: items: diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index f4ff9acef9d5..124d259fc85e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -13,7 +13,7 @@ description: | Qualcomm video clock control module provides the clocks, resets and power domains on Qualcomm SoCs. - See also:: + See also: include/dt-bindings/clock/qcom,sm6350-videocc.h include/dt-bindings/clock/qcom,videocc-sc7180.h include/dt-bindings/clock/qcom,videocc-sc7280.h diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml index 938a2f1ff3fc..e7cb8cfa957a 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml @@ -8,12 +8,14 @@ title: Qualcomm Camera Clock & Reset Controller on x1e80100 maintainers: - Bryan O'Donoghue <bryan.odonoghue@linaro.org> + - Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> description: | Qualcomm camera clock control module provides the clocks, resets and power domains on x1e80100. See also: + include/dt-bindings/clock/qcom,glymur-camcc.h include/dt-bindings/clock/qcom,x1e80100-camcc.h allOf: @@ -22,7 +24,9 @@ allOf: properties: compatible: enum: + - qcom,glymur-camcc - qcom,x1e80100-camcc + - qcom,x1p42100-camcc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml index a0e09b7002f0..703b5bf26717 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -41,7 +41,7 @@ properties: clock-output-names: minItems: 3 - maxItems: 17 + maxItems: 19 renesas,mode: description: Board-specific settings of the MD_CK* bits on R-Mobile A1 @@ -90,6 +90,8 @@ allOf: - const: zx - const: zs - const: hp + - const: ztr + - const: zt - if: properties: @@ -123,6 +125,8 @@ allOf: - const: zb - const: m3 - const: cp + - const: ztr + - const: zt required: - renesas,mode @@ -240,6 +244,6 @@ examples: #clock-cells = <1>; clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", "m1", "hp", "hpp", - "usbp", "s", "zb", "m3", "cp"; + "usbp", "s", "zb", "m3", "cp", "ztr", "zt"; renesas,mode = <0x05>; }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml index 2197c952e21d..b6ee8c8efd46 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml @@ -60,7 +60,7 @@ examples: clock-output-names = "main", "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; + "zx", "zs", "hp", "ztr", "zt"; }; sdhi2_clk: sdhi2_clk@e615007c { diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml new file mode 100644 index 000000000000..4e23bba33438 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,r8a78000-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car X5H Clock Pulse Generator + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The R-Car X5H Clock Pulse Generator (CLK CONTROL) consists of oscillators, + PLL circuits, clock dividers and clock control circuits. It provides various + clocks for other modules. + +properties: + compatible: + const: renesas,r8a78000-cpg + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: extal + - const: extalr + + '#clock-cells': + description: + The single clock specifier cell must be the clock number, as defined in + <dt-bindings/clock/renesas,r8a78000-cpg.h>. + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@c1320000 { + compatible = "renesas,r8a78000-cpg"; + reg = <0xc1320000 0x10000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml index c84f29f1810f..a14be249fa33 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml @@ -13,8 +13,8 @@ description: | If you connect an external clock to the USB_EXTAL pin only, you should set the clock rate to "usb_extal" node only. If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module - is not needed because this is default setting. (Of course, you can set the - clock rates to both "usb_extal" and "usb_xtal" nodes. + is not needed because this is default setting (Of course, you can set the + clock rates to both "usb_extal" and "usb_xtal" nodes). Case 1: An external clock connects to R-Car SoC +----------+ +--- R-Car ---------------------+ diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index f261445bf341..dd3e66a4559b 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -26,16 +26,22 @@ properties: maxItems: 1 clocks: + minItems: 3 items: - description: AUDIO_EXTAL clock input - description: RTXIN clock input - description: QEXTAL clock input + - description: AUDIO_CLKB clock input + - description: AUDIO_CLKC clock input clock-names: + minItems: 3 items: - const: audio_extal - const: rtxin - const: qextal + - const: audio_clkb + - const: audio_clkc '#clock-cells': description: | diff --git a/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml index b339f1f9f072..990d287d0a90 100644 --- a/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas Versaclock7 Programmable Clock maintainers: - - Alex Helms <alexander.helms.jy@renesas.com> + - Biju Das <biju.das.jz@bp.renesas.com> description: | Renesas Versaclock7 is a family of configurable clock generator and diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml new file mode 100644 index 000000000000..b99dce9ff935 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RV1106 Clock and Reset Unit + +maintainers: + - Simon Glass <sjg@chromium.org> + - Heiko Stuebner <heiko@sntech.de> + +description: + The RV1106 clock controller generates the clock and also implements a + reset controller for SoC peripherals. + +properties: + compatible: + const: rockchip,rv1106-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 1 + + clock-names: + const: xin24m + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the "general register files" (GRF). + If missing, pll rates are not changeable due to the missing pll + lock status, and the MMC drive and sample phase clocks, whose + control registers live in the GRF region, are not registered. + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff3b0000 { + compatible = "rockchip,rv1106-cru"; + reg = <0xff3b0000 0x20000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml index b05f83533e3d..56ab972c3da5 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml @@ -14,17 +14,17 @@ maintainers: description: | Expected external clocks, defined in DTS as fixed-rate clocks with a matching - name:: + name: - "fin_pll" - PLL input clock from XXTI - "xrtcxti" - input clock from XRTCXTI - "ioclk_pcm_extclk" - pcm external operation clock - "ioclk_spdif_extclk" - spdif external operation clock - "ioclk_i2s_cdclk" - i2s0 codec clock - Phy clocks:: + Phy clocks: There are several clocks which are generated by specific PHYs. These clocks are fed into the clock controller and then routed to the hardware blocks. - These clocks are defined as fixed clocks in the driver with following names:: + These clocks are defined as fixed clocks in the driver with following names: - "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 - "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 - "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml index b737c9d35a1c..1d907dd8fbf1 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml @@ -14,7 +14,7 @@ maintainers: description: | Expected external clocks, defined in DTS as fixed-rate clocks with a matching - name:: + name: - "fin_pll" - PLL input clock from XXTI All available clocks are defined as preprocessor macros in diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml index 3f9326e09f79..8a289f1e2ace 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml @@ -14,7 +14,7 @@ maintainers: description: | Expected external clocks, defined in DTS as fixed-rate clocks with a matching - name:: + name: - "oscclk" - PLL input clock from XXTI All available clocks are defined as preprocessor macros in diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml index c137c6744ef9..a51cd4fafb41 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml @@ -14,7 +14,7 @@ maintainers: description: | Expected external clocks, defined in DTS as fixed-rate clocks with a matching - name:: + name: - "fin_pll" - PLL input clock from XXTI All available clocks are defined as preprocessor macros in diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml index cdc5ded59fe5..68c2fd318765 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -17,7 +17,7 @@ description: | Exynos850 clock controller is comprised of several CMU units, generating clocks for different domains. Those CMU units are modeled as separate device tree nodes, and might depend on each other. Root clocks in that clock tree are - two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external + two external clocks: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external clocks must be defined as fixed-rate clocks in dts. CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml index 32f39e543b36..3dcdfa7a8792 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Samsung Exynos Auto v9 SoC clock controller maintainers: - - Chanho Park <chanho61.park@samsung.com> + - Alim Akhtar <alim.akhtar@samsung.com> - Chanwoo Choi <cw00.choi@samsung.com> - Krzysztof Kozlowski <krzk@kernel.org> - Sylwester Nawrocki <s.nawrocki@samsung.com> @@ -17,7 +17,7 @@ description: | Exynos Auto v9 clock controller is comprised of several CMU units, generating clocks for different domains. Those CMU units are modeled as separate device tree nodes, and might depend on each other. Root clocks in that clock tree are - two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz). + two external clocks: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz). The external OSCCLK must be defined as fixed-rate clock in dts. CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml index 6b1fc61a2ff9..475db824d4d3 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml @@ -17,7 +17,7 @@ description: | ExynosAuto v920 clock controller is comprised of several CMU units, generating clocks for different domains. Those CMU units are modeled as separate device tree nodes, and might depend on each other. Root clocks in that clock tree are - two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz). + two external clocks: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz). The external OSCCLK must be defined as fixed-rate clock in dts. CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and diff --git a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml index 67a33665cf00..b1617d96d3fb 100644 --- a/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml @@ -14,7 +14,7 @@ maintainers: description: | Expected external clocks, defined in DTS as fixed-rate clocks with a matching - name:: + name: - "xxti" - external crystal oscillator connected to XXTI and XXTO pins of the SoC, - "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO diff --git a/Documentation/devicetree/bindings/clock/silabs,si544.yaml b/Documentation/devicetree/bindings/clock/silabs,si544.yaml index f87e71867108..218f5abdef26 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si544.yaml +++ b/Documentation/devicetree/bindings/clock/silabs,si544.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/clock/silabs,si544.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Silicon Labs SI514/SI544 clock generator +title: Silicon Labs SI514/SI544/SI549 clock generator maintainers: - Mike Looijmans <mike.looijmans@topic.nl> @@ -13,8 +13,9 @@ description: > Silicon Labs 514/544 programmable I2C clock generator. Details about the device can be found in the datasheet: - https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf - https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si514.pdf + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si544-datasheet.pdf + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si549-datasheet.pdf properties: compatible: @@ -23,6 +24,9 @@ properties: - silabs,si544a - silabs,si544b - silabs,si544c + - silabs,si549a + - silabs,si549b + - silabs,si549c reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml index 4368063c6709..e4d64d4b63c6 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml @@ -125,75 +125,75 @@ examples: reg = <0x44200000 0x10000>; #clock-cells = <1>; #reset-cells = <1>; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_MSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>, - <&scmi_clk CK_SCMI_HSE_DIV2>, - <&scmi_clk CK_SCMI_ICN_HS_MCU>, - <&scmi_clk CK_SCMI_ICN_LS_MCU>, - <&scmi_clk CK_SCMI_ICN_SDMMC>, - <&scmi_clk CK_SCMI_ICN_DDR>, - <&scmi_clk CK_SCMI_ICN_DISPLAY>, - <&scmi_clk CK_SCMI_ICN_HSL>, - <&scmi_clk CK_SCMI_ICN_NIC>, - <&scmi_clk CK_SCMI_FLEXGEN_07>, - <&scmi_clk CK_SCMI_FLEXGEN_08>, - <&scmi_clk CK_SCMI_FLEXGEN_09>, - <&scmi_clk CK_SCMI_FLEXGEN_10>, - <&scmi_clk CK_SCMI_FLEXGEN_11>, - <&scmi_clk CK_SCMI_FLEXGEN_12>, - <&scmi_clk CK_SCMI_FLEXGEN_13>, - <&scmi_clk CK_SCMI_FLEXGEN_14>, - <&scmi_clk CK_SCMI_FLEXGEN_16>, - <&scmi_clk CK_SCMI_FLEXGEN_17>, - <&scmi_clk CK_SCMI_FLEXGEN_18>, - <&scmi_clk CK_SCMI_FLEXGEN_19>, - <&scmi_clk CK_SCMI_FLEXGEN_20>, - <&scmi_clk CK_SCMI_FLEXGEN_21>, - <&scmi_clk CK_SCMI_FLEXGEN_22>, - <&scmi_clk CK_SCMI_FLEXGEN_23>, - <&scmi_clk CK_SCMI_FLEXGEN_24>, - <&scmi_clk CK_SCMI_FLEXGEN_25>, - <&scmi_clk CK_SCMI_FLEXGEN_26>, - <&scmi_clk CK_SCMI_FLEXGEN_27>, - <&scmi_clk CK_SCMI_FLEXGEN_29>, - <&scmi_clk CK_SCMI_FLEXGEN_30>, - <&scmi_clk CK_SCMI_FLEXGEN_31>, - <&scmi_clk CK_SCMI_FLEXGEN_33>, - <&scmi_clk CK_SCMI_FLEXGEN_36>, - <&scmi_clk CK_SCMI_FLEXGEN_37>, - <&scmi_clk CK_SCMI_FLEXGEN_38>, - <&scmi_clk CK_SCMI_FLEXGEN_39>, - <&scmi_clk CK_SCMI_FLEXGEN_40>, - <&scmi_clk CK_SCMI_FLEXGEN_41>, - <&scmi_clk CK_SCMI_FLEXGEN_42>, - <&scmi_clk CK_SCMI_FLEXGEN_43>, - <&scmi_clk CK_SCMI_FLEXGEN_44>, - <&scmi_clk CK_SCMI_FLEXGEN_45>, - <&scmi_clk CK_SCMI_FLEXGEN_46>, - <&scmi_clk CK_SCMI_FLEXGEN_47>, - <&scmi_clk CK_SCMI_FLEXGEN_48>, - <&scmi_clk CK_SCMI_FLEXGEN_50>, - <&scmi_clk CK_SCMI_FLEXGEN_51>, - <&scmi_clk CK_SCMI_FLEXGEN_52>, - <&scmi_clk CK_SCMI_FLEXGEN_53>, - <&scmi_clk CK_SCMI_FLEXGEN_54>, - <&scmi_clk CK_SCMI_FLEXGEN_55>, - <&scmi_clk CK_SCMI_FLEXGEN_56>, - <&scmi_clk CK_SCMI_FLEXGEN_57>, - <&scmi_clk CK_SCMI_FLEXGEN_58>, - <&scmi_clk CK_SCMI_FLEXGEN_61>, - <&scmi_clk CK_SCMI_FLEXGEN_62>, - <&scmi_clk CK_SCMI_FLEXGEN_63>, - <&scmi_clk CK_SCMI_ICN_APB1>, - <&scmi_clk CK_SCMI_ICN_APB2>, - <&scmi_clk CK_SCMI_ICN_APB3>, - <&scmi_clk CK_SCMI_ICN_APB4>, - <&scmi_clk CK_SCMI_ICN_APB5>, - <&scmi_clk CK_SCMI_ICN_APBDBG>, - <&scmi_clk CK_SCMI_TIMG1>, - <&scmi_clk CK_SCMI_TIMG2>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APB5>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>; }; ... diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml index 1e3b5d218bb0..3b7925d2c175 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml @@ -135,85 +135,85 @@ examples: reg = <0x44200000 0x10000>; #clock-cells = <1>; #reset-cells = <1>; - clocks = <&scmi_clk CK_SCMI_HSE>, - <&scmi_clk CK_SCMI_HSI>, - <&scmi_clk CK_SCMI_MSI>, - <&scmi_clk CK_SCMI_LSE>, - <&scmi_clk CK_SCMI_LSI>, - <&scmi_clk CK_SCMI_HSE_DIV2>, - <&scmi_clk CK_SCMI_ICN_HS_MCU>, - <&scmi_clk CK_SCMI_ICN_LS_MCU>, - <&scmi_clk CK_SCMI_ICN_SDMMC>, - <&scmi_clk CK_SCMI_ICN_DDR>, - <&scmi_clk CK_SCMI_ICN_DISPLAY>, - <&scmi_clk CK_SCMI_ICN_HSL>, - <&scmi_clk CK_SCMI_ICN_NIC>, - <&scmi_clk CK_SCMI_ICN_VID>, - <&scmi_clk CK_SCMI_FLEXGEN_07>, - <&scmi_clk CK_SCMI_FLEXGEN_08>, - <&scmi_clk CK_SCMI_FLEXGEN_09>, - <&scmi_clk CK_SCMI_FLEXGEN_10>, - <&scmi_clk CK_SCMI_FLEXGEN_11>, - <&scmi_clk CK_SCMI_FLEXGEN_12>, - <&scmi_clk CK_SCMI_FLEXGEN_13>, - <&scmi_clk CK_SCMI_FLEXGEN_14>, - <&scmi_clk CK_SCMI_FLEXGEN_15>, - <&scmi_clk CK_SCMI_FLEXGEN_16>, - <&scmi_clk CK_SCMI_FLEXGEN_17>, - <&scmi_clk CK_SCMI_FLEXGEN_18>, - <&scmi_clk CK_SCMI_FLEXGEN_19>, - <&scmi_clk CK_SCMI_FLEXGEN_20>, - <&scmi_clk CK_SCMI_FLEXGEN_21>, - <&scmi_clk CK_SCMI_FLEXGEN_22>, - <&scmi_clk CK_SCMI_FLEXGEN_23>, - <&scmi_clk CK_SCMI_FLEXGEN_24>, - <&scmi_clk CK_SCMI_FLEXGEN_25>, - <&scmi_clk CK_SCMI_FLEXGEN_26>, - <&scmi_clk CK_SCMI_FLEXGEN_27>, - <&scmi_clk CK_SCMI_FLEXGEN_28>, - <&scmi_clk CK_SCMI_FLEXGEN_29>, - <&scmi_clk CK_SCMI_FLEXGEN_30>, - <&scmi_clk CK_SCMI_FLEXGEN_31>, - <&scmi_clk CK_SCMI_FLEXGEN_32>, - <&scmi_clk CK_SCMI_FLEXGEN_33>, - <&scmi_clk CK_SCMI_FLEXGEN_34>, - <&scmi_clk CK_SCMI_FLEXGEN_35>, - <&scmi_clk CK_SCMI_FLEXGEN_36>, - <&scmi_clk CK_SCMI_FLEXGEN_37>, - <&scmi_clk CK_SCMI_FLEXGEN_38>, - <&scmi_clk CK_SCMI_FLEXGEN_39>, - <&scmi_clk CK_SCMI_FLEXGEN_40>, - <&scmi_clk CK_SCMI_FLEXGEN_41>, - <&scmi_clk CK_SCMI_FLEXGEN_42>, - <&scmi_clk CK_SCMI_FLEXGEN_43>, - <&scmi_clk CK_SCMI_FLEXGEN_44>, - <&scmi_clk CK_SCMI_FLEXGEN_45>, - <&scmi_clk CK_SCMI_FLEXGEN_46>, - <&scmi_clk CK_SCMI_FLEXGEN_47>, - <&scmi_clk CK_SCMI_FLEXGEN_48>, - <&scmi_clk CK_SCMI_FLEXGEN_49>, - <&scmi_clk CK_SCMI_FLEXGEN_50>, - <&scmi_clk CK_SCMI_FLEXGEN_51>, - <&scmi_clk CK_SCMI_FLEXGEN_52>, - <&scmi_clk CK_SCMI_FLEXGEN_53>, - <&scmi_clk CK_SCMI_FLEXGEN_54>, - <&scmi_clk CK_SCMI_FLEXGEN_55>, - <&scmi_clk CK_SCMI_FLEXGEN_56>, - <&scmi_clk CK_SCMI_FLEXGEN_57>, - <&scmi_clk CK_SCMI_FLEXGEN_58>, - <&scmi_clk CK_SCMI_FLEXGEN_59>, - <&scmi_clk CK_SCMI_FLEXGEN_60>, - <&scmi_clk CK_SCMI_FLEXGEN_61>, - <&scmi_clk CK_SCMI_FLEXGEN_62>, - <&scmi_clk CK_SCMI_FLEXGEN_63>, - <&scmi_clk CK_SCMI_ICN_APB1>, - <&scmi_clk CK_SCMI_ICN_APB2>, - <&scmi_clk CK_SCMI_ICN_APB3>, - <&scmi_clk CK_SCMI_ICN_APB4>, - <&scmi_clk CK_SCMI_ICN_APBDBG>, - <&scmi_clk CK_SCMI_TIMG1>, - <&scmi_clk CK_SCMI_TIMG2>, - <&scmi_clk CK_SCMI_PLL3>, - <&clk_dsi_txbyte>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_ICN_VID>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_15>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_28>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_32>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_34>, + <&scmi_clk CK_SCMI_FLEXGEN_35>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_49>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_59>, + <&scmi_clk CK_SCMI_FLEXGEN_60>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>, + <&scmi_clk CK_SCMI_PLL3>, + <&clk_dsi_txbyte>; }; ... diff --git a/Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml b/Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml new file mode 100644 index 000000000000..ed42adb27832 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,keystone,psc-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone PSC clock + +maintainers: + - Santosh Shilimkar <santosh.shilimkar@ti.com> + - Murali Karicheri <m-karicheri2@ti.com> + +properties: + compatible: + const: ti,keystone,psc-clock + + reg: + items: + - description: PSC control + - description: Domain + + reg-names: + items: + - const: control + - const: domain + + domain-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: PSC domain id needed to check the transition state register + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + "#clock-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - domain-id + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + clkusb@2350008 { + compatible = "ti,keystone,psc-clock"; + reg = <0x02350008 0xb00>, <0x02350000 0x400>; + reg-names = "control", "domain"; + domain-id = <0>; + clocks = <&chipclk16>; + clock-output-names = "usb"; + #clock-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/clock/ti/apll.txt b/Documentation/devicetree/bindings/clock/ti/apll.txt deleted file mode 100644 index bbd505c1199d..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/apll.txt +++ /dev/null @@ -1,43 +0,0 @@ -Binding for Texas Instruments APLL clock. - -This binding uses the common clock binding[1]. It assumes a -register-mapped APLL with usually two selectable input clocks -(reference clock and bypass clock), with analog phase locked -loop logic for multiplying the input clock to a desired output -clock. This clock also typically supports different operation -modes (locked, low power stop etc.) APLL mostly behaves like -a subtype of a DPLL [2], although a simplified one at that. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt -[2] Documentation/devicetree/bindings/clock/ti/dpll.txt - -Required properties: -- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of parent clocks (clk-ref and clk-bypass) -- reg : address and length of the register set for controlling the APLL. - It contains the information of registers in the following order: - "control" - contains the control register offset - "idlest" - contains the idlest register offset - "autoidle" - contains the autoidle register offset (OMAP2 only) -- ti,clock-frequency : static clock frequency for the clock (OMAP2 only) -- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only) -- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only) - -Examples: - apll_pcie_ck: apll_pcie_ck { - #clock-cells = <0>; - clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; - reg = <0x021c>, <0x0220>; - compatible = "ti,dra7-apll-clock"; - }; - - apll96_ck: apll96_ck { - #clock-cells = <0>; - compatible = "ti,omap2-apll-clock"; - clocks = <&sys_ck>; - ti,bit-shift = <2>; - ti,idlest-shift = <8>; - ti,clock-frequency = <96000000>; - reg = <0x0500>, <0x0530>, <0x0520>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt deleted file mode 100644 index edf0b5d42768..000000000000 --- a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt +++ /dev/null @@ -1,25 +0,0 @@ -Binding for Texas Instruments clockdomain. - -This binding uses the common clock binding[1] in consumer role. -Every clock on TI SoC belongs to one clockdomain, but software -only needs this information for specific clocks which require -their parent clockdomain to be controlled when the clock is -enabled/disabled. This binding doesn't define a new clock -binding type, it is used to group existing clock nodes under -hardware hierarchy. - -[1] Documentation/devicetree/bindings/clock/clock-bindings.txt - -Required properties: -- compatible : shall be "ti,clockdomain" -- #clock-cells : from common clock binding; shall be set to 0. -- clocks : link phandles of clocks within this domain - -Optional properties: -- clock-output-names : from common clock binding. - -Examples: - dss_clkdm: dss_clkdm { - compatible = "ti,clockdomain"; - clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; - }; diff --git a/Documentation/devicetree/bindings/clock/ti/ti,apll-clock.yaml b/Documentation/devicetree/bindings/clock/ti/ti,apll-clock.yaml new file mode 100644 index 000000000000..e14a76254ce7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,apll-clock.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,apll-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments APLL clock + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +allOf: + - $ref: /schemas/clock/clock.yaml# + +description: + This binding assumes a register-mapped APLL with usually two selectable + input clocks (reference clock and bypass clock), with analog phase locked + loop logic for multiplying the input clock to a desired output clock. + This clock also typically supports different operation modes (locked, low + power stop etc.) APLL mostly behaves like a subtype of a DPLL, although + a simplified one at that. + +properties: + compatible: + enum: + - ti,dra7-apll-clock + - ti,omap2-apll-clock + + "#clock-cells": + const: 0 + + clocks: + minItems: 1 + maxItems: 2 + description: Link phandles of parent clocks (clk-ref and clk-bypass) + + reg: + minItems: 2 + maxItems: 3 + description: | + Address and length of the register set for controlling the APLL. + It contains the information of registers in the following order: + "control" - contains the control register offset + "idlest" - contains the idlest register offset + "autoidle" - contains the autoidle register offset (OMAP2 only) + + ti,clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: static clock frequency for the clock (OMAP2 only) + + ti,idlest-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: bit-shift for the idlest field (OMAP2 only) + + ti,bit-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + description: bit-shift for enable and autoidle fields (OMAP2 only) + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + clock@21c { + #clock-cells = <0>; + compatible = "ti,dra7-apll-clock"; + clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; + reg = <0x021c>, <0x0220>; + }; + + clock@500 { + #clock-cells = <0>; + compatible = "ti,omap2-apll-clock"; + clocks = <&sys_ck>; + ti,bit-shift = <2>; + ti,idlest-shift = <8>; + ti,clock-frequency = <96000000>; + reg = <0x0500>, <0x0530>, <0x0520>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/ti/ti,clockdomain.yaml b/Documentation/devicetree/bindings/clock/ti/ti,clockdomain.yaml new file mode 100644 index 000000000000..95746bfdced4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/ti,clockdomain.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti/ti,clockdomain.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments clockdomain + +maintainers: + - Tero Kristo <kristo@kernel.org> + +description: + This binding uses the common clock binding in consumer role. Every clock on TI + SoC belongs to one clockdomain, but software only needs this information for + specific clocks which require their parent clockdomain to be controlled when + the clock is enabled/disabled. This binding doesn't define a new clock binding + type, it is used to group existing clock nodes under hardware hierarchy. + +properties: + compatible: + const: ti,clockdomain + + "#clock-cells": + const: 0 + + clocks: + minItems: 1 + maxItems: 64 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + dss_clkdm { + compatible = "ti,clockdomain"; + clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>; + }; diff --git a/Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml b/Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml index eaa727ab0d7f..438e190d1067 100644 --- a/Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml +++ b/Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml @@ -19,7 +19,7 @@ description: | that is used. [1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml - [2] Documentation/devicetree/bindings/clock/ti/clockdomain.txt + [2] Documentation/devicetree/bindings/clock/ti/ti,clockdomain.yaml properties: compatible: diff --git a/Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml b/Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml new file mode 100644 index 000000000000..ede565ec440c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ultrarisc,dp1000-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 Clock Controller + +maintainers: + - Jia Wang <wangjia@ultrarisc.com> + +description: | + The UltraRISC DP1000 clock controller is driven from a single external + oscillator input. It provides a system PLL with fractional multiplier + and post-divider stages, several fixed-ratio derived clocks for + the on-chip subsystem, Clock Configuration Register (CCR) divider + outputs for GMAC and the UART, I2C, and SPI root clocks, and + per-instance gate clocks for UART0-3, I2C0-3, and SPI0-1. + + All available clocks are defined as preprocessor macros in + include/dt-bindings/clock/ultrarisc,dp1000-clk.h + +properties: + compatible: + const: ultrarisc,dp1000-clk + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + External oscillator input clock used as the parent of the PLLs. + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/ultrarisc,dp1000-clk.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@11080000 { + compatible = "ultrarisc,dp1000-clk"; + reg = <0x0 0x11080000 0x0 0x1000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml index b497c28e8094..3f311f90294e 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -70,7 +70,7 @@ additionalProperties: false examples: - | - clock-controller@b0000000 { + clock-controller@b0000000 { compatible = "xlnx,clocking-wizard"; reg = <0xb0000000 0x10000>; #clock-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index bef109d163a8..1f36ccc4cde1 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -17,9 +17,7 @@ description: | properties: compatible: oneOf: - - enum: - - xlnx,versal-clk - - xlnx,zynqmp-clk + - const: xlnx,versal-clk - items: - enum: - xlnx,versal-net-clk @@ -32,11 +30,17 @@ properties: description: List of clock specifiers which are external input clocks to the given clock controller. minItems: 2 - maxItems: 8 + items: + - description: reference clock + - description: alternate reference clock for programmable logic + - description: alternate reference clock clock-names: minItems: 2 - maxItems: 8 + items: + - const: ref + - const: pl_alt_ref + - const: alt_ref required: - compatible @@ -52,79 +56,25 @@ allOf: compatible: contains: enum: - - xlnx,versal-clk - - then: - properties: - clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - clock-names: - items: - - const: ref - - const: pl_alt_ref - - - if: - properties: - compatible: - contains: - enum: - xlnx,versal-net-clk - then: properties: clocks: - items: - - description: reference clock - - description: alternate reference clock for programmable logic - - description: alternate reference clock - + minItems: 3 clock-names: - items: - - const: ref - - const: pl_alt_ref - - const: alt_ref - - - if: - properties: - compatible: - contains: - enum: - - xlnx,zynqmp-clk - - then: + minItems: 3 + else: properties: clocks: - minItems: 5 - items: - - description: PS reference clock - - description: reference clock for video system - - description: alternative PS reference clock - - description: auxiliary reference clock - - description: transceiver reference clock - - description: (E)MIO clock source (Optional clock) - - description: GEM emio clock (Optional clock) - - description: Watchdog external clock (Optional clock) - + maxItems: 2 clock-names: - minItems: 5 - items: - - const: pss_ref_clk - - const: video_clk - - const: pss_alt_ref_clk - - const: aux_ref_clk - - const: gt_crx_ref_clk - - pattern: "^mio_clk[00-77]+.*$" - - pattern: "gem[0-3]+_emio_clk.*$" - - pattern: "swdt[0-1]+_ext_clk.*$" + maxItems: 2 examples: - | firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; + versal-firmware { + compatible = "xlnx,versal-firmware"; method = "smc"; versal_clk: clock-controller { #clock-cells = <1>; @@ -135,12 +85,11 @@ examples: }; }; + - | clock-controller { - #clock-cells = <1>; - compatible = "xlnx,zynqmp-clk"; - clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, - <&aux_ref_clk>, <>_crx_ref_clk>; - clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", - "aux_ref_clk", "gt_crx_ref_clk"; + compatible = "xlnx,versal-net-clk", "xlnx,versal-clk"; + clocks = <&ref>, <&pl_alt_ref>, <&alt_ref>; + clock-names = "ref", "pl_alt_ref", "alt_ref"; + #clock-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml new file mode 100644 index 000000000000..c64550471581 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,zynqmp-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP clock controller + +maintainers: + - Michal Simek <michal.simek@amd.com> + +description: + The clock controller is a hardware block of Xilinx ZynqMP clock tree. It + reads required input clock frequencies from the devicetree and acts as clock + provider for all clock consumers of PS clocks. + +properties: + compatible: + const: xlnx,zynqmp-clk + + "#clock-cells": + const: 1 + + clocks: + description: List of clock specifiers which are external input + clocks to the given clock controller. + minItems: 5 + items: + - description: PS reference clock + - description: reference clock for video system + - description: alternative PS reference clock + - description: auxiliary reference clock + - description: transceiver reference clock + - description: (E)MIO clock source + - description: GEM emio clock + - description: Watchdog external clock + + clock-names: + minItems: 5 + items: + - const: pss_ref_clk + - const: video_clk + - const: pss_alt_ref_clk + - const: aux_ref_clk + - const: gt_crx_ref_clk + - pattern: "^mio_clk([0-6][0-9]|7[0-7])+.*$" + - pattern: "gem[0-3]+_emio_clk.*$" + - pattern: "swdt[0-1]+_ext_clk.*$" + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml b/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml new file mode 100644 index 000000000000..1a3105e86980 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/qcom,shikra-epss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra SoC EPSS + +maintainers: + - Imran Shaik <imran.shaik@oss.qualcomm.com> + - Taniya Das <taniya.das@oss.qualcomm.com> + +description: | + EPSS is a hardware engine used by some Qualcomm SoCs to manage + frequency in hardware. It is capable of controlling frequency for + multiple clusters. + + The Qualcomm Shikra SoC EPSS supports up to 12 frequency lookup table + (LUT) entries. + +properties: + compatible: + enum: + - qcom,shikra-epss + + reg: + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + + reg-names: + items: + - const: freq-domain0 + - const: freq-domain1 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + interrupts: + items: + - description: IRQ line for DCVSH 0 + - description: IRQ line for DCVSH 1 + + interrupt-names: + items: + - const: dcvsh-irq-0 + - const: dcvsh-irq-1 + + '#freq-domain-cells': + const: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - '#freq-domain-cells' + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <1>; + #size-cells = <1>; + + cpufreq@fd91000 { + compatible = "qcom,shikra-epss"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gpll0>; + clock-names = "xo", "alternate"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index 876bf90ed96e..23bf98c2b9fa 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -14,22 +14,37 @@ properties: items: - enum: - qcom,eliza-inline-crypto-engine + - qcom,hawi-inline-crypto-engine - qcom,kaanapali-inline-crypto-engine + - qcom,maili-inline-crypto-engine - qcom,milos-inline-crypto-engine + - qcom,nord-inline-crypto-engine - qcom,qcs8300-inline-crypto-engine - qcom,sa8775p-inline-crypto-engine - qcom,sc7180-inline-crypto-engine - qcom,sc7280-inline-crypto-engine + - qcom,shikra-inline-crypto-engine - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine - qcom,sm8750-inline-crypto-engine + - qcom,x1e80100-inline-crypto-engine - const: qcom,inline-crypto-engine reg: maxItems: 1 clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: core + - const: iface + + power-domains: maxItems: 1 operating-points-v2: true @@ -44,6 +59,36 @@ required: additionalProperties: false +# Do not extend the list. +# Legacy SoCs are allowed for single clock. +# New SoCs must provide both clocks and power domains. +allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - qcom,kaanapali-inline-crypto-engine + - qcom,qcs8300-inline-crypto-engine + - qcom,sa8775p-inline-crypto-engine + - qcom,sc7180-inline-crypto-engine + - qcom,sc7280-inline-crypto-engine + - qcom,sm8450-inline-crypto-engine + - qcom,sm8550-inline-crypto-engine + - qcom,sm8650-inline-crypto-engine + - qcom,sm8750-inline-crypto-engine + + then: + required: + - power-domains + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + examples: - | #include <dt-bindings/clock/qcom,sm8550-gcc.h> @@ -52,7 +97,11 @@ examples: compatible = "qcom,sm8550-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0x01d88000 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; operating-points-v2 = <&ice_opp_table>; diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml index 41402599e9ab..de323969fe64 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -17,16 +17,21 @@ properties: - qcom,prng-ee # 8996 and later using EE - items: - enum: + - qcom,glymur-trng + - qcom,hawi-trng - qcom,ipq5332-trng - qcom,ipq5424-trng - qcom,ipq9574-trng - qcom,kaanapali-trng + - qcom,maili-trng - qcom,milos-trng + - qcom,nord-trng - qcom,qcs615-trng - qcom,qcs8300-trng - qcom,sa8255p-trng - qcom,sa8775p-trng - qcom,sc7280-trng + - qcom,shikra-trng - qcom,sm8450-trng - qcom,sm8550-trng - qcom,sm8650-trng diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index 79d5be2548bc..5a653757ee75 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -45,11 +45,16 @@ properties: - items: - enum: + - qcom,eliza-qce + - qcom,glymur-qce - qcom,kaanapali-qce + - qcom,milos-qce + - qcom,nord-qce - qcom,qcs615-qce - qcom,qcs8300-qce - qcom,sa8775p-qce - qcom,sc7280-qce + - qcom,shikra-qce - qcom,sm6350-qce - qcom,sm8250-qce - qcom,sm8350-qce diff --git a/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml b/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml index d27dcb2fef12..a3f0cd508b3a 100644 --- a/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml +++ b/Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml @@ -40,7 +40,7 @@ properties: type: object patternProperties: - '^ppmu-event[0-9]+(-[a-z0-9]+){,2}$': + '^ppmu-event[0-9]+(-[a-z0-9]+){0,2}$': type: object properties: event-name: diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml index 9a6e9b25d14a..7cfe92a8bcd7 100644 --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml @@ -36,18 +36,56 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Primary MIPI DSI port-1 for MIPI input or LVDS port-1 for LVDS input or DPI input. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + port@1: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Additional MIPI port-2 for MIPI input or LVDS port-2 for LVDS input. Used in combination with primary port-1 to drive higher resolution displays + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + port@2: $ref: /schemas/graph.yaml#/properties/port description: @@ -99,6 +137,7 @@ examples: reg = <0>; endpoint { + data-lanes = <1 2 3 4>; remote-endpoint = <&dsi0_out>; }; }; diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index 7586d681bcc6..3c727e4d1096 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -34,10 +34,12 @@ properties: - items: - enum: - doestek,dtc34lm85am # For the Doestek DTC34LM85AM Flat Panel Display (FPD) Transmitter + - idt,v103 # For the Triple 10-BIT LVDS Transmitter - onnn,fin3385 # OnSemi FIN3385 - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter + - ti,sn75lvds93 # For the TI SN75LVDS93 FlatLink transmitter - const: lvds-encoder # Generic LVDS encoder compatible fallback - items: - enum: diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index c20625b8425e..3832a553871b 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -28,6 +28,7 @@ properties: - const: renesas,r9a09g057-mipi-dsi - enum: + - renesas,r9a08g046-mipi-dsi # RZ/G3L - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) reg: diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml new file mode 100644 index 000000000000..4cd7b688fbf7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lvds.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3L LVDS Encoder + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + - Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> + +description: | + This binding describes the LVDS encoder embedded in the Renesas RZ/G3L + SoC. The encoder can operate in LVDS Single-link mode with 4 lanes + (Data) + 1 lane (Clock). + +properties: + compatible: + const: renesas,r9a08g046-lvds + + reg: + maxItems: 1 + + clocks: + items: + - description: Peripheral clock + - description: PHY clock + - description: Dot clock + + clock-names: + items: + - const: pclk + - const: phyclk + - const: dotclk + + resets: + items: + - description: LVDS_RESET_N + - description: MIPI_DSI_PRESET_N + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + + reset-names: + items: + - const: lvdrst + - const: prst + - const: rst + - const: arst + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input channel, directly connected to the Display Unit. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: | + Output channel, directly connected to the LVDS panel or bridge. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/renesas,r9a08g046-cpg.h> + + lvds@108a0000 { + compatible = "renesas,r9a08g046-lvds"; + reg = <0x108a0000 0x10000>; + clocks = <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>, + <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>; + clock-names = "pclk", "phyclk", "dotclk"; + resets = <&cpg R9A08G046_LVDS_RESET_N>, + <&cpg R9A08G046_MIPI_DSI_PRESET_N>, + <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>, + <&cpg R9A08G046_MIPI_DSI_ARESET_N>; + reset-names = "lvdrst", "prst", "rst", "arst"; + power-domains = <&cpg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + + port@1 { + reg = <1>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml index e6808419f625..7636c24906ba 100644 --- a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +++ b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml @@ -30,6 +30,7 @@ properties: - algoltek,ag6311 - asl-tek,cs5263 - dumb-vga-dac + - mstar,tsumu88adt3-lf-1 - parade,ps185hdm - radxa,ra620 - realtek,rtd2171 diff --git a/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml b/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml index e2d293d623b8..760645493031 100644 --- a/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml +++ b/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml @@ -10,6 +10,7 @@ maintainers: - Svyatoslav Ryhel <clamor95@gmail.com> allOf: + - $ref: /schemas/display/dsi-controller.yaml# - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: @@ -86,7 +87,7 @@ required: - compatible - ports -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml index 3820dd7e11af..4d34a92192bf 100644 --- a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml @@ -10,11 +10,14 @@ maintainers: - Joseph Guo <qijian.guo@nxp.com> description: - Waveshare bridge board is part of Waveshare panel which converts DSI to DPI. + Waveshare bridge board is part of Waveshare panel which converts DSI to DPI + or LVDS. properties: compatible: - const: waveshare,dsi2dpi + enum: + - waveshare,dsi2dpi + - waveshare,dsi2lvds reg: maxItems: 1 @@ -53,7 +56,7 @@ properties: port@1: $ref: /schemas/graph.yaml#/properties/port description: - Video port for MIPI DPI output panel. + Video port for MIPI DPI or LVDS output to the panel. required: - port@0 diff --git a/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml b/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml index 72d14babe993..6ac5ababbe00 100644 --- a/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml +++ b/Documentation/devicetree/bindings/display/fsl,ls1021a-dcu.yaml @@ -45,6 +45,15 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: The phandle to the timing controller node. + display: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to display panel + deprecated: true + + display0: + $ref: panel/panel-common.yaml# + deprecated: true + required: - compatible - reg @@ -53,6 +62,19 @@ required: additionalProperties: false +allOf: + - if: + not: + properties: + compatible: + contains: + enum: + - fsl,ls1021a-dcu + then: + properties: + display: false + display0: false + examples: - | display-controller@2ce0000 { diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml index bbcfe7e2958b..b0c5869771fa 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml @@ -42,6 +42,17 @@ properties: unevaluatedProperties: false description: output port connected to a panel + port: + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + deprecated: true + description: input port connected to the IPU display interface, see port@0 + + display-timings: + $ref: /schemas/display/panel/display-timings.yaml# + unevaluatedProperties: false + deprecated: true + required: - compatible diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx53-tve.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx53-tve.yaml new file mode 100644 index 000000000000..2fcf44745912 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx53-tve.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx53-tve.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX53 Television Encoder (TVE) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The Television Encoder (TVE) is a hardware block in the i.MX53 SoC that + converts digital video data into analog TV signals (NTSC/PAL). + +properties: + compatible: + const: fsl,imx53-tve + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: TVE gate clock + - description: Display interface selector clock + + clock-names: + items: + - const: tve + - const: di_sel + + ddc-i2c-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the I2C bus used for DDC (Display Data Channel) communication + to read EDID information from the connected display. + + dac-supply: + description: + Regulator supply for the TVE DAC (Digital-to-Analog Converter). + + fsl,tve-mode: + $ref: /schemas/types.yaml#/definitions/string + description: + TVE output mode selection. + enum: + - ntsc + - pal + - vga + + fsl,hsync-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pin number for horizontal sync signal in VGA mode. + minimum: 0 + maximum: 8 + + fsl,vsync-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pin number for vertical sync signal in VGA mode. + minimum: 0 + maximum: 8 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Port node with one endpoint connected to the IPU display interface. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - fsl,tve-mode + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx5-clock.h> + #include <dt-bindings/interrupt-controller/irq.h> + + tve@63ff0000 { + compatible = "fsl,imx53-tve"; + reg = <0x63ff0000 0x1000>; + interrupts = <92>; + clocks = <&clks IMX5_CLK_TVE_GATE>, + <&clks IMX5_CLK_IPU_DI1_SEL>; + clock-names = "tve", "di_sel"; + fsl,tve-mode = "vga"; + + port { + endpoint { + remote-endpoint = <&ipu_di1_tve>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml index 27118f4c0d28..fd095e5742c5 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml @@ -41,7 +41,7 @@ properties: - const: sw3 sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: phandle pointing to the mmio-sram device node required: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml index 080cf321209e..bc288b1c6f07 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,cec.yaml @@ -15,10 +15,13 @@ description: | properties: compatible: - enum: - - mediatek,mt7623-cec - - mediatek,mt8167-cec - - mediatek,mt8173-cec + oneOf: + - const: mediatek,mt8173-cec + - items: + - enum: + - mediatek,mt7623-cec + - mediatek,mt8167-cec + - const: mediatek,mt8173-cec reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml index bacdfe7d08a6..ac0d924a451b 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml @@ -45,9 +45,8 @@ properties: - description: OVL-2L Clock iommus: - description: - This property should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + minItems: 1 + maxItems: 2 mediatek,gce-client-reg: description: The register of client driver can be configured by gce with diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 679f731f0f15..4df5c7b410c6 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -66,9 +66,8 @@ properties: - description: OVL Clock iommus: - description: - This property should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + minItems: 1 + maxItems: 2 mediatek,gce-client-reg: description: The register of client driver can be configured by gce with diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index cb187a95c11e..d914c06640df 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -65,9 +65,7 @@ properties: - description: RDMA Clock iommus: - description: - This property should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + maxItems: 1 mediatek,rdma-fifo-size: description: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml index 816841a96133..97d052b0fb61 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml @@ -45,9 +45,7 @@ properties: - description: WDMA Clock iommus: - description: - This property should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + maxItems: 1 mediatek,gce-client-reg: description: The register of client driver can be configured by gce with diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 8239adb7f7d3..094a6383bb77 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -219,6 +219,7 @@ allOf: - required: - "#sound-dai-cells" else: + $ref: /schemas/sound/dai-common.yaml# properties: aux-bus: false required: @@ -243,7 +244,7 @@ allOf: clocks: minItems: 5 maxItems: 5 - clocks-names: + clock-names: minItems: 5 maxItems: 5 @@ -264,7 +265,7 @@ allOf: clocks: minItems: 5 maxItems: 6 - clocks-names: + clock-names: minItems: 5 maxItems: 6 @@ -277,7 +278,6 @@ allOf: - qcom,sc8180x-dp - qcom,sdm845-dp - qcom,sm8350-dp - - qcom,sm8650-dp then: properties: reg: @@ -286,6 +286,24 @@ allOf: clocks: minItems: 6 maxItems: 6 + clock-names: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8650-dp + then: + properties: + reg: + minItems: 5 + maxItems: 9 + clocks: + minItems: 6 + maxItems: 6 clocks-names: minItems: 6 maxItems: 6 @@ -306,7 +324,7 @@ allOf: clocks: minItems: 6 maxItems: 8 - clocks-names: + clock-names: minItems: 6 maxItems: 8 @@ -326,7 +344,7 @@ allOf: clocks: minItems: 5 maxItems: 6 - clocks-names: + clock-names: minItems: 5 maxItems: 6 diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index a24fcb914418..e4fd1cbbd4e0 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -16,6 +16,7 @@ properties: - enum: - qcom,apq8064-dsi-ctrl - qcom,kaanapali-dsi-ctrl + - qcom,milos-dsi-ctrl - qcom,msm8226-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl @@ -47,6 +48,10 @@ properties: - qcom,sm8750-dsi-ctrl - const: qcom,mdss-dsi-ctrl - items: + - const: qcom,shikra-dsi-ctrl + - const: qcom,qcm2290-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + - items: - enum: - qcom,qcs8300-dsi-ctrl - qcom,sc8280xp-dsi-ctrl @@ -72,16 +77,16 @@ properties: clocks: description: | - Several clocks are used, depending on the variant. Typical ones are:: - - bus:: Display AHB clock. - - byte:: Display byte clock. - - byte_intf:: Display byte interface clock. - - core:: Display core clock. - - core_mss:: Core MultiMedia SubSystem clock. - - iface:: Display AXI clock. - - mdp_core:: MDP Core clock. - - mnoc:: MNOC clock - - pixel:: Display pixel clock. + Several clocks are used, depending on the variant. Typical ones are: + - bus: Display AHB clock. + - byte: Display byte clock. + - byte_intf: Display byte interface clock. + - core: Display core clock. + - core_mss: Core MultiMedia SubSystem clock. + - iface: Display AXI clock. + - mdp_core: MDP Core clock. + - mnoc: MNOC clock + - pixel: Display pixel clock. minItems: 3 maxItems: 12 @@ -339,6 +344,7 @@ allOf: compatible: contains: enum: + - qcom,milos-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,sa8775p-dsi-ctrl - qcom,sar2130p-dsi-ctrl diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 93e5e6e19754..9e459f12ce3f 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -262,6 +262,7 @@ allOf: compatible: contains: enum: + - qcom,adreno-gmu-722.0 - qcom,adreno-gmu-730.1 - qcom,adreno-gmu-740.1 - qcom,adreno-gmu-750.1 @@ -304,6 +305,36 @@ allOf: properties: compatible: contains: + const: qcom,adreno-gmu-810.0 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: hub + + - if: + properties: + compatible: + contains: const: qcom,adreno-gmu-840.1 then: properties: diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 04b2328903ca..e5efe2d35ddc 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -84,13 +84,9 @@ properties: maxItems: 64 sram: - $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 4 - items: - maxItems: 1 - description: | - phandles to one or more reserved on-chip SRAM regions. + description: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and a4xx Snapdragon SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml @@ -357,6 +353,7 @@ allOf: - qcom,adreno-610.0 - qcom,adreno-619.1 - qcom,adreno-07000200 + - qcom,adreno-07000400 then: properties: clocks: @@ -416,6 +413,24 @@ allOf: compatible: contains: enum: + - qcom,adreno-44010000 + - qcom,adreno-44050a01 + - qcom,adreno-44070001 + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + reg-names: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: - qcom,adreno-615.0 - qcom,adreno-618.0 - qcom,adreno-619.0 @@ -430,10 +445,14 @@ allOf: - qcom,adreno-680.1 - qcom,adreno-690.0 - qcom,adreno-730.1 + - qcom,adreno-43020100 - qcom,adreno-43030c00 - qcom,adreno-43050a01 - qcom,adreno-43050c01 - qcom,adreno-43051401 + - qcom,adreno-44010000 + - qcom,adreno-44050a01 + - qcom,adreno-44070001 then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml index 47938d13d1ca..bd4ba91a171f 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,eliza-mdss.yaml @@ -119,7 +119,7 @@ examples: mdss_mdp: display-controller@ae01000 { compatible = "qcom,eliza-dpu"; reg = <0x0ae01000 0x93000>, - <0x0aeb0000 0x2008>; + <0x0aeb0000 0x3000>; reg-names = "mdp", "vbif"; @@ -304,7 +304,7 @@ examples: mdss_dsi0_phy: phy@ae95000 { compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; reg = <0x0ae95000 0x200>, - <0x0ae95200 0x280>, + <0x0ae95200 0x300>, <0x0ae95500 0x400>; reg-names = "dsi_phy", "dsi_phy_lane", @@ -388,7 +388,7 @@ examples: mdss_dsi1_phy: phy@ae97000 { compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm"; reg = <0x0ae97000 0x200>, - <0x0ae97200 0x280>, + <0x0ae97200 0x300>, <0x0ae97500 0x400>; reg-names = "dsi_phy", "dsi_phy_lane", @@ -407,11 +407,15 @@ examples: displayport-controller@af54000 { compatible = "qcom,eliza-dp", "qcom,sm8650-dp"; - reg = <0xaf54000 0x104>, - <0xaf54200 0xc0>, - <0xaf55000 0x770>, - <0xaf56000 0x9c>, - <0xaf57000 0x9c>; + reg = <0x0af54000 0x200>, + <0x0af54200 0x200>, + <0x0af55000 0xc00>, + <0x0af56000 0x400>, + <0x0af57000 0x400>, + <0x0af58000 0x400>, + <0x0af59000 0x400>, + <0x0af5a000 0x600>, + <0x0af5b000 0x600>; interrupts-extended = <&mdss 12>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml new file mode 100644 index 000000000000..7010ffa0ae35 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml @@ -0,0 +1,286 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,milos-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos Display MDSS + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: + Milos MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,milos-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,milos-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dsi-phy-4nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> + #include <dt-bindings/clock/qcom,milos-dispcc.h> + #include <dt-bindings/clock/qcom,milos-gcc.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,milos-rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,milos-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,milos-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-402000000 { + opp-hz = /bits/ 64 <402000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-535000000 { + opp-hz = /bits/ 64 <535000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x1000>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,milos-dsi-phy-4nm"; + reg = <0x0ae95000 0x200>, + <0x0ae95200 0x300>, + <0x0ae95500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml index be6cd8adb3b6..034d3df8d247 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml @@ -13,7 +13,11 @@ $ref: /schemas/display/msm/dpu-common.yaml# properties: compatible: - const: qcom,qcm2290-dpu + oneOf: + - const: qcom,qcm2290-dpu + - items: + - const: qcom,shikra-dpu + - const: qcom,qcm2290-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml index bb09ecd1a5b4..49a7b5c4c678 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm QCM220 Display MDSS +title: Qualcomm QCM2290 and Shikra Display MDSS maintainers: - Loic Poulain <loic.poulain@linaro.org> @@ -12,13 +12,18 @@ maintainers: description: Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS - are mentioned for QCM2290 target. + are mentioned for QCM2290 and Shikra targets. Shikra uses the same MDSS/DPU/DSI + hardware as QCM2290 (DPU 6.5) and shares the same register layout. $ref: /schemas/display/msm/mdss-common.yaml# properties: compatible: - const: qcom,qcm2290-mdss + oneOf: + - const: qcom,qcm2290-mdss + - items: + - const: qcom,shikra-mdss + - const: qcom,qcm2290-mdss clocks: items: @@ -52,7 +57,8 @@ patternProperties: properties: compatible: - const: qcom,qcm2290-dpu + contains: + const: qcom,qcm2290-dpu "^dsi@[0-9a-f]+$": type: object @@ -60,9 +66,8 @@ patternProperties: properties: compatible: - items: - - const: qcom,qcm2290-dsi-ctrl - - const: qcom,mdss-dsi-ctrl + contains: + const: qcom,qcm2290-dsi-ctrl "^phy@[0-9a-f]+$": type: object diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml index c41a86203e78..287cce4dbddc 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml @@ -150,7 +150,7 @@ examples: reg = <0>; dpu_intf0_out: endpoint { - remote-endpoint = <&mdss_dp0_in>; + remote-endpoint = <&mdss_dp0_in>; }; }; @@ -352,9 +352,9 @@ examples: }; port@1 { - reg = <1>; + reg = <1>; - mdss_dp_out: endpoint { }; + mdss_dp_out: endpoint { }; }; }; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index e2730a2f25cf..6c827cf9692b 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -200,9 +200,11 @@ examples: <0x0aec2000 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml index 44c1bb9e4109..fb3d24bbac7d 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -248,9 +248,9 @@ examples: remote-endpoint = <&usb_dp_qmpphy_dp_in>; }; }; - }; + }; - dp_opp_table: opp-table { + dp_opp_table: opp-table { compatible = "operating-points-v2"; opp-162000000 { diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml index b4f437172218..8cbf99f9fcba 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6150-dpu.yaml @@ -81,7 +81,7 @@ examples: port@1 { reg = <1>; dpu_intf1_out: endpoint { - remote-endpoint = <&mdss_dsi0_in>; + remote-endpoint = <&mdss_dsi0_in>; }; }; }; @@ -90,18 +90,18 @@ examples: compatible = "operating-points-v2"; opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_low_svs>; + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_low_svs>; }; opp-25600000 { - opp-hz = /bits/ 64 <25600000>; - required-opps = <&rpmhpd_opp_svs>; + opp-hz = /bits/ 64 <25600000>; + required-opps = <&rpmhpd_opp_svs>; }; opp-307200000 { - opp-hz = /bits/ 64 <307200000>; - required-opps = <&rpmhpd_opp_nom>; + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmhpd_opp_nom>; }; }; }; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml index 68176de854b3..f5acf528d0e4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -223,7 +223,7 @@ examples: phys = <&mdss_dsi0_phy>; ports { - #address-cells = <1>; + #address-cells = <1>; #size-cells = <0>; port@0 { diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index dccac525d202..aa0cf0ec5b93 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -18,6 +18,7 @@ properties: - qcom,eliza-dpu - qcom,glymur-dpu - qcom,kaanapali-dpu + - qcom,milos-dpu - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,sm8750-dpu @@ -70,7 +71,7 @@ examples: display-controller@ae01000 { compatible = "qcom,sm8650-dpu"; reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; + <0x0aeb0000 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc_axi_clk>, diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml index a1c53e191033..0f7f79527748 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-mdss.yaml @@ -112,7 +112,7 @@ examples: display-controller@ae01000 { compatible = "qcom,sm8650-dpu"; reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; + <0x0aeb0000 0x3000>; reg-names = "mdp", "vbif"; clocks = <&gcc_axi_clk>, diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml index a38c2261ef1a..46dc0d28da29 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -117,7 +117,7 @@ examples: display-controller@ae01000 { compatible = "qcom,sm8750-dpu"; reg = <0x0ae01000 0x93000>, - <0x0aeb0000 0x2008>; + <0x0aeb0000 0x3000>; reg-names = "mdp", "vbif"; @@ -389,11 +389,15 @@ examples: displayport-controller@af54000 { compatible = "qcom,sm8750-dp", "qcom,sm8650-dp"; - reg = <0xaf54000 0x104>, - <0xaf54200 0xc0>, - <0xaf55000 0x770>, - <0xaf56000 0x9c>, - <0xaf57000 0x9c>; + reg = <0x0af54000 0x200>, + <0x0af54200 0x200>, + <0x0af55000 0xc00>, + <0x0af56000 0x400>, + <0x0af57000 0x400>, + <0x0af58000 0x400>, + <0x0af59000 0x400>, + <0x0af5a000 0x600>, + <0x0af5b000 0x600>; interrupts-extended = <&mdss 12>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml index 8d698a2e055a..8c65a80b46e4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -208,47 +208,47 @@ examples: #sound-dai-cells = <0>; ports { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; + port@0 { + reg = <0>; - mdss_dp0_in: endpoint { - remote-endpoint = <&mdss_intf0_out>; - }; - }; + mdss_dp0_in: endpoint { + remote-endpoint = <&mdss_intf0_out>; + }; + }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - mdss_dp0_out: endpoint { - }; - }; + mdss_dp0_out: endpoint { + }; + }; }; mdss_dp0_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; }; }; }; diff --git a/Documentation/devicetree/bindings/display/panel/anbernic,td4310.yaml b/Documentation/devicetree/bindings/display/panel/anbernic,td4310.yaml new file mode 100644 index 000000000000..f820dc2f732b --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/anbernic,td4310.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/anbernic,td4310.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Anbernic TD4310 Based Panels + +maintainers: + - Chris Morgan <macromorgan@hotmail.com> + +description: + Anbernic TD4310 Based Panels, such as the RG-Vita-Pro panel + (a 1080x1920 5.5 inch panel). + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - anbernic,panel-vita-pro + - const: anbernic,td4310 + + reg: + maxItems: 1 + + vdd-supply: + description: Panel power supply + +required: + - compatible + - port + - reg + - reset-gpios + - vdd-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "anbernic,panel-vita-pro", "anbernic,td4310"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + rotation = <270>; + vdd-supply = <&vdd_lcd>; + + port { + endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/chipone,icna3512.yaml b/Documentation/devicetree/bindings/display/panel/chipone,icna3512.yaml new file mode 100644 index 000000000000..90e69f30cd91 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/chipone,icna3512.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/chipone,icna3512.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chipone ICNA3512 and ICNA3520 display drivers + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: + The Chipone ICNA3512 and ICNA3520 are DDICs connected + using a MIPI-DSI video interface. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - ayaneo,pocketds-panel-top + - ayntec,odin2portal-panel + - const: chipone,icna3512 + + - items: + - enum: + - ayntec,odin3-panel + - ayntec,thor-panel-top + - const: chipone,icna3520 + + reg: + maxItems: 1 + description: DSI virtual channel + + vdd-supply: true + vddio-supply: true + vci-supply: true + disp-supply: true + blvdd-supply: true + + port: true + reset-gpios: true + rotation: true + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + - vci-supply + - disp-supply + - blvdd-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "ayntec,odin2portal-panel", "chipone,icna3512"; + reg = <0>; + vdd-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + disp-supply = <&vdd_disp_2v8>; + blvdd-supply = <&vdd_bl_5v0>; + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml b/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml new file mode 100644 index 000000000000..c8d7b61037e6 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/chipwealth,ch13726a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chip Wealth Technology CH13726A AMOLED driver + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: + Chip Wealth Technology CH13726A is a single-chip solution + for AMOLED connected using a MIPI-DSI video interface. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: ayntec,thor-panel-bottom + - const: chipwealth,ch13726a + + reg: + maxItems: 1 + description: DSI virtual channel + + vdd-supply: true + vddio-supply: true + vdd1v2-supply: true + avdd-supply: true + + port: true + reset-gpios: true + rotation: true + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + - vdd1v2-supply + - avdd-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "ayntec,thor-panel-bottom", "chipwealth,ch13726a"; + reg = <0>; + vdd1v2-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vdd_disp_1v8>; + vdd-supply = <&vreg_l13b_3p0>; + avdd-supply = <&vdd_disp2_2v8>; + reset-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml b/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml new file mode 100644 index 000000000000..db6775f4d75c --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/focaltech,ota7290b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Focaltech OTA7290B DSI panels + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: waveshare,8.8-dsi-touch-a + + reg: + maxItems: 1 + + vdd-supply: + description: supply regulator for VDD, usually 3.3V + + vdda-supply: + description: supply regulator for VDDA, 7-10V + + vcc-supply: + description: supply regulator for VCCIO, usually 1.5V + + reset-gpios: true + backlight: true + rotation: true + port: true + +required: + - compatible + - reg + - vdd-supply + - vcc-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "waveshare,8.8-dsi-touch-a"; + reg = <0>; + vdd-supply = <&vdd>; + vcc-supply = <&vccio>; + reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + + port { + endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; + +... + diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml index 66404b425af3..7667428bf9a8 100644 --- a/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml +++ b/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml @@ -30,6 +30,8 @@ properties: - starry,2082109qfh040022-50e # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel - starry,himax83102-j02 + # Waveshare 12.3-DSI-TOUCH-A panel + - waveshare,12.3-dsi-touch-a - const: himax,hx83102 reg: diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx83121a.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx83121a.yaml index e067a2f6d0b2..aeca3c9a599c 100644 --- a/Documentation/devicetree/bindings/display/panel/himax,hx83121a.yaml +++ b/Documentation/devicetree/bindings/display/panel/himax,hx83121a.yaml @@ -40,6 +40,9 @@ properties: vddi-supply: description: power supply for IC + bl-supply: + description: power supply for backlight, in case it's managed via DSC + backlight: true ports: true diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml index 84e840e0224f..83c343b02835 100644 --- a/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml +++ b/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml @@ -23,6 +23,8 @@ properties: - hannstar,hsd060bhw4 - microchip,ac40t08a-mipi-panel - powkiddy,x55-panel + - waveshare,5.0-dsi-touch-a + - waveshare,5.5-dsi-touch-a - const: himax,hx8394 - items: - enum: diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili7807s.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili7807s.yaml new file mode 100644 index 000000000000..ba8c5bbf8ffc --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili7807s.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ilitek,ili7807s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek ILI7807S-based DSI panels + +maintainers: + - Arpit Saini <arpit.saini@oss.qualcomm.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - dlc,dlc0697 + - const: ilitek,ili7807s + + reg: + maxItems: 1 + description: DSI virtual channel + + vddi-supply: + description: I/O voltage supply (1.8V) + + avdd-supply: + description: Positive LCD bias supply (AVDD), typically +5.5V + (range 4.5V to 6.3V) + + avee-supply: + description: Negative LCD bias supply (AVEE), typically -5.5V + (range -6.3V to -4.5V) + +required: + - compatible + - reg + - reset-gpios + - vddi-supply + - avdd-supply + - avee-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "dlc,dlc0697", "ilitek,ili7807s"; + reg = <0>; + + reset-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + vddi-supply = <&pm4125_l15>; + avdd-supply = <&avdd>; + avee-supply = <&avee>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9488.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9488.yaml new file mode 100644 index 000000000000..ea7449273022 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9488.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/ilitek,ili9488.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ilitek ILI9488 based MIPI-DSI panels + +maintainers: + - Igor Reznichenko <igor@reznichenko.net> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - focuslcds,e35gh-i-mw800cb + - const: ilitek,ili9488 + + reg: + maxItems: 1 + + vci-supply: true + iovcc-supply: true + +required: + - compatible + - reg + - vci-supply + - iovcc-supply + - reset-gpios + - backlight + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "focuslcds,e35gh-i-mw800cb", "ilitek,ili9488"; + reg = <0>; + vci-supply = <®_vci_panel>; + iovcc-supply = <®_iovcc_panel>; + reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + backlight = <&pwm_bl>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml index d979701a00a8..42e35986fbf6 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml @@ -24,6 +24,7 @@ properties: - raspberrypi,dsi-7inch - startek,kd050hdfia020 - tdo,tl050hdv35 + - waveshare,7.0-dsi-touch-a - wanchanglong,w552946aaa - wanchanglong,w552946aba - const: ilitek,ili9881c @@ -34,6 +35,7 @@ properties: backlight: true port: true power-supply: true + iovcc-supply: true reset-gpios: true rotation: true diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml index e39efb44ed42..9e20e2faf82f 100644 --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml @@ -19,11 +19,18 @@ properties: - anbernic,rg-ds-display-bottom - anbernic,rg-ds-display-top - chongzhou,cz101b4001 + - dcltek,dt300250 - kingdisplay,kd101ne3-40ti - melfas,lmfbx101117480 - radxa,display-10hd-ad001 - radxa,display-8hd-ad002 - taiguanck,xti05101-01a + - waveshare,3.4-dsi-touch-c + - waveshare,4.0-dsi-touch-c + - waveshare,8.0-dsi-touch-a + - waveshare,9.0-dsi-touch-b + - waveshare,10.1-dsi-touch-a + - waveshare,10.1-dsi-touch-b - const: jadard,jd9365da-h3 reg: diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml new file mode 100644 index 000000000000..ff6fdad7febf --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt35532.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT35532-based DSI display panels + +maintainers: + - Cristian Cozzolino <cristian_ci@protonmail.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - flipkart,rimob-panel-nt35532-cs + - const: novatek,nt35532 + + reg: + maxItems: 1 + + backlight: true + reset-gpios: true + + avdd-supply: + description: positive boost supply regulator + + avee-supply: + description: negative boost supply regulator + + vci-supply: + description: regulator that supplies the analog voltage + + vddam-supply: + description: power supply for MIPI interface + + vddi-supply: + description: regulator that supplies the I/O voltage + + port: true + +required: + - compatible + - reg + - reset-gpios + - vddi-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "flipkart,rimob-panel-nt35532-cs", "novatek,nt35532"; + reg = <0>; + + backlight = <&pmi8950_wled>; + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; + avdd-supply = <&lab>; + avee-supply = <&ibb>; + vci-supply = <&pm8953_l17>; + vddi-supply = <&pm8953_l6>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36536.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36536.yaml new file mode 100644 index 000000000000..1e86f5329b22 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36536.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt36536.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT36536 based DSI display Panels + +maintainers: + - Pengyu Luo <mitltlatltl@gmail.com> + +description: + The Novatek NT36536 is a generic DSI Panel IC used to drive dsi + panels. Support video mode panels from China Star Optoelectronics + Technology (CSOT), such as PP8807HB1-1 which is a dual-link 10-bit + panel. + +allOf: + - $ref: panel-common-dual.yaml# + +properties: + compatible: + items: + - enum: + - csot,pp8807hb1-1 + - const: novatek,nt36536 + + reg: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + vddio-supply: + description: I/O source voltage rail + + vsp-supply: + description: Positive source voltage rail + + vsn-supply: + description: Negative source voltage rail + + backlight: true + ports: true + +required: + - compatible + - reg + - vddio-supply + - reset-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "csot,pp8807hb1-1", "novatek,nt36536"; + reg = <0>; + + vddio-supply = <&vreg_iovdd_1p8>; + reset-gpios = <&tlmm 98 GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1{ + reg = <1>; + panel_in_1: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml index b31c67babaa8..8382d4920bfd 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml @@ -58,6 +58,12 @@ properties: - hydis,hv070wx2-1e0 # Jenson Display BL-JT60050-01A 7" WSVGA (1024x600) color TFT LCD LVDS panel - jenson,bl-jt60050-01a + # Opto Logic SCX1001511GGC49 10.1" WXGA (1280x800) TFT LCD LVDS panel + - optologic,scx1001511ggc49 + # Riverdi RVT101HVLNWC00 10.1" WXGA (1280x800) TFT LCD LVDS panel + - riverdi,rvt101hvlnwc00 + # Riverdi RVT70HSLNWCA0 7.0" WSVGA (1024x600) TFT LCD LVDS panel + - riverdi,rvt70hslnwca0 # Samsung LTN070NL01 7.0" WSVGA (1024x600) TFT LCD LVDS panel - samsung,ltn070nl01 # Samsung LTN101AL03 10.1" WXGA (800x1280) TFT LCD LVDS panel diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index cc8d795df732..6d4133b91e7c 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -63,6 +63,8 @@ properties: - samsung,s6e3fa7-ams559nk06 # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel - tdo,tl070wsh30 + # Team Source Display Technology 7" TST070WSBE-196C 1024x600 TFT LCD panel + - team-source-display,tst070wsbe-196c reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 3e41ed0ef5d5..3d1cc11ba3aa 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -31,10 +31,14 @@ properties: # Ampire AM-1280800N3TZQW-T00H 10.1" WQVGA TFT LCD panel - ampire,am-1280800n3tzqw-t00h + # Ampire AM-1280800W8TZQW-T00H 10.1" WXGA TFT LCD panel + - ampire,am-1280800w8tzqw-t00h # Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel - ampire,am-480272h3tmqw-t01h # Ampire AM-800480L1TMQW-T00H 5" WVGA TFT LCD panel - ampire,am-800480l1tmqw-t00h + # Ampire AM-800480N3TZQW-00H 5" WVGA TFT LCD panel + - ampire,am-800480n3tzqw-00h # Ampire AM-800480R3TMQW-A1H 7.0" WVGA TFT LCD panel - ampire,am800480r3tmqwa1h # Ampire AM-800600P5TMQW-TB8H 8.0" SVGA TFT LCD panel @@ -97,6 +101,8 @@ properties: - dataimage,fg1001l0dsswmg01 # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. - dataimage,scf0700c48ggu18 + # Displaytech DT050BTFT-PTS 5.0" 800x480 TFT LCD Panel + - displaytech,dt050btft-pts # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel - dlc,dlc1010gig # Emerging Display Technology Corp. 3.5" QVGA TFT LCD panel @@ -232,6 +238,8 @@ properties: - nec,nl12880bc20-05 # NEC LCD Technologies,Ltd. WQVGA TFT LCD panel - nec,nl4827hc19-05b + # NEC LCD Technologies,Ltd. VGA TFT LCD panel + - nec,nl6448bc33-70c # Netron-DY E231732 7.0" WSVGA TFT LCD panel - netron-dy,e231732 # Newhaven Display International 480 x 272 TFT LCD panel @@ -304,6 +312,8 @@ properties: - shelly,sca07010-bfn-lnn # Starry KR070PE2T 7" WVGA TFT LCD panel - starry,kr070pe2t + # Startek KD070HDFLD092 7" WSVGA TFT LCD panel + - startek,kd070hdfld092 # Startek KD070WVFPA043-C069A 7" TFT LCD panel - startek,kd070wvfpa # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel @@ -341,10 +351,38 @@ properties: - vivax,tpc9150-panel # VXT 800x480 color TFT LCD panel - vxt,vl050-8048nt-c01 + # Waveshare 10.1" WXGA (1280x800) LCD panel + - waveshare,10.1inch-c-panel + # Waveshare 11.9" (320x1480) LCD panel + - waveshare,11.9inch-panel # Waveshare 13.3" FHD (1920x1080) LCD panel - waveshare,13.3inch-panel + # Waveshare 2.8" VGA (480x640) LCD panel + - waveshare,2.8inch-panel + # Waveshare 3.4" (800x800) LCD panel + - waveshare,3.4inch-c-panel + # Waveshare 4.0" WVGA (480x800) LCD panel + - waveshare,4.0inch-panel + # Waveshare 4.0" (720x720) LCD panel + - waveshare,4.0inch-c-panel + # Waveshare 5.0" WSVGA (1024x600) LCD panel + - waveshare,5.0inch-c-panel + # Waveshare 5.0" HD 720p (720x1280) LCD panel + - waveshare,5.0inch-d-panel + # Waveshare 6.25" (720x1560) LCD panel + - waveshare,6.25inch-panel # Waveshare 7.0" WSVGA (1024x600) LCD panel - waveshare,7.0inch-c-panel + # Waveshare 7.0" WXGA (1280x800) LCD panel + - waveshare,7.0inch-e-panel + # Waveshare 7.0" HD 720p (720x1280) LCD panel + - waveshare,7.0inch-h-panel + # Waveshare 7.9" (400x1280) LCD panel + - waveshare,7.9inch-panel + # Waveshare 8.0" WXGA (1280x800) LCD panel + - waveshare,8.0inch-c-panel + # Waveshare 8.8" (480x1920) LCD panel + - waveshare,8.8inch-panel # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel - winstar,wf35ltiacd # Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/renesas,r63419.yaml b/Documentation/devicetree/bindings/display/panel/renesas,r63419.yaml new file mode 100644 index 000000000000..adfdd2c300a3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/renesas,r63419.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/renesas,r63419.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R63419 based dual-DSI video mode Display Panel + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: + The Renesas R63419 is a generic DDIC used to control dual-DSI LCD panels. + +allOf: + - $ref: panel-common-dual.yaml# + +properties: + compatible: + items: + - enum: + - ayaneo,wt0600-2k + - ayaneo,wt0630-2k + - const: renesas,r63419 + + reg: + maxItems: 1 + + vdd-supply: true + vddio-supply: true + vsp-supply: true + vsn-supply: true + vci-supply: true + + backlight: true + reset-gpios: true + rotation: true + ports: true + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + - vsp-supply + - vsn-supply + - vci-supply + - backlight + - reset-gpios + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "ayaneo,wt0600-2k", "renesas,r63419"; + reg = <0>; + + reset-gpios = <&gpio 176 GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_3v0_lcd>; + vddio-supply = <&vdd_1v8_io>; + vsn-supply = <&vdd_5v0_neg>; + vsp-supply = <&vdd_5v0_pos>; + vci-supply = <&vdd_3v0_vci>; + + backlight = <&backlight>; + + rotation = <90>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + panel_in1: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml b/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml index ebfc825b8346..91e06d6a6819 100644 --- a/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml +++ b/Documentation/devicetree/bindings/display/panel/rocktech,jh057n00900.yaml @@ -22,6 +22,8 @@ properties: enum: # Anberic RG353V-V2 5.0" 640x480 TFT LCD panel - anbernic,rg353v-panel-v2 + # AYANEO Pocket DS lower 5.0" 1024x768 IPS LCD panel + - ayaneo,pocket-ds-lower-panel # GameForce Chi 3.5" 640x480 TFT LCD panel - gameforce,chi-panel # Powkiddy RGB10MAX3 5.0" 720x1280 TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml index 1bbe0da3997c..27536eeaed85 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml @@ -25,6 +25,8 @@ properties: - samsung,atna40ct06 # Samsung 14" WQXGA+ (2880x1800 pixels) eDP AMOLED panel - samsung,atna40cu11 + # Samsung 14" WQXGA+ (2880x1800 pixels) eDP AMOLED panel + - samsung,atna40hq08 # Samsung 14" WQXGA+ (2880×1800 pixels) eDP AMOLED panel - samsung,atna40yk20 # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel diff --git a/Documentation/devicetree/bindings/display/panel/samsung,sofef01-m.yaml b/Documentation/devicetree/bindings/display/panel/samsung,sofef01-m.yaml new file mode 100644 index 000000000000..bccc667aa072 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/samsung,sofef01-m.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,sofef01-m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SOFEF01-M DDI for 1080x2520@60Hz 6.0"/6.1" OLED DSI panels + +maintainers: + - Marijn Suijten <marijn.suijten@somainline.org> + +description: | + Samsung SOFEF01-M Display-Driver-IC found in multiple Sony smartphones, paired with + the following panel: + - Sony Xperia 5 (kumano bahamut): amb609tc01 + - Sony Xperia 10 II (seine pdx201): ams597ut01 + - Sony Xperia 10 III (lena pdx213): ams597ut04 + - Sony Xperia 10 IV (murray pdx225): ams597ut05 + - Sony Xperia 10 V (zambezi pdx235): ams605dk01 + - Sony Xperia 10 VI (columbia pdx246): ams605dk01 + + The assembly features a Samsung touchscreen compatible with + samsung,s6sy761. + +properties: + compatible: + enum: + - samsung,sofef01-m-amb609tc01 # 6.1" + - samsung,sofef01-m-ams597ut01 # 6.0" + - samsung,sofef01-m-ams597ut04 # 6.0" + - samsung,sofef01-m-ams597ut05 # 6.0" + - samsung,sofef01-m-ams605dk01 # 6.1" + + port: true + + reg: + maxItems: 1 + description: DSI virtual channel + + reset-gpios: true + + vci-supply: + description: DisplayIC Operation supply (3.0V) + + vddio-supply: + description: I/O voltage supply (1.8V) + +required: + - compatible + - port + - reg + - reset-gpios + - vddio-supply + +allOf: + - $ref: panel-common.yaml# + - if: + properties: + compatible: + contains: + const: samsung,sofef01-m-amb609tc01 + then: + required: + - vci-supply + else: + properties: + vci-supply: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "samsung,sofef01-m-amb609tc01"; + reg = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + vci-supply = <&vreg_l17a_3p0>; + vddio-supply = <&vreg_l14a_1p8>; + + port { + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 2cc66dcef870..5c9b15a09dee 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -20,7 +20,9 @@ properties: - enum: - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} + - renesas,r9a08g046-du # RZ/G3L - renesas,r9a09g057-du # RZ/V2H(P) + - renesas,r9a09g077-du # RZ/T2H - items: - enum: - renesas,r9a07g054-du # RZ/V2L @@ -28,6 +30,9 @@ properties: - items: - const: renesas,r9a09g056-du # RZ/V2N - const: renesas,r9a09g057-du # RZ/V2H(P) fallback + - items: + - const: renesas,r9a09g087-du # RZ/N2H + - const: renesas,r9a09g077-du # RZ/T2H fallback reg: maxItems: 1 @@ -61,7 +66,7 @@ properties: model-dependent. Each port shall have a single endpoint. patternProperties: - "^port@[0-1]$": + "^port@[0-2]$": $ref: /schemas/graph.yaml#/properties/port unevaluatedProperties: false @@ -83,7 +88,6 @@ required: - interrupts - clocks - clock-names - - resets - power-domains - ports - renesas,vsps @@ -95,13 +99,17 @@ allOf: properties: compatible: contains: - const: renesas,r9a07g043u-du + enum: + - renesas,r9a07g043u-du + - renesas,r9a09g077-du then: properties: ports: properties: port@0: description: DPI + port@1: false + port@2: false required: - port@0 @@ -118,10 +126,31 @@ allOf: description: DSI port@1: description: DPI + port@2: false + + required: + - port@0 + - port@1 + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-du + then: + properties: + ports: + properties: + port@0: + description: DSI + port@1: + description: DPI + port@2: + description: LVDS required: - port@0 - port@1 + - port@2 - if: properties: compatible: @@ -134,9 +163,21 @@ allOf: port@0: description: DSI port@1: false + port@2: false required: - port@0 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-du + then: + properties: + resets: false + else: + required: + - resets examples: # RZ/G2L DU diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml index d99b23b88cc5..6548f157fd96 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml @@ -15,18 +15,24 @@ properties: enum: - rockchip,rk3288-dp - rockchip,rk3399-edp + - rockchip,rk3576-edp - rockchip,rk3588-edp clocks: minItems: 2 - maxItems: 3 + items: + - description: Reference clock + - description: APB bus clock + - description: GRF or AHB bus clock clock-names: minItems: 2 items: - const: dp - const: pclk - - const: grf + - enum: + - grf + - hclk power-domains: maxItems: 1 @@ -65,9 +71,46 @@ allOf: compatible: contains: enum: + - rockchip,rk3288-dp + then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3399-edp + then: + properties: + clocks: + minItems: 3 + clock-names: + items: + - const: dp + - const: pclk + - const: grf + + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-edp - rockchip,rk3588-edp then: properties: + clocks: + minItems: 3 + clock-names: + items: + - const: dp + - const: pclk + - const: hclk resets: minItems: 2 reset-names: diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml index 1a33128e77f5..195f665970bf 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml @@ -41,7 +41,9 @@ properties: minItems: 1 items: - description: Extcon device providing the cable state for DP PHY device 0 + maxItems: 1 - description: Extcon device providing the cable state for DP PHY device 1 + maxItems: 1 description: List of phandle to the extcon device providing the cable state for the DP PHY. diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml index ff685031bb2c..729705f419bb 100644 --- a/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml +++ b/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml @@ -41,7 +41,7 @@ properties: additionalProperties: false description: | Timing configuration for lcd i80 interface support. - The parameters are defined as:: + The parameters are defined as: VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|?? : : : : : Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX @@ -132,7 +132,7 @@ patternProperties: "^port@[0-4]+$": $ref: /schemas/graph.yaml#/properties/port description: | - Contains ports with port with index:: + Contains ports with port with index: 0 - for CAMIF0 input, 1 - for CAMIF1 input, 2 - for CAMIF2 input, diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml index 7200095ef19e..bdf981781bd5 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml @@ -22,6 +22,7 @@ properties: - nvidia,tegra186-vic - nvidia,tegra194-vic - nvidia,tegra234-vic + - nvidia,tegra264-vic - items: - const: nvidia,tegra132-vic diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml index 3563378a01af..8312b7699cbe 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml @@ -25,6 +25,7 @@ properties: - nvidia,tegra186-host1x - nvidia,tegra194-host1x - nvidia,tegra234-host1x + - nvidia,tegra264-host1x - items: - const: nvidia,tegra132-host1x @@ -57,7 +58,8 @@ properties: enum: [1, 2] ranges: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: description: Must contain one entry, for the module clock. See @@ -192,6 +194,7 @@ allOf: contains: enum: - nvidia,tegra234-host1x + - nvidia,tegra264-host1x then: properties: reg-names: @@ -239,6 +242,21 @@ allOf: required: - reg-names + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra264-host1x + then: + properties: + ranges: + minItems: 2 + maxItems: 2 + else: + properties: + ranges: + maxItems: 1 examples: - | diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 49a007cbcd3a..d1e530e12604 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -261,9 +261,9 @@ examples: "ovr1", "ovr2", "vp1", "vp2", "common1"; ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 67 1>, - <&k3_clks 216 1>, - <&k3_clks 67 2>; + clocks = <&k3_clks 67 1>, + <&k3_clks 216 1>, + <&k3_clks 67 2>; clock-names = "fck", "vp1", "vp2"; interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; ports { @@ -299,9 +299,9 @@ examples: reg-names = "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2", "common1"; power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; - clocks = <&k3_clks 186 6>, - <&vp1_clock>, - <&k3_clks 186 2>; + clocks = <&k3_clks 186 6>, + <&vp1_clock>, + <&k3_clks 186 2>; clock-names = "fck", "vp1", "vp2"; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; oldi-transmitters { diff --git a/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml index 65ae8a1c3998..cac5ef1743d3 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml @@ -154,54 +154,54 @@ examples: #include <dt-bindings/soc/ti,sci_pm_domain.h> dss: dss@4a00000 { - compatible = "ti,j721e-dss"; - reg = <0x04a00000 0x10000>, /* common_m */ - <0x04a10000 0x10000>, /* common_s0*/ - <0x04b00000 0x10000>, /* common_s1*/ - <0x04b10000 0x10000>, /* common_s2*/ - <0x04a20000 0x10000>, /* vidl1 */ - <0x04a30000 0x10000>, /* vidl2 */ - <0x04a50000 0x10000>, /* vid1 */ - <0x04a60000 0x10000>, /* vid2 */ - <0x04a70000 0x10000>, /* ovr1 */ - <0x04a90000 0x10000>, /* ovr2 */ - <0x04ab0000 0x10000>, /* ovr3 */ - <0x04ad0000 0x10000>, /* ovr4 */ - <0x04a80000 0x10000>, /* vp1 */ - <0x04aa0000 0x10000>, /* vp2 */ - <0x04ac0000 0x10000>, /* vp3 */ - <0x04ae0000 0x10000>, /* vp4 */ - <0x04af0000 0x10000>; /* wb */ - reg-names = "common_m", "common_s0", - "common_s1", "common_s2", - "vidl1", "vidl2","vid1","vid2", - "ovr1", "ovr2", "ovr3", "ovr4", - "vp1", "vp2", "vp3", "vp4", - "wb"; - clocks = <&k3_clks 152 0>, - <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; - clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; - power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; - interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "common_m", - "common_s0", - "common_s1", - "common_s2"; - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - - dpi_out_0: endpoint { - remote-endpoint = <&dp_bridge_input>; - }; - }; + compatible = "ti,j721e-dss"; + reg = <0x04a00000 0x10000>, /* common_m */ + <0x04a10000 0x10000>, /* common_s0*/ + <0x04b00000 0x10000>, /* common_s1*/ + <0x04b10000 0x10000>, /* common_s2*/ + <0x04a20000 0x10000>, /* vidl1 */ + <0x04a30000 0x10000>, /* vidl2 */ + <0x04a50000 0x10000>, /* vid1 */ + <0x04a60000 0x10000>, /* vid2 */ + <0x04a70000 0x10000>, /* ovr1 */ + <0x04a90000 0x10000>, /* ovr2 */ + <0x04ab0000 0x10000>, /* ovr3 */ + <0x04ad0000 0x10000>, /* ovr4 */ + <0x04a80000 0x10000>, /* vp1 */ + <0x04aa0000 0x10000>, /* vp2 */ + <0x04ac0000 0x10000>, /* vp3 */ + <0x04ae0000 0x10000>, /* vp4 */ + <0x04af0000 0x10000>; /* wb */ + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + clocks = <&k3_clks 152 0>, + <&k3_clks 152 1>, + <&k3_clks 152 4>, + <&k3_clks 152 9>, + <&k3_clks 152 13>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + dpi_out_0: endpoint { + remote-endpoint = <&dp_bridge_input>; + }; }; + }; }; diff --git a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml index 96b1439f88e3..87721da0a8af 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml @@ -80,26 +80,26 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> - dss: dss@2540000 { - compatible = "ti,k2g-dss"; - reg = <0x02540000 0x400>, - <0x02550000 0x1000>, - <0x02557000 0x1000>, - <0x0255a800 0x100>, - <0x0255ac00 0x100>; - reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; - clocks = <&k2g_clks 0x2 0>, - <&k2g_clks 0x2 1>; - clock-names = "fck", "vp1"; - interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>; - - power-domains = <&k2g_pds 0x2>; - - max-memory-bandwidth = <230000000>; - - port { - dpi_out: endpoint { - remote-endpoint = <&sii9022_in>; - }; + dss@2540000 { + compatible = "ti,k2g-dss"; + reg = <0x02540000 0x400>, + <0x02550000 0x1000>, + <0x02557000 0x1000>, + <0x0255a800 0x100>, + <0x0255ac00 0x100>; + reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; + clocks = <&k2g_clks 0x2 0>, + <&k2g_clks 0x2 1>; + clock-names = "fck", "vp1"; + interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>; + + power-domains = <&k2g_pds 0x2>; + + max-memory-bandwidth = <230000000>; + + port { + dpi_out: endpoint { + remote-endpoint = <&sii9022_in>; }; + }; }; diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml index 9dc35ab973f2..919a90012201 100644 --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -75,6 +75,8 @@ required: - interrupts - clocks - clock-names + - resets + - reset-names - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml index 391bf5838602..bea302b89453 100644 --- a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml +++ b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera mSGDMA IP core maintainers: - - Olivier Dautricourt <olivierdautricourt@gmail.com> + - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> description: | Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index fa4248e2f1b9..f609038e35ae 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -12,6 +12,9 @@ description: | DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. + This binding has an inverted dma-channel-mask definition compared to + the common DMA binding for historical reasons. + maintainers: - Peng Fan <peng.fan@nxp.com> @@ -95,6 +98,12 @@ properties: eDMA are implemented in big endian mode, otherwise in little mode. type: boolean + dma-channel-mask: + description: | + Bitmask of available DMA channels (inverted definition). + Bit semantics: 0 means channel available, 1 means channel unavailable + default: 0 + required: - "#dma-cells" - compatible diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index 3708518fe7fc..bba20e88a6dc 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -40,6 +40,7 @@ properties: - items: - enum: - mediatek,mt6991-uart-dma + - mediatek,mt8189-uart-dma - mediatek,mt8196-uart-dma - const: mediatek,mt6985-uart-dma - enum: diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 0dabe9bbb219..bc093c783d98 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -14,17 +14,16 @@ description: | maintainers: - Jon Hunter <jonathanh@nvidia.com> - Rajesh Gumasta <rgumasta@nvidia.com> - -allOf: - - $ref: dma-controller.yaml# + - Akhil R <akhilrajeev@nvidia.com> properties: compatible: oneOf: - - const: nvidia,tegra186-gpcdma + - enum: + - nvidia,tegra264-gpcdma + - nvidia,tegra186-gpcdma - items: - enum: - - nvidia,tegra264-gpcdma - nvidia,tegra234-gpcdma - nvidia,tegra194-gpcdma - const: nvidia,tegra186-gpcdma @@ -51,6 +50,14 @@ properties: iommus: maxItems: 1 + iommu-map: + description: + Maps DMA channel numbers to IOMMU stream IDs. A single entry can map all + channels when stream IDs are contiguous. In systems where the channels or + stream IDs are not contiguous, multiple entries may be needed. + minItems: 1 + maxItems: 32 + dma-coherent: true dma-channel-mask: @@ -60,12 +67,23 @@ required: - compatible - reg - interrupts - - resets - - reset-names - "#dma-cells" - iommus - dma-channel-mask +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-gpcdma + then: + required: + - resets + - reset-names + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 6493a6968bb4..e72adc172af1 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -23,6 +23,8 @@ properties: - qcom,bam-v1.4.0 # MSM8916, SDM630 - qcom,bam-v1.7.0 + # Kaanapali + - qcom,bam-v2.0.0 - items: - enum: # SDM845, SM6115, SM8150, SM8250 and QCM2290 @@ -46,7 +48,7 @@ properties: iommus: minItems: 1 - maxItems: 6 + maxItems: 7 num-channels: $ref: /schemas/types.yaml#/definitions/uint32 @@ -118,4 +120,23 @@ examples: #dma-cells = <1>; qcom,ee = <0>; }; + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dma-controller@1dc4000 { + compatible = "qcom,bam-v2.0.0"; + reg = <0x0 0x01dc4000 0x0 0x22000>; + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + iommus = <&apps_smmu 0xc0 0>, <&apps_smmu 0xc1 0>; + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + }; ... diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index fde1df035ad1..54dca623223d 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -24,7 +24,9 @@ properties: - qcom,sm6350-gpi-dma - items: - enum: + - qcom,eliza-gpi-dma - qcom,glymur-gpi-dma + - qcom,hawi-gpi-dma - qcom,kaanapali-gpi-dma - qcom,milos-gpi-dma - qcom,qcm2290-gpi-dma @@ -35,6 +37,7 @@ properties: - qcom,sc7280-gpi-dma - qcom,sc8280xp-gpi-dma - qcom,sdx75-gpi-dma + - qcom,shikra-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 804514732dbe..0a30a455b0ee 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -21,11 +21,12 @@ properties: - enum: - snps,axi-dma-1.01a - intel,kmb-axi-dma - - sophgo,cv1800b-axi-dma - starfive,jh7110-axi-dma - starfive,jh8100-axi-dma - items: - - const: altr,agilex5-axi-dma + - enum: + - altr,agilex5-axi-dma + - sophgo,cv1800b-axi-dma - const: snps,axi-dma-1.01a reg: diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml index ec06235baf5c..62ce6d81526b 100644 --- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: spacemit,k1-pdma + enum: + - spacemit,k1-pdma + - spacemit,k3-pdma reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml index 607da11e7baa..d8f92838f4c9 100644 --- a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml +++ b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml @@ -136,13 +136,9 @@ properties: maxItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: A phandle array with inner size 1 (no arg cells). - First phandle is the LCPA (Logical Channel Parameter Address) memory. - Second phandle is the LCLA (Logical Channel Link base Address) memory. - maxItems: 2 items: - maxItems: 1 + - description: LCPA (Logical Channel Parameter Address) memory. + - description: LCLA (Logical Channel Link base Address) memory. memcpy-channels: $ref: /schemas/types.yaml#/definitions/uint32-array diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml index 340ae9e91cb0..2c88e927d9d3 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml @@ -81,8 +81,13 @@ properties: description: Should be the number of framebuffers as configured in h/w. xlnx,flush-fsync: - type: boolean - description: Tells which channel to Flush on Frame sync. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Tells which channel to flush on frame sync. + 1 - flush both channels + 2 - flush mm2s channel + 3 - flush s2mm channel xlnx,sg-length-width: $ref: /schemas/types.yaml#/definitions/uint32 @@ -93,7 +98,7 @@ properties: Width in bits of the length register as configured in hardware. xlnx,irq-delay: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint8 minimum: 0 maximum: 255 description: @@ -251,7 +256,7 @@ examples: "m_axi_s2mm_aclk", "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; xlnx,num-fstores = <8>; - xlnx,flush-fsync; + xlnx,flush-fsync = <1>; xlnx,addrwidth = <32>; dma-channel-mm2s { diff --git a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml index fa5a8f8e390c..17983e6c3597 100644 --- a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml +++ b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml @@ -14,15 +14,22 @@ description: provides up to 5 independent DPLL channels, up to 10 differential or single-ended inputs and 10 differential or 20 single-ended outputs. These devices support both I2C and SPI interfaces. + The ZL3064x line card timing ICs share the ZL3073x register map + and are described with a fallback to the register equivalent ZL3073x + part. properties: compatible: - enum: - - microchip,zl30731 - - microchip,zl30732 - - microchip,zl30733 - - microchip,zl30734 - - microchip,zl30735 + oneOf: + - enum: + - microchip,zl30731 + - microchip,zl30732 + - microchip,zl30733 + - microchip,zl30734 + - microchip,zl30735 + - items: + - const: microchip,zl30643 + - const: microchip,zl30733 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml b/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml index abc52978be7a..994afb1c31ff 100644 --- a/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml @@ -81,7 +81,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> dsp@10803000 { - compatible = "mediatek,mt8195-dsp"; + compatible = "mediatek,mt8195-dsp"; reg = <0x10803000 0x1000>, <0x10840000 0x40000>; reg-names = "cfg", "sram"; diff --git a/Documentation/devicetree/bindings/dts-coding-style.rst b/Documentation/devicetree/bindings/dts-coding-style.rst index 4a02ea60cbbe..63648db377e1 100644 --- a/Documentation/devicetree/bindings/dts-coding-style.rst +++ b/Documentation/devicetree/bindings/dts-coding-style.rst @@ -114,15 +114,16 @@ Order of Properties in Device Node The following order of properties in device nodes is preferred: -1. "compatible" -2. "reg" -3. "ranges" -4. Standard/common properties (defined by common bindings, e.g. without +1. "device_type" (if applicable) +2. "compatible" +3. "reg" +4. "ranges" +5. Standard/common properties (defined by common bindings, e.g. without vendor-prefixes) -5. Vendor-specific properties -6. "status" (if applicable), preceded by a blank line if there is content +6. Vendor-specific properties +7. "status" (if applicable), preceded by a blank line if there is content before the property -7. Child nodes, where each node is preceded with a blank line +8. Child nodes, where each node is preceded with a blank line The "status" property is by default "okay", thus it can be omitted. diff --git a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml index cc930660b794..09bbd2e33786 100644 --- a/Documentation/devicetree/bindings/dvfs/performance-domain.yaml +++ b/Documentation/devicetree/bindings/dvfs/performance-domain.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic performance domains maintainers: - - Sudeep Holla <sudeep.holla@arm.com> + - Sudeep Holla <sudeep.holla@kernel.org> description: |+ This binding is intended for performance management of groups of devices or diff --git a/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-rt-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-rt-ec.yaml new file mode 100644 index 000000000000..0fee574a3015 --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-rt-ec.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/microsoft,surface-rt-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsoft Surface RT fuel gauge and charger EC + +maintainers: + - Jonas Schwöbel <jonasschwoebel@yahoo.de> + - Svyatoslav Ryhel <clamor95@gmail.com> + +description: + An Embedded Controller used in Microsoft Surface RT for monitoring + battery properties and charger status. + +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + +properties: + compatible: + const: microsoft,surface-rt-ec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + enable-gpios: + maxItems: 1 + + monitored-battery: true + +required: + - compatible + - reg + - interrupts + - enable-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@a { + compatible = "microsoft,surface-rt-ec"; + reg = <0x0a>; + + interrupt-parent = <&gpio>; + interrupts = <74 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&gpio 88 GPIO_ACTIVE_HIGH>; + monitored-battery = <&battery>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml new file mode 100644 index 000000000000..ac5a08f8f76d --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/qcom,hamoa-crd-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hamoa Embedded Controller + +maintainers: + - Sibi Sankar <sibi.sankar@oss.qualcomm.com> + - Anvesh Jain P <anvesh.p@oss.qualcomm.com> + +description: + Qualcomm Snapdragon based Hamoa/Purwa and Glymur reference devices have an + EC running on different MCU chips. The EC handles things like fan control, + temperature sensors, access to EC internal state changes. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,glymur-crd-ec + - qcom,hamoa-iot-evk-ec + - const: qcom,hamoa-crd-ec + - enum: + - qcom,hamoa-crd-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@76 { + compatible = "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml b/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml new file mode 100644 index 000000000000..0a320d5e2a35 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/samsung,s2mu005-muic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MUIC Device for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty <kauschluss@disroot.org> + +description: | + The Samsung S2M series PMIC MUIC device is a USB port accessory + detector. It reports multiple states depending on the ID-GND + resistance measured by an internal ADC. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mu005-muic + + connector: + $ref: /schemas/connector/usb-connector.yaml# + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Port connecting to the USB controller or PHY. + +required: + - compatible + - connector + - port + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index d06cca9273c4..6fc44105f1c3 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: System Control and Management Interface (SCMI) Message Protocol maintainers: - - Sudeep Holla <sudeep.holla@arm.com> + - Sudeep Holla <sudeep.holla@kernel.org> description: | The SCMI is intended to allow agents such as OSPM to manage various functions diff --git a/Documentation/devicetree/bindings/firmware/arm,scpi.yaml b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml index 241317239ffc..08c7e05c577c 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scpi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: System Control and Power Interface (SCPI) Message Protocol maintainers: - - Sudeep Holla <sudeep.holla@arm.com> + - Sudeep Holla <sudeep.holla@kernel.org> description: | Firmware implementing the SCPI described in ARM document number ARM DUI diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 7918d31f58b4..037d4ad8f718 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -25,6 +25,7 @@ properties: - qcom,scm-apq8084 - qcom,scm-eliza - qcom,scm-glymur + - qcom,scm-hawi - qcom,scm-ipq4019 - qcom,scm-ipq5018 - qcom,scm-ipq5210 @@ -36,6 +37,7 @@ properties: - qcom,scm-ipq9574 - qcom,scm-ipq9650 - qcom,scm-kaanapali + - qcom,scm-maili - qcom,scm-mdm9607 - qcom,scm-milos - qcom,scm-msm8226 @@ -49,6 +51,7 @@ properties: - qcom,scm-msm8994 - qcom,scm-msm8996 - qcom,scm-msm8998 + - qcom,scm-nord - qcom,scm-qcm2290 - qcom,scm-qcs615 - qcom,scm-qcs8300 @@ -65,6 +68,7 @@ properties: - qcom,scm-sdx55 - qcom,scm-sdx65 - qcom,scm-sdx75 + - qcom,scm-shikra - qcom,scm-sm6115 - qcom,scm-sm6125 - qcom,scm-sm6350 @@ -127,6 +131,13 @@ properties: - description: offset of the download mode control register description: TCSR hardware block + sram: + description: + Phandle to a region in always-on SRAM used to store the download + mode value for boot firmware to read before DDR is initialised on + the next warm reset. + maxItems: 1 + allOf: # Clocks - if: @@ -146,6 +157,7 @@ allOf: - qcom,scm-msm8974 - qcom,scm-msm8976 - qcom,scm-qcm2290 + - qcom,scm-shikra - qcom,scm-sm6375 then: required: @@ -165,6 +177,7 @@ allOf: - qcom,scm-msm8660 - qcom,scm-msm8960 - qcom,scm-qcm2290 + - qcom,scm-shikra - qcom,scm-sm6375 then: properties: @@ -208,7 +221,9 @@ allOf: contains: enum: - qcom,scm-eliza + - qcom,scm-hawi - qcom,scm-kaanapali + - qcom,scm-maili - qcom,scm-milos - qcom,scm-sm8450 - qcom,scm-sm8550 diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml index d50438b0fca8..72af37cdb103 100644 --- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml +++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml @@ -48,8 +48,7 @@ properties: const: 1 clock-controller: - $ref: /schemas/clock/xlnx,versal-clk.yaml# - description: The clock controller is a hardware block of Xilinx versal + description: The clock controller is a hardware block of Xilinx SoC clock tree. It reads required input clock frequencies from the devicetree and acts as clock provider for all clock consumers of PS clocks.list of clock specifiers which are external input clocks to the given clock @@ -113,10 +112,14 @@ allOf: const: xlnx,zynqmp-firmware then: properties: + clock-controller: + $ref: /schemas/clock/xlnx,zynqmp-clk.yaml# pinctrl: $ref: /schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# else: properties: + clock-controller: + $ref: /schemas/clock/xlnx,versal-clk.yaml# pinctrl: $ref: /schemas/pinctrl/xlnx,versal-pinctrl.yaml# @@ -132,6 +135,14 @@ examples: zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; + clock-controller { + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + #clock-cells = <1>; + }; soc-nvmem { compatible = "xlnx,zynqmp-nvmem-fw"; nvmem-layout { diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt deleted file mode 100644 index 52a294cf2730..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt +++ /dev/null @@ -1,12 +0,0 @@ -Altera Arria10 Partial Reconfiguration IP - -Required properties: -- compatible : should contain "altr,a10-pr-ip" -- reg : base address and size for memory mapped io. - -Example: - - fpga_mgr: fpga-mgr@ff20c000 { - compatible = "altr,a10-pr-ip"; - reg = <0xff20c000 0x10>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt deleted file mode 100644 index d52f3340414d..000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt +++ /dev/null @@ -1,17 +0,0 @@ -Altera SOCFPGA FPGA Manager - -Required properties: -- compatible : should contain "altr,socfpga-fpga-mgr" -- reg : base address and size for memory mapped io. - - The first index is for FPGA manager register access. - - The second index is for writing FPGA configuration data. -- interrupts : interrupt for the FPGA Manager device. - -Example: - - hps_0_fpgamgr: fpgamgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xFF706000 0x1000 - 0xFFB90000 0x1000>; - interrupts = <0 175 4>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml b/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml new file mode 100644 index 000000000000..1f4df40308bd --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/altr,a10-pr-ip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Arria10 Partial Reconfiguration IP + +maintainers: + - Matthew Gerlach <matthew.gerlach@linux.intel.com> + +description: + The Altera Arria 10 Partial Reconfiguration IP core allows the host + processor to perform partial reconfiguration of the FPGA fabric. + +properties: + compatible: + const: altr,a10-pr-ip + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fpga-mgr@ff20c000 { + compatible = "altr,a10-pr-ip"; + reg = <0xff20c000 0x10>; + }; diff --git a/Documentation/devicetree/bindings/fpga/altr,socfpga-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/altr,socfpga-fpga-mgr.yaml new file mode 100644 index 000000000000..9bcc1200d61d --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altr,socfpga-fpga-mgr.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA FPGA Manager + +maintainers: + - Steffen Trumtrar <s.trumtrar@pengutronix.de> + +properties: + compatible: + const: altr,socfpga-fpga-mgr + + reg: + items: + - description: FPGA manager register access + - description: Writing FPGA configuration data + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + fpgamgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000>, + <0xffb90000 0x1000>; + interrupts = <0 175 4>; + }; diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml new file mode 100644 index 000000000000..7c7444ff9c3a --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,trion-config.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel <iansdannapel@gmail.com> + +description: | + Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitstreams + through "SPI Passive Mode". + Additional pin hogs for bus width configuration should be set + elsewhere, if necessary. + + References: + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.pdf + - https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - efinix,titanium-config + - efinix,topaz-config + - const: efinix,trion-config + - const: efinix,trion-config + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + reset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + - spi-cpha + - spi-cpol + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible = "efinix,trion-config"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible = "efinix,titanium-config", "efinix,trion-config"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml b/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml new file mode 100644 index 000000000000..c93e3a1a135b --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/technologic,ts7300-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems TS-7300 FPGA Manager + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +description: + FPGA manager for the Altera Cyclone II FPGA on Technologic Systems + TS-7300 board. The FPGA is programmed via the memory-mapped interface + implemented in the CPLD. + +properties: + compatible: + const: technologic,ts7300-fpga + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fpga-mgr@13c00000 { + compatible = "technologic,ts7300-fpga"; + reg = <0x13c00000 0x2>; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml index a84d60b39459..7eacf5af6554 100644 --- a/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/cdns,gpio.yaml @@ -14,8 +14,11 @@ properties: oneOf: - const: cdns,gpio-r1p02 - items: - - enum: - - axiado,ax3000-gpio + - const: axiado,ax3000-gpio + - const: cdns,gpio-r1p02 + - items: + - const: axiado,ax3005-gpio + - const: axiado,ax3000-gpio - const: cdns,gpio-r1p02 reg: diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index 23410aeca300..451538df63f7 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -45,6 +45,18 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: Number of daisy-chained shift registers + lines-initial-states: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bitmask that specifies the initial state of each output line, written + by the driver before the gpiochip is registered. Bit N corresponds to + GPIO line N, following the convention already documented for + nxp,pcf8575. Because the 74HC595/74LVC594 family is push-pull output + only, a bit set to zero drives the line low and a bit set to one + drives it high. The bitmask covers up to 32 lines (four cascaded + registers); outputs beyond that come up zeroed. When the property is + absent all outputs come up low, preserving the previous behaviour. + enable-gpios: description: GPIO connected to the OE (Output Enable) pin. maxItems: 1 @@ -79,6 +91,7 @@ examples: gpio-controller; #gpio-cells = <2>; registers-number = <4>; + lines-initial-states = <0xffff0000>; spi-max-frequency = <100000>; }; }; diff --git a/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml new file mode 100644 index 000000000000..1d2ab44fcd3c --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/fsl,mpc8323-qe-pario-bank.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale QUICC Engine Parallel I/O (QE PARIO) GPIO Bank + +maintainers: + - Christophe Leroy <christophe.leroy@csgroup.eu> + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,mpc8360-qe-pario-bank + - fsl,mpc8569-qe-pario-bank + - const: fsl,mpc8323-qe-pario-bank + - const: fsl,mpc8323-qe-pario-bank + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 2 + + interrupt-map: + description: | + Specifies the mapping of GPIO lines to the parent interrupt controller, as the + GPIO controller does not do interrupt handling itself. + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + gpio-controller@1400 { + compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank"; + reg = <0x1400 0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio-controller@1418 { + compatible = "fsl,mpc8323-qe-pario-bank"; + reg = <0x1418 0x18>; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <0>; + #interrupt-cells = <2>; + interrupt-map = < + 7 IRQ_TYPE_EDGE_FALLING &pic 4 IRQ_TYPE_EDGE_FALLING + 7 IRQ_TYPE_EDGE_BOTH &pic 4 IRQ_TYPE_EDGE_BOTH + 7 0 &pic 4 IRQ_TYPE_NONE + + 9 IRQ_TYPE_EDGE_FALLING &pic 5 IRQ_TYPE_EDGE_FALLING + 9 IRQ_TYPE_EDGE_BOTH &pic 5 IRQ_TYPE_EDGE_BOTH + 9 0 &pic 5 IRQ_TYPE_NONE + + 25 IRQ_TYPE_EDGE_FALLING &pic 6 IRQ_TYPE_EDGE_FALLING + 25 IRQ_TYPE_EDGE_BOTH &pic 6 IRQ_TYPE_EDGE_BOTH + 25 0 &pic 6 IRQ_TYPE_NONE + + 27 IRQ_TYPE_EDGE_FALLING &pic 7 IRQ_TYPE_EDGE_FALLING + 27 IRQ_TYPE_EDGE_BOTH &pic 7 IRQ_TYPE_EDGE_BOTH + 27 0 &pic 7 IRQ_TYPE_NONE + >; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml index 4f955f855e1a..4631388a7d91 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml @@ -23,6 +23,9 @@ properties: - const: diodes,pi4ioe5v6534q - const: nxp,pcal6534 - items: + - const: kinetic,kts1622 + - const: ti,tcal6416 + - items: - enum: - exar,xra1202 - maxim,max7310 diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml index 5e2496379a3c..de24bb361e9f 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -12,10 +12,11 @@ maintainers: properties: compatible: enum: + - xlnx,eio-gpio-1.0 + - xlnx,pmc-gpio-1.0 + - xlnx,versal-gpio-1.0 - xlnx,zynq-gpio-1.0 - xlnx,zynqmp-gpio-1.0 - - xlnx,versal-gpio-1.0 - - xlnx,pmc-gpio-1.0 reg: maxItems: 1 @@ -30,7 +31,7 @@ properties: gpio-line-names: description: strings describing the names of each gpio line - minItems: 58 + minItems: 52 maxItems: 174 interrupt-controller: true @@ -89,6 +90,16 @@ allOf: minItems: 116 maxItems: 116 + - if: + properties: + compatible: + enum: + - xlnx,eio-gpio-1.0 + then: + properties: + gpio-line-names: + maxItems: 52 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 17748dd1015d..adeb3b3a2902 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -85,6 +85,8 @@ properties: - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio - nvidia,tegra234-gpio-aon + - nvidia,tegra238-gpio + - nvidia,tegra238-gpio-aon - nvidia,tegra256-gpio - nvidia,tegra264-gpio - nvidia,tegra264-gpio-uphy @@ -163,6 +165,7 @@ allOf: - nvidia,tegra186-gpio - nvidia,tegra194-gpio - nvidia,tegra234-gpio + - nvidia,tegra238-gpio - nvidia,tegra256-gpio - nvidia,tegra264-gpio - nvidia,tegra264-gpio-uphy @@ -180,6 +183,7 @@ allOf: - nvidia,tegra186-gpio-aon - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio-aon + - nvidia,tegra238-gpio-aon - nvidia,tegra264-gpio-aon then: properties: @@ -192,6 +196,8 @@ allOf: compatible: contains: enum: + - nvidia,tegra238-gpio + - nvidia,tegra238-gpio-aon - nvidia,tegra264-gpio - nvidia,tegra264-gpio-uphy - nvidia,tegra264-gpio-aon diff --git a/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml new file mode 100644 index 000000000000..f13c910b73c6 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/realtek,rtd1625-gpio.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/realtek,rtd1625-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1625 GPIO controller + +maintainers: + - Tzuyi Chang <tychang@realtek.com> + +description: | + GPIO controller for the Realtek RTD1625 SoC, featuring a per-pin register + architecture that differs significantly from earlier RTD series controllers. + Each GPIO has dedicated registers for configuration (direction, input/output + values, debounce), and interrupt control supporting edge and level detection + modes. + +properties: + compatible: + enum: + - realtek,rtd1625-iso-gpio + - realtek,rtd1625-isom-gpio + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt number of the assert GPIO interrupt, which is + triggered when there is a rising edge. + - description: Interrupt number of the deassert GPIO interrupt, which is + triggered when there is a falling edge. + - description: Interrupt number of the level-sensitive GPIO interrupt, + triggered by a configured logic level. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + gpio-ranges: true + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + - gpio-ranges + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + gpio@89100 { + compatible = "realtek,rtd1625-isom-gpio"; + reg = <0x89100 0x30>; + interrupt-parent = <&iso_m_irq_mux>; + interrupts = <0>, <1>, <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&isom_pinctrl 0 0 4>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml index bdd83f42615c..774e9c7de606 100644 --- a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml +++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml @@ -44,6 +44,13 @@ properties: power-domains: maxItems: 1 + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node managing the IO control registers + of this bank, on SoCs such as the RV1106 where each GPIO bank has + its own IOC block. + patternProperties: "^.+-hog(-[0-9]+)?$": type: object diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml index bba6f5b6606f..55069533f6d9 100644 --- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml @@ -95,6 +95,12 @@ patternProperties: '#interrupt-cells': const: 2 + patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/gpio/st,nomadik-gpio.yaml b/Documentation/devicetree/bindings/gpio/st,nomadik-gpio.yaml index 40b4a7551449..e871149c520f 100644 --- a/Documentation/devicetree/bindings/gpio/st,nomadik-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/st,nomadik-gpio.yaml @@ -85,7 +85,7 @@ examples: - | gpio@8012e080 { compatible = "st,nomadik-gpio"; - reg = <0x8012e080 0x80>; + reg = <0x8012e080 0x80>; interrupts = <0 120 0x4>; #gpio-cells = <2>; gpio-controller; diff --git a/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml new file mode 100644 index 000000000000..091e1fffcd47 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/waveshare,dsi-touch-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Waveshare GPIO controller on DSI TOUCH panels + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> + +description: + Waveshare DSI TOUCH panel kits contain separate GPIO controller for toggling + power supplies and panel / touchscreen resets. + +properties: + compatible: + const: waveshare,dsi-touch-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + wsgpio: gpio@45 { + compatible = "waveshare,dsi-touch-gpio"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + panel_avdd: regulator-panel-avdd { + compatible = "regulator-fixed"; + regulator-name = "panel-avdd"; + gpios = <&wsgpio 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel_iovcc: regulator-panel-iovcc { + compatible = "regulator-fixed"; + regulator-name = "panel-iovcc"; + gpios = <&wsgpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel_vcc: regulator-panel-vcc { + compatible = "regulator-fixed"; + regulator-name = "panel-vcc"; + gpios = <&wsgpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +... diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index db49b8ff8c74..9db9f84ad964 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -26,6 +26,7 @@ properties: - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a08g046-mali - renesas,r9a09g047-mali - renesas,r9a09g056-mali - renesas,r9a09g057-mali @@ -150,6 +151,7 @@ allOf: enum: - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a08g046-mali - renesas,r9a09g047-mali - renesas,r9a09g056-mali - renesas,r9a09g057-mali diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml index ba4c6473ff92..84a84275432a 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding <treding@gmail.com> + - Thierry Reding <thierry.reding@kernel.org> - Mikko Perttunen <mperttunen@nvidia.com> properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml index c23dae713eb8..8916a868dafb 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding <treding@gmail.com> + - Thierry Reding <thierry.reding@kernel.org> - Mikko Perttunen <mperttunen@nvidia.com> properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml index 99a33a5eac3f..582eb44eb157 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml @@ -12,7 +12,7 @@ description: | through Host1x channels. maintainers: - - Thierry Reding <treding@gmail.com> + - Thierry Reding <thierry.reding@kernel.org> - Mikko Perttunen <mperttunen@nvidia.com> properties: diff --git a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml index 0b7561c8b9bb..4eb325cfd296 100644 --- a/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml +++ b/Documentation/devicetree/bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml @@ -12,7 +12,7 @@ description: | programmed through Host1x channels. maintainers: - - Thierry Reding <treding@gmail.com> + - Thierry Reding <thierry.reding@kernel.org> - Mikko Perttunen <mperttunen@nvidia.com> properties: diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index a1f54dbae3f3..e9218e0f363d 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -8,13 +8,15 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Imagination Technologies PowerVR and IMG Rogue GPUs maintainers: - - Frank Binns <frank.binns@imgtec.com> + - Alessio Belle <alessio.belle@imgtec.com> + - Luigi Santivetti <luigi.santivetti@imgtec.com> properties: compatible: oneOf: - items: - enum: + - mediatek,mt8173-gpu - renesas,r8a7796-gpu - renesas,r8a77961-gpu - const: img,img-gx6250 diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml index f5898b04381c..58b799b8e96e 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml @@ -9,7 +9,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Imagination Technologies PowerVR SGX GPUs maintainers: - - Frank Binns <frank.binns@imgtec.com> + - Alessio Belle <alessio.belle@imgtec.com> + - Luigi Santivetti <luigi.santivetti@imgtec.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml index dada28b47ea0..2900224aac74 100644 --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml @@ -15,6 +15,9 @@ description: | represented by CTRLMMR_xxx_JTAGID register which contains information about SoC id and revision. + On some SoCs like AM62P, the silicon revision is determined by reading + alternative registers via NVMEM cells. + properties: $nodename: pattern: "^chipid@[0-9a-f]+$" @@ -26,6 +29,14 @@ properties: reg: maxItems: 1 + nvmem-cells: + items: + - description: Alternate silicon revision register + + nvmem-cell-names: + items: + - const: gpsw1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml index d6a7517f2a50..283cd1662689 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml @@ -25,19 +25,38 @@ description: | https://www.silergy.com/ download/downloadFile?id=5669&type=product&ftype=note + The BD12780 and BD12780A are hot-swap controllers from ROHM. They are + functionally compatible with the ADM1278. The main difference between + the BD12780A and the BD12780 is amount of configurable I2C addresses. + + Datasheets: + https://fscdn.rohm.com/en/products/databook/datasheet/ic/power/power_switch/bd12780muv-lb-e.pdf + https://fscdn.rohm.com/en/products/databook/datasheet/ic/power/power_switch/bd12780amuv-lb-e.pdf + + The BD12790 is a ROHM hot-swap controller, functionally similar to the + ADM1272. + properties: compatible: - enum: - - adi,adm1075 - - adi,adm1272 - - adi,adm1273 - - adi,adm1275 - - adi,adm1276 - - adi,adm1278 - - adi,adm1281 - - adi,adm1293 - - adi,adm1294 - - silergy,mc09c + oneOf: + - enum: + - adi,adm1075 + - adi,adm1272 + - adi,adm1273 + - adi,adm1275 + - adi,adm1276 + - adi,adm1278 + - adi,adm1281 + - adi,adm1293 + - adi,adm1294 + - rohm,bd12780 + - rohm,bd12790 + - silergy,mc09c + + # Require BD12780 as a fall-back for BD12780A. + - items: + - const: rohm,bd12780a + - const: rohm,bd12780 reg: maxItems: 1 @@ -88,6 +107,7 @@ allOf: enum: - adi,adm1272 - adi,adm1273 + - rohm,bd12790 then: properties: adi,volt-curr-sample-average: @@ -104,6 +124,7 @@ allOf: - adi,adm1281 - adi,adm1293 - adi,adm1294 + - rohm,bd12780 - silergy,mc09c then: properties: diff --git a/Documentation/devicetree/bindings/hwmon/adi,adt7470.yaml b/Documentation/devicetree/bindings/hwmon/adi,adt7470.yaml new file mode 100644 index 000000000000..a701542898ee --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/adi,adt7470.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,adt7470.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADT7470 hwmon sensor + +maintainers: + - Luiz Angelo Daros de Luca <luizluca@gmail.com> + +description: + Multi-channel temperature monitor and PWM fan controller. + It supports monitoring up to 10 external temperature sensors and + controlling up to 4 fans. The fan control lines are modeled + as standard PWM channels. + +properties: + compatible: + const: adi,adt7470 + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + "#thermal-sensor-cells": + const: 1 + description: + Valid index values are 0 to 9, corresponding to temp1 through temp10. + +required: + - compatible + - reg + +allOf: + - if: + required: + - "#thermal-sensor-cells" + then: + $ref: /schemas/thermal/thermal-sensor.yaml# + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hwmon@2f { + compatible = "adi,adt7470"; + reg = <0x2f>; + #pwm-cells = <3>; + #thermal-sensor-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml new file mode 100644 index 000000000000..05e2132ad4d8 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml @@ -0,0 +1,272 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,ltc4283.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LTC4283 Negative Voltage Hot Swap Controller + +maintainers: + - Nuno Sá <nuno.sa@analog.com> + +description: | + The LTC4283 negative voltage hot swap controller drives an external N-channel + MOSFET to allow a board to be safely inserted and removed from a live + backplane. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4283.pdf + +properties: + compatible: + enum: + - adi,ltc4283 + + reg: + maxItems: 1 + + adi,rsense-nano-ohms: + description: Value of the sense resistor. + + adi,current-limit-sense-microvolt: + description: + The current limit sense voltage of the chip is adjustable between + 15mV and 30mV in 1mV steps. This effectively limits the current + on the load. + minimum: 15000 + maximum: 30000 + default: 15000 + + adi,current-limit-foldback-factor: + description: + Specifies the foldback factor for the current limit. The current limit + can be reduced (folded back) to one of four preset levels. The value + represents the percentage of the current limit sense voltage to use + during foldback. A value of 100 means no foldback. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 50, 100] + default: 100 + + adi,cooling-delay-ms: + description: + Cooling time to apply after an overcurrent fault, FET bad or + external fault. + enum: [512, 1002, 2005, 4100, 8190, 16400, 32800, 65600] + default: 512 + + adi,fet-bad-timer-delay-ms: + description: + FET bad timer delay. After a FET bad status condition is detected, + this timer is started. If the condition persists for the + specified time, the FET is turned off and a fault is logged. + enum: [256, 512, 1002, 2005] + default: 256 + + adi,power-good-reset-on-fet: + description: + If set, resets the power good status when the MOSFET is turned off. + Otherwise, it resets when a low output voltage is detected. + type: boolean + + adi,fet-turn-off-disable: + description: + If set, the MOSFET is not turned off when a FET fault is detected. + type: boolean + + adi,tmr-pull-down-disable: + description: Disables 2uA pull-down current on the TMR pin. + type: boolean + + adi,dvdt-inrush-control-disable: + description: + Disables dV/dt inrush control during startup. In dV/dt mode, the inrush + current is limited by controlling a constant output voltage ramp rate. + When disabled, the inrush control mechanism is active current limiting. + type: boolean + + adi,fault-log-enable: + description: + If set, enables logging fault registers and ADC data into EEPROM upon a + fault. + type: boolean + + adi,vpower-drns-enable: + description: + If set, enables the attenuated MOSFET drain voltage to be monitored. This + effectively means that the MOSFET power is monitored. If not set, the + attenuated input voltage (and hence input power) is monitored. + type: boolean + + adi,external-fault-fet-off-enable: + description: Turns MOSFET off following an external fault. + type: boolean + + adi,undervoltage-retry-disable: + description: Do not retry to turn on the MOSFET after an undervoltage fault. + type: boolean + + adi,overvoltage-retry-disable: + description: Do not retry to turn on the MOSFET after an overvoltage fault. + type: boolean + + adi,external-fault-retry-enable: + description: Retry to turn on the MOSFET after an external fault. + type: boolean + + adi,overcurrent-retries: + description: Configures auto-retry following an Overcurrent fault. + $ref: /schemas/types.yaml#/definitions/string + enum: [latch-off, "1", "7", unlimited] + default: latch-off + + adi,fet-bad-retries: + description: + Configures auto-retry following a FET bad fault and a consequent MOSFET + turn off. + $ref: /schemas/types.yaml#/definitions/string + enum: [latch-off, "1", "7", unlimited] + default: latch-off + + adi,pgio1-func: + description: Configures the function of the PGIO1 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good, power_good, gpio] + default: inverted_power_good + + adi,pgio2-func: + description: Configures the function of the PGIO2 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good, power_good, gpio, active_current_limiting] + default: inverted_power_good + + adi,pgio3-func: + description: Configures the function of the PGIO3 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good_input, power_good_input, gpio] + default: inverted_power_good_input + + adi,pgio4-func: + description: Configures the function of the PGIO4 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_external_fault, external_fault, gpio] + default: inverted_external_fault + + adi,gpio-on-adio1: + description: If set, the ADIO1 pin is used as a GPIO. + type: boolean + + adi,gpio-on-adio2: + description: If set, the ADIO2 pin is used as a GPIO. + type: boolean + + adi,gpio-on-adio3: + description: If set, the ADIO3 pin is used as a GPIO. + type: boolean + + adi,gpio-on-adio4: + description: If set, the ADIO4 pin is used as a GPIO. + type: boolean + + gpio-controller: true + + '#gpio-cells': + const: 2 + +dependencies: + adi,gpio-on-adio1: + - gpio-controller + - '#gpio-cells' + adi,gpio-on-adio2: + - gpio-controller + - '#gpio-cells' + adi,gpio-on-adio3: + - gpio-controller + - '#gpio-cells' + adi,gpio-on-adio4: + - gpio-controller + - '#gpio-cells' + adi,external-fault-retry-enable: + - adi,pgio4-func + adi,external-fault-fet-off-enable: + - adi,pgio4-func + +required: + - compatible + - reg + - adi,rsense-nano-ohms + +allOf: + - if: + properties: + adi,pgio1-func: + const: gpio + required: + - adi,pgio1-func + then: + required: + - gpio-controller + - '#gpio-cells' + + - if: + properties: + adi,pgio2-func: + const: gpio + required: + - adi,pgio2-func + then: + required: + - gpio-controller + - '#gpio-cells' + + - if: + properties: + adi,pgio3-func: + const: gpio + required: + - adi,pgio3-func + then: + required: + - gpio-controller + - '#gpio-cells' + + - if: + properties: + adi,pgio4-func: + const: gpio + required: + - adi,pgio4-func + then: + properties: + adi,external-fault-retry-enable: false + adi,external-fault-fet-off-enable: false + required: + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + swap-controller@15 { + compatible = "adi,ltc4283"; + reg = <0x15>; + + adi,rsense-nano-ohms = <500>; + adi,current-limit-sense-microvolt = <25000>; + adi,current-limit-foldback-factor = <10>; + adi,cooling-delay-ms = <8190>; + adi,fet-bad-timer-delay-ms = <512>; + + adi,external-fault-fet-off-enable; + adi,pgio4-func = "external_fault"; + + adi,gpio-on-adio1; + adi,pgio1-func = "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/amphenol,chipcap2.yaml b/Documentation/devicetree/bindings/hwmon/amphenol,chipcap2.yaml index 17351fdbefce..56b0cecfca5f 100644 --- a/Documentation/devicetree/bindings/hwmon/amphenol,chipcap2.yaml +++ b/Documentation/devicetree/bindings/hwmon/amphenol,chipcap2.yaml @@ -45,6 +45,8 @@ properties: - const: low - const: high + label: true + vdd-supply: description: Dedicated, controllable supply-regulator to reset the device and @@ -55,6 +57,9 @@ required: - reg - vdd-supply +allOf: + - $ref: hwmon-common.yaml# + additionalProperties: false examples: @@ -72,6 +77,7 @@ examples: <5 IRQ_TYPE_EDGE_RISING>, <6 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ready", "low", "high"; + label = "Room"; vdd-supply = <®_vdd>; }; }; diff --git a/Documentation/devicetree/bindings/hwmon/apple,smc-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/apple,smc-hwmon.yaml new file mode 100644 index 000000000000..64149ef4cc59 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/apple,smc-hwmon.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/apple,smc-hwmon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SMC Hardware Monitoring + +description: + Apple's System Management Controller (SMC) exposes a vast array of + hardware monitoring sensors, including temperature probes, current and + voltage sense, power meters, and fan speeds. It also provides endpoints + to manually control the speed of each fan individually. Each Apple + Silicon device exposes a different set of endpoints via SMC keys. This + is true even when two machines share an SoC. The CPU core temperature + sensor keys on an M1 Mac mini are different to those on an M1 MacBook + Pro, for example. + +maintainers: + - James Calligeros <jcalligeros99@gmail.com> + +$defs: + sensor: + type: object + + properties: + apple,key-id: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: The SMC FourCC key of the desired sensor. + Must match the node's suffix. + + label: + description: Human-readable name for the sensor + + required: + - apple,key-id + +properties: + compatible: + const: apple,smc-hwmon + +patternProperties: + "^current-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + + "^fan-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + + properties: + apple,fan-minimum: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: SMC key containing the fan's minimum speed + + apple,fan-maximum: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: SMC key containing the fan's maximum speed + + apple,fan-target: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: Writeable endpoint for setting desired fan speed + + apple,fan-mode: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: Writeable key to enable/disable manual fan control + + "^power-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + + "^temperature-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + + "^voltage-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/hwmon/eswin,eic7700-pvt.yaml b/Documentation/devicetree/bindings/hwmon/eswin,eic7700-pvt.yaml new file mode 100644 index 000000000000..58ec8635dce3 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/eswin,eic7700-pvt.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/eswin,eic7700-pvt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN EIC7700 PVT Sensor + +maintainers: + - Yulin Lu <luyulin@eswincomputing.com> + - Huan He <hehuan1@eswincomputing.com> + +description: + ESWIN EIC7700 SoC integrates embedded voltage and temperature sensors to + monitor the internal SoC environment. The system includes two PVT sensor + instances. The PVT0 monitors the main SoC power domain. The PVT1 sensor + monitors the DDR core power domain. + +allOf: + - $ref: /schemas/hwmon/hwmon-common.yaml# + +properties: + compatible: + const: eswin,eic7700-pvt + + reg: + maxItems: 1 + + clocks: + items: + - description: PVT enable clock + - description: APB bus clock + + clock-names: + items: + - const: enable + - const: apb + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + '#thermal-sensor-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - resets + - '#thermal-sensor-cells' + +unevaluatedProperties: false + +examples: + - | + sensor@50b00000 { + compatible = "eswin,eic7700-pvt"; + reg = <0x50b00000 0x10000>; + clocks = <&clocks 244>, <&clocks 234>; + clock-names = "enable", "apb"; + interrupts = <349>; + interrupt-parent = <&plic>; + label = "pvt0"; + resets = <&reset 111>; + #thermal-sensor-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml b/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml index 4a52aac6be72..963aa640dc05 100644 --- a/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml +++ b/Documentation/devicetree/bindings/hwmon/hpe,gxp-fan-ctrl.yaml @@ -18,21 +18,12 @@ properties: const: hpe,gxp-fan-ctrl reg: - items: - - description: Fan controller PWM - - description: Programmable logic - - description: Function 2 - - reg-names: - items: - - const: base - - const: pl - - const: fn2 + description: Fan controller PWM + maxItems: 1 required: - compatible - reg - - reg-names additionalProperties: false @@ -40,6 +31,5 @@ examples: - | fan-controller@1000c00 { compatible = "hpe,gxp-fan-ctrl"; - reg = <0x1000c00 0x200>, <0xd1000000 0xff>, <0x80200000 0x100000>; - reg-names = "base", "pl", "fn2"; + reg = <0x1000c00 0x200>; }; diff --git a/Documentation/devicetree/bindings/hwmon/lm75.yaml b/Documentation/devicetree/bindings/hwmon/lm75.yaml index 0b9fda81e3ec..b48bf3fd721f 100644 --- a/Documentation/devicetree/bindings/hwmon/lm75.yaml +++ b/Documentation/devicetree/bindings/hwmon/lm75.yaml @@ -54,6 +54,13 @@ properties: interrupts: maxItems: 1 + ti,alert-polarity-active-high: + description: Alert pin is asserted based on the value of alert polarity + bit of configuration register. Default value is normal (0 which maps to + active-low). The other value is inverted (1 which maps to active-high). + Specify this property to set the alert polarity to active-high. + $ref: /schemas/types.yaml#/definitions/flag + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml new file mode 100644 index 000000000000..1a273621db82 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/microchip,emc1812.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip EMC1812/13/14/15/33 multichannel temperature sensor + +maintainers: + - Marius Cristea <marius.cristea@microchip.com> + +description: | + The Microchip EMC1812/13/14/15/33 is a high-accuracy 2-wire multichannel + low-voltage remote diode temperature monitor. + + The datasheet can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/EMC1812-3-4-5-33-Data-Sheet-DS20005751.pdf + + EMC1812 has one external remote temperature monitoring channel + EMC1813 has two external remote temperature monitoring channels + EMC1814 has three external remote temperature monitoring channels and + channels 2 and 3 support anti parallel diode + EMC1815 has four external remote temperature monitoring channels and + channels 1/2 and 3/4 support anti parallel diode + EMC1833 has two external remote temperature monitoring channels and + channels 1 and 2 support anti parallel diode + +properties: + compatible: + enum: + - microchip,emc1812 + - microchip,emc1813 + - microchip,emc1814 + - microchip,emc1815 + - microchip,emc1833 + + reg: + maxItems: 1 + + interrupts: + items: + - description: alert-therm2 asserts when the ALERT limit is exceeded. + - description: therm-addr asserts when the THERM limit is exceeded. + minItems: 1 + + interrupt-names: + items: + - const: alert-therm2 + - const: therm-addr + minItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + microchip,enable-anti-parallel: + description: + Enable anti-parallel diode mode operation. EMC1814, EMC1815 and EMC1833 + support reading two external diodes in anti-parallel connection on the + same set of pins. Disabling APD functionality to implement substrate + diodes on devices that support APD eliminates the benefit of APD + (two diodes on one channel). + type: boolean + + microchip,parasitic-res-on-channel1-2: + description: + Indicates that the chip and the diodes/transistors are sufficiently + far apart that a parasitic resistance is added to the wires, which can + affect the measurements. Due to the availability of only a single + configuration bit in hardware, channels 1 and 2 are affected together. + If channel 2 is not available in hardware, this setting affects only + channel 1. + type: boolean + + microchip,parasitic-res-on-channel3-4: + description: + Indicates that the chip and the diodes/transistors are sufficiently + far apart that a parasitic resistance is added to the wires, which can + affect the measurements. Due to the availability of only a single + configuration bit in hardware, channels 3 and 4 are affected together. + If channel 4 is not available in hardware, this setting affects only + channel 3. + type: boolean + + vdd-supply: true + +patternProperties: + "^channel@[0-4]$": + description: | + Represents the temperature channels. + 0: Internal sensor + 1-4: External remote diodes + type: object + + properties: + reg: + maxItems: 1 + + label: + description: Unique name to identify which channel this is. + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - vdd-supply + +allOf: + # EMC1812: 1 Internal, 1 External Channels, No APD, + # parasitic-res-on-channel1-2: for channel 1 + - if: + properties: + compatible: + const: microchip,emc1812 + then: + properties: + microchip,enable-anti-parallel: false + microchip,parasitic-res-on-channel3-4: false + patternProperties: + "^channel@[2-4]$": false + + # EMC1813: 1 Internal, 2 External Channels, No APD, + # parasitic-res-on-channel1-2: on both channel 1 & 2 + - if: + properties: + compatible: + const: microchip,emc1813 + then: + properties: + microchip,enable-anti-parallel: false + microchip,parasitic-res-on-channel3-4: false + patternProperties: + "^channel@[3-4]$": false + + # EMC1833: 1 Internal, 2 External Channels, Supports APD, + # parasitic-res-on-channel1-2: on both channel 1 & 2 + - if: + properties: + compatible: + const: microchip,emc1833 + then: + properties: + microchip,parasitic-res-on-channel3-4: false + patternProperties: + "^channel@[3-4]$": false + + # EMC1814: 1 Internal, 3 External Channels, Supports APD, + # parasitic-res-on-channel1-2: on both channel 1 & 2 + # parasitic-res-on-channel3-4: for channel 3 + - if: + properties: + compatible: + const: microchip,emc1814 + then: + properties: + channel@4: false + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@4c { + compatible = "microchip,emc1813"; + reg = <0x4c>; + + #address-cells = <1>; + #size-cells = <0>; + + microchip,parasitic-res-on-channel1-2; + + vdd-supply = <&vdd>; + + channel@1 { + reg = <1>; + label = "External CH1 Temperature"; + }; + + channel@2 { + reg = <2>; + label = "External CH2 Temperature"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml index d3f06ebc19fa..8c2548539d7f 100644 --- a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml +++ b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml @@ -54,6 +54,12 @@ patternProperties: The fan number used to determine the associated PWM channel. maxItems: 1 + fan-shutdown-percent: + description: + PWM duty cycle in percent applied to the fan during shutdown. + minimum: 0 + maximum: 100 + required: - reg @@ -80,12 +86,14 @@ examples: fan@0 { reg = <0x0>; pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>; + fan-shutdown-percent = <100>; #cooling-cells = <2>; }; fan@1 { reg = <0x1>; pwms = <&fan_controller 26000 0 1>; + fan-shutdown-percent = <50>; #cooling-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt b/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt deleted file mode 100644 index 0863e067c85b..000000000000 --- a/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt +++ /dev/null @@ -1,20 +0,0 @@ -Bindings for the fan / temperature monitor microcontroller used on -the Zyxel NSA 320 and several subsequent models. - -Required properties: -- compatible : "zyxel,nsa320-mcu" -- data-gpios : The GPIO pin connected to the data line on the MCU -- clk-gpios : The GPIO pin connected to the clock line on the MCU -- act-gpios : The GPIO pin connected to the active line on the MCU - -Example: - - hwmon { - compatible = "zyxel,nsa320-mcu"; - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; - pinctrl-names = "default"; - - data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml new file mode 100644 index 000000000000..cc50a4ee44a2 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,max20830.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX20830 Step-Down Switching Regulator with PMBus + +maintainers: + - Alexis Czezar Torreno <alexisczezar.torreno@analog.com> + +description: | + The MAX20830 is a fully integrated step-down DC-DC switching regulator with + PMBus interface. It provides 2.7V to 16V input, 0.4V to 5.8V adjustable + output, and up to 30A output current. It allows monitoring of input/output + voltage, output current and temperature through the PMBus serial interface. + Datasheet: + https://www.analog.com/en/products/max20830.html + +allOf: + - $ref: /schemas/regulator/regulator.yaml# + +properties: + compatible: + oneOf: + - const: adi,max20830 + - items: + - enum: + - adi,max20830c + - adi,max20840c + - const: adi,max20830 + + reg: + maxItems: 1 + + vddh-supply: + description: + Phandle to the regulator that provides the VDDH power supply. + + avdd-supply: + description: + Phandle to the regulator that provides the AVDD power supply. + + ldoin-supply: + description: + Optional 2.5V to 5.5V LDO input supply. + + pwr-good-gpios: + description: + GPIO connected to the power-good status output pin. + maxItems: 1 + + adi,vout-rfb1-ohms: + description: + Top feedback resistor (RFB1) value in ohms for VOUT sensing divider. + When the desired output voltage is higher than VREF, a resistor divider + is required. VOUT = VREF × (1 + RFB1/RFB2) + + adi,vout-rfb2-ohms: + description: + Bottom feedback resistor (RFB2) value in ohms for VOUT sensing divider. + Datasheet recommends that RFB2 does not exceed 2.5kΩ. + +required: + - compatible + - reg + - vddh-supply + +dependencies: + adi,vout-rfb1-ohms: ['adi,vout-rfb2-ohms'] + adi,vout-rfb2-ohms: ['adi,vout-rfb1-ohms'] + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@30 { + compatible = "adi,max20830"; + reg = <0x30>; + vddh-supply = <&vddh>; + avdd-supply = <&avdd>; + ldoin-supply = <&ldoin>; + pwr-good-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + adi,vout-rfb1-ohms = <10000>; + adi,vout-rfb2-ohms = <2000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20860a.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20860a.yaml new file mode 100644 index 000000000000..dd238265d462 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20860a.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,max20860a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX20860A Step-Down Converter + +maintainers: + - Sanman Pradhan <psanman@juniper.net> + +description: | + The MAX20860A is a fully integrated step-down DC-DC switching regulator + with PMBus interface for monitoring input/output voltage, output current + and temperature. + + Datasheet: https://www.analog.com/en/products/max20860a.html + +allOf: + - $ref: /schemas/regulator/regulator.yaml# + +properties: + compatible: + const: adi,max20860a + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@40 { + compatible = "adi,max20860a"; + reg = <0x40>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml new file mode 100644 index 000000000000..ce5e9456c318 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,vt7505.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,vt7505.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX16545/MAX16550 and Volterra VT7505 PMBus controllers + +maintainers: + - Sanman Pradhan <psanman@juniper.net> + +description: | + The Analog Devices MAX16545 and MAX16550, and the Volterra VT7505, are PMBus + controllers that provide input/output voltage, input/output current, + input power and temperature monitoring over the PMBus interface. + + The MAX16545 uses the same programming model as the VT7505. + + Datasheets: + https://www.analog.com/media/en/technical-documentation/data-sheets/max16545b-max16545c.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/max16550.pdf + +properties: + compatible: + oneOf: + - enum: + - adi,max16550 + - adi,vt7505 + - items: + - const: adi,max16545 + - const: adi,vt7505 + + reg: + maxItems: 1 + + adi,rload-ohms: + description: + Resistance in ohms of the external telemetry load resistor connected + between the ILOAD current-output pin and ground. This is not a + current-path shunt resistor; it sets the scaling of the reported input + current, output current and input power. + minimum: 1 + maximum: 283383959 + default: 4750 + + adi,ocp-severe-filter-us: + description: + Deglitch time, in microseconds, applied to the severe + overcurrent-protection comparator, programmed into the + MFR_CONFIG[15:14] field. The MAX16550 and VT7505 expose this field. + On the MAX16545 the severe overcurrent delay is fixed and these bits + are reserved. If omitted, the existing hardware setting is retained. + enum: [0, 1, 2, 10] + +required: + - compatible + - reg + +allOf: + # The severe OCP deglitch filter is fixed on the MAX16545, so the property + # is only valid for the MAX16550 and VT7505. + - if: + properties: + compatible: + contains: + const: adi,max16545 + then: + properties: + adi,ocp-severe-filter-us: false + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@40 { + compatible = "adi,vt7505"; + reg = <0x40>; + adi,rload-ohms = <4750>; + adi,ocp-severe-filter-us = <10>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/infineon,xdp720.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/infineon,xdp720.yaml index 72bc3a5e7139..4a949c53f7ae 100644 --- a/Documentation/devicetree/bindings/hwmon/pmbus/infineon,xdp720.yaml +++ b/Documentation/devicetree/bindings/hwmon/pmbus/infineon,xdp720.yaml @@ -5,23 +5,31 @@ $id: http://devicetree.org/schemas/hwmon/pmbus/infineon,xdp720.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Infineon XDP720 Digital eFuse Controller +title: Infineon XDP720 / XDP730 Digital eFuse Controllers maintainers: - Ashish Yadav <ashish.yadav@infineon.com> description: | - The XDP720 is an eFuse with integrated current sensor and digital - controller. It provides accurate system telemetry (V, I, P, T) and - reports analog current at the IMON pin for post-processing. + The XDP720 and XDP730 are PMBus-compliant digital eFuse controllers + with an integrated current sensor. They provide accurate system + telemetry (V, I, P, T) and report analog current at the IMON pin for + post-processing. - Datasheet: - https://www.infineon.com/assets/row/public/documents/24/49/infineon-xdp720-001-datasheet-en.pdf + Both parts share the same PMBus register map and direct-format + coefficients; they differ in the GIMON gain step exposed via the + TELEMETRY_AVG register (bit 10) and in the VDD_VIN pin number + (XDP720: pin 9, XDP730: pin 20). + + Datasheets: + - XDP720: https://www.infineon.com/assets/row/public/documents/24/49/infineon-xdp720-001-datasheet-en.pdf + - XDP730: https://www.infineon.com/assets/row/public/documents/24/49/infineon-xdp730-001-datasheet-en.pdf properties: compatible: enum: - infineon,xdp720 + - infineon,xdp730 reg: maxItems: 1 @@ -33,9 +41,9 @@ properties: vdd-vin-supply: description: - Supply for the VDD_VIN pin (pin 9), the IC controller power supply. - Typically connected to the input bus (VIN) through a 100 ohm / 100 nF - RC filter. + Supply for the VDD_VIN pin (XDP720 pin 9, XDP730 pin 20), the IC + controller power supply. Typically connected to the input bus + (VIN) through a 100 ohm / 100 nF RC filter. required: - compatible @@ -50,7 +58,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - hwmon@11 { + efuse@11 { compatible = "infineon,xdp720"; reg = <0x11>; vdd-vin-supply = <&vdd_vin>; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/mps,mpq8785.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/mps,mpq8785.yaml index 90970a0433e9..d7a32fb3b7af 100644 --- a/Documentation/devicetree/bindings/hwmon/pmbus/mps,mpq8785.yaml +++ b/Documentation/devicetree/bindings/hwmon/pmbus/mps,mpq8785.yaml @@ -18,6 +18,7 @@ properties: - mps,mpm3695 - mps,mpm3695-25 - mps,mpm82504 + - mps,mpq8646 - mps,mpq8785 reg: @@ -52,7 +53,9 @@ allOf: - if: properties: compatible: - const: mps,mpq8785 + enum: + - mps,mpq8646 + - mps,mpq8785 then: properties: mps,vout-fb-divider-ratio-permille: diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/silergy,sq24860.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/silergy,sq24860.yaml new file mode 100644 index 000000000000..03ef82c11e1a --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/silergy,sq24860.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/hwmon/pmbus/silergy,sq24860.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silergy SQ24860 eFuse + +maintainers: + - Ziming Zhu <ziming.zhu@silergycorp.com> + +description: + The Silergy SQ24860 is an integrated, high-current circuit protection and + power management device with PMBus interface. + +properties: + compatible: + const: silergy,sq24860 + + reg: + maxItems: 1 + + silergy,rimon-micro-ohms: + description: + Micro-ohms value of the resistance installed between the IMON pin and + the ground reference. + + interrupts: + description: PMBus SMBAlert interrupt. + maxItems: 1 + + regulators: + type: object + description: + List of regulators provided by this controller. + + properties: + vout: + $ref: /schemas/regulator/regulator.yaml# + type: object + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - silergy,rimon-micro-ohms + +additionalProperties: false + +examples: + - | + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + hw-monitor@40 { + compatible = "silergy,sq24860"; + reg = <0x40>; + + interrupt-parent = <&gpio>; + interrupts = <42 8>; + silergy,rimon-micro-ohms = <1600000000>; + + regulators { + cpu0_vout: vout { + regulator-name = "main_cpu0"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/ti,lm25066.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/ti,lm25066.yaml index a20f140dc79a..fe42daabaaa8 100644 --- a/Documentation/devicetree/bindings/hwmon/pmbus/ti,lm25066.yaml +++ b/Documentation/devicetree/bindings/hwmon/pmbus/ti,lm25066.yaml @@ -46,12 +46,32 @@ properties: additionalProperties: false + ti,current-range: + description: | + Configure the current limit setting. When present, this property + overrides the hardware setting of the physical CL pin by configuring + the DEVICE_SETUP register. + - "low": maps to 25 mV (LM25066) or 26 mV (LM5064, LM5066, LM5066i) + - "high": maps to 46 mV (LM25066) or 50 mV (LM5064, LM5066, LM5066i) + $ref: /schemas/types.yaml#/definitions/string + enum: + - low + - high + required: - compatible - reg allOf: - $ref: /schemas/hwmon/hwmon-common.yaml# + - if: + properties: + compatible: + contains: + const: ti,lm25056 + then: + properties: + ti,current-range: false unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml b/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml index a84cc3a4cfdc..6a24851fd80d 100644 --- a/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml +++ b/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml @@ -63,7 +63,8 @@ properties: description: The PWM that is used to control the fan. maxItems: 1 - "#cooling-cells": true + "#cooling-cells": + const: 2 required: - compatible diff --git a/Documentation/devicetree/bindings/hwmon/sensirion,sht30.yaml b/Documentation/devicetree/bindings/hwmon/sensirion,sht30.yaml new file mode 100644 index 000000000000..dee0252941c2 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/sensirion,sht30.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/sensirion,sht30.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sensirion SHT3x and GXCAS GXHT30 humidity and temperature sensors + +maintainers: + - Zaixiang Xu <zaixiang.xu.dev@gmail.com> + +properties: + compatible: + oneOf: + - enum: + - sensirion,sht30 + - sensirion,sts30 + - items: + - enum: + - gxcas,gxht30 + - sensirion,sht31 + - sensirion,sht35 + - sensirion,sht85 + - const: sensirion,sht30 + - items: + - enum: + - sensirion,sts31 + - sensirion,sts32 + - sensirion,sts35 + - const: sensirion,sts30 + + reg: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the VDD pin. + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the nRESET pin. Active low. + + interrupts: + maxItems: 1 + description: + Interrupt connected to the ALERT pin. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + humidity-sensor@44 { + compatible = "gxcas,gxht30", "sensirion,sht30"; + reg = <0x44>; + vdd-supply = <&vcc_3v3_reg>; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio1>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/smsc,emc1403.yaml b/Documentation/devicetree/bindings/hwmon/smsc,emc1403.yaml new file mode 100644 index 000000000000..d7873a37c329 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/smsc,emc1403.yaml @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/smsc,emc1403.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SMSC EMC1402/1403/1404/1428 thermal sensors + +maintainers: + - Svyatoslav Ryhel <clamor95@gmail.com> + +properties: + compatible: + oneOf: + - enum: + - smsc,emc1402 + - smsc,emc1403 + - smsc,emc1404 + - smsc,emc1428 + + - items: + - enum: + - smsc,emc1412 + - smsc,emc1422 + - smsc,emc1442 + - const: smsc,emc1402 + + - items: + - enum: + - smsc,emc1413 + - smsc,emc1423 + - const: smsc,emc1403 + + - items: + - enum: + - smsc,emc1414 + - smsc,emc1424 + - const: smsc,emc1404 + + - items: + - enum: + - smsc,emc1438 + - const: smsc,emc1428 + + interrupts: + items: + - description: Sensors "ALERT" pin output. + + reg: + maxItems: 1 + + "#thermal-sensor-cells": + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + vdd-supply: true + +required: + - compatible + - reg + +patternProperties: + "^channel@([0-7])$": + type: object + description: Represents channels of the device and their specific configuration. + + properties: + reg: + description: The channel number. 0 is local channel, 1-7 are remote channels. + items: + minimum: 0 + maximum: 7 + + label: + description: A descriptive name for this channel, like "ambient" or "psu". + + required: + - reg + + additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - smsc,emc1402 + then: + patternProperties: + "^channel@([0-7])$": + properties: + reg: + items: + maximum: 1 + + - if: + properties: + compatible: + contains: + enum: + - smsc,emc1403 + then: + patternProperties: + "^channel@([0-7])$": + properties: + reg: + items: + maximum: 2 + + - if: + properties: + compatible: + contains: + enum: + - smsc,emc1404 + then: + patternProperties: + "^channel@([0-7])$": + properties: + reg: + items: + maximum: 3 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@4c { + compatible = "smsc,emc1412", "smsc,emc1402"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + }; + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + sensor@29 { + compatible = "smsc,emc1428"; + reg = <0x29>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0x0>; + label = "local"; + }; + + channel@1 { + reg = <0x1>; + label = "chan1"; + }; + + channel@2 { + reg = <0x2>; + label = "chan2"; + }; + + channel@3 { + reg = <0x3>; + label = "chan3"; + }; + + channel@4 { + reg = <0x4>; + label = "chan4"; + }; + + channel@5 { + reg = <0x5>; + label = "chan5"; + }; + + channel@6 { + reg = <0x6>; + label = "chan6"; + }; + + channel@7 { + reg = <0x7>; + label = "chan7"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index 009d78b30859..a79ade3142fa 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -28,6 +28,7 @@ properties: - ti,ina228 - ti,ina230 - ti,ina231 + - ti,ina232 - ti,ina233 - ti,ina234 - ti,ina237 @@ -114,6 +115,7 @@ allOf: - ti,ina228 - ti,ina230 - ti,ina231 + - ti,ina232 - ti,ina234 - ti,ina237 - ti,ina238 @@ -136,6 +138,7 @@ allOf: - ti,ina226 - ti,ina230 - ti,ina231 + - ti,ina232 - ti,ina234 - ti,ina260 - ti,ina700 diff --git a/Documentation/devicetree/bindings/hwmon/zyxel,nsa320-mcu.yaml b/Documentation/devicetree/bindings/hwmon/zyxel,nsa320-mcu.yaml new file mode 100644 index 000000000000..a111f8125e09 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/zyxel,nsa320-mcu.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/zyxel,nsa320-mcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZyXEL NSA320 MCU + +maintainers: + - Adam Baker <linux@baker-net.org.uk> + - Guenter Roeck <linux@roeck-us.net> + +description: + The ZyXEL NSA320 uses a dedicated microcontroller to manage system-critical + functions like fan speed and power monitoring. It is connected to the SoC + via a GPIO-based serial protocol. + +properties: + compatible: + const: zyxel,nsa320-mcu + + data-gpios: + maxItems: 1 + description: GPIO pin connected to the data line on the MCU. + + clk-gpios: + maxItems: 1 + description: GPIO pin connected to the clock line on the MCU. + + act-gpios: + maxItems: 1 + description: GPIO pin connected to the active line on the MCU. + +required: + - compatible + - data-gpios + - clk-gpios + - act-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + hwmon { + compatible = "zyxel,nsa320-mcu"; + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; + pinctrl-names = "default"; + + data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/devicetree/bindings/i2c/altr,softip-i2c-v1.0.yaml b/Documentation/devicetree/bindings/i2c/altr,softip-i2c-v1.0.yaml new file mode 100644 index 000000000000..d04570680c05 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/altr,softip-i2c-v1.0.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/altr,softip-i2c-v1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera I2C Controller + +maintainers: + - Thor Thayer <thor.thayer@linux.intel.com> + - Chaitanya Sabnis <chaitanya.msabnis@gmail.com> + +description: + Altera's synthesizable logic block I2C Controller for use in Altera's FPGAs. + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: altr,softip-i2c-v1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Size of the RX and TX FIFOs in bytes. + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@80000 { + compatible = "altr,softip-i2c-v1.0"; + reg = <0x80000 0x40>; + interrupt-parent = <&intc>; + interrupts = <0 43 4>; + clocks = <&clk_0>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + fifo-size = <4>; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml b/Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml index c4cc8af18280..7b59b60b62e5 100644 --- a/Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/amlogic,meson6-i2c.yaml @@ -16,10 +16,15 @@ allOf: properties: compatible: - enum: - - amlogic,meson6-i2c # Meson6, Meson8 and compatible SoCs - - amlogic,meson-gxbb-i2c # GXBB and compatible SoCs - - amlogic,meson-axg-i2c # AXG and compatible SoCs + oneOf: + - items: + - enum: + - amlogic,t7-i2c + - const: amlogic,meson-axg-i2c + - enum: + - amlogic,meson6-i2c # Meson6, Meson8 and compatible SoCs + - amlogic,meson-gxbb-i2c # GXBB and compatible SoCs + - amlogic,meson-axg-i2c # AXG and compatible SoCs reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index 500a965bdb7a..d39f5e3f1df4 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -22,7 +22,11 @@ properties: compatible: oneOf: - items: - - const: apple,t6020-i2c + - enum: + - apple,t6020-i2c + - apple,t6030-i2c + - apple,t6031-i2c + - apple,t8122-i2c - const: apple,t8103-i2c - items: - enum: diff --git a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml index 9f1d35ce1fe8..4dc69d54f75d 100644 --- a/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml +++ b/Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml @@ -14,9 +14,13 @@ allOf: properties: compatible: - enum: - - cdns,i2c-r1p10 # cadence i2c controller version 1.0 - - cdns,i2c-r1p14 # cadence i2c controller version 1.4 + oneOf: + - enum: + - cdns,i2c-r1p10 # cadence i2c controller version 1.0 + - cdns,i2c-r1p14 # cadence i2c controller version 1.4 + - items: + - const: axiado,ax3005-i2c + - const: cdns,i2c-r1p14 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/i2c/i2c-altera.txt b/Documentation/devicetree/bindings/i2c/i2c-altera.txt deleted file mode 100644 index 767664f448ec..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-altera.txt +++ /dev/null @@ -1,39 +0,0 @@ -* Altera I2C Controller -* This is Altera's synthesizable logic block I2C Controller for use -* in Altera's FPGAs. - -Required properties : - - compatible : should be "altr,softip-i2c-v1.0" - - reg : Offset and length of the register set for the device - - interrupts : <IRQ> where IRQ is the interrupt number. - - clocks : phandle to input clock. - - #address-cells = <1>; - - #size-cells = <0>; - -Recommended properties : - - clock-frequency : desired I2C bus clock frequency in Hz. - -Optional properties : - - fifo-size : Size of the RX and TX FIFOs in bytes. - - Child nodes conforming to i2c bus binding - -Example : - - i2c@100080000 { - compatible = "altr,softip-i2c-v1.0"; - reg = <0x00000001 0x00080000 0x00000040>; - interrupt-parent = <&intc>; - interrupts = <0 43 4>; - clocks = <&clk_0>; - clock-frequency = <100000>; - #address-cells = <1>; - #size-cells = <0>; - fifo-size = <4>; - - eeprom@51 { - compatible = "atmel,24c32"; - reg = <0x51>; - pagesize = <32>; - }; - }; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-axxia.txt b/Documentation/devicetree/bindings/i2c/i2c-axxia.txt deleted file mode 100644 index 7d53a2b79553..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-axxia.txt +++ /dev/null @@ -1,30 +0,0 @@ -LSI Axxia I2C - -Required properties : -- compatible : Must be "lsi,api2c" -- reg : Offset and length of the register set for the device -- interrupts : the interrupt specifier -- #address-cells : Must be <1>; -- #size-cells : Must be <0>; -- clock-names : Must contain "i2c". -- clocks: Must contain an entry for each name in clock-names. See the common - clock bindings. - -Optional properties : -- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, - the default 100 kHz frequency will be used. As only Normal and Fast modes - are supported, possible values are 100000 and 400000. - -Example : - -i2c@2010084000 { - compatible = "lsi,api2c"; - device_type = "i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x20 0x10084000 0x00 0x1000>; - interrupts = <0 19 4>; - clocks = <&clk_per>; - clock-names = "i2c"; - clock-frequency = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt deleted file mode 100644 index 6590501c53d4..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Texas Instruments Davinci/Keystone I2C - -This file provides information, what the device node for the -davinci/keystone i2c interface contains. - -Required properties: -- compatible: "ti,davinci-i2c" or "ti,keystone-i2c"; -- reg : Offset and length of the register set for the device -- clocks: I2C functional clock phandle. - For 66AK2G this property should be set per binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.yaml - -SoC-specific Required Properties: - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the I2C device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml - -Recommended properties : -- interrupts : standard interrupt property. -- clock-frequency : desired I2C bus clock frequency in Hz. -- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC - registers. PFUNC registers allow to switch I2C pins to function as - GPIOs, so they can be toggled manually. - -Example (enbw_cmc board): - i2c@1c22000 { - compatible = "ti,davinci-i2c"; - reg = <0x22000 0x1000>; - clock-frequency = <100000>; - interrupts = <15>; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <0>; - - dtt@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml index 1eaf00b90a77..deca72bfc8cf 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml @@ -40,6 +40,7 @@ properties: i2c-parent: $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 2 items: maxItems: 1 description: diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml index 4a93d1f78f93..6e44510aaef6 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: GPIO-based I2C Bus Mux maintainers: - - Wolfram Sang <wsa@kernel.org> + - Peter Korsgaard <peter.korsgaard@barco.com> description: | This binding describes an I2C bus multiplexer that uses GPIOs to route the I2C signals. diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml index 2e3d555eb96c..99812a893476 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Pinctrl-based I2C Bus Mux maintainers: - - Wolfram Sang <wsa@kernel.org> + - Thierry Reding <thierry.reding@kernel.org> description: | This binding describes an I2C bus multiplexer that uses pin multiplexing to route the I2C diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt deleted file mode 100644 index b9d9755e4172..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt +++ /dev/null @@ -1,74 +0,0 @@ -Register-based I2C Bus Mux - -This binding describes an I2C bus multiplexer that uses a single register -to route the I2C signals. - -Required properties: -- compatible: i2c-mux-reg -- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side - port is connected to. -* Standard I2C mux properties. See i2c-mux.yaml in this directory. -* I2C child bus nodes. See i2c-mux.yaml in this directory. - -Optional properties: -- reg: this pair of <offset size> specifies the register to control the mux. - The <offset size> depends on its parent node. It can be any memory-mapped - address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the - resource of this device will be used. -- little-endian: The existence indicates the register is in little endian. -- big-endian: The existence indicates the register is in big endian. - If both little-endian and big-endian are omitted, the endianness of the - CPU will be used. -- write-only: The existence indicates the register is write-only. -- idle-state: value to set the muxer to when idle. When no value is - given, it defaults to the last value used. - -Whenever an access is made to a device on a child bus, the value set -in the relevant node's reg property will be output to the register. - -If an idle state is defined, using the idle-state (optional) property, -whenever an access is not being made to a device on a child bus, the -register will be set according to the idle value. - -If an idle state is not defined, the most recently used value will be -left programmed into the register. - -Example of a mux on PCIe card, the host is a powerpc SoC (big endian): - - i2c-mux { - /* the <offset size> depends on the address translation - * of the parent device. If omitted, device resource - * will be used instead. The size is to determine - * whether iowrite32, iowrite16, or iowrite8 will be used. - */ - reg = <0x6028 0x4>; - little-endian; /* little endian register on PCIe */ - compatible = "i2c-mux-reg"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c1>; - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - si5338: clock-generator@70 { - compatible = "silabs,si5338"; - reg = <0x70>; - /* other stuff */ - }; - }; - - i2c@1 { - /* data is written using iowrite32 */ - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - si5338: clock-generator@70 { - compatible = "silabs,si5338"; - reg = <0x70>; - /* other stuff */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.yaml new file mode 100644 index 000000000000..01ade0771c60 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-mux-reg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Register-based I2C Bus Mux + +maintainers: + - Peter Rosin <peda@axentia.se> + +description: | + This binding describes an I2C bus multiplexer that uses a single + memory-mapped register to route the I2C signals. + + Whenever an access is made to a device on a child bus, the value + set in the relevant node's reg property is output to the register. + + If an idle state is defined via the idle-state property, the + register is set to that value whenever no access is being made. + Otherwise the most recently used value is left programmed. + +allOf: + - $ref: /schemas/i2c/i2c-mux.yaml# + +properties: + compatible: + const: i2c-mux-reg + + reg: + maxItems: 1 + description: | + Offset and size of the register that selects the active child + bus, relative to the parent node's address space. The size + determines the access width and must be 1, 2, or 4 bytes. If + omitted, the platform device's own memory resource is used + instead. + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the I2C bus that this multiplexer's master-side port + is connected to. + + little-endian: + type: boolean + description: Register is accessed in little-endian byte order. + + big-endian: + type: boolean + description: Register is accessed in big-endian byte order. + + write-only: + type: boolean + description: + Register is write-only; the driver must not read back the + current selection. + + idle-state: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value to write to the register when no child bus is selected. + +required: + - compatible + - i2c-parent + +unevaluatedProperties: false + +examples: + - | + i2c-mux@6028 { + compatible = "i2c-mux-reg"; + reg = <0x6028 0x4>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c1>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml b/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml index 67882ec6e06a..ee09c6d9c5f0 100644 --- a/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - loongson,ls2k-i2c + - loongson,ls2k0300-i2c - loongson,ls7a-i2c reg: @@ -24,6 +25,9 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/lsi,api2c.yaml b/Documentation/devicetree/bindings/i2c/lsi,api2c.yaml new file mode 100644 index 000000000000..2d1c3069c3a3 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/lsi,api2c.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/lsi,api2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LSI Axxia I2C Controller + +maintainers: + - Anders Berg <anders.berg@lsi.com> + - Chaitanya Sabnis <chaitanya.msabnis@gmail.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: lsi,api2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: i2c + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + i2c@10084000 { + compatible = "lsi,api2c"; + reg = <0x10084000 0x1000>; + interrupts = <0 19 4>; + clocks = <&clk_per>; + clock-names = "i2c"; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml index 6ff58b64d496..bd63c70aac6b 100644 --- a/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml +++ b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml @@ -37,6 +37,9 @@ properties: modes are supported, possible values are 100000 and 400000. enum: [100000, 400000] + resets: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml b/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml index d9ef86729011..736e9a3eab8a 100644 --- a/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml +++ b/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml @@ -95,8 +95,8 @@ examples: interrupts = <10>; opencores,ip-clock-frequency = <20000000>; - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ + reg-shift = <0>; /* 8 bit registers */ + reg-io-width = <1>; /* 8 bit read/write */ }; i2c@b0000000 { @@ -108,7 +108,7 @@ examples: clocks = <&osc>; clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ + reg-shift = <0>; /* 8 bit registers */ + reg-io-width = <1>; /* 8 bit read/write */ }; ... diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 7c497a358e1d..1e8def25ec0e 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: + - qcom,glymur-cci - qcom,kaanapali-cci - qcom,milos-cci - qcom,qcm2290-cci @@ -35,6 +36,7 @@ properties: - qcom,sc8280xp-cci - qcom,sdm670-cci - qcom,sdm845-cci + - qcom,shikra-cci - qcom,sm6150-cci - qcom,sm6350-cci - qcom,sm8250-cci @@ -134,9 +136,11 @@ allOf: compatible: contains: enum: + - qcom,glymur-cci - qcom,kaanapali-cci - qcom,qcm2290-cci - qcom,qcs8300-cci + - qcom,shikra-cci - qcom,sm8750-cci then: properties: diff --git a/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml b/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml new file mode 100644 index 000000000000..04caf622b3ba --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/qcom,sa8255p-geni-i2c.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/qcom,sa8255p-geni-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8255p QUP GENI I2C Controller + +maintainers: + - Praveen Talari <praveen.talari@oss.qualcomm.com> + +properties: + compatible: + oneOf: + - const: qcom,sa8255p-geni-i2c + - items: + - const: qcom,sa8797p-geni-i2c + - const: qcom,sa8255p-geni-i2c + + reg: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + +required: + - compatible + - reg + - interrupts + - power-domains + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/dma/qcom-gpi.h> + + i2c@a90000 { + compatible = "qcom,sa8255p-geni-i2c"; + reg = <0xa90000 0x4000>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; +... diff --git a/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml b/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml index 6cc60c3f61cd..f9ede03c3287 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,rcar-i2c.yaml @@ -56,6 +56,11 @@ properties: - renesas,i2c-r8a779h0 # R-Car V4M - const: renesas,rcar-gen4-i2c # R-Car Gen4 + - items: + - enum: + - renesas,i2c-r8a78000 # R-Car X5H + - const: renesas,rcar-gen5-i2c # R-Car Gen5 + reg: maxItems: 1 @@ -140,6 +145,7 @@ allOf: - renesas,rcar-gen2-i2c - renesas,rcar-gen3-i2c - renesas,rcar-gen4-i2c + - renesas,rcar-gen5-i2c then: required: - resets diff --git a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml index a2ddc6803617..07600b49f2f9 100644 --- a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml @@ -35,7 +35,7 @@ properties: gpios: description: | - The order of the GPIOs should be the following:: <SDA, SCL>. The GPIO + The order of the GPIOs should be the following: <SDA, SCL>. The GPIO specifier depends on the gpio controller. Required in all cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output lines are permanently wired to the respective client. diff --git a/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml index 08f9c1e446fd..4efbe82b6d68 100644 --- a/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml @@ -60,7 +60,7 @@ examples: i2c@fed40000 { compatible = "st,comms-ssc4-i2c"; reg = <0xfed40000 0x110>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_s_a0_ls CLK_ICN_REG>; clock-names = "ssc"; clock-frequency = <400000>; diff --git a/Documentation/devicetree/bindings/i2c/ti,davinci-i2c.yaml b/Documentation/devicetree/bindings/i2c/ti,davinci-i2c.yaml new file mode 100644 index 000000000000..b94ac06dce36 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/ti,davinci-i2c.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/ti,davinci-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DaVinci/Keystone I2C + +maintainers: + - Chaitanya Sabnis <chaitanya.msabnis@gmail.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: ti,keystone-i2c + then: + required: + - power-domains + +properties: + compatible: + enum: + - ti,davinci-i2c + - ti,keystone-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + ti,has-pfunc: + description: + Indicates that the SoC supports PFUNC registers, allowing I2C pins + to function as GPIOs for manual toggling. + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@1c22000 { + compatible = "ti,davinci-i2c"; + reg = <0x01c22000 0x1000>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + interrupts = <15>; + #address-cells = <1>; + #size-cells = <0>; + + sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + }; diff --git a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml index 6fa3078074d0..280f0ada3c43 100644 --- a/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml +++ b/Documentation/devicetree/bindings/i3c/cdns,i3c-master.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - axiado,ax3000-i3c + - axiado,ax3005-i3c - const: cdns,i3c-master reg: diff --git a/Documentation/devicetree/bindings/i3c/i3c.yaml b/Documentation/devicetree/bindings/i3c/i3c.yaml index e25fa72fd785..5603f2e7807d 100644 --- a/Documentation/devicetree/bindings/i3c/i3c.yaml +++ b/Documentation/devicetree/bindings/i3c/i3c.yaml @@ -31,10 +31,12 @@ properties: described in the device tree, which in turn means we have to describe I3C devices. - Another use case for describing an I3C device in the device tree is when - this I3C device has a static I2C address and we want to assign it a - specific I3C dynamic address before the DAA takes place (so that other - devices on the bus can't take this dynamic address). + Other use-cases for describing an I3C device in the device tree are: + - When the I3C device has a static I2C address and we want to assign + it a specific I3C dynamic address before the DAA takes place (so + that other devices on the bus can't take this dynamic address). + - When the I3C device requires SETAASA for its discovery and uses a + pre-defined static address. "#size-cells": const: 0 @@ -145,7 +147,31 @@ patternProperties: Dynamic address to be assigned to this device. In case static address is present (first cell of the reg property != 0), this address is assigned through SETDASA. If static address is not present, this address is assigned - through SETNEWDA after assigning a temporary address via ENTDAA. + through SETNEWDA after assigning a temporary address via ENTDAA. If + SETAASA is used, this property is not used, and the static address itself + becomes the dynamic address. + + mipi-i3c-static-method: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x1 + maximum: 0x7 + default: 1 + description: | + Bitmap describing which methods of Dynamic Address Assignment from a + static address are supported by this I3C Target. For each defined bit + position, a set bit indicates support for that method and a cleared + bit indicates lack of support. + + Bit 0: SETDASA CCC (Direct) + Bit 1: SETAASA CCC (Broadcast) + Bit 2: Other CCC (vendor / standards extension) + All other bits are reserved. + + This property follows the MIPI I3C specification. The primary use + of this property is to indicate support for SETAASA, i.e Bit 1, but + will allow other values mentioned in the specification so that it + mirrors the specification. SETDASA will remain as the default method + even if this property is not present. required: - reg diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml index 39bb1a1784c9..d488fb420945 100644 --- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml +++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml @@ -9,9 +9,6 @@ title: MIPI I3C HCI maintainers: - Nicolas Pitre <npitre@baylibre.com> -allOf: - - $ref: /schemas/i3c/i3c.yaml# - description: | MIPI I3C Host Controller Interface @@ -28,9 +25,17 @@ description: | properties: compatible: - const: mipi-i3c-hci + enum: + - mipi-i3c-hci + - microchip,sama7d65-i3c-hci reg: maxItems: 1 + + clocks: + items: + - description: Peripheral bus clock + - description: System Generic clock + interrupts: maxItems: 1 @@ -39,6 +44,20 @@ required: - reg - interrupts +allOf: + - $ref: /schemas/i3c/i3c.yaml# + - if: + properties: + compatible: + contains: + const: microchip,sama7d65-i3c-hci + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml index e803457d3f55..dc7ee38001d6 100644 --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml @@ -38,6 +38,9 @@ properties: interrupts: maxItems: 1 + resets: + maxItems: 1 + power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml b/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml new file mode 100644 index 000000000000..2caa245a8656 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/xlnx,axi-i3c-1.0.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/xlnx,axi-i3c-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD I3C master + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + - Shubham Patil <shubhamsanjay.patil@amd.com> + +description: + The AXI-I3C IP is an I3C Controller with an AXI4-Lite interface, compatible + with the MIPI I3C Specification v1.1.1. The design includes bidirectional I/O + buffers that implement open collector drivers for the SDA and SCL signals. + External pull-up resistors are required to properly hold the bus at a Logic-1 + level when the drivers are released. + + For more details, please see https://docs.amd.com/r/en-US/pg439-axi-i3c + +properties: + compatible: + const: xlnx,axi-i3c-1.0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +allOf: + - $ref: i3c.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + i3c@80000000 { + compatible = "xlnx,axi-i3c-1.0"; + reg = <0x80000000 0x10000>; + clocks = <&zynqmp_clk 71>; + interrupt-parent = <&imux>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + }; +... diff --git a/Documentation/devicetree/bindings/iio/adc/adc.yaml b/Documentation/devicetree/bindings/iio/adc/adc.yaml index b9bc02b5b07a..b673eaa5d072 100644 --- a/Documentation/devicetree/bindings/iio/adc/adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adc.yaml @@ -73,6 +73,47 @@ properties: device design and can interact with other characteristics such as settling time. + reference-sources: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Indicates the voltage reference source or sources for this channel. Some + ADCs usually allow choosing between internal reference sources or a pair + of external pins. + + input-chopping: + type: boolean + description: + If set, the positive and negative input channels are swapped on every + other conversion to reduce offset error. This generally comes at the + expense of added settling time between conversions, so should be omitted + on systems with high-frequency signals or high data rate requirements. + + excitation-channels: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Excitation current sources provide current to resistive temperature + devices (RTDs), thermistors, diodes and other resistive sensors that + require constant current biasing. + + This array describes the mux configuration of the excitation current + sources. The values correspond to pins similar to the diff-channels and + single-channel properties. + + excitation-current-nanoamp: + description: + Excitation current sources provide current to resistive temperature + devices (RTDs), thermistors, diodes and other resistive sensors that + require constant current biasing. + + This array describes the current configuration of the excitation current + sources. The index in the array corresponds to the same index in the + excitation-channels array. + + burn-out-current-nanoamp: + description: + Burn-out current sources provide current to the channel's input pins for + open-circuit or short-circuit detection. + anyOf: - oneOf: - required: diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index 79df2696ef24..db8467b98e67 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -18,7 +18,11 @@ description: | service a wide variety of precision, wide bandwidth data acquisition applications. + The AD4880 is a dual-channel variant with two independent ADC channels, + each with its own SPI configuration interface. + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4080.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4880.pdf $ref: /schemas/spi/spi-peripheral-props.yaml# @@ -34,9 +38,17 @@ properties: - adi,ad4086 - adi,ad4087 - adi,ad4088 + - adi,ad4880 + - adi,ad4883 + - adi,ad4884 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + description: + SPI chip select(s). For single-channel devices, one chip select. + For multi-channel devices like AD4880, two chip selects are required + as each channel has its own SPI configuration interface. spi-max-frequency: description: Configuration of the SPI bus. @@ -60,7 +72,10 @@ properties: vrefin-supply: true io-backends: - maxItems: 1 + minItems: 1 + items: + - description: Backend for channel A (primary) + - description: Backend for channel B (secondary) adi,lvds-cnv-enable: description: Enable the LVDS signal type on the CNV pin. Default is CMOS. @@ -81,6 +96,28 @@ required: - vdd33-supply - vrefin-supply +allOf: + - if: + properties: + compatible: + contains: + enum: + - adi,ad4880 + - adi,ad4883 + - adi,ad4884 + then: + properties: + reg: + minItems: 2 + io-backends: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + io-backends: + maxItems: 1 + additionalProperties: false examples: @@ -101,4 +138,21 @@ examples: io-backends = <&iio_backend>; }; }; + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4880"; + reg = <0>, <1>; + spi-max-frequency = <10000000>; + vdd33-supply = <&vdd33>; + vddldo-supply = <&vddldo>; + vrefin-supply = <&vrefin>; + clocks = <&cnv>; + clock-names = "cnv"; + io-backends = <&iio_backend_cha>, <&iio_backend_chb>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml index d00690a8d3fb..cc38617bb829 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml @@ -5,19 +5,30 @@ $id: http://devicetree.org/schemas/iio/adc/adi,ad4130.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices AD4130 ADC device driver +title: Analog Devices AD4130 family ADCs maintainers: - Cosmin Tanislav <cosmin.tanislav@analog.com> description: | - Bindings for the Analog Devices AD4130 ADC. Datasheet can be found here: + Bindings for the Analog Devices AD4130 family ADCs. + Datasheets can be found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4129-4.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4129-8.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-4.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4131-4.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4131-8.pdf properties: compatible: enum: + - adi,ad4129-4 + - adi,ad4129-8 + - adi,ad4130-4 - adi,ad4130 + - adi,ad4131-4 + - adi,ad4131-8 reg: maxItems: 1 @@ -32,6 +43,10 @@ properties: interrupts: maxItems: 1 + description: | + Data Ready / FIFO interrupt. For devices with FIFO support, the + interrupt polarity specified here is inverted when the device enters + FIFO mode, and normal for data ready. interrupt-names: description: | diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml new file mode 100644 index 000000000000..af28a0c1cfa9 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4691.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4691 Family Multichannel SAR ADCs + +maintainers: + - Radu Sabau <radu.sabau@analog.com> + +description: | + The AD4691 family are high-speed, low-power, multichannel successive + approximation register (SAR) analog-to-digital converters (ADCs) with + an SPI-compatible serial interface. The ADC supports CNV Burst Mode, + where an external PWM drives the CNV pin, and Manual Mode, where CNV + is directly tied to the SPI chip-select. + + Datasheets: + * https://www.analog.com/en/products/ad4691.html + * https://www.analog.com/en/products/ad4692.html + * https://www.analog.com/en/products/ad4693.html + * https://www.analog.com/en/products/ad4694.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4691 + - adi,ad4692 + - adi,ad4693 + - adi,ad4694 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 40000000 + + spi-cpol: true + spi-cpha: true + + avdd-supply: + description: Analog power supply (4.5V to 5.5V). + + vdd-supply: + description: + External 1.8V digital core supply. When present, the internal LDO is + disabled (LDO_EN = 0). Mutually exclusive with ldo-in-supply. + + ldo-in-supply: + description: + LDO input supply (2.4V to 5.5V). When present and vdd-supply is absent, + the internal LDO generates 1.8V VDD from this input (LDO_EN = 1). + Mutually exclusive with vdd-supply. + + vio-supply: + description: I/O voltage supply (1.71V to 1.89V or VDD). + + ref-supply: + description: External reference voltage supply (2.4V to 5.25V). + + refin-supply: + description: Internal reference buffer input supply. + + reset-gpios: + description: + GPIO line controlling the hardware reset pin (active-low). + maxItems: 1 + + pwms: + description: + PWM connected to the CNV pin. When present, selects CNV Burst Mode where + the PWM drives the conversion rate. When absent, Manual Mode is used + (CNV tied to SPI CS). + maxItems: 1 + + interrupts: + description: + Interrupt lines connected to the ADC GP pins. Each GP pin can be + physically wired to an interrupt-capable input on the SoC. + maxItems: 4 + + interrupt-names: + description: Names of the interrupt lines, matching the GP pin names. + minItems: 1 + maxItems: 4 + items: + enum: + - gp0 + - gp1 + - gp2 + - gp3 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + '#trigger-source-cells': + description: + This node can act as a trigger source. The single cell in a consumer + reference specifies the GP pin number (0-3) used as the trigger output. + const: 1 + +required: + - compatible + - reg + - avdd-supply + - vio-supply + +allOf: + # vdd-supply and ldo-in-supply are mutually exclusive, one is required: + # either an external 1.8V VDD is provided or the internal LDO is fed from + # ldo-in-supply to generate VDD. + - oneOf: + - required: + - vdd-supply + - required: + - ldo-in-supply + # ref-supply and refin-supply are mutually exclusive, one is required + - oneOf: + - required: + - ref-supply + - required: + - refin-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + /* AD4692 in CNV Burst Mode with SPI offload */ + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4692"; + reg = <0>; + spi-cpol; + spi-cpha; + spi-max-frequency = <40000000>; + + avdd-supply = <&avdd_supply>; + ldo-in-supply = <&avdd_supply>; + vio-supply = <&vio_supply>; + ref-supply = <&ref_5v>; + + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + + pwms = <&pwm_gen 0 0>; + + #trigger-source-cells = <1>; + }; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + /* AD4692 in Manual Mode (CNV tied to SPI CS) */ + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4692"; + reg = <0>; + spi-cpol; + spi-cpha; + spi-max-frequency = <31250000>; + + avdd-supply = <&avdd_supply>; + ldo-in-supply = <&avdd_supply>; + vio-supply = <&vio_supply>; + refin-supply = <&refin_supply>; + + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ltc2378.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ltc2378.yaml new file mode 100644 index 000000000000..33de1dc4c256 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ltc2378.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ltc2378.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices LTC2378 and similar Analog to Digital Converters + +maintainers: + - Marcelo Schmitt <marcelo.schmitt@analog.com> + +description: | + Analog Devices LTC2378 series of ADCs. + Specifications can be found at: + https://www.analog.com/media/en/technical-documentation/data-sheets/233818fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/236416fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/236418f.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/236716fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/236718f.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/236816f.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/236818f.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/236918fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237016fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237616fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237618fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237620fb.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237716fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237718fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237720fb.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237816fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237818fa.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237820fb.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/237918fb.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/238016fb.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + # Single compatible string match. + - enum: + - adi,ltc2338-18 + - adi,ltc2364-16 + - adi,ltc2364-18 + - adi,ltc2376-16 + - adi,ltc2376-18 + - adi,ltc2376-20 + + # Low sample rate fallback for 16-bit unipolar sensors. + - items: + - enum: + - adi,ltc2370-16 # 2 MSPS + - adi,ltc2368-16 # 1 MSPS + - adi,ltc2367-16 # 500 kSPS + - const: adi,ltc2364-16 # fallback (250 kSPS) + + # Low sample rate fallback for 18-bit unipolar sensors. + - items: + - enum: + - adi,ltc2369-18 # 1.6 MSPS + - adi,ltc2368-18 # 1 MSPS + - adi,ltc2367-18 # 500 kSPS + - const: adi,ltc2364-18 # fallback (250 kSPS) + + # Low sample rate fallback for 16-bit bipolar sensors. + - items: + - enum: + - adi,ltc2380-16 # 2 MSPS + - adi,ltc2378-16 # 1 MSPS + - adi,ltc2377-16 # 500 kSPS + - const: adi,ltc2376-16 # fallback (250 kSPS) + + # Low sample rate fallback for 18-bit bipolar sensors. + - items: + - enum: + - adi,ltc2379-18 # 1.6 MSPS + - adi,ltc2378-18 # 1 MSPS + - adi,ltc2377-18 # 500 kSPS + - const: adi,ltc2376-18 # fallback (250 kSPS) + + # Low sample rate fallback for 20-bit bipolar sensors. + - items: + - enum: + - adi,ltc2378-20 # 1 MSPS + - adi,ltc2377-20 # 500 kSPS + - const: adi,ltc2376-20 # fallback (250 kSPS) + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 100000000 + + vdd-supply: + description: A 2.5V supply that powers the chip (VDD). + + ovdd-supply: + description: + A 1.71V to 5.25V supply that sets the logic level for digital interface. + + ref-supply: + description: + Voltage reference input that determines the scale of ADC conversions. + + refin-supply: + description: + Alternative voltage reference input. + + cnv-gpios: + description: + When provided, this property indicates the GPIO that is connected to the + CNV pin. + maxItems: 1 + + pwms: + description: PWM signal connected to the CNV pin. + maxItems: 1 + + interrupts: + description: + Interrupt for signaling the completion of conversion results. The active + low signal provided on the BUSY pin asserts when ADC conversions finish. + maxItems: 1 + +required: + - compatible + - reg + - vdd-supply + - ovdd-supply + +allOf: + # Except for LTC2338, all designs require a voltage reference input + - if: + properties: + compatible: + not: + contains: + enum: + - adi,ltc2338-18 + then: + required: + - ref-supply + properties: + refin-supply: false + else: + properties: + ref-supply: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + adc@0 { + compatible = "adi,ltc2378-20", "adi,ltc2376-20"; + reg = <0>; + spi-max-frequency = <71000000>; + vdd-supply = <&supply_2_5V>; + ovdd-supply = <&supply_3_3V>; + ref-supply = <&supply_5V>; + cnv-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml b/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml index da605a051b94..6467800d30e2 100644 --- a/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - allwinner,sun20i-d1-gpadc + - allwinner,sun55i-a523-gpadc - items: - enum: - allwinner,sun50i-h616-gpadc @@ -29,7 +30,12 @@ properties: const: 0 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -40,6 +46,30 @@ properties: resets: maxItems: 1 +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-gpadc + then: + properties: + clocks: + items: + - description: Bus clock + - description: Module clock + clock-names: + items: + - const: bus + - const: mod + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + clock-names: false + patternProperties: "^channel@[0-9a-f]+$": $ref: adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml index 9c57eb13f892..099235b5fd54 100644 --- a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml +++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml @@ -10,14 +10,9 @@ maintainers: - Andreas Klinger <ak@it-klinger.de> description: | - Bit-banging driver using two GPIOs: - - sck-gpio gives a clock to the sensor with 24 cycles for data retrieval - and up to 3 cycles for selection of the input channel and gain for the - next measurement - - dout-gpio is the sensor data the sensor responds to the clock - - Specifications about the driver can be found at: - http://www.aviaic.com/ENProducts.aspx + The HX711 is a 24-bit ADC with selectable gain (32/64/128) and two + differential input channels. Channel A supports gain 64 and 128; + channel B supports gain 32. properties: compatible: @@ -26,23 +21,43 @@ properties: sck-gpios: description: - Definition of the GPIO for the clock (output). In the datasheet it is - named PD_SCK + GPIO for the clock output (PD_SCK in the datasheet). maxItems: 1 dout-gpios: description: - Definition of the GPIO for the data-out sent by the sensor in - response to the clock (input). - See Documentation/devicetree/bindings/gpio/gpio.txt for information - on how to specify a consumer gpio. + GPIO for the data output from the sensor (DOUT in the datasheet). maxItems: 1 avdd-supply: description: - Definition of the regulator used as analog supply + Analog supply voltage (AVDD). + + vsup-supply: + description: + Supply voltage for the on-chip regulator (VSUP). + + dvdd-supply: + description: + Digital supply voltage (DVDD). On the HX711, DVDD is a + board-supplied digital rail; it was missing from the original + binding. On the HX710B, DVDD must be greater than or equal to + AVDD; when DVDD is a battery rail and AVDD is a regulated supply, + one channel monitors the DVDD-AVDD difference for battery level + detection. + + rate-gpios: + description: + GPIO connected to the RATE pin. When driven low the output data + rate is 10 SPS; when driven high it is 80 SPS. If omitted the + RATE pin state is determined by the board wiring. + maxItems: 1 clock-frequency: + description: + Controls the SCK bit-bang timing. The value is used to derive the + delay between SCK edges; keep the SCK high time below 60 us to + avoid triggering chip power-down mode. minimum: 20000 maximum: 2500000 default: 400000 @@ -62,6 +77,7 @@ examples: compatible = "avia,hx711"; sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + rate-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; avdd-supply = <&avdd>; clock-frequency = <100000>; }; diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml index 5d4ab701f51a..c2f7387e4bfc 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/adc/mediatek,mt6359-auxadc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: MediaTek MT6350 series PMIC AUXADC +title: MediaTek MT6350 series and similar PMIC AUXADC maintainers: - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> @@ -18,12 +18,18 @@ description: properties: compatible: - enum: - - mediatek,mt6357-auxadc - - mediatek,mt6358-auxadc - - mediatek,mt6359-auxadc - - mediatek,mt6363-auxadc - - mediatek,mt6373-auxadc + oneOf: + - enum: + - mediatek,mt6323-auxadc + - mediatek,mt6357-auxadc + - mediatek,mt6358-auxadc + - mediatek,mt6359-auxadc + - mediatek,mt6363-auxadc + - mediatek,mt6373-auxadc + - items: + - enum: + - mediatek,mt6365-auxadc + - const: mediatek,mt6359-auxadc "#io-channel-cells": const: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml index c978c3a3e31a..63aac8de22ad 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml @@ -78,6 +78,10 @@ patternProperties: reg: maxItems: 1 + label: + description: | + Unique name to identify which channel this is. + qcom,decimation: $ref: /schemas/types.yaml#/definitions/uint32 description: | @@ -130,36 +134,47 @@ examples: vcoin: adc-channel@0 { reg = <0x00 0x00>; + label = "vcoin"; }; vbat: adc-channel@1 { reg = <0x00 0x01>; + label = "vbat"; }; dcin: adc-channel@2 { reg = <0x00 0x02>; + label = "dcin"; }; ichg: adc-channel@3 { reg = <0x00 0x03>; + label = "ichg"; }; vph_pwr: adc-channel@4 { reg = <0x00 0x04>; + label = "vph_pwr"; }; usb_vbus: adc-channel@a { reg = <0x00 0x0a>; + label = "usb_vbus"; }; die_temp: adc-channel@b { reg = <0x00 0x0b>; + label = "die_temp"; }; ref_625mv: adc-channel@c { reg = <0x00 0x0c>; + label = "ref_625mv"; }; ref_1250mv: adc-channel@d { reg = <0x00 0x0d>; + label = "ref_1250mv"; }; ref_325mv: adc-channel@e { reg = <0x00 0x0e>; + label = "ref_325mv"; }; ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; + label = "ref_muxoff"; }; }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml index 6769d679c907..f0551d665916 100644 --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml @@ -22,7 +22,9 @@ properties: - const: rockchip,rk3562-saradc - const: rockchip,rk3588-saradc - items: - - const: rockchip,rk3576-saradc + - enum: + - rockchip,rk3576-saradc + - rockchip,rv1106-saradc - const: rockchip,rk3588-saradc - items: - enum: diff --git a/Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml index dd9ec3038703..c8b8f28541ce 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml @@ -65,5 +65,5 @@ examples: interrupt-parent = <&vic1>; interrupts = <6>; sampling-frequency = <5000000>; - vref-external = <2500>; /* 2.5V VRef */ + vref-external = <2500>; /* 2.5V VRef */ }; diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads112c14.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads112c14.yaml new file mode 100644 index 000000000000..facfeee61330 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads112c14.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads112c14.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments' ADS112C14 and similar ADC chips + +description: | + Supports the following Texas Instruments' ADC chips: + - ADS112C14 (16-bit) + - ADS122C14 (24-bit) + + https://www.ti.com/lit/ds/symlink/ads122c14.pdf + + These chips are primarily designed for use with resistive sensors such as + RTDs, thermocouples, Wheatstone bridges, etc. The channel bindings reflect + this in that each channel represents the conditions required to make a + measurement rather than strictly just the physical input channels. + +maintainers: + - David Lechner <dlechner@baylibre.com> + +properties: + compatible: + enum: + - ti,ads112c14 + - ti,ads122c14 + + reg: + items: + - minimum: 0x40 + maximum: 0x47 + + clocks: + maxItems: 1 + description: Optional external clock connected to GPIO3 pin. + + avdd-supply: true + dvdd-supply: true + + refp-supply: true + refn-supply: true + + ti,refp-refn-resistor-ohms: + description: + The resistance of the external resistor between REFP and REFN when using + resistor bridge driven by current outputs for RTD measurements. + + interrupts: + minItems: 1 + items: + - description: /FAULT interrupt (GPIO2 pin) + - description: /DRDY interrupt (GPIO3 pin) + + interrupt-names: + minItems: 1 + maxItems: 2 + items: + enum: [fault, drdy] + + gpio-controller: true + '#gpio-cells': + const: 2 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + ^channel@[0-9a-f]$: + $ref: adc.yaml + + unevaluatedProperties: false + + properties: + reg: + items: + - maximum: 15 # arbitrary limit, channel@ can be any combination of AIN0-AIN7 + + single-channel: + maximum: 7 + + diff-channels: + items: + maximum: 7 + + bipolar: true + + input-chopping: true + + excitation-channels: + maxItems: 2 + items: + maximum: 7 + + excitation-current-nanoamp: + maxItems: 2 + items: + enum: [1000, 10000, 20000, 30000, 40000, 50000, 60000, 70000, 80000, + 90000, 100000, 200000, 300000, 400000, 500000, 600000, 700000, + 800000, 900000, 1000000] + + burn-out-current-nanoamp: + items: + - enum: [200, 1000, 10000] + + reference-sources: + items: + - enum: [internal-2.5v, internal-1.25v, external, avdd] + default: internal-2.5v + + dependencies: + excitation-channels: [ excitation-current-nanoamp ] + excitation-current-nanoamp: [ excitation-channels ] + + oneOf: + - required: [ single-channel ] + - required: [ diff-channels ] + +unevaluatedProperties: false + +required: + - compatible + - reg + - avdd-supply + - dvdd-supply + +dependencies: + refn-supply: [ refp-supply ] + +oneOf: + - required: [ refp-supply ] + - required: [ "ti,refp-refn-resistor-ohms" ] + - properties: + refp-supply: false + refn-supply: false + ti,refp-refn-resistor-ohms: false + +# /DRDY out and CLK in use the same AIN7/GPIO3 pin. +if: + required: + - interrupt-names + properties: + interrupt-names: + contains: + const: drdy +then: + properties: + clocks: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@40 { + compatible = "ti,ads112c14"; + reg = <0x40>; + + avdd-supply = <&avdd>; + dvdd-supply = <&dvdd>; + + /* 3-Wire RTD: Two IDACs, One Measurement (AIN1-AIN2) */ + + ti,refp-refn-resistor-ohms = <500>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + diff-channels = <1>, <2>; + input-chopping; + excitation-channels = <0>, <3>; + excitation-current-nanoamp = <500000>, <500000>; + reference-sources = "external"; + label = "rtd"; + }; + }; + }; + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@40 { + compatible = "ti,ads112c14"; + reg = <0x40>; + + avdd-supply = <&avdd>; + dvdd-supply = <&dvdd>; + + /* Resistive Bridge Measurement With a Thermistor for Temperature Compensation */ + + refp-supply = <&avdd>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + diff-channels = <6>, <7>; + bipolar; + reference-sources = "external"; + label = "bridge"; + }; + + channel@1 { + reg = <1>; + diff-channels = <1>, <2>; + reference-sources = "internal-2.5v"; + label = "thermistor"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,versal-sysmon.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,versal-sysmon.yaml new file mode 100644 index 000000000000..1ad58e3d6163 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/xlnx,versal-sysmon.yaml @@ -0,0 +1,154 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/xlnx,versal-sysmon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD/Xilinx Versal System Monitor + +maintainers: + - Salih Erim <salih.erim@amd.com> + +description: + The AMD/Xilinx Versal System Monitor (SysMon) is the successor to the + Zynq UltraScale+ AMS block. It provides on-chip voltage and temperature + monitoring with up to 160 voltage measurement points and up to + 64 temperature satellites distributed across the SoC. The hardware + supports configurable threshold alarms and oversampling. The device + can be accessed via memory-mapped I/O or via an I2C interface. + +properties: + compatible: + const: xlnx,versal-sysmon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#io-channel-cells': + const: 1 + + voltage-channels: + type: object + description: + Container for voltage measurement channels. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + '^channel@([0-9a-f]|[1-9][0-9a-f])$': + $ref: adc.yaml + + description: + Measures a voltage rail. The register index and rail + name are assigned by the hardware design tool (Vivado). + + properties: + reg: + minimum: 0 + maximum: 159 + description: + Voltage measurement register index assigned by the hardware + design tool. + + required: + - reg + - label + + unevaluatedProperties: false + + required: + - '#address-cells' + - '#size-cells' + + additionalProperties: false + + temperature-channels: + type: object + description: + Container for temperature satellite measurement channels. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + '^channel@([1-9a-f]|[1-3][0-9a-f]|40)$': + $ref: adc.yaml + + description: + Reads a temperature satellite sensor. Each satellite monitors + a specific region of the SoC die. + + properties: + reg: + minimum: 1 + maximum: 64 + description: + Temperature satellite number (1-based hardware index). + + required: + - reg + - label + + unevaluatedProperties: false + + required: + - '#address-cells' + - '#size-cells' + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + sysmon@f1270000 { + compatible = "xlnx,versal-sysmon"; + reg = <0xf1270000 0x4000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + + voltage-channels { + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + label = "vccaux"; + }; + + channel@3 { + reg = <3>; + label = "vcc_ram"; + bipolar; + }; + }; + + temperature-channels { + #address-cells = <1>; + #size-cells = <0>; + + channel@a { + reg = <10>; + label = "aie-temp-ch1"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/chemical/sensirion,scd30.yaml b/Documentation/devicetree/bindings/iio/chemical/sensirion,scd30.yaml index 40d87346ff4c..ea0e72f2a690 100644 --- a/Documentation/devicetree/bindings/iio/chemical/sensirion,scd30.yaml +++ b/Documentation/devicetree/bindings/iio/chemical/sensirion,scd30.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sensirion SCD30 carbon dioxide sensor maintainers: - - Tomasz Duszynski <tomasz.duszynski@octakon.com> + - Maxwell Doose <maxwell@maxwelld.cc> + - Tomasz Duszynski <tduszyns@gmail.com> description: | Air quality sensor capable of measuring co2 concentration, temperature diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml index a355d52a9d64..2fe098619772 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad3530r.yaml @@ -10,15 +10,17 @@ maintainers: - Kim Seer Paller <kimseer.paller@analog.com> description: | - The AD3530/AD3530R (8-channel) and AD3531/AD3531R (4-channel) are low-power, - 16-bit, buffered voltage output digital-to-analog converters (DACs) with - software-programmable gain controls, providing full-scale output spans of 2.5V - or 5V for reference voltages of 2.5V. These devices operate from a single 2.7V - to 5.5V supply and are guaranteed monotonic by design. The "R" variants - include a 2.5V, 5ppm/°C internal reference, which is disabled by default. + The AD3530/AD3530R (8-channel), AD3531/AD3531R (4-channel), and AD3532/AD3532R + (16-channel) are low-power, 16-bit, buffered voltage output digital-to-analog + converters (DACs) with software-programmable gain controls, providing + full-scale output spans of 2.5V or 5V for reference voltages of 2.5V. These + devices operate from a single 2.7V to 5.5V supply and are guaranteed monotonic + by design. The "R" variants include a 2.5V, 5ppm/°C internal reference, which + is disabled by default. Datasheet can be found here: https://www.analog.com/media/en/technical-documentation/data-sheets/ad3530_ad530r.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ad3531-ad3531r.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad3532r.pdf properties: compatible: @@ -27,6 +29,8 @@ properties: - adi,ad3530r - adi,ad3531 - adi,ad3531r + - adi,ad3532 + - adi,ad3532r reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml index 713f535bb33a..d1bb09054440 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5686.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/dac/adi,ad5686.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices AD5360 and similar SPI DACs +title: Analog Devices AD5686 and similar SPI DACs maintainers: - Michael Hennerich <michael.hennerich@analog.com> @@ -14,10 +14,14 @@ properties: compatible: enum: - adi,ad5310r + - adi,ad5313r + - adi,ad5317r - adi,ad5672r + - adi,ad5674 - adi,ad5674r - adi,ad5676 - adi,ad5676r + - adi,ad5679 - adi,ad5679r - adi,ad5681r - adi,ad5682r @@ -28,31 +32,107 @@ properties: - adi,ad5685r - adi,ad5686 - adi,ad5686r + - adi,ad5687 + - adi,ad5687r + - adi,ad5689 + - adi,ad5689r reg: maxItems: 1 + vdd-supply: + description: Input power supply. + + vlogic-supply: + description: + Digital power supply. On some tiny package variants for single-channel + devices, this supply is internally connected to vdd; in that case, specify + this property with the same regulator as vdd. + + vref-supply: + description: + Reference voltage supply. If not supplied the internal reference is used. + vcc-supply: - description: If not supplied the internal reference is used. + deprecated: true + description: Use vref-supply instead. + + reset-gpios: + description: Active-low RESET pin to reset the device. + maxItems: 1 + + ldac-gpios: + description: + Active-low LDAC pin used to asynchronously update the DAC channels. + maxItems: 1 + + gain-gpios: + description: + GAIN pin that sets a multiplier for the DAC output voltage. When high, + the DAC output voltage is multiplied by 2, otherwise it is unchanged. + maxItems: 1 + + adi,range-double: + description: + Sets the initial voltage output range from 0 to 2xVREF. On devices that + have a GAIN pin and no gain-gpios property is set, this indicates the pin + is hardwired high. + type: boolean required: - compatible - reg + - vdd-supply + - vlogic-supply allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + enum: + - adi,ad5674 + - adi,ad5676 + - adi,ad5679 + - adi,ad5683 + - adi,ad5684 + - adi,ad5686 + - adi,ad5687 + - adi,ad5689 + then: + required: + - vref-supply + - if: + properties: + compatible: + contains: + enum: + - adi,ad5310r + - adi,ad5681r + - adi,ad5682r + - adi,ad5683 + - adi,ad5683r + then: + properties: + gain-gpios: false unevaluatedProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> spi { #address-cells = <1>; #size-cells = <0>; dac@0 { reg = <0>; compatible = "adi,ad5310r"; - vcc-supply = <&dac_vref0>; + vdd-supply = <&dac_vdd>; + vlogic-supply = <&dac_vlogic>; + vref-supply = <&dac_vref>; + reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + ldac-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5696.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5696.yaml index b5a88b03dc2f..835fa21c474e 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5696.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5696.yaml @@ -16,10 +16,14 @@ properties: compatible: enum: - adi,ad5311r + - adi,ad5316r - adi,ad5337r - adi,ad5338r - adi,ad5671r + - adi,ad5673r + - adi,ad5675 - adi,ad5675r + - adi,ad5677r - adi,ad5691r - adi,ad5692r - adi,ad5693 @@ -29,22 +33,88 @@ properties: - adi,ad5695r - adi,ad5696 - adi,ad5696r + - adi,ad5697r reg: maxItems: 1 + vdd-supply: + description: Input power supply. + + vlogic-supply: + description: + Digital power supply. On some tiny package variants for single-channel + devices, this supply is internally connected to vdd; in that case, specify + this property with the same regulator as vdd. + + vref-supply: + description: + Reference voltage supply. If not supplied the internal reference is used. + vcc-supply: - description: | - The regulator supply for DAC reference voltage. + deprecated: true + description: Use vref-supply instead. + + reset-gpios: + description: Active-low RESET pin to reset the device. + maxItems: 1 + + ldac-gpios: + description: + Active-low LDAC pin used to asynchronously update the DAC channels. + maxItems: 1 + + gain-gpios: + description: + GAIN pin that sets a multiplier for the DAC output voltage. When high, + the DAC output voltage is multiplied by 2, otherwise it is unchanged. + maxItems: 1 + + adi,range-double: + description: + Sets the initial voltage output range from 0 to 2xVREF. On devices that + have a GAIN pin and no gain-gpios property is set, this indicates the pin + is hardwired high. + type: boolean required: - compatible - reg + - vdd-supply + - vlogic-supply + +allOf: + - if: + properties: + compatible: + contains: + enum: + - adi,ad5675 + - adi,ad5693 + - adi,ad5694 + - adi,ad5696 + then: + required: + - vref-supply + - if: + properties: + compatible: + contains: + enum: + - adi,ad5311r + - adi,ad5691r + - adi,ad5692r + - adi,ad5693 + - adi,ad5693r + then: + properties: + gain-gpios: false additionalProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> i2c { #address-cells = <1>; #size-cells = <0>; @@ -52,7 +122,10 @@ examples: ad5696: dac@0 { compatible = "adi,ad5696"; reg = <0>; - vcc-supply = <&dac_vref>; + vdd-supply = <&dac_vdd>; + vlogic-supply = <&dac_vlogic>; + vref-supply = <&dac_vref>; + ldac-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5706r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5706r.yaml new file mode 100644 index 000000000000..19cc744a9f0f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5706r.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5706r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5706R 4-Channel Current Output DAC + +maintainers: + - Alexis Czezar Torreno <alexisczezar.torreno@analog.com> + +description: | + The AD5706R is a 4-channel, 16-bit resolution, current output + digital-to-analog converter (DAC) with programmable output current + ranges (50mA, 150mA, 200mA, 300mA), an integrated 2.5V voltage + reference, and load DAC, A/B toggle, and dither functions. + + Datasheet: + https://www.analog.com/en/products/ad5706r.html + +properties: + compatible: + enum: + - adi,ad5706r + + reg: + maxItems: 1 + + avdd-supply: + description: Analog power supply (2.9V to 3.6V). + + iovdd-supply: + description: Logic power supply (1.14V to 1.89V). + + pvdd0-supply: + description: Power supply for IDAC0 channel (1.65V to AVDD). + + pvdd1-supply: + description: Power supply for IDAC1 channel (1.65V to AVDD). + + pvdd2-supply: + description: Power supply for IDAC2 channel (1.65V to AVDD). + + pvdd3-supply: + description: Power supply for IDAC3 channel (1.65V to AVDD). + + vref-supply: + description: + Optional external 2.5V voltage reference. If not provided, the + internal 2.5V reference is used. + + pwms: + maxItems: 1 + description: + Optional PWM connected to the LDAC/TGP/DCK pin for hardware + triggered DAC updates, toggle, or dither clock generation. + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the active low RESET pin. If not provided, + software reset is used. + + enable-gpios: + maxItems: 1 + description: + GPIO connected to the active low OUT_EN pin. Controls whether + the current outputs are enabled or in high-Z/ground state. + +required: + - compatible + - reg + - avdd-supply + - iovdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + compatible = "adi,ad5706r"; + reg = <0>; + avdd-supply = <&avdd>; + iovdd-supply = <&iovdd>; + pvdd0-supply = <&pvdd>; + pvdd1-supply = <&pvdd>; + pvdd2-supply = <&pvdd>; + pvdd3-supply = <&pvdd>; + vref-supply = <&vref>; + spi-max-frequency = <50000000>; + pwms = <&pwm0 0 1000000 0>; + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5791.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5791.yaml index 2bd89e0aa46b..80fb98035c6f 100644 --- a/Documentation/devicetree/bindings/iio/dac/adi,ad5791.yaml +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5791.yaml @@ -36,11 +36,11 @@ properties: vrefp-supply: description: - Positive referance input voltage range. From 5v to (vdd - 2.5) + Positive reference input voltage range. From 5v to (vdd - 2.5) vrefn-supply: description: - Negative referance input voltage range. From (vss + 2.5) to 0. + Negative reference input voltage range. From (vss + 2.5) to 0. adi,rbuf-gain2-en: description: Specify to allow an external amplifier to be connected in a diff --git a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47a1.yaml b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47a1.yaml new file mode 100644 index 000000000000..b181fe73dce8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47a1.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/iio/dac/microchip,mcp47a1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MCP47A1 DAC + +maintainers: + - Joshua Crofts <joshua.crofts1@gmail.com> + +description: | + The Microchip MCP47A1 is a 6-bit single output volatile DAC. + This device can have different IDs (0x2e and 0x3e). + https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/25154A.pdf + +properties: + compatible: + const: microchip,mcp47a1 + + reg: + items: + - enum: [0x2e, 0x3e] + + vref-supply: true + + vdd-supply: true + +required: + - compatible + - reg + - vref-supply + - vdd-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + dac@2e { + compatible = "microchip,mcp47a1"; + reg = <0x2e>; + vref-supply = <&vref_regulator>; + vdd-supply = <&vdd_regulator>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml index d2466aa6bda2..d131f136bd15 100644 --- a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml +++ b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml @@ -161,8 +161,8 @@ patternProperties: properties: reg: description: The channel number. - minItems: 1 - maxItems: 8 + minimum: 0 + maximum: 7 label: description: Unique name to identify which channel this is. @@ -280,23 +280,23 @@ examples: #address-cells = <1>; #size-cells = <0>; - dac@0 { - compatible = "microchip,mcp47feb02"; - reg = <0>; - vdd-supply = <&vdac_vdd>; - vref-supply = <&vref_reg>; + dac@60 { + compatible = "microchip,mcp47feb02"; + reg = <0x60>; + vdd-supply = <&vdac_vdd>; + vref-supply = <&vref_reg>; - #address-cells = <1>; - #size-cells = <0>; - channel@0 { - reg = <0>; - label = "Adjustable_voltage_ch0"; - }; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + label = "Adjustable_voltage_ch0"; + }; - channel@1 { - reg = <0x1>; - label = "Adjustable_voltage_ch1"; - }; - }; + channel@1 { + reg = <0x1>; + label = "Adjustable_voltage_ch1"; + }; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/flow/sensirion,slf3s.yaml b/Documentation/devicetree/bindings/iio/flow/sensirion,slf3s.yaml new file mode 100644 index 000000000000..79718f4f98bd --- /dev/null +++ b/Documentation/devicetree/bindings/iio/flow/sensirion,slf3s.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/flow/sensirion,slf3s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sensirion SLF3S liquid flow sensor + +maintainers: + - Wadim Mueller <wafgo01@gmail.com> + +description: + Family of digital liquid-flow sensors from Sensirion with I2C interface. All + family members share the same register map; sub-types differ only in the flow + scale factor and the calibrated measurement range. The sub-type can be + identified from the product-information register. + +properties: + compatible: + enum: + - sensirion,slf3s-0600f + - sensirion,slf3s-1300f + - sensirion,slf3s-4000b + + reg: + maxItems: 1 + + vdd-supply: true + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + flow-sensor@8 { + compatible = "sensirion,slf3s-0600f"; + reg = <0x08>; + vdd-supply = <®_3v3>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml new file mode 100644 index 000000000000..f4fae9210382 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf41513.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,adf41513.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADF41513 PLL Frequency Synthesizer + +maintainers: + - Rodrigo Alencar <rodrigo.alencar@analog.com> + +description: + The ADF41513 is an ultralow noise frequency synthesizer that can be used to + implement local oscillators (LOs) as high as 26.5 GHz in the upconversion and + downconversion sections of wireless receivers and transmitters. The ADF41510 + supports frequencies up to 10 GHz. + + https://www.analog.com/en/products/adf41510.html + https://www.analog.com/en/products/adf41513.html + +properties: + compatible: + enum: + - adi,adf41510 + - adi,adf41513 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + clocks: + maxItems: 1 + description: Clock that provides the reference input frequency. + + avdd1-supply: + description: PFD and Up and Down Digital Driver Power Supply (3.3 V) + + avdd2-supply: + description: RF Buffer and Prescaler Power Supply (3.3 V) + + avdd3-supply: + description: N Divider Power Supply (3.3 V) + + avdd4-supply: + description: R Divider and Lock Detector Power Supply (3.3 V) + + avdd5-supply: + description: Sigma-Delta Modulator and SPI Power Supply (3.3 V) + + vp-supply: + description: Charge Pump Power Supply (3.3 V) + + enable-gpios: + description: + GPIO that controls the chip enable pin. A logic low on this pin + powers down the device and puts the charge pump output into + three-state mode. + maxItems: 1 + + lock-detect-gpios: + description: + GPIO for lock detect functionality. When configured for digital lock + detect, this pin will output a logic high when the PLL is locked. + maxItems: 1 + + adi,power-up-frequency-mhz: + minimum: 1000 + maximum: 26500 + default: 10000 + description: + The PLL tunes to this frequency during the initialization sequence. + This property should be set to a frequency supported by the loop filter + and VCO used in the design. Range is 1 GHz to 26.5 GHz for ADF41513, + and 1 GHz to 10 GHz for ADF41510. + + adi,reference-div-factor: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + default: 1 + description: + Value for the reference division factor (R Counter). The driver will + increment R Counter as needed to achieve a PFD frequency within the + allowed range. High R counter values will reduce the PFD frequency, which + lowers the frequency resolution, and affects phase noise performance. + As it affects the PFD frequency, this value depends on the loop filter + design. + + adi,reference-doubler-enable: + description: + Enables the reference doubler when deriving the PFD frequency. + The maximum reference frequency when the doubler is enabled is 225 MHz. + As it affects the PFD frequency, this value depends on the loop filter + design. + type: boolean + + adi,reference-div2-enable: + description: + Enables the reference divide-by-2 function when deriving the PFD + frequency. As it affects the PFD frequency, this value depends on the + loop filter design. + type: boolean + + adi,charge-pump-resistor-ohms: + minimum: 1800 + maximum: 10000 + default: 2700 + description: + External charge pump resistor (R_SET) value in ohms. This sets the maximum + charge pump current along with the charge pump current setting. + + adi,charge-pump-current-microamp: + minimum: 81 + maximum: 7200 + description: + Charge pump current (I_CP) in microamps. The value will be rounded to the + nearest supported value. Range of acceptable values depends on the + charge pump resistor value, such that 810 mV <= I_CP * R_SET <= 12960 mV. + This value depends on the loop filter and the VCO design. + + adi,logic-level-1v8-enable: + description: + Set MUXOUT and DLD logic levels to 1.8V. Default is 3.3V. + type: boolean + + adi,phase-detector-polarity-positive-enable: + description: + Set phase detector polarity to positive. Default is negative. + Use positive polarity with non-inverting loop filter and VCO with + positive tuning slope, or with inverting loop filter and VCO with + negative tuning slope. + type: boolean + + adi,lock-detector-count: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 64 + description: + Sets the value for Lock Detector count of the PLL, which determines the + number of consecutive phase detector cycles that must be within the lock + detector window before lock is declared. Lower values increase the lock + detection sensitivity, while higher values provides a more stable lock + detection. Applications that consume the lock detect signal may require + different settings based on system requirements. + enum: [2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192] + + adi,phase-resync-period-ns: + default: 0 + description: + When this value is non-zero, enable phase resync functionality, which + produces a consistent output phase offset with respect to the input + reference. The value specifies the resync period in nanoseconds, used + to configure clock dividers with respect to the PFD frequency. This value + should be set to a value that is at least as long as the worst case lock + time, i.e., it depends mostly on the loop filter design. + + adi,le-sync-enable: + description: + Synchronizes Load Enable (LE) transitions with the reference signal to + avoid asynchronous glitches in the output. This is recommended when using + the PLL as a frequency synthesizer, where the reference signal will always + be present while the device is being configured. When using the PLL as a + frequency tracker, where the reference signal may be absent, LE sync + should be left disabled. + type: boolean + +dependencies: + adi,charge-pump-resistor-ohms: [ 'adi,charge-pump-current-microamp' ] + +required: + - compatible + - reg + - clocks + - avdd1-supply + - avdd2-supply + - avdd3-supply + - avdd4-supply + - avdd5-supply + - vp-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + const: adi,adf41510 + then: + properties: + adi,power-up-frequency-mhz: + maximum: 10000 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + pll@0 { + compatible = "adi,adf41513"; + reg = <0>; + spi-max-frequency = <25000000>; + clocks = <&ref_clk>; + avdd1-supply = <&avdd1_3v3>; + avdd2-supply = <&avdd2_3v3>; + avdd3-supply = <&avdd3_3v3>; + avdd4-supply = <&avdd4_3v3>; + avdd5-supply = <&avdd5_3v3>; + vp-supply = <&vp_3v3>; + enable-gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + lock-detect-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + + adi,power-up-frequency-mhz = <15500>; + adi,charge-pump-current-microamp = <3600>; + adi,charge-pump-resistor-ohms = <2700>; + adi,reference-doubler-enable; + adi,lock-detector-count = <64>; + adi,phase-resync-period-ns = <0>; + adi,phase-detector-polarity-positive-enable; + adi,le-sync-enable; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml b/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml index fcbd4b430e48..8e094651381c 100644 --- a/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml +++ b/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml @@ -26,6 +26,9 @@ properties: vdd-supply: true vddio-supply: true + mount-matrix: + description: an optional 3x3 mounting rotation matrix. + spi-max-frequency: maximum: 10000000 @@ -56,6 +59,9 @@ examples: reg = <0x69>; interrupt-parent = <&gpio6>; interrupts = <18 IRQ_TYPE_EDGE_RISING>; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "1"; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml index 119e28a833fd..81b6e85decd5 100644 --- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml @@ -30,6 +30,8 @@ properties: - invensense,icm42600 - invensense,icm42602 - invensense,icm42605 + - invensense,icm42607 + - invensense,icm42607p - invensense,icm42622 - invensense,icm42631 - invensense,icm42686 @@ -53,6 +55,8 @@ properties: drive-open-drain: type: boolean + mount-matrix: true + vdd-supply: description: Regulator that provides power to the sensor @@ -65,10 +69,24 @@ properties: required: - compatible - reg - - interrupts allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + enum: + - invensense,icm42600 + - invensense,icm42602 + - invensense,icm42605 + - invensense,icm42622 + - invensense,icm42631 + - invensense,icm42686 + - invensense,icm42688 + then: + required: + - interrupts unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/iio/light/brcm,apds9999.yaml b/Documentation/devicetree/bindings/iio/light/brcm,apds9999.yaml new file mode 100644 index 000000000000..9f5b3b294c2c --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/brcm,apds9999.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/brcm,apds9999.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: Broadcom APDS-9999 Digital Proximity and RGB Sensor + +maintainers: + - Jose A. Perez de Azpillaga <azpijr@gmail.com> + +description: | + Broadcom APDS-9999 is a digital proximity and RGB sensor with + ambient light sensing (ALS) capability. The device uses individual + R, G, B, and IR channels plus a Vertical Cavity Surface Emitting + Laser (VCSEL) for proximity detection. + + Datasheet: https://docs.broadcom.com/docs/APDS-9999-DS + +properties: + compatible: + enum: + - brcm,apds9999 + + reg: + maxItems: 1 + + vdd-supply: true + + vcsel-supply: + description: VCSEL power supply (VVCSEL pin) + + interrupts: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - vdd-supply + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@52 { + compatible = "brcm,apds9999"; + reg = <0x52>; + vdd-supply = <&vdd_reg>; + vcsel-supply = <&vcsel_reg>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/light/tsl2772.yaml b/Documentation/devicetree/bindings/iio/light/tsl2772.yaml index d81229857944..9921ccaa64a0 100644 --- a/Documentation/devicetree/bindings/iio/light/tsl2772.yaml +++ b/Documentation/devicetree/bindings/iio/light/tsl2772.yaml @@ -26,6 +26,8 @@ properties: - amstaos,tmd2672 - amstaos,tsl2772 - amstaos,tmd2772 + - avago,apds9900 + - avago,apds9901 - avago,apds9930 reg: diff --git a/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml b/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml index 4ea69f1fdd63..0041e1db6838 100644 --- a/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml +++ b/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/light/vishay,veml6030.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: VEML3235, VEML6030, VEML6035 and VEML7700 Ambient Light Sensors (ALS) +title: VEML3235, VEML3328, VEML6030, VEML6035 and VEML7700 Ambient Light Sensors (ALS) maintainers: - Rishi Gupta <gupt21@gmail.com> @@ -21,6 +21,7 @@ description: | Specifications about the sensors can be found at: https://www.vishay.com/docs/80131/veml3235.pdf + https://www.vishay.com/docs/84968/veml3328.pdf https://www.vishay.com/docs/84366/veml6030.pdf https://www.vishay.com/docs/84889/veml6035.pdf https://www.vishay.com/docs/84286/veml7700.pdf @@ -29,6 +30,7 @@ properties: compatible: enum: - vishay,veml3235 + - vishay,veml3328 - vishay,veml6030 - vishay,veml6035 - vishay,veml7700 @@ -79,6 +81,7 @@ allOf: compatible: enum: - vishay,veml3235 + - vishay,veml3328 - vishay,veml7700 then: properties: diff --git a/Documentation/devicetree/bindings/iio/magnetometer/memsic,mmc5983.yaml b/Documentation/devicetree/bindings/iio/magnetometer/memsic,mmc5983.yaml new file mode 100644 index 000000000000..4a4df6bb70fe --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/memsic,mmc5983.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/memsic,mmc5983.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MEMSIC MMC5983MA 3-axis magnetic sensor + +maintainers: + - Vladislav Kulikov <vlad.kulikov.c@gmail.com> + +properties: + compatible: + const: memsic,mmc5983 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the sensor + + vddio-supply: + description: Regulator that provides power to the digital interface and INT pin + +required: + - compatible + - reg + - vdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@30 { + compatible = "memsic,mmc5983"; + reg = <0x30>; + vdd-supply = <&vdd_3v3_reg>; + vddio-supply = <&vdd_3v3_reg>; + }; + }; + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@0 { + compatible = "memsic,mmc5983"; + reg = <0>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdd_3v3_reg>; + vddio-supply = <&vdd_3v3_reg>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/magnetometer/qstcorp,qmc5883l.yaml b/Documentation/devicetree/bindings/iio/magnetometer/qstcorp,qmc5883l.yaml new file mode 100644 index 000000000000..38abd083a4fb --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/qstcorp,qmc5883l.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/qstcorp,qmc5883l.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QST QMC5883L 3-Axis Magnetic Sensor + +maintainers: + - Siratul Islam <siratul.islam@linux.dev> + +description: | + QST QMC5883L 3-Axis Magnetic Sensor on I2C bus. + https://www.qstcorp.com/upload/pdf/202512/13-52-04%20QMC5883L%20Datasheet%20Rev.%20B.pdf + +properties: + compatible: + enum: + - qstcorp,qmc5883l + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: true + + vddio-supply: true + +additionalProperties: false + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@d { + compatible = "qstcorp,qmc5883l"; + reg = <0x0d>; + vdd-supply = <&vdd_3v3_reg>; + vddio-supply = <&vdd_3v3_reg>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/magnetometer/qstcorp,qmc6308.yaml b/Documentation/devicetree/bindings/iio/magnetometer/qstcorp,qmc6308.yaml new file mode 100644 index 000000000000..b7ab6decdfbc --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/qstcorp,qmc6308.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/qstcorp,qmc6308.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QST QMC6308 3-Axis Magnetic Sensor + +maintainers: + - Jorijn van der Graaf <jorijnvdgraaf@catcrafts.net> + +description: + QST QMC6308 3-axis anisotropic magnetoresistive (AMR) magnetic sensor + on I2C bus, with a single supply and no interrupt pin. + https://qstcorp.com/upload/pdf/202202/13-52-15%20QMC6308%20Datasheet%20Rev.%20F(1).pdf + +properties: + compatible: + const: qstcorp,qmc6308 + + reg: + maxItems: 1 + + vdd-supply: true + + mount-matrix: true + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@2c { + compatible = "qstcorp,qmc6308"; + reg = <0x2c>; + vdd-supply = <&vdd_1v8_reg>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml b/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml index f7f8be1e379d..d23dc59505cc 100644 --- a/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml +++ b/Documentation/devicetree/bindings/iio/proximity/st,vl53l0x.yaml @@ -8,7 +8,7 @@ title: ST VL53L0X/VL53L1X ToF ranging sensor maintainers: - Song Qiang <songqiang1304521@gmail.com> - - Siratul Islam <email@sirat.me> + - Siratul Islam <siratul.islam@linux.dev> properties: compatible: diff --git a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml index a22725f7619b..13e5f29f0588 100644 --- a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml @@ -4,14 +4,18 @@ $id: http://devicetree.org/schemas/iio/temperature/adi,ltc2983.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices LTC2983, LTC2986, LTM2985 Multi-sensor Temperature system +title: Analog Devices LTC2983 and similar Multi-sensor Temperature systems maintainers: - Nuno Sá <nuno.sa@analog.com> description: | - Analog Devices LTC2983, LTC2984, LTC2986, LTM2985 Multi-Sensor Digital - Temperature Measurement Systems + Analog Devices Multi-Sensor Digital Temperature Measurement Systems: + - ADT7604 + - LTC2983 + - LTC2984 + - LTC2986 + - LTM2985 https://www.analog.com/media/en/technical-documentation/data-sheets/2983fc.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/2984fb.pdf @@ -43,6 +47,7 @@ properties: compatible: oneOf: - enum: + - adi,adt7604 - adi,ltc2983 - adi,ltc2986 - adi,ltm2985 @@ -436,6 +441,121 @@ patternProperties: required: - adi,custom-temp + '^copper-trace@': + $ref: '#/$defs/sensor-node' + unevaluatedProperties: false + description: | + Copper trace resistance sensor (some parts only). Two variants exist: + sub-ohm (< 1 ohm, no custom table allowed) and standard (> 1 ohm, + required custom table). + + properties: + reg: + minimum: 2 + maximum: 20 + + adi,sensor-type: + description: Sensor type for copper trace sensors. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 32 + + adi,rsense-handle: + description: Associated sense resistor sensor. + $ref: /schemas/types.yaml#/definitions/phandle + + adi,copper-trace-sub-ohm: + description: + Select the sub-ohm (< 1 ohm) copper trace variant. Custom table + and excitation current are not allowed in this mode. + type: boolean + + adi,excitation-current-microamp: + description: + Excitation current applied to the copper trace. Not used in + sub-ohm mode. The datasheet recommends 1mA for copper trace + sensors due to their typically small resistance. + enum: [5, 10, 25, 50, 100, 250, 500, 1000] + default: 1000 + + adi,custom-copper-trace: + description: + Resistance-to-temperature table for copper trace sensors with + resistance > 1 ohm. Required when adi,copper-trace-sub-ohm is not + set. See Page 36 of the datasheet. + $ref: /schemas/types.yaml#/definitions/uint64-matrix + minItems: 3 + maxItems: 64 + items: + items: + - description: Resistance point in uOhms. + - description: Temperature point in uK. + + required: + - adi,rsense-handle + + allOf: + - if: + required: + - adi,copper-trace-sub-ohm + then: + properties: + adi,custom-copper-trace: false + adi,excitation-current-microamp: false + - if: + not: + required: + - adi,copper-trace-sub-ohm + then: + required: + - adi,custom-copper-trace + + '^leak-detector@': + $ref: '#/$defs/sensor-node' + unevaluatedProperties: false + description: | + Leak detector sensor (some parts only). Outputs resistance in ohms and + a coverage percentage via IIO_COVERAGE (raw/1024 = coverage %). + + properties: + reg: + minimum: 2 + maximum: 20 + + adi,sensor-type: + description: Sensor type for leak detector sensors. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 33 + + adi,rsense-handle: + description: Associated sense resistor sensor. + $ref: /schemas/types.yaml#/definitions/phandle + + adi,excitation-current-nanoamp: + description: + Excitation current applied to the leak detector. The correct value + depends on the electrical characteristics of the liquid being sensed. + For example, 10000 (10µA) is recommended for PG25 (see datasheet + Table 39). + enum: [250, 500, 1000, 5000, 10000, 25000, 50000, 100000, 250000, + 500000, 1000000] + + adi,custom-leak-detector: + description: | + Lookup table mapping resistance to coverage percentage. Entries must + be in ascending resistance order. + $ref: /schemas/types.yaml#/definitions/uint64-matrix + minItems: 3 + maxItems: 64 + items: + items: + - description: Resistance point in uOhms. + - description: Coverage data percentage (0 to 100). + + required: + - adi,rsense-handle + - adi,excitation-current-nanoamp + - adi,custom-leak-detector + '^rsense@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false @@ -477,6 +597,32 @@ allOf: patternProperties: '^temp@': false + - if: + properties: + compatible: + contains: + const: adi,adt7604 + then: + patternProperties: + '^thermocouple@': false + '^diode@': false + '^adc@': false + '^temp@': false + '^rtd@': + properties: + adi,sensor-type: + not: + const: 18 + '^thermistor@': + properties: + adi,sensor-type: + not: + const: 27 + else: + patternProperties: + '^copper-trace@': false + '^leak-detector@': false + examples: - | #include <dt-bindings/interrupt-controller/irq.h> @@ -556,4 +702,69 @@ examples: }; }; }; + + - | + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@0 { + compatible = "adi,adt7604"; + reg = <0>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&supply>; + + trace_rsense: rsense@2 { + reg = <2>; + adi,sensor-type = <29>; + adi,rsense-val-milli-ohms = <100000>; // 100 ohm + }; + + copper-trace@4 { + reg = <4>; + adi,sensor-type = <32>; + adi,rsense-handle = <&trace_rsense>; + adi,copper-trace-sub-ohm; + }; + + r_sense: rsense@12 { + reg = <12>; + adi,sensor-type = <29>; + adi,rsense-val-milli-ohms = <1000000>; // 1 kohm + }; + + leak-detector@14 { + reg = <14>; + adi,sensor-type = <33>; + adi,rsense-handle = <&r_sense>; + adi,excitation-current-nanoamp = <10000>; + adi,custom-leak-detector = + /bits/ 64 < 0 100>, + /bits/ 64 < 202020000 99>, + /bits/ 64 < 285710000 70>, + /bits/ 64 < 333330000 60>, + /bits/ 64 < 400000000 50>, + /bits/ 64 < 500000000 40>, + /bits/ 64 < 666670000 30>, + /bits/ 64 < 1000000000 20>, + /bits/ 64 < 2000000000 10>, + /bits/ 64 <1000000000000 0>; + }; + + rtd@18 { + reg = <18>; + adi,sensor-type = <12>; // PT100 + adi,rsense-handle = <&r_sense>; + adi,number-of-wires = <2>; + adi,rsense-share; + adi,excitation-current-microamp = <500>; + adi,rtd-curve = <0>; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml index fbba5e934861..7fb3e6820791 100644 --- a/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/ti,tmp117.yaml @@ -7,19 +7,25 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: TI TMP117 - Digital temperature sensor with integrated NV memory description: | - TI TMP116/117 - Digital temperature sensor with integrated NV memory that - supports I2C interface. + TI TMP116/117/119 - Digital temperature sensor with integrated NV memory + that supports I2C interface. https://www.ti.com/lit/gpn/tmp116 https://www.ti.com/lit/gpn/tmp117 + https://www.ti.com/lit/gpn/tmp119 maintainers: - Puranjay Mohan <puranjay12@gmail.com> properties: compatible: - enum: - - ti,tmp116 - - ti,tmp117 + oneOf: + - enum: + - ti,tmp116 + - ti,tmp117 + - items: + - enum: + - ti,tmp119 + - const: ti,tmp117 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml index 6bdb8040be65..524c8b51f53f 100644 --- a/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml +++ b/Documentation/devicetree/bindings/input/allwinner,sun4i-a10-lradc-keys.yaml @@ -23,6 +23,7 @@ properties: - const: allwinner,sun50i-r329-lradc - items: - enum: + - allwinner,sun50i-a100-lradc - allwinner,sun50i-h616-lradc - allwinner,sun20i-d1-lradc - const: allwinner,sun50i-r329-lradc diff --git a/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml b/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml index 9bf07acea599..26ea78df27c4 100644 --- a/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml +++ b/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml @@ -88,8 +88,7 @@ properties: - 2 # ATMEL_MXT_WAKEUP_GPIO default: 0 - wakeup-source: - type: boolean + wakeup-source: true required: - compatible diff --git a/Documentation/devicetree/bindings/input/focaltech,ft8112.yaml b/Documentation/devicetree/bindings/input/focaltech,ft8112.yaml index 197f30b14d45..5ffa1246aba1 100644 --- a/Documentation/devicetree/bindings/input/focaltech,ft8112.yaml +++ b/Documentation/devicetree/bindings/input/focaltech,ft8112.yaml @@ -18,8 +18,13 @@ allOf: properties: compatible: - enum: - - focaltech,ft8112 + oneOf: + - items: + - enum: + - focaltech,ft3d81 + - const: focaltech,ft8112 + - enum: + - focaltech,ft8112 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/input/fsl,scu-key.yaml b/Documentation/devicetree/bindings/input/fsl,scu-key.yaml index 29921aab9d97..2566cffc252d 100644 --- a/Documentation/devicetree/bindings/input/fsl,scu-key.yaml +++ b/Documentation/devicetree/bindings/input/fsl,scu-key.yaml @@ -18,7 +18,9 @@ allOf: properties: compatible: items: - - const: fsl,imx8qxp-sc-key + - enum: + - fsl,imx8qm-sc-key + - fsl,imx8qxp-sc-key - const: fsl,imx-sc-key linux,keycodes: diff --git a/Documentation/devicetree/bindings/input/gpio-charlieplex-keypad.yaml b/Documentation/devicetree/bindings/input/gpio-charlieplex-keypad.yaml index c085de6dab85..c6842c017934 100644 --- a/Documentation/devicetree/bindings/input/gpio-charlieplex-keypad.yaml +++ b/Documentation/devicetree/bindings/input/gpio-charlieplex-keypad.yaml @@ -11,7 +11,7 @@ maintainers: - Hugo Villeneuve <hvilleneuve@dimonoff.com> description: | - The charlieplex keypad supports N^2)-N different key combinations (where N is + The charlieplex keypad supports (N^2)-N different key combinations (where N is the number of I/O lines). Key presses and releases are detected by configuring only one line as output at a time, and reading other line states. This process is repeated for each line. Diodes are required to ensure current flows in only diff --git a/Documentation/devicetree/bindings/input/imagis,isa1200.yaml b/Documentation/devicetree/bindings/input/imagis,isa1200.yaml new file mode 100644 index 000000000000..4bc8630edcdd --- /dev/null +++ b/Documentation/devicetree/bindings/input/imagis,isa1200.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/imagis,isa1200.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagis ISA1200 haptic motor driver + +maintainers: + - Svyatoslav Ryhel <clamor95@gmail.com> + - Linus Walleij <linusw@kernel.org> + +description: + The ISA1200 is a high-performance enhanced haptic motor driver designed + for mobile hand-held devices. It supports various voltages for both ERM + (Eccentric Rotating Mass) and LRA (Linear Resonant Actuator) type + actuators. Thanks to an embedded LDO, battery power can be used directly + in handheld applications. + +properties: + compatible: + const: imagis,isa1200 + + reg: + maxItems: 1 + + control-gpios: + description: + One or two GPIOs flagged as active high linked to HEN and LEN pins + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + pwms: + maxItems: 1 + + vdd-supply: + description: + Regulator for 2.4V - 5.5V power supply + + vddp-supply: + description: + Regulator for 2.4V - 3.6V IO power supply + + imagis,clk-div: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Divider for the external input clock/PWM + enum: [128, 256, 512, 1024] + default: 128 + + imagis,pll-div: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Divider for the internal PLL clock + minimum: 1 + maximum: 15 + default: 1 + + imagis,mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Defines the motor type isa1200 drives + 0 - LRA (Linear Resonant Actuator) + 1 - ERM (Eccentric Rotating Mass) + enum: [0, 1] + default: 0 + + imagis,period-ns: + description: + Period of the internal PWM channel in nanoseconds. + minimum: 10000 + maximum: 30000 + + imagis,duty-cycle-ns: + description: + Duty cycle of the external/internal PWM channel in nanoseconds, + defaults to 50% of the channel's period + + ldo: + $ref: /schemas/regulator/regulator.yaml# + type: object + description: + Embedded LDO regulator with voltage range 2.3V - 3.8V + unevaluatedProperties: false + + required: + - regulator-min-microvolt + - regulator-max-microvolt + +required: + - compatible + - reg + - ldo + +oneOf: + - required: + - clocks + - imagis,period-ns + - required: + - pwms + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + haptic-engine@49 { + compatible = "imagis,isa1200"; + reg = <0x49>; + + clocks = <&isa1200_refclk>; + + control-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>, + <&gpio 23 GPIO_ACTIVE_HIGH>; + + vdd-supply = <&vdd_3v3_vbat>; + vddp-supply = <&vdd_2v8_vvib>; + + imagis,clk-div = <256>; + imagis,pll-div = <2>; + + imagis,mode = <0>; /* LRA_MODE */ + + imagis,period-ns = <13400>; + imagis,duty-cycle-ns = <100>; + + ldo { + regulator-name = "vdd_vib"; + regulator-min-microvolt = <2300000>; + regulator-max-microvolt = <2300000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/input/imx-keypad.yaml b/Documentation/devicetree/bindings/input/imx-keypad.yaml index b110eb1f3358..175256cb1295 100644 --- a/Documentation/devicetree/bindings/input/imx-keypad.yaml +++ b/Documentation/devicetree/bindings/input/imx-keypad.yaml @@ -66,20 +66,20 @@ examples: clocks = <&clks 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_kpp_1>; - linux,keymap = <0x00000067 /* KEY_UP */ - 0x0001006c /* KEY_DOWN */ - 0x00020072 /* KEY_VOLUMEDOWN */ - 0x00030066 /* KEY_HOME */ - 0x0100006a /* KEY_RIGHT */ - 0x01010069 /* KEY_LEFT */ - 0x0102001c /* KEY_ENTER */ - 0x01030073 /* KEY_VOLUMEUP */ - 0x02000040 /* KEY_F6 */ - 0x02010042 /* KEY_F8 */ - 0x02020043 /* KEY_F9 */ - 0x02030044 /* KEY_F10 */ - 0x0300003b /* KEY_F1 */ - 0x0301003c /* KEY_F2 */ - 0x0302003d /* KEY_F3 */ - 0x03030074>; /* KEY_POWER */ + linux,keymap = <0x00000067 /* KEY_UP */ + 0x0001006c /* KEY_DOWN */ + 0x00020072 /* KEY_VOLUMEDOWN */ + 0x00030066 /* KEY_HOME */ + 0x0100006a /* KEY_RIGHT */ + 0x01010069 /* KEY_LEFT */ + 0x0102001c /* KEY_ENTER */ + 0x01030073 /* KEY_VOLUMEUP */ + 0x02000040 /* KEY_F6 */ + 0x02010042 /* KEY_F8 */ + 0x02020043 /* KEY_F9 */ + 0x02030044 /* KEY_F10 */ + 0x0300003b /* KEY_F1 */ + 0x0301003c /* KEY_F2 */ + 0x0302003d /* KEY_F3 */ + 0x03030074>; /* KEY_POWER */ }; diff --git a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml index 914dd3283df3..20fa41f691ed 100644 --- a/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,mt6779-keypad.yaml @@ -26,6 +26,7 @@ properties: - const: mediatek,mt6779-keypad - items: - enum: + - mediatek,mt6572-keypad - mediatek,mt6873-keypad - mediatek,mt8183-keypad - mediatek,mt8365-keypad diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index b95435bd6a9b..140a862ecfbe 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -23,14 +23,19 @@ description: | properties: compatible: - enum: - - mediatek,mt6323-keys - - mediatek,mt6328-keys - - mediatek,mt6331-keys - - mediatek,mt6357-keys - - mediatek,mt6358-keys - - mediatek,mt6359-keys - - mediatek,mt6397-keys + oneOf: + - enum: + - mediatek,mt6323-keys + - mediatek,mt6328-keys + - mediatek,mt6331-keys + - mediatek,mt6357-keys + - mediatek,mt6358-keys + - mediatek,mt6359-keys + - mediatek,mt6397-keys + - items: + - enum: + - mediatek,mt6365-keys + - const: mediatek,mt6359-keys power-off-time-sec: true diff --git a/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml b/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml index 7ade03f1b32b..983f4701b51e 100644 --- a/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml +++ b/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml @@ -10,6 +10,16 @@ description: | The Microchip CAP1xxx Family of RightTouchTM multiple-channel capacitive touch controllers and LED drivers. The device communication via I2C only. + For more product information please see the links below: + CAP1106: https://ww1.microchip.com/downloads/en/DeviceDoc/00001624B.pdf + CAP1114: https://ww1.microchip.com/downloads/en/DeviceDoc/00002444A.pdf + CAP1126: https://ww1.microchip.com/downloads/en/DeviceDoc/00001623B.pdf + CAP1188: https://ww1.microchip.com/downloads/en/DeviceDoc/00001620C.pdf + CAP1203: https://ww1.microchip.com/downloads/en/DeviceDoc/00001572B.pdf + CAP1206: https://ww1.microchip.com/downloads/en/DeviceDoc/00001567B.pdf + CAP1293: https://ww1.microchip.com/downloads/en/DeviceDoc/00001566B.pdf + CAP1298: https://ww1.microchip.com/downloads/en/DeviceDoc/00001571B.pdf + maintainers: - Rob Herring <robh@kernel.org> @@ -17,6 +27,7 @@ properties: compatible: enum: - microchip,cap1106 + - microchip,cap1114 - microchip,cap1126 - microchip,cap1188 - microchip,cap1203 @@ -40,13 +51,20 @@ properties: device's ALERT#/CM_IRQ# pin is connected to. The device only has one interrupt source. + reset-gpios: + description: | + GPIO connected to the active-high RESET pin of the chip; + driving it high asserts reset and deep sleep, while driving + it low releases reset for normal operation. + maxItems: 1 + autorepeat: description: | Enables the Linux input system's autorepeat feature on the input device. linux,keycodes: minItems: 3 - maxItems: 8 + maxItems: 14 description: | Specifies an array of numeric keycode values to be used for the channels. If this property is @@ -106,6 +124,8 @@ properties: is required for a touch to be registered, making the touch sensor less sensitive. The number of entries must correspond to the number of channels. + CAP1114 is an exception where channels 8~14 reuse the eighth entry's + threshold, so counts differ. microchip,calib-sensitivity: $ref: /schemas/types.yaml#/definitions/uint32-array @@ -124,14 +144,16 @@ properties: The number of entries must correspond to the number of channels. patternProperties: - "^led@[0-7]$": + "^led@[0-9a]$": type: object description: CAP11xx LEDs $ref: /schemas/leds/common.yaml# properties: reg: - enum: [0, 1, 2, 3, 4, 5, 6, 7] + description: LED channel number + minimum: 0 + maximum: 10 label: true @@ -157,8 +179,63 @@ allOf: - microchip,cap1293 - microchip,cap1298 then: + properties: + reset-gpios: false + + - if: + properties: + compatible: + contains: + enum: + - microchip,cap1114 + then: + properties: + linux,keycodes: + minItems: 14 + else: + properties: + linux,keycodes: + maxItems: 8 + + - if: + properties: + compatible: + contains: + enum: + - microchip,cap1106 + - microchip,cap1203 + - microchip,cap1206 + - microchip,cap1293 + - microchip,cap1298 + then: + patternProperties: + "^led@": false + + - if: + properties: + compatible: + contains: + enum: + - microchip,cap1126 + then: patternProperties: - "^led@[0-7]$": false + "^led@": + properties: + reg: + maximum: 1 + + - if: + properties: + compatible: + contains: + enum: + - microchip,cap1188 + then: + patternProperties: + "^led@": + properties: + reg: + maximum: 7 - if: properties: @@ -166,6 +243,7 @@ allOf: contains: enum: - microchip,cap1106 + - microchip,cap1114 - microchip,cap1126 - microchip,cap1188 - microchip,cap1203 @@ -183,6 +261,8 @@ additionalProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> + i2c { #address-cells = <1>; #size-cells = <0>; @@ -197,12 +277,14 @@ examples: microchip,sensitivity-delta-sense = <16>; microchip,input-threshold = <21>, <18>, <46>, <46>, <46>, <21>; - linux,keycodes = <103>, /* KEY_UP */ - <106>, /* KEY_RIGHT */ - <108>, /* KEY_DOWN */ - <105>, /* KEY_LEFT */ - <109>, /* KEY_PAGEDOWN */ - <104>; /* KEY_PAGEUP */ + linux,keycodes = <103>, /* KEY_UP */ + <106>, /* KEY_RIGHT */ + <108>, /* KEY_DOWN */ + <105>, /* KEY_LEFT */ + <109>, /* KEY_PAGEDOWN */ + <104>; /* KEY_PAGEUP */ + + reset-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/input/qcom,spmi-haptics.yaml b/Documentation/devicetree/bindings/input/qcom,spmi-haptics.yaml new file mode 100644 index 000000000000..e6cdaed9ce5b --- /dev/null +++ b/Documentation/devicetree/bindings/input/qcom,spmi-haptics.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/qcom,spmi-haptics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Haptics device inside Qualcomm Technologies, Inc. PMIC + +maintainers: + - Fenglin Wu <fenglin.wu@oss.qualcomm.com> + +description: | + Certain Qualcomm PMICs integrate a haptics module, such as the HAP530_HV haptics + module in the PMIH0108 PMIC, which drives an LRA (Linear Resonant Actuator) with + an output voltage up to 10 V. Several play modes are supported in HAP530_HV: + + DIRECT_PLAY: The hardware outputs sinusoidal waveforms whose period is + defined by qcom,lra-period-us and whose peak voltage is defined by + qcom,vmax-microvolt. The driving amplitude can be scaled in the range + [0, 255] via a single register byte. Hardware-based LRA auto-resonance + tracking is enabled by default in this mode, allowing the haptics engine + to follow the actual resonant frequency of the LRA and update the driving + period accordingly to achieve stronger vibration magnitude. + + FIFO: The hardware can play an arbitrary waveform composed of a sequence + of 8-bit samples at a configurable play rate. Samples are pre-filled + into the internal FIFO memory of the haptics module and continuously + replenished via the FIFO-empty IRQ until all samples have been played. + An 8K-byte FIFO memory bank is available in the HAP530_HV haptics module, + shared between the FIFO and PAT_MEM play modes. The memory partition + between the two modes is configurable via registers, and FIFO mode always + uses the 1st partition starting from offset 0. + + PAT_MEM: This mode is very similar to FIFO streaming mode but without the + data refilling capability. It is designed mainly for short, latency-critical + vibrations. The memory space for PAT_MEM mode must be reserved for dedicated + usage, and the waveform data should be preloaded and remain unchanged + thereafter. The haptics module can play the waveform data from the memory + region specified by the PAT_MEM play start address and length registers. + + In either FIFO mode or PAT_MEM mode, the following play rates are supported: + -- 0(T_LRA): each FIFO byte drives one full sinusoidal cycle with the + period defined in qcom,lra-period-us. + -- 1/2/3(T_LRA_DIV_2/4/8): each FIFO byte drives a half/quarter/eighth + sinusoidal cycle with the period defined in qcom,lra-period-us. + -- 4/5/6(T_LRA_X_2/4/8): each FIFO byte drives 2/4/8 sinusoidal cycles + with the period defined in qcom,lra-period-us. + -- 8/9/10/11/12/13(8KHz/16KHz/24KHz/32KHz/44.1KHz/48KHz): the FIFO + data is treated as PCM samples and drives the output with an + arbitrarily shaped waveform. This mode is typically used to define + custom driving waveforms for specific vibration effects such as fast + attack, crisp brake, etc. + + The drive voltage in FIFO or PAT_MEM mode can exceed the value defined in + qcom,vmax-microvolt to achieve a special vibration effect, but the waveform + must be short enough to prevent the LRA from being damaged by operating at + an overvoltage. + + Also, hardware-based LRA auto-resonance tracking is normally disabled in + FIFO or PAT_MEM mode, as these modes are intended to drive arbitrary + waveforms that may not follow the resonant frequency; autonomous hardware + resonance correction would interfere with the intended output. + +properties: + compatible: + items: + - const: qcom,pmih0108-haptics + - const: qcom,spmi-haptics + + reg: + items: + - description: HAP_CFG module base address + - description: HAP_PTN module base address + + reg-names: + items: + - const: cfg + - const: ptn + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: fifo-empty + + qcom,vmax-microvolt: + description: + Maximum allowed output driving voltage in microvolts, must be a multiple + of 50,000 uV. This is the peak driving voltage in DIRECT_PLAY mode, + which outputs sinusoidal waveforms. The value should be equal to the + square root of 2 times the Vrms voltage of the LRA. + minimum: 50000 + maximum: 10000000 + multipleOf: 50000 + + qcom,lra-period-us: + description: + LRA actuator initial resonance period in microseconds + (1,000,000 / resonant_freq_hz). Used to configure T_LRA-based play + rates and the auto-resonance zero-crossing window. It could be also used + as the initial period if the LRA wants to be driven off resonance. + minimum: 5 + maximum: 20475 + multipleOf: 5 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - qcom,vmax-microvolt + - qcom,lra-period-us + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/input/syna,rmi4.yaml b/Documentation/devicetree/bindings/input/syna,rmi4.yaml index 8685ef4481f4..fb4804ac3544 100644 --- a/Documentation/devicetree/bindings/input/syna,rmi4.yaml +++ b/Documentation/devicetree/bindings/input/syna,rmi4.yaml @@ -18,9 +18,14 @@ description: | properties: compatible: - enum: - - syna,rmi4-i2c - - syna,rmi4-spi + oneOf: + - enum: + - syna,rmi4-i2c + - syna,rmi4-spi + - items: + - enum: + - syna,rmi4-s3706b # OnePlus 6/6T + - const: syna,rmi4-i2c reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/input/ti,tps65217-pwrbutton.yaml b/Documentation/devicetree/bindings/input/ti,tps65217-pwrbutton.yaml new file mode 100644 index 000000000000..3526d8b045fd --- /dev/null +++ b/Documentation/devicetree/bindings/input/ti,tps65217-pwrbutton.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/ti,tps65217-pwrbutton.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TPS65217 and TPS65218 Power Button + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +description: + This module is part of the TPS65217/TPS65218 PMIC. It provides a simple + power button event via an interrupt. + +properties: + compatible: + enum: + - ti,tps65217-pwrbutton + - ti,tps65218-pwrbutton + + interrupts: + maxItems: 1 + +required: + - compatible + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + pmic { + #address-cells = <1>; + #size-cells = <0>; + + power-button { + compatible = "ti,tps65218-pwrbutton"; + interrupts = <3 IRQ_TYPE_EDGE_BOTH>; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml index 12256ae7df90..64c4f24ea3dd 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml @@ -40,6 +40,10 @@ properties: vdd-supply: description: Power supply + reset-gpios: + description: Reset GPIO (active-low) + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml b/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml index 8f6335d7da1c..1b58fc263dce 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml @@ -165,9 +165,9 @@ examples: touchscreen@0 { compatible = "ti,tsc2046"; - reg = <0>; /* CS0 */ + reg = <0>; /* CS0 */ interrupt-parent = <&gpio1>; - interrupts = <8 0>; /* BOOT6 / GPIO 8 */ + interrupts = <8 0>; /* BOOT6 / GPIO 8 */ pendown-gpio = <&gpio1 8 0>; spi-max-frequency = <1000000>; vcc-supply = <®_vcc3>; diff --git a/Documentation/devicetree/bindings/input/touchscreen/wacom,w9007a-lt03.yaml b/Documentation/devicetree/bindings/input/touchscreen/wacom,w9007a-lt03.yaml new file mode 100644 index 000000000000..6d1da6a435d3 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/wacom,w9007a-lt03.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/wacom,w9007a-lt03.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wacom W9000-series penabled I2C touchscreen + +maintainers: + - Hendrik Noack <hendrik-noack@gmx.de> + +description: | + The W9000-series are penabled touchscreen controllers by Wacom. + + The firmware of controllers in different devices may differ. This can also + affect the controller's behavior. + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - wacom,w9002 + - wacom,w9007a-lt03 + - wacom,w9007a-v1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: true + + flash-mode-gpios: + maxItems: 1 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + digitizer@56 { + compatible = "wacom,w9007a-lt03"; + reg = <0x56>; + interrupt-parent = <&gpd1>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&stylus_reg>; + + flash-mode-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; + + touchscreen-x-mm = <216>; + touchscreen-y-mm = <135>; + touchscreen-inverted-x; + }; + }; diff --git a/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt b/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt deleted file mode 100644 index 8682ab6d4a50..000000000000 --- a/Documentation/devicetree/bindings/input/tps65218-pwrbutton.txt +++ /dev/null @@ -1,30 +0,0 @@ -Texas Instruments TPS65217 and TPS65218 power button - -This module is part of the TPS65217/TPS65218. For more details about the whole -TPS65217 chip see Documentation/devicetree/bindings/regulator/tps65217.txt. - -This driver provides a simple power button event via an Interrupt. - -Required properties: -- compatible: should be "ti,tps65217-pwrbutton" or "ti,tps65218-pwrbutton" - -Required properties: -- interrupts: should be one of the following - - <2>: For controllers compatible with tps65217 - - <3 IRQ_TYPE_EDGE_BOTH>: For controllers compatible with tps65218 - -Examples: - -&tps { - tps65217-pwrbutton { - compatible = "ti,tps65217-pwrbutton"; - interrupts = <2>; - }; -}; - -&tps { - power-button { - compatible = "ti,tps65218-pwrbutton"; - interrupts = <3 IRQ_TYPE_EDGE_BOTH>; - }; -}; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml new file mode 100644 index 000000000000..49a2dca5db62 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,hawi-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Hawi + +maintainers: + - Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,hawi-rpmh.h + +properties: + compatible: + enum: + - qcom,hawi-aggre1-noc + - qcom,hawi-clk-virt + - qcom,hawi-cnoc-main + - qcom,hawi-gem-noc + - qcom,hawi-llclpi-noc + - qcom,hawi-lpass-ag-noc + - qcom,hawi-lpass-lpiaon-noc + - qcom,hawi-lpass-lpicx-noc + - qcom,hawi-mc-virt + - qcom,hawi-mmss-noc + - qcom,hawi-nsp-noc + - qcom,hawi-pcie-anoc + - qcom,hawi-stdst-cfg + - qcom,hawi-stdst-main + - qcom,hawi-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-clk-virt + - qcom,hawi-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-aggre1-noc + - qcom,hawi-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clk_virt: interconnect-0 { + compatible = "qcom,hawi-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@f00000 { + compatible = "qcom,hawi-aggre1-noc"; + reg = <0x0 0xf00000 0x0 0x54400>; + #interconnect-cells = <2>; + clocks = <&gcc_aggre_ufs_phy_axi_clk>, + <&gcc_aggre_usb3_prim_axi_clk>, + <&rpmhcc_ipa_clk>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml new file mode 100644 index 000000000000..3db8d8b23219 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,maili-rpmh.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,maili-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Maili SoC + +maintainers: + - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,maili-rpmh.h + +properties: + compatible: + enum: + - qcom,maili-aggre-noc + - qcom,maili-clk-virt + - qcom,maili-cnoc-main + - qcom,maili-gem-noc + - qcom,maili-llclpi-noc + - qcom,maili-lpass-ag-noc + - qcom,maili-lpass-lpiaon-noc + - qcom,maili-lpass-lpicx-noc + - qcom,maili-mc-virt + - qcom,maili-mmss-noc + - qcom,maili-nsp-noc + - qcom,maili-pcie-anoc + - qcom,maili-stdst-cfg + - qcom,maili-stdst-main + - qcom,maili-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,maili-clk-virt + - qcom,maili-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,maili-aggre-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,maili-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,maili-aggre-noc + - qcom,maili-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + gem_noc: interconnect@31100000 { + compatible = "qcom,maili-gem-noc"; + reg = <0x31100000 0x160200>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@f00000 { + compatible = "qcom,maili-aggre-noc"; + reg = <0x00f00000 0x56200>; + #interconnect-cells = <2>; + clocks = <&gcc_phy_axi_clk>, + <&gcc_prim_axi_clk>, + <&rpmhcc_ipa_clk>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index ce79521bb1ef..21b4e04727de 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -13,7 +13,7 @@ description: | Bandwidth Monitor measures current throughput on buses between various NoC fabrics and provides information when it crosses configured thresholds. - Certain SoCs might have more than one Bandwidth Monitors, for example on SDM845:: + Certain SoCs might have more than one Bandwidth Monitors, for example on SDM845: - Measuring the bandwidth between CPUs and Last Level Cache Controller - called just BWMON, - Measuring the bandwidth between Last Level Cache Controller and memory @@ -25,8 +25,11 @@ properties: - const: qcom,msm8998-bwmon # BWMON v4 - items: - enum: + - qcom,eliza-cpu-bwmon - qcom,glymur-cpu-bwmon + - qcom,hawi-cpu-bwmon - qcom,kaanapali-cpu-bwmon + - qcom,maili-cpu-bwmon - qcom,qcm2290-cpu-bwmon - qcom,qcs615-cpu-bwmon - qcom,qcs8300-cpu-bwmon @@ -45,11 +48,14 @@ properties: - const: qcom,sdm845-bwmon # BWMON v4, unified register space - items: - enum: + - qcom,eliza-llcc-bwmon + - qcom,hawi-llcc-bwmon - qcom,qcs615-llcc-bwmon - qcom,qcs8300-llcc-bwmon - qcom,sa8775p-llcc-bwmon - qcom,sc7180-llcc-bwmon - qcom,sc8280xp-llcc-bwmon + - qcom,shikra-cpu-bwmon - qcom,sm6350-cpu-bwmon - qcom,sm8250-llcc-bwmon - qcom,sm8550-llcc-bwmon diff --git a/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml new file mode 100644 index 000000000000..3650d3d5b918 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,nord-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Nord + +maintainers: + - Odelu Kukatla <odelu.kukatla@oss.qualcomm.com> + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,nord-rpmh.h + +properties: + compatible: + enum: + - qcom,nord-aggre1-noc + - qcom,nord-aggre1-noc-tile + - qcom,nord-aggre2-noc + - qcom,nord-aggre2-noc-tile + - qcom,nord-clk-virt + - qcom,nord-cnoc-cfg + - qcom,nord-cnoc-main + - qcom,nord-hpass-ag-noc + - qcom,nord-hscnoc + - qcom,nord-mc-virt + - qcom,nord-mmss-noc + - qcom,nord-nsp-data-noc-0 + - qcom,nord-nsp-data-noc-1 + - qcom,nord-nsp-data-noc-2 + - qcom,nord-nsp-data-noc-3 + - qcom,nord-pcie-cfg + - qcom,nord-pcie-data-inbound + - qcom,nord-pcie-data-outbound + - qcom,nord-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-clk-virt + - qcom,nord-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre1-noc-tile + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB2 AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre1-noc-tile + - qcom,nord-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + clk_virt: interconnect-clk-virt { + compatible = "qcom,nord-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc_tile: interconnect@1720000 { + compatible = "qcom,nord-aggre1-noc-tile"; + reg = <0x01720000 0x23400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&ne_gcc_aggre_noc_ufs_phy_axi_clk>, + <&ne_gcc_aggre_noc_usb2_axi_clk>, + <&ne_gcc_aggre_noc_usb3_prim_axi_clk>, + <&ne_gcc_aggre_noc_usb3_sec_axi_clk>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 41b9f758bf8b..3b8ebe17a976 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -17,6 +17,8 @@ description: properties: compatible: oneOf: + - enum: + - qcom,shikra-epss-l3 - items: - enum: - qcom,sc7180-osm-l3 diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml index 2a5a7594bafd..cd327a3bf3b9 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sc8280xp-rpmh.yaml @@ -32,18 +32,115 @@ properties: - qcom,sc8280xp-nspb-noc - qcom,sc8280xp-system-noc + reg: + maxItems: 1 + + clocks: + minItems: 7 + maxItems: 8 + required: - compatible allOf: - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-clk-virt + - qcom,sc8280xp-mc-virt + then: + properties: + reg: false + clocks: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + - description: aggre USB3 MP AXI clock + - description: aggre USB4 AXI clock + - description: aggre USB4 1 AXI clock + - description: aggre USB NOC SOUTH AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre2-noc + then: + properties: + clocks: + items: + - description: aggre NOC PCIE0 tunnel AXI clock + - description: aggre NOC PCIE1 tunnel AXI clock + - description: aggre NOC PCIE 4 AXI clock + - description: aggre NOC PCIE SOUTH SF AXI clock + - description: aggre UFS CARD AXI clock + - description: DDRSS GPU AXI clock + - description: DDRSS PCIE SF TBU clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-aggre1-noc + - qcom,sc8280xp-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false unevaluatedProperties: false examples: - | - interconnect-0 { + #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + interconnect { + compatible = "qcom,sc8280xp-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + interconnect@9100000 { + compatible = "qcom,sc8280xp-gem-noc"; + reg = <0x9100000 0xb8400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + interconnect@16c0000 { compatible = "qcom,sc8280xp-aggre1-noc"; + reg = <0x16c0000 0x3af80>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_AXI_CLK>, + <&gcc GCC_AGGRE_USB4_1_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&rpmhcc RPMH_IPA_CLK>; }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml index 8f6bc6399626..51428a2b0ce0 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml @@ -79,6 +79,19 @@ allOf: - const: aggre2_usb3_axi - const: cfg_noc_usb2_axi + - if: + properties: + compatible: + enum: + - qcom,sdm660-bimc + - qcom,sdm660-cnoc + - qcom,sdm660-gnoc + - qcom,sdm660-snoc + then: + properties: + clocks: false + clock-names: false + examples: - | #include <dt-bindings/clock/qcom,gcc-sdm660.h> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml new file mode 100644 index 000000000000..a0c26de94ccf --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,shikra.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra Network-On-Chip interconnect + +maintainers: + - Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> + +description: + The Qualcomm Shikra interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,shikra-config-noc + - qcom,shikra-mem-noc-core + - qcom,shikra-sys-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + $ref: qcom,rpm-common.yaml# + + properties: + compatible: + enum: + - qcom,shikra-clk-virt + - qcom,shikra-mc-virt + - qcom,shikra-mmrt-virt + - qcom,shikra-mmnrt-virt + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: qcom,rpm-common.yaml# + - if: + properties: + compatible: + const: qcom,shikra-mem-noc-core + + then: + properties: + clocks: + items: + - description: GPU-NoC AXI clock + + clock-names: + items: + - const: gpu_axi + patternProperties: + '^interconnect-[a-z0-9]+$': false + + - if: + properties: + compatible: + const: qcom,shikra-sys-noc + + then: + properties: + clocks: + items: + - description: EMAC0-NoC AXI clock. + - description: EMAC1-NoC AXI clock. + - description: USB2-NoC AXI clock. + - description: USB3-NoC AXI clock. + + clock-names: + items: + - const: emac0_axi + - const: emac1_axi + - const: usb2_axi + - const: usb3_axi + + - if: + properties: + compatible: + const: qcom,shikra-config-noc + + then: + properties: + clocks: false + clock-names: false + patternProperties: + '^interconnect-[a-z0-9]+$': false + +unevaluatedProperties: false + +examples: + - | + interconnect@1880000 { + compatible = "qcom,shikra-sys-noc"; + reg = <0x01880000 0x6a080>; + #interconnect-cells = <2>; + clocks = <&gcc_emac0_axi_sys_noc_clk>, + <&gcc_emac1_axi_sys_noc_clk>, + <&gcc_sys_noc_usb2_prim_axi_clk>, + <&gcc_sys_noc_usb3_prim_axi_clk>; + clock-names = "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi"; + + interconnect-clk { + compatible = "qcom,shikra-clk-virt"; + #interconnect-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml index 14b1a0b08e73..cdae0acf3a1d 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml @@ -62,23 +62,33 @@ allOf: - if: properties: compatible: - const: qcom,sm6115-cnoc + const: qcom,sm6115-bimc + then: + properties: + clocks: false + clock-names: false + patternProperties: + '^interconnect-[a-z0-9]+$': false + - if: + properties: + compatible: + const: qcom,sm6115-cnoc then: properties: clocks: items: - description: USB-NoC AXI clock - clock-names: items: - const: usb_axi + patternProperties: + '^interconnect-[a-z0-9]+$': false - if: properties: compatible: const: qcom,sm6115-snoc - then: properties: clocks: @@ -87,7 +97,6 @@ allOf: - description: UFS-NoC AXI clock. - description: USB-NoC AXI clock. - description: IPA clock. - clock-names: items: - const: cpu_axi @@ -95,20 +104,6 @@ allOf: - const: usb_axi - const: ipa - - if: - properties: - compatible: - enum: - - qcom,sm6115-bimc - - qcom,sm6115-clk-virt - - qcom,sm6115-mmrt-virt - - qcom,sm6115-mmnrt-virt - - then: - properties: - clocks: false - clock-names: false - unevaluatedProperties: false examples: @@ -149,4 +144,6 @@ examples: compatible = "qcom,sm6115-cnoc"; reg = <0x01900000 0x8200>; #interconnect-cells = <1>; + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; + clock-names = "usb_axi"; }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml index 0840b0ec6e27..d863cddb21ac 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,x1e80100-rpmh.yaml @@ -46,6 +46,10 @@ properties: reg: maxItems: 1 + clocks: + minItems: 1 + maxItems: 6 + required: - compatible @@ -65,6 +69,73 @@ allOf: required: - reg + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-usb-north-anoc + then: + properties: + clocks: + items: + - description: aggre USB2 PRIM AXI clock + - description: aggre USB3 MP AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-usb-south-anoc + then: + properties: + clocks: + items: + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + - description: aggre USB3 TERT AXI clock + - description: aggre USB4_0 AXI clock + - description: aggre USB4_1 AXI clock + - description: aggre USB4_2 AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-aggre2-noc + - qcom,x1e80100-clk-virt + - qcom,x1e80100-cnoc-cfg + - qcom,x1e80100-cnoc-main + - qcom,x1e80100-gem-noc + - qcom,x1e80100-lpass-ag-noc + - qcom,x1e80100-lpass-lpiaon-noc + - qcom,x1e80100-lpass-lpicx-noc + - qcom,x1e80100-mc-virt + - qcom,x1e80100-mmss-noc + - qcom,x1e80100-nsp-noc + - qcom,x1e80100-pcie-center-anoc + - qcom,x1e80100-pcie-north-anoc + - qcom,x1e80100-pcie-south-anoc + - qcom,x1e80100-system-noc + - qcom,x1e80100-usb-center-anoc + then: + properties: + clocks: false + unevaluatedProperties: false examples: @@ -80,4 +151,5 @@ examples: reg = <0x016e0000 0x14400>; #interconnect-cells = <2>; qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&gcc_aggre_ufs_phy_axi_clk>; }; diff --git a/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml b/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml index 5e26e48c7217..0203959c8995 100644 --- a/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml +++ b/Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml @@ -23,7 +23,7 @@ description: | The each AXI bus has the owned source clock but, has not the only owned power line. The power line might be shared among one more sub-blocks. So, we can divide into two type of device as the role of each sub-block. There are two - type of bus devices as following:: + type of bus devices as following: - parent bus device - passive bus device @@ -44,8 +44,8 @@ description: | able to support the bus frequency for all Exynos SoCs. Detailed correlation between sub-blocks and power line according - to Exynos SoC:: - - In case of Exynos3250, there are two power line as following:: + to Exynos SoC: + - In case of Exynos3250, there are two power line as following: VDD_MIF |--- DMC (Dynamic Memory Controller) VDD_INT |--- LEFTBUS (parent device) @@ -89,7 +89,7 @@ description: | |L5 |200000 |200000 |400000 |300000 | ||1000000 | ---------------------------------------------------------- - - In case of Exynos4210, there is one power line as following:: + - In case of Exynos4210, there is one power line as following: VDD_INT |--- DMC (parent device, Dynamic Memory Controller) |--- LEFTBUS |--- PERIL @@ -106,7 +106,7 @@ description: | |--- LCD0 |--- LCD1 - - In case of Exynos4x12, there are two power line as following:: + - In case of Exynos4x12, there are two power line as following: VDD_MIF |--- DMC (Dynamic Memory Controller) VDD_INT |--- LEFTBUS (parent device) @@ -124,7 +124,7 @@ description: | |--- LCD0 |--- ISP - - In case of Exynos5422, there are two power line as following:: + - In case of Exynos5422, there are two power line as following: VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller) |--- DREX 1 @@ -143,7 +143,7 @@ description: | |--- FSYS |--- FSYS2 - - In case of Exynos5433, there is VDD_INT power line as following:: + - In case of Exynos5433, there is VDD_INT power line as following: VDD_INT |--- G2D (parent device) |--- MSCL |--- GSCL diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index 06e3621a8c06..bb9273ec2457 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -33,6 +33,9 @@ properties: - allwinner,sun50i-a100-nmi - allwinner,sun50i-h616-nmi - const: allwinner,sun9i-a80-nmi + - items: + - const: allwinner,sun60i-a733-nmi + - const: allwinner,sun55i-a523-nmi reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml index d0fad930de9d..d26671913e89 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -38,6 +38,8 @@ properties: - amlogic,a4-gpio-intc - amlogic,a4-gpio-ao-intc - amlogic,a5-gpio-intc + - amlogic,a9-gpio-intc + - amlogic,a9-gpio-ao-intc - amlogic,c3-gpio-intc - amlogic,s6-gpio-intc - amlogic,s7-gpio-intc @@ -56,7 +58,7 @@ properties: amlogic,channel-interrupts: description: Array with the upstream hwirq numbers minItems: 2 - maxItems: 12 + maxItems: 20 $ref: /schemas/types.yaml#/definitions/uint32-array required: @@ -76,9 +78,20 @@ then: amlogic,channel-interrupts: maxItems: 2 else: - properties: - amlogic,channel-interrupts: - minItems: 8 + if: + properties: + compatible: + contains: + const: amlogic,a9-gpio-ao-intc + then: + properties: + amlogic,channel-interrupts: + minItems: 20 + else: + properties: + amlogic,channel-interrupts: + minItems: 8 + maxItems: 12 additionalProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml index d0d9a90e96e7..726a6720e05f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -44,6 +44,7 @@ properties: - items: - enum: - apple,t6030-aic3 + - apple,t6031-aic3 - const: apple,t8122-aic3 - const: apple,t8122-aic3 @@ -128,16 +129,17 @@ allOf: compatible: contains: enum: - - apple,t8112-aic - - apple,t8122-aic3 + - apple,t6000-aic + - apple,t6020-aic + - apple,t6031-aic3 then: properties: '#interrupt-cells': - const: 3 + const: 4 else: properties: '#interrupt-cells': - const: 4 + const: 3 examples: - | diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml deleted file mode 100644 index 258d21fe6e35..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml +++ /dev/null @@ -1,90 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Aspeed AST2700 Interrupt Controller - -description: - This interrupt controller hardware is second level interrupt controller that - is hooked to a parent interrupt controller. It's useful to combine multiple - interrupt sources into 1 interrupt to parent interrupt controller. - -maintainers: - - Kevin Chen <kevin_chen@aspeedtech.com> - -properties: - compatible: - enum: - - aspeed,ast2700-intc-ic - - reg: - maxItems: 1 - - interrupt-controller: true - - '#interrupt-cells': - const: 1 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - minItems: 1 - maxItems: 10 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable and raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 - -required: - - compatible - - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts - -additionalProperties: false - -examples: - - | - #include <dt-bindings/interrupt-controller/arm-gic.h> - - bus { - #address-cells = <2>; - #size-cells = <2>; - - interrupt-controller@12101b00 { - compatible = "aspeed,ast2700-intc-ic"; - reg = <0 0x12101b00 0 0x10>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml new file mode 100644 index 000000000000..a62f0fd2435b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-interrupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1) + +description: | + The ASPEED AST2700 SoC integrates two interrupt controller designs: + + - INTC0: Primary controller that routes interrupt sources to upstream, + processor-specific interrupt controllers + + - INTC1: Secondary controller whose interrupt outputs feed into INTC0 + + The SoC contains four processors to which interrupts can be routed: + + - PSP: Primary Service Processor (Cortex-A35) + - SSP: Secondary Service Processor (Cortex-M4) + - TSP: Tertiary Service Processor (Cortex-M4) + - BMCU: Boot MCU (a RISC-V microcontroller) + + The following diagram illustrates the overall architecture of the + ASPEED AST2700 interrupt controllers: + + +-----------+ +-----------+ + | INTC0 | | INTC1(0) | + +-----------+ +-----------+ + | Router | +-----------+ | Router | + | out int | +Peripheral + | out int | + +-----------+ | 0 0 <-+Controllers+ | INTM | +-----------+ + |PSP GIC <-|---+ . . | +-----------+ | . . <-+Peripheral + + +-----------+ | . . | | . . | +Controllers+ + +-----------+ | . . | | . . | +-----------+ + |SSP NVIC <-|---+ . . <----------------+ . . | + +-----------+ | . . | | . . | + +-----------+ | . . <-------- | . . | + |TSP NVIC <-|---+ . . | | ----+ . . | + +-----------+ | . . | | | | O P | + | . . | | | +-----------+ + | . . <---- | -------------------- + | . . | | | +-----------+ | + | M N | | ---------+ INTC1(1) | | + +-----------+ | +-----------+ | + | . | + | +-----------+ | + -------------+ INTC1(N) | | + +-----------+ | + +--------------+ | + + BMCU APLIC <-+--------------------------------------------- + +--------------+ + + INTC0 supports: + - 128 local peripheral interrupt inputs + - Fan-in from up to three INTC1 instances via banked interrupt lines (INTM) + - Local peripheral interrupt outputs + - Merged interrupt outputs + - Software interrupt outputs (SWINT) + - Configurable interrupt routes targeting the PSP, SSP, and TSP + + INTC1 supports: + - 192 local peripheral interrupt inputs + - Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank) + - Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU + + One INTC1 instance is always present, on the SoC's IO die. A further two + instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS + Tunneling Protocol & Interface). + + Interrupt numbering model + ------------------------- + The binding uses a controller-local numbering model. Peripheral device + nodes use the INTCx local interrupt number (hwirq) in their 'interrupts' or + 'interrupts-extended' properties. + + For AST2700, INTC0 exposes the following (inclusive) input ranges: + + - 000..479: Independent interrupts + - 480..489: INTM0-INTM9 + - 490..499: INTM10-INTM19 + - 500..509: INTM20-INTM29 + - 510..519: INTM30-INTM39 + - 520..529: INTM40-INTM49 + + INTC0's (inclusive) output ranges are as follows: + + - 000..127: 1:1 local peripheral interrupt output to PSP + - 144..151: Software interrupts from the SSP output to PSP + - 152..159: Software interrupts from the TSP output to PSP + - 192..201: INTM0-INTM9 banked outputs to PSP + - 208..217: INTM30-INTM39 banked outputs to PSP + - 224..233: INTM40-INTM49 banked outputs to PSP + - 256..383: 1:1 local peripheral interrupt output to SSP + - 384..393: INTM10-INTM19 banked outputs to SSP + - 400..407: Software interrupts from the PSP output to SSP + - 408..415: Software interrupts from the TSP output to SSP + - 426..553: 1:1 local peripheral interrupt output to TSP + - 554..563: INTM20-INTM29 banked outputs to TSP + - 570..577: Software interrupts from the PSP output to TSP + - 578..585: Software interrupts from the SSP output to TSP + + Inputs and outputs for INTC1 instances are context-dependent. However, for the + first instance of INTC1, the (inclusive) output ranges are: + + - 00..05: INTM0-INTM5 + - 10..15: INTM10-INTM15 + - 20..25: INTM20-INTM25 + - 30..35: INTM30-INTM35 + - 40..45: INTM40-INTM45 + - 50..50: BootMCU + +maintainers: + - Ryan Chen <ryan_chen@aspeedtech.com> + - Andrew Jeffery <andrew@codeconstruct.com.au> + +properties: + compatible: + enum: + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: Single cell encoding the INTC local interrupt number (hwirq). + + aspeed,interrupt-ranges: + description: | + Describes how ranges of controller output pins are routed to a parent + interrupt controller. + + Each range entry is encoded as: + + <out count phandle parent-specifier...> + + where: + - out: First controller interrupt output index in the range. + - count: Number of consecutive controller interrupt outputs and parent + interrupt inputs in this range. + - phandle: Phandle to the parent interrupt controller node. + - parent-specifier: Interrupt specifier, as defined by the parent + interrupt controller binding. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + items: + description: Range descriptors with a parent interrupt specifier. + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - aspeed,interrupt-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@12100000 { + compatible = "aspeed,ast2700-intc0"; + reg = <0x12100000 0x3b00>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <1>; + + aspeed,interrupt-ranges = + <0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <256 128 &ssp_nvic 0 0>, + <384 10 &ssp_nvic 160 0>, + <400 8 &ssp_nvic 144 0>, + <408 8 &ssp_nvic 152 0>, + <426 128 &tsp_nvic 0 0>, + <554 10 &tsp_nvic 160 0>, + <570 8 &tsp_nvic 144 0>, + <578 8 &tsp_nvic 152 0>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml index 5536319c49c3..44c09785e6bb 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml @@ -52,6 +52,25 @@ properties: - description: primary per-CPU IRQ - description: shadow IRQ number + econet,cpu-interrupt-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + When running in VEIC mode, the hardware re-routes interrupts from the + CPU interrupt controller core to the "external" interrupt controller + (this device). It then prioritizes them and sends them back to the CPU + along with its own interrupts. The CPU hardware handles interrupts using + a special dispatch table (the normal interrupt handler is not invoked). + In this interrupt controller, the CPU interrupts are renumbered as they + are merged with this controller's own hardware interrupts. + + This is the inverse of an interrupt-map, mapping which interrupts from + this controller must be routed back to the CPU interrupt domain for + correct handling there. + items: + items: + - description: The interrupt number as received in this controller + - description: The interrupt number to be dispatched on the CPU intc + required: - compatible - reg @@ -74,5 +93,6 @@ examples: interrupts = <2>; econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; + econet,cpu-interrupt-map = <7 0>, <8 1>; }; ... diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml index 2b8e7b9c6d7a..2b7c6b4f0389 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,qe-ports-ic.yaml @@ -23,7 +23,7 @@ properties: const: 0 '#interrupt-cells': - const: 1 + const: 2 interrupts: maxItems: 1 @@ -45,7 +45,7 @@ examples: reg = <0xc00 0x18>; interrupt-controller; #address-cells = <0>; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupts = <74 0x8>; interrupt-parent = <&ipic>; }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml index 30d76692ca87..b94fc3cec175 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml @@ -49,7 +49,8 @@ properties: interrupt-controller: true "#interrupt-cells": - $ref: arm,gic.yaml#/properties/#interrupt-cells + const: 3 + description: The cells have the same encoding as defined in arm,gic.yaml. required: - reg diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index b4942881b9c9..8162a49d49a6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -30,7 +30,9 @@ properties: - qcom,glymur-pdc - qcom,hawi-pdc - qcom,kaanapali-pdc + - qcom,maili-pdc - qcom,milos-pdc + - qcom,nord-pdc - qcom,qcs615-pdc - qcom,qcs8300-pdc - qcom,qdu1000-pdc diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml index 833a01cdd1b1..5c52e57c6647 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,rtl-intc.yaml @@ -32,8 +32,9 @@ properties: "#interrupt-cells": description: - SoC interrupt line index. - const: 1 + First cell is the SoC interrupt line index. Optional second cell + specifies the parent interrupt index to route to. + enum: [1, 2] reg: minItems: 1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml index 78c01d14e765..a809bc4f7515 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml @@ -165,7 +165,7 @@ examples: icu: interrupt-controller@802a0000 { compatible = "renesas,r9a09g077-icu"; reg = <0x802a0000 0x10000>, - <0x812a0000 0x50>; + <0x812a0000 0x10000>; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index e0267223887e..cde4bb691897 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -66,13 +66,16 @@ properties: - spacemit,k1-plic - starfive,jh7100-plic - starfive,jh7110-plic + - starfive,jhb100-plic - tenstorrent,blackhole-plic - const: sifive,plic-1.0.0 - items: - enum: - allwinner,sun20i-d1-plic + - canaan,k230-plic - sophgo,cv1800b-plic - sophgo,cv1812h-plic + - sophgo,sg2000-plic - sophgo,sg2002-plic - sophgo,sg2042-plic - sophgo,sg2044-plic diff --git a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml index ada5788602d6..d8a0a3862ae2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# +$id: http://devicetree.org/schemas/interrupt-controller/starfive,jhb100-intc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: StarFive External Interrupt Controller description: - StarFive SoC JH8100 contain a external interrupt controller. It can be used + StarFive SoC JHB100 contain a external interrupt controller. It can be used to handle high-level input interrupt signals. It also send the output interrupt signal to RISC-V PLIC. @@ -16,19 +16,11 @@ maintainers: properties: compatible: - const: starfive,jh8100-intc + const: starfive,jhb100-intc reg: maxItems: 1 - clocks: - description: APB clock for the interrupt controller - maxItems: 1 - - resets: - description: APB reset for the interrupt controller - maxItems: 1 - interrupts: maxItems: 1 @@ -40,8 +32,6 @@ properties: required: - compatible - reg - - clocks - - resets - interrupts - interrupt-controller - "#interrupt-cells" @@ -51,10 +41,8 @@ additionalProperties: false examples: - | interrupt-controller@12260000 { - compatible = "starfive,jh8100-intc"; + compatible = "starfive,jhb100-intc"; reg = <0x12260000 0x10000>; - clocks = <&syscrg_ne 76>; - resets = <&syscrg_ne 13>; interrupts = <45>; interrupt-controller; #interrupt-cells = <1>; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossbar.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossbar.yaml new file mode 100644 index 000000000000..a919db1d0645 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossbar.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,irq-crossbar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments IRQ Crossbar + +maintainers: + - Sricharan R <r.sricharan@ti.com> + +description: + Some socs have a large number of interrupts requests to service the needs of + its many peripherals and subsystems. All of the interrupt lines from the + subsystems are not needed at the same time, so they have to be muxed to the + irq-controller appropriately. In such places a interrupt controllers are + preceded by an CROSSBAR that provides flexibility in muxing the device + requests to the controller inputs. + +properties: + compatible: + const: ti,irq-crossbar + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + + ti,max-irqs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Total number of irqs available at the parent interrupt controller. + minimum: 1 + + ti,max-crossbar-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of crossbar sources that can be routed. + minimum: 1 + + ti,reg-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of a individual register in bytes. Every individual + register is assumed to be of same size. + enum: [1, 2, 4] + + ti,irqs-reserved: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of the reserved irq lines that are not muxed using crossbar. These + interrupt lines are reserved in the soc, so crossbar bar driver should not + consider them as free lines. + + ti,irqs-skip: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Similar to "ti,irqs-reserved", but these are for SOC-specific hard-wiring + of those irqs which unexpectedly bypasses the crossbar. These irqs have a + crossbar register, but still cannot be used. + + ti,irqs-safe-map: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + integer which maps to a safe configuration to use when the interrupt + controller irq is unused. + default: 0 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - ti,max-irqs + - ti,max-crossbar-sources + - ti,reg-size + - ti,irqs-reserved + +additionalProperties: false + +examples: + - | + crossbar@4a002a48 { + compatible = "ti,irq-crossbar"; + reg = <0x4a002a48 0x130>; + interrupt-controller; + #interrupt-cells = <3>; + ti,max-irqs = <160>; + ti,max-crossbar-sources = <400>; + ti,reg-size = <2>; + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; + ti,irqs-skip = <10 133 139 140>; + }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 06fb5c8e7547..ffa33b7f4a96 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -37,8 +37,12 @@ properties: - enum: - qcom,eliza-smmu-500 - qcom,glymur-smmu-500 + - qcom,hawi-smmu-500 + - qcom,ipq9650-smmu-500 - qcom,kaanapali-smmu-500 + - qcom,maili-smmu-500 - qcom,milos-smmu-500 + - qcom,nord-smmu-500 - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 - qcom,qcs8300-smmu-500 @@ -55,6 +59,7 @@ properties: - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - qcom,sdx75-smmu-500 + - qcom,shikra-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 @@ -92,6 +97,7 @@ properties: - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" items: - enum: + - qcom,eliza-smmu-500 - qcom,glymur-smmu-500 - qcom,hawi-smmu-500 - qcom,kaanapali-smmu-500 @@ -105,6 +111,7 @@ properties: - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 + - qcom,shikra-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm8150-smmu-500 @@ -540,6 +547,7 @@ allOf: - enum: - qcom,milos-smmu-500 - qcom,sar2130p-smmu-500 + - qcom,shikra-smmu-500 - qcom,sm8550-smmu-500 - qcom,sm8650-smmu-500 - qcom,x1e80100-smmu-500 @@ -566,7 +574,12 @@ allOf: properties: compatible: items: - - const: qcom,sm8750-smmu-500 + - enum: + - qcom,eliza-smmu-500 + - qcom,glymur-smmu-500 + - qcom,hawi-smmu-500 + - qcom,kaanapali-smmu-500 + - qcom,sm8750-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -595,6 +608,7 @@ allOf: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 + - qcom,sdx75-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 then: @@ -602,6 +616,42 @@ allOf: clock-names: false clocks: false + # Disallow clocks for all other platforms where specific compatible is used + # with different fallbacks and only one combination has no clocks + - if: + properties: + compatible: + items: + - enum: + - qcom,eliza-smmu-500 + - qcom,glymur-smmu-500 + - qcom,hawi-smmu-500 + - qcom,ipq9650-smmu-500 + - qcom,kaanapali-smmu-500 + - qcom,maili-smmu-500 + - qcom,milos-smmu-500 + - qcom,nord-smmu-500 + - qcom,qcs615-smmu-500 + - qcom,qcs8300-smmu-500 + - qcom,sa8775p-smmu-500 + - qcom,shikra-smmu-500 + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 + - qcom,sm8150-smmu-500 + - qcom,sm8250-smmu-500 + - qcom,sm8350-smmu-500 + - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 + - qcom,sm8750-smmu-500 + - qcom,x1e80100-smmu-500 + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: + properties: + clock-names: false + clocks: false + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml index 3f5006a59805..76ef34fe5c72 100644 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -38,5 +38,5 @@ examples: cmdqv@5200000 { compatible = "nvidia,tegra264-cmdqv"; reg = <0x5200000 0x830000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; }; diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml index d4838c3b3741..f83efb3ee000 100644 --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml @@ -32,22 +32,35 @@ properties: # should be specified along with 'reg' property providing MMIO location. compatible: oneOf: - - items: + - description: Platform (non-PCIe) IOMMU implementations + items: - enum: - qemu,riscv-iommu + - tenstorrent,riscv-iommu - const: riscv,iommu - - items: + - description: PCIe IOMMU implementations + items: - enum: - pci1efd,edf1 - const: riscv,pci-iommu reg: - maxItems: 1 - description: - For non-PCI devices this represents base address and size of for the - IOMMU memory mapped registers interface. - For PCI IOMMU hardware implementation this should represent an address - of the IOMMU, as defined in the PCI Bus Binding reference. + minItems: 1 + items: + - description: + For non-PCI devices, base address and size of the IOMMU memory + mapped registers interface. For PCI IOMMU hardware + implementation, an address of the IOMMU, as defined in the PCI + Bus Binding reference. + - description: + Region containing platform specific MMRs for machine-mode + configuration, such as PMA and PMP registers. + + reg-names: + minItems: 1 + items: + - const: base + - const: machine '#iommu-cells': const: 1 @@ -75,6 +88,26 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - tenstorrent,riscv-iommu + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + examples: - |+ /* Example 1 (IOMMU device with wired interrupts) */ @@ -145,3 +178,13 @@ examples: }; }; }; + + - |+ + /* Example 5 (Tenstorrent IOMMU device with MSIs) */ + iommu5: iommu@d2020000 { + compatible = "tenstorrent,riscv-iommu", "riscv,iommu"; + reg = <0xd2020000 0x10000>, <0xaa000000 0x10000>; + reg-names = "base", "machine"; + msi-parent = <&imsics_smode>; + #iommu-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt deleted file mode 100644 index 4bd10dd881b8..000000000000 --- a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt +++ /dev/null @@ -1,59 +0,0 @@ -OMAP2+ IOMMU - -Required properties: -- compatible : Should be one of, - "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances - "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances - "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances - "ti,dra7-iommu" for DRA7xx IOMMU instances -- ti,hwmods : Name of the hwmod associated with the IOMMU instance -- reg : Address space for the configuration registers -- interrupts : Interrupt specifier for the IOMMU instance -- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices, - and needs no additional data in the pargs specifier. Please - also refer to the generic bindings document for more info - on this property, - Documentation/devicetree/bindings/iommu/iommu.txt - -Optional properties: -- ti,#tlb-entries : Number of entries in the translation look-aside buffer. - Should be either 8 or 32 (default: 32) -- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing - back a bus error response on MMU faults. -- ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM - syscon node that contains the additional control - register for enabling the MMU, and the MMU instance - number (0-indexed) within the sub-system. This property - is required for DSP IOMMU instances on DRA7xx SoCs. The - instance number should be 0 for DSP MDMA MMUs and 1 for - DSP EDMA MMUs. - -Example: - /* OMAP3 ISP MMU */ - mmu_isp: mmu@480bd400 { - #iommu-cells = <0>; - compatible = "ti,omap2-iommu"; - reg = <0x480bd400 0x80>; - interrupts = <24>; - ti,hwmods = "mmu_isp"; - ti,#tlb-entries = <8>; - }; - - /* DRA74x DSP2 MMUs */ - mmu0_dsp2: mmu@41501000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41501000 0x100>; - interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmu0_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x0>; - }; - - mmu1_dsp2: mmu@41502000 { - compatible = "ti,dra7-dsp-iommu"; - reg = <0x41502000 0x100>; - interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "mmu1_dsp2"; - #iommu-cells = <0>; - ti,syscon-mmuconfig = <&dsp2_system 0x1>; - }; diff --git a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml new file mode 100644 index 000000000000..9588eb60376e --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/ti,omap-iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP2+ IOMMU + +maintainers: + - Bhargav Joshi <j.bhargav.u@gmail.com> + +properties: + compatible: + enum: + - ti,omap2-iommu + - ti,omap4-iommu + - ti,dra7-dsp-iommu + - ti,dra7-iommu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#iommu-cells': + const: 0 + + ti,#tlb-entries: + description: Number of entries in the translation look-aside buffer. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 32] + default: 32 + + ti,iommu-bus-err-back: + description: + Indicates the IOMMU instance supports throwing back a bus error response + on MMU faults. + type: boolean + + ti,syscon-mmuconfig: + description: + Pair of the phandle to the DSP_SYSTEM syscon node that + contains the additional control register for enabling the MMU, and the + MMU instance number (0-indexed) within the sub-system. The instance number + should be 0 for DSP MDMA MMUs and 1 for DSP EDMA MMUs. + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 1 + items: + items: + - description: phandle to the DSP_SYSTEM syscon node + - description: MMU instance number + enum: [0, 1] + + ti,hwmods: + description: Name of the hwmod associated with the IOMMU instance + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - reg + - '#iommu-cells' + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: ti,dra7-dsp-iommu + then: + required: + - ti,syscon-mmuconfig + else: + properties: + ti,syscon-mmuconfig: false + +additionalProperties: false + +examples: + - | + mmu@480bd400 { + #iommu-cells = <0>; + compatible = "ti,omap2-iommu"; + reg = <0x480bd400 0x80>; + interrupts = <24>; + ti,hwmods = "mmu_isp"; + ti,#tlb-entries = <8>; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mmu@41501000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x41501000 0x100>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "mmu0_dsp2"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x0>; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mmu@41502000 { + compatible = "ti,dra7-dsp-iommu"; + reg = <0x41502000 0x100>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "mmu1_dsp2"; + #iommu-cells = <0>; + ti,syscon-mmuconfig = <&dsp2_system 0x1>; + }; diff --git a/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml b/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml new file mode 100644 index 000000000000..d3ce9e603b61 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/verisilicon,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Verisilicon IOMMU + +maintainers: + - Benjamin Gaignard <benjamin.gaignard@collabora.com> + +description: |+ + A Versilicon iommu translates io virtual addresses to physical addresses for + its associated video decoder. + +properties: + compatible: + items: + - const: rockchip,rk3588-av1-iommu + - const: verisilicon,iommu-1.2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Core clock + - description: Interface clock + + clock-names: + items: + - const: core + - const: iface + + "#iommu-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + iommu@fdca0000 { + compatible = "rockchip,rk3588-av1-iommu","verisilicon,iommu-1.2"; + reg = <0x0 0xfdca0000 0x0 0x600>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "core", "iface"; + #iommu-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/leds/adi,ltc3220.yaml b/Documentation/devicetree/bindings/leds/adi,ltc3220.yaml new file mode 100644 index 000000000000..48215ad82d9a --- /dev/null +++ b/Documentation/devicetree/bindings/leds/adi,ltc3220.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/adi,ltc3220.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices LTC3220 LED Driver + +maintainers: + - Edelweise Escala <edelweise.escala@analog.com> + +description: > + The LTC3220 is a multi-display LED driver, which contains a high-efficiency, + low-noise charge pump to provide power to up to 18 LED current sources. + The LEDs are individually configurable to 64-step linear brightness control, + blinking and gradation control via 2-wire I2C interface. + + For more product information please see the link below + https://www.analog.com/en/products/ltc3220.html + +properties: + compatible: + const: adi,ltc3220 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reset-gpios: + maxItems: 1 + +patternProperties: + '^led@([1-9a-f]|1[0-2])$': + type: object + $ref: /schemas/leds/common.yaml# + unevaluatedProperties: false + properties: + reg: + description: + Output channel for the LED (1-18 maps to LED outputs D1-D18). + Unit-address must be in hexadecimal (1-12 hex = 1-18 decimal). + For aggregated LED control, define only one LED node with reg = <0x1> + and use led-sources to list all controlled outputs. Only reg 1 should + be present when using led-sources. + items: + - minimum: 1 + maximum: 18 + + required: + - reg + + if: + required: + - led-sources + then: + properties: + reg: + items: + - const: 1 + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + // Independent LEDs + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@1c { + compatible = "adi,ltc3220"; + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio 17 GPIO_ACTIVE_LOW>; + + led@1 { + reg = <0x1>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + led@2 { + reg = <0x2>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led@3 { + reg = <0x3>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; + }; + }; + + - | + // Aggregated LED + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@1c { + compatible = "adi,ltc3220"; + reg = <0x1c>; + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <0x1>; + led-sources = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12>; + function = LED_FUNCTION_BACKLIGHT; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/leds/backlight/88pm860x.txt b/Documentation/devicetree/bindings/leds/backlight/88pm860x.txt index 261df2799315..9e17807d2ce5 100644 --- a/Documentation/devicetree/bindings/leds/backlight/88pm860x.txt +++ b/Documentation/devicetree/bindings/leds/backlight/88pm860x.txt @@ -13,3 +13,4 @@ Example: }; backlight-2 { }; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/awinic,aw99706.yaml b/Documentation/devicetree/bindings/leds/backlight/awinic,aw99706.yaml index f48ce7a3434d..60eae50ff742 100644 --- a/Documentation/devicetree/bindings/leds/backlight/awinic,aw99706.yaml +++ b/Documentation/devicetree/bindings/leds/backlight/awinic,aw99706.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Awinic AW99706 6-channel WLED Backlight Driver maintainers: - - Junjie Cao <caojunjie650@gmail.com> + - Junjie Cao <junjie.cao@linux.dev> allOf: - $ref: common.yaml# diff --git a/Documentation/devicetree/bindings/leds/backlight/maxim,max25014.yaml b/Documentation/devicetree/bindings/leds/backlight/maxim,max25014.yaml new file mode 100644 index 000000000000..d00be2e08193 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/maxim,max25014.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/maxim,max25014.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim max25014 backlight controller + +maintainers: + - Maud Spierings <maudspierings@gocontroll.com> + +properties: + compatible: + enum: + - maxim,max25014 + + reg: + maxItems: 1 + + default-brightness: + minimum: 0 + maximum: 100 + default: 50 + + enable-gpios: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-supply: + description: Regulator which controls the boost converter input rail. + + pwms: + maxItems: 1 + + maxim,iset: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + default: 11 + description: + Value of the ISET field in the ISET register. This controls the current + scale of the outputs, a higher number means more current. + + maxim,strings: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + A 4-bit bitfield that describes which led strings to turn on. + minItems: 4 + maxItems: 4 + items: + maximum: 1 + default: + [1 1 1 1] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + backlight@6f { + compatible = "maxim,max25014"; + reg = <0x6f>; + default-brightness = <50>; + enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + power-supply = <®_backlight>; + pwms = <&pwm1>; + maxim,iset = <7>; + maxim,strings = <1 1 1 0>; + }; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/silergy,sy7758.yaml b/Documentation/devicetree/bindings/leds/backlight/silergy,sy7758.yaml new file mode 100644 index 000000000000..64af6b34641a --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/silergy,sy7758.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/silergy,sy7758.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silergy SY7758 6-channel High Efficiency LED Driver + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: + Silergy SY7758 is a high efficiency 6-channels LED backlight + driver with I2C brightness control. + +allOf: + - $ref: common.yaml# + +properties: + compatible: + const: silergy,sy7758 + + reg: + maxItems: 1 + + vdd-supply: true + + enable-gpios: + maxItems: 1 + +required: + - compatible + - reg + - enable-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + backlight@11 { + compatible = "silergy,sy7758"; + reg = <0x11>; + vdd-supply = <&bl_vdd>; + enable-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/ti,tps65217.yaml b/Documentation/devicetree/bindings/leds/backlight/ti,tps65217.yaml new file mode 100644 index 000000000000..4d2f4dbd2d52 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/ti,tps65217.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/ti,tps65217.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TPS65217 family of regulators + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +description: + The TPS65217 chip contains a boost converter and current sinks which can be + used to drive LEDs for use as backlights. + +properties: + compatible: + const: ti,tps65217 + + reg: + maxItems: 1 + description: I2C slave address + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + + ti,pmic-shutdown-controller: + type: boolean + description: + Set the PMIC to shutdown on PWR_EN toggle. + + backlight: + type: object + additionalProperties: false + description: + Node for specifying WLED1 and WLED2 lines in TPS65217. + + properties: + isel: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + description: | + Selection bit. Valid values: + 1 - ISEL1 (low-level) + 2 - ISEL2 (high-level) + + fdim: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [100, 200, 500, 1000] + description: + PWM dimming frequency in Hz. + + default-brightness: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 100 + + required: + - isel + - fdim + - default-brightness + + regulators: + type: object + additionalProperties: false + description: + List of child nodes that specify the regulator initialization data. + Not all regulators for the given device need to be present. + + patternProperties: + "^(dcdc[1-3]|ldo[1-4])$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + charger: + $ref: /schemas/power/supply/tps65217-charger.yaml# + unevaluatedProperties: false + + pwrbutton: + $ref: /schemas/input/ti,tps65217-pwrbutton.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@24 { + compatible = "ti,tps65217"; + reg = <0x24>; + interrupt-controller; + #interrupt-cells = <1>; + ti,pmic-shutdown-controller; + + backlight { + isel = <1>; /* 1 - ISET1, 2 ISET2 */ + fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ + default-brightness = <50>; + }; + + charger { + compatible = "ti,tps65217-charger"; + interrupts = <0>, <1>; + interrupt-names = "USB", "AC"; + }; + + pwrbutton { + compatible = "ti,tps65217-pwrbutton"; + interrupts = <2>; + }; + + regulators { + dcdc1 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/tps65217-backlight.txt b/Documentation/devicetree/bindings/leds/backlight/tps65217-backlight.txt deleted file mode 100644 index 5fb9279ac287..000000000000 --- a/Documentation/devicetree/bindings/leds/backlight/tps65217-backlight.txt +++ /dev/null @@ -1,27 +0,0 @@ -TPS65217 family of regulators - -The TPS65217 chip contains a boost converter and current sinks which can be -used to drive LEDs for use as backlights. - -Required properties: -- compatible: "ti,tps65217" -- reg: I2C slave address -- backlight: node for specifying WLED1 and WLED2 lines in TPS65217 -- isel: selection bit, valid values: 1 for ISEL1 (low-level) and 2 for ISEL2 (high-level) -- fdim: PWM dimming frequency, valid values: 100, 200, 500, 1000 -- default-brightness: valid values: 0-100 - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps: tps@24 { - reg = <0x24>; - compatible = "ti,tps65217"; - backlight { - isel = <1>; /* 1 - ISET1, 2 ISET2 */ - fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ - default-brightness = <50>; - }; - }; - diff --git a/Documentation/devicetree/bindings/leds/brcm,bcm6358-leds.yaml b/Documentation/devicetree/bindings/leds/brcm,bcm6358-leds.yaml new file mode 100644 index 000000000000..95fa311fddb5 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/brcm,bcm6358-leds.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/brcm,bcm6358-leds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LEDs connected to Broadcom BCM6358 controller + +description: | + This controller is present on BCM6358 and BCM6368. + In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller), + which can either be controlled by software (exporting the 74x164 as spi-gpio. + See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), or + by hardware using this driver. + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + +properties: + compatible: + const: brcm,bcm6358-leds + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + brcm,clk-div: + description: SCK signal divider. + default: 1 + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 4, 8] + + brcm,clk-dat-low: + description: Makes clock and data signals active low. + type: boolean + +patternProperties: + "^led@1?[0-9a-f]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + description: Each LED is represented as a sub-node of + this device. + + properties: + reg: + description: LED pin number (0 to 31). + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + led-controller@fffe00d0 { + compatible = "brcm,bcm6358-leds"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfffe00d0 0x8>; + + led@0 { + reg = <0>; + active-low; + label = "white:alarm"; + }; + led@2 { + reg = <2>; + active-low; + label = "white:tv"; + }; + led@3 { + reg = <3>; + active-low; + label = "white:tel"; + }; + led@4 { + reg = <4>; + active-low; + label = "white:adsl"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml index f4e44b33f56d..a0ef2f2f0724 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -73,6 +73,16 @@ properties: - keep default: off + default-intensity: + description: + The initial intensity of the LED color component. As the intensity of + each sub-LED is multiplied with the overall brightness, without this + property on a sub-LED, it may effectively be initialized at minimum + brightness regardless of its linux,default-trigger and default-brightness + properties. + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + linux,default-trigger: description: This parameter, if present, is a string defining the trigger assigned to @@ -106,6 +116,8 @@ properties: - bluetooth-power # LED indicates camera flash state - flash + # LED indicates level of GPIO input referenced by trigger-sources + - gpio # LED indicated keyboard capslock - kbd-capslock # LED indicates MTD memory activity diff --git a/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml b/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml index 72cadebf6e3e..0297bfbb2750 100644 --- a/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml +++ b/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml @@ -25,7 +25,7 @@ properties: duty-cycle: $ref: /schemas/types.yaml#/definitions/uint8 - enum: [50, 60, 70, 75, 80, 90] + enum: [30, 50, 60, 70, 75, 80, 90] description: Percentage of one period in which the signal is active. diff --git a/Documentation/devicetree/bindings/leds/lacie,ns2-leds.yaml b/Documentation/devicetree/bindings/leds/lacie,ns2-leds.yaml new file mode 100644 index 000000000000..2138c75c0413 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/lacie,ns2-leds.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/lacie,ns2-leds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Dual-GPIO LEDs found on Network Space v2 (and parents) + +maintainers: + - Simon Guinot <simon.guinot@sequanux.org> + +description: + The Network Space v2 dual-GPIO LED is wired to a CPLD. Three different LED + modes are available, off, on and SATA activity blinking. The LED modes are + controlled through two GPIOs (command and slow), each combination of values + for the command/slow GPIOs corresponds to a LED mode. + +properties: + compatible: + const: lacie,ns2-leds + +additionalProperties: + type: object + $ref: common.yaml# + unevaluatedProperties: false + + description: Each child node represents a single LED + + properties: + cmd-gpio: + maxItems: 1 + description: GPIO connected to the command LED output + + slow-gpio: + maxItems: 1 + description: GPIO connected to the slow LED output + + num-modes: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of entries in modes-map. + + modes-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + A mapping between LED modes (off, on or SATA activity blinking) and + the corresponding cmd-gpio/slow-gpio values. All the GPIO values + combinations should be given in order to avoid having an unknown + mode at driver probe time. + + items: + items: + - description: LED mode + enum: [0, 1, 2] + - description: Command GPIO level + enum: [0, 1] + - description: Slow GPIO level + enum: [0, 1] + + required: + - cmd-gpio + - slow-gpio + - modes-map + +required: + - compatible + +examples: + - | + #include <dt-bindings/leds/leds-ns2.h> + + led-controller { + compatible = "lacie,ns2-leds"; + + led-0 { + label = "ns2:blue:sata"; + slow-gpio = <&gpio0 29 0>; + cmd-gpio = <&gpio0 30 0>; + modes-map = <NS_V2_LED_OFF 0 1 + NS_V2_LED_ON 1 0 + NS_V2_LED_ON 0 0 + NS_V2_LED_SATA 1 1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/leds/leds-bcm6358.txt b/Documentation/devicetree/bindings/leds/leds-bcm6358.txt deleted file mode 100644 index 211ffc3c4a20..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-bcm6358.txt +++ /dev/null @@ -1,143 +0,0 @@ -LEDs connected to Broadcom BCM6358 controller - -This controller is present on BCM6358 and BCM6368. -In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller), -which can either be controlled by software (exporting the 74x164 as spi-gpio. -See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), or -by hardware using this driver. - -Required properties: - - compatible : should be "brcm,bcm6358-leds". - - #address-cells : must be 1. - - #size-cells : must be 0. - - reg : BCM6358 LED controller address and size. - -Optional properties: - - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8. - Default : 1 - - brcm,clk-dat-low : Boolean, makes clock and data signals active low. - Default : false - -Each LED is represented as a sub-node of the brcm,bcm6358-leds device. - -LED sub-node required properties: - - reg : LED pin number (only LEDs 0 to 31 are valid). - -LED sub-node optional properties: - - label : see Documentation/devicetree/bindings/leds/common.txt - - default-state : see - Documentation/devicetree/bindings/leds/common.txt - - linux,default-trigger : see - Documentation/devicetree/bindings/leds/common.txt - -Examples: -Scenario 1 : BCM6358 - leds0: led-controller@fffe00d0 { - compatible = "brcm,bcm6358-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfffe00d0 0x8>; - - alarm_white { - reg = <0>; - active-low; - label = "white:alarm"; - }; - tv_white { - reg = <2>; - active-low; - label = "white:tv"; - }; - tel_white { - reg = <3>; - active-low; - label = "white:tel"; - }; - adsl_white { - reg = <4>; - active-low; - label = "white:adsl"; - }; - }; - -Scenario 2 : BCM6368 - leds0: led-controller@100000d0 { - compatible = "brcm,bcm6358-leds"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x100000d0 0x8>; - brcm,pol-low; - brcm,clk-div = <4>; - - power_red { - reg = <0>; - active-low; - label = "red:power"; - }; - power_green { - reg = <1>; - active-low; - label = "green:power"; - default-state = "on"; - }; - power_blue { - reg = <2>; - label = "blue:power"; - }; - broadband_red { - reg = <3>; - active-low; - label = "red:broadband"; - }; - broadband_green { - reg = <4>; - label = "green:broadband"; - }; - broadband_blue { - reg = <5>; - active-low; - label = "blue:broadband"; - }; - wireless_red { - reg = <6>; - active-low; - label = "red:wireless"; - }; - wireless_green { - reg = <7>; - active-low; - label = "green:wireless"; - }; - wireless_blue { - reg = <8>; - label = "blue:wireless"; - }; - phone_red { - reg = <9>; - active-low; - label = "red:phone"; - }; - phone_green { - reg = <10>; - active-low; - label = "green:phone"; - }; - phone_blue { - reg = <11>; - label = "blue:phone"; - }; - upgrading_red { - reg = <12>; - active-low; - label = "red:upgrading"; - }; - upgrading_green { - reg = <13>; - active-low; - label = "green:upgrading"; - }; - upgrading_blue { - reg = <14>; - label = "blue:upgrading"; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml b/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml index fe8aaecf3010..67637efac378 100644 --- a/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml +++ b/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml @@ -183,7 +183,7 @@ examples: compatible = "ti,lp8501"; reg = <0x32>; clock-mode = /bits/ 8 <2>; - pwr-sel = /bits/ 8 <3>; /* D1~9 connected to VOUT */ + pwr-sel = /bits/ 8 <3>; /* D1~9 connected to VOUT */ ti,charge-pump-mode = <LP55XX_CP_BYPASS>; led@0 { diff --git a/Documentation/devicetree/bindings/leds/leds-ns2.txt b/Documentation/devicetree/bindings/leds/leds-ns2.txt deleted file mode 100644 index 9f81258a5b6e..000000000000 --- a/Documentation/devicetree/bindings/leds/leds-ns2.txt +++ /dev/null @@ -1,35 +0,0 @@ -Binding for dual-GPIO LED found on Network Space v2 (and parents). - -Required properties: -- compatible: "lacie,ns2-leds". - -Each LED is represented as a sub-node of the ns2-leds device. - -Required sub-node properties: -- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification. -- slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification. -- modes-map: A mapping between LED modes (off, on or SATA activity blinking) and - the corresponding cmd-gpio/slow-gpio values. All the GPIO values combinations - should be given in order to avoid having an unknown mode at driver probe time. - -Optional sub-node properties: -- label: Name for this LED. If omitted, the label is taken from the node name. -- linux,default-trigger: Trigger assigned to the LED. - -Example: - -#include <dt-bindings/leds/leds-ns2.h> - -ns2-leds { - compatible = "lacie,ns2-leds"; - - blue-sata { - label = "ns2:blue:sata"; - slow-gpio = <&gpio0 29 0>; - cmd-gpio = <&gpio0 30 0>; - modes-map = <NS_V2_LED_OFF 0 1 - NS_V2_LED_ON 1 0 - NS_V2_LED_ON 0 0 - NS_V2_LED_SATA 1 1>; - }; -}; diff --git a/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml index a31a202afe5c..7bf687c89411 100644 --- a/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml +++ b/Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml @@ -45,6 +45,8 @@ properties: color: true + default-intensity: true + required: - pwms - color @@ -63,12 +65,14 @@ examples: multi-led { color = <LED_COLOR_ID_RGB>; + linux,default-trigger = "default-on"; function = LED_FUNCTION_INDICATOR; max-brightness = <65535>; led-red { pwms = <&pwm1 0 1000000>; color = <LED_COLOR_ID_RED>; + default-intensity = <65535>; }; led-green { diff --git a/Documentation/devicetree/bindings/leds/nxp,pca963x.yaml b/Documentation/devicetree/bindings/leds/nxp,pca963x.yaml index 938d0e48fe51..a16ca11f630b 100644 --- a/Documentation/devicetree/bindings/leds/nxp,pca963x.yaml +++ b/Documentation/devicetree/bindings/leds/nxp,pca963x.yaml @@ -62,18 +62,52 @@ properties: open-drain, newer chips to totem pole). patternProperties: - "^led@[0-9a-f]+$": + "^led@[0-9a-f]$": type: object $ref: common.yaml# unevaluatedProperties: false properties: reg: - minimum: 0 + maximum: 15 required: - reg + "^multi-led@[0-9a-f]$": + type: object + $ref: leds-class-multicolor.yaml# + unevaluatedProperties: false + + properties: + reg: + maximum: 15 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + maximum: 15 + + required: + - reg + - color + + required: + - reg + - "#address-cells" + - "#size-cells" + allOf: - if: properties: @@ -84,16 +118,34 @@ allOf: - nxp,pca9633 then: patternProperties: - "^led@[0-9a-f]+$": + "^.*led@[0-9a-f]$": properties: reg: maximum: 3 - else: + "^multi-led@[0-9a-f]$": + patternProperties: + "^led@[0-9a-f]$": + properties: + reg: + maximum: 3 + - if: + properties: + compatible: + contains: + enum: + - nxp,pca9634 + then: patternProperties: - "^led@[0-9a-f]+$": + "^.*led@[0-9a-f]$": properties: reg: maximum: 7 + "^multi-led@[0-9a-f]$": + patternProperties: + "^led@[0-9a-f]$": + properties: + reg: + maximum: 7 additionalProperties: false @@ -137,4 +189,50 @@ examples: }; }; + - | + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@62 { + compatible = "nxp,pca9633"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + + /* Three channels controlling one RGB LED */ + multi-led@0 { + reg = <0>; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_RED>; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + }; + }; + + /* Remaining channel used as a plain white LED */ + led@3 { + reg = <3>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_STATUS; + }; + }; + }; + ... diff --git a/Documentation/devicetree/bindings/leds/qcom,pm8058-led.yaml b/Documentation/devicetree/bindings/leds/qcom,pm8058-led.yaml index b409b2a8b5c5..5165bfddcd54 100644 --- a/Documentation/devicetree/bindings/leds/qcom,pm8058-led.yaml +++ b/Documentation/devicetree/bindings/leds/qcom,pm8058-led.yaml @@ -10,10 +10,10 @@ maintainers: - Krzysztof Kozlowski <krzk@kernel.org> description: | - The Qualcomm PM8058 contains an LED block for up to six LEDs:: three normal + The Qualcomm PM8058 contains an LED block for up to six LEDs: three normal LEDs, two "flash" LEDs and one "keypad backlight" LED. The names are quoted because sometimes these LED drivers are used for wildly different things than - flash or keypad backlight:: their names are more of a suggestion than a + flash or keypad backlight: their names are more of a suggestion than a hard-wired usecase. Hardware-wise the different LEDs support slightly different output currents. diff --git a/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml b/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml new file mode 100644 index 000000000000..36051ab20509 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/samsung,s2mu005-flash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Flash and Torch LED Controller for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty <kauschluss@disroot.org> + +description: | + The Samsung S2M series PMIC flash LED has two led channels (typically + as back and front camera flashes), with support for both torch and + flash modes. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mu005-flash + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^led@[0-1]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + enum: [0, 1] + + required: + - reg + +required: + - compatible + - "#address-cells" + - "#size-cells" + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/leds/skyworks,aat1290.yaml b/Documentation/devicetree/bindings/leds/skyworks,aat1290.yaml index a6aaa92dbccd..65576dfdca11 100644 --- a/Documentation/devicetree/bindings/leds/skyworks,aat1290.yaml +++ b/Documentation/devicetree/bindings/leds/skyworks,aat1290.yaml @@ -11,7 +11,7 @@ maintainers: - Krzysztof Kozlowski <krzk@kernel.org> description: | - The device is controlled through two pins:: FL_EN and EN_SET. The pins when, + The device is controlled through two pins: FL_EN and EN_SET. The pins when, asserted high, enable flash strobe and movie mode (max 1/2 of flash current) respectively. In order to add a capability of selecting the strobe signal source (e.g. CPU or camera sensor) there is an additional switch required, @@ -39,11 +39,11 @@ properties: flash-max-microamp: description: | Maximum flash LED supply current can be calculated using following - formula:: I = 1A * 162 kOhm / Rset. + formula: I = 1A * 162 kOhm / Rset. flash-max-timeout-us: description: | - Maximum flash timeout can be calculated using following formula:: + Maximum flash timeout can be calculated using following formula: T = 8.82 * 10^9 * Ct. required: diff --git a/Documentation/devicetree/bindings/leds/ti,lm3560.yaml b/Documentation/devicetree/bindings/leds/ti,lm3560.yaml new file mode 100644 index 000000000000..6cf8cf91ab2e --- /dev/null +++ b/Documentation/devicetree/bindings/leds/ti,lm3560.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/ti,lm3560.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI LM3560 Synchronous Boost Flash Driver + +maintainers: + - Svyatoslav Ryhel <clamor95@gmail.com> + +description: + The LM3560 is a 2-MHz fixed frequency synchronous boost converter with two + 1000-mA constant current drivers for high-current white LEDs. The dual high- + side current sources allow for grounded cathode LED operation and can be + tied together for providing flash currents at up to 2 A through a single LED. + An adaptive regulation method ensures the current for each LED remains in + regulation and maximizes efficiency. + +properties: + compatible: + enum: + - ti,lm3559 + - ti,lm3560 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + enable-gpios: + description: GPIO connected to the HWEN pin. + maxItems: 1 + + vin-supply: + description: Supply connected to the IN line. + + flash-max-timeout-us: + minimum: 32000 + maximum: 1024000 + default: 32000 + + ti,peak-current-microamp: + description: + The LM3560 features 4 selectable current limits 1.6A, 2.3A, 3A, and 3.6A + (in case of LM3559 - 1.4A, 2.1A, 2.7A, and 3.2A). When the current limit + is reached, the LM3559/LM3560 stops switching for the remainder of the + switching cycle. + +patternProperties: + '^led@[01]$': + type: object + $ref: /schemas/leds/common.yaml# + description: LED control bank nodes. + unevaluatedProperties: false + + properties: + reg: + description: Control bank selection (0 = bank A, 1 = bank B). + maximum: 1 + + required: + - reg + - flash-max-microamp + - led-max-microamp + +allOf: + - $ref: /schemas/leds/common.yaml# + - if: + properties: + compatible: + contains: + const: ti,lm3559 + then: + properties: + ti,peak-current-microamp: + enum: [1400000, 2100000, 2700000, 3200000] + default: 1400000 + patternProperties: + '^led@[01]$': + properties: + flash-max-microamp: + minimum: 56250 + maximum: 900000 + led-max-microamp: + minimum: 28125 + maximum: 225000 + + - if: + properties: + compatible: + contains: + const: ti,lm3560 + then: + properties: + ti,peak-current-microamp: + enum: [1600000, 2300000, 3000000, 3600000] + default: 1600000 + patternProperties: + '^led@[01]$': + properties: + flash-max-microamp: + minimum: 62500 + maximum: 1000000 + led-max-microamp: + minimum: 31250 + maximum: 250000 + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@53 { + compatible = "ti,lm3560"; + reg = <0x53>; + + enable-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_3v3_sys>; + + flash-max-timeout-us = <1024000>; + ti,peak-current-microamp = <1600000>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + + flash-max-microamp = <562500>; + led-max-microamp = <156250>; + }; + + led@1 { + reg = <1>; + + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_YELLOW>; + + flash-max-microamp = <562500>; + led-max-microamp = <156250>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhuv3.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhuv3.yaml index 449b55afeb7d..025a5c55b284 100644 --- a/Documentation/devicetree/bindings/mailbox/arm,mhuv3.yaml +++ b/Documentation/devicetree/bindings/mailbox/arm,mhuv3.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: ARM MHUv3 Mailbox Controller maintainers: - - Sudeep Holla <sudeep.holla@arm.com> + - Sudeep Holla <sudeep.holla@kernel.org> - Cristian Marussi <cristian.marussi@arm.com> description: | diff --git a/Documentation/devicetree/bindings/mailbox/axiado,ax3005-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/axiado,ax3005-mailbox.yaml new file mode 100644 index 000000000000..82bf7d1848c9 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/axiado,ax3005-mailbox.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/axiado,ax3005-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axiado AX3005 Mailbox Controller + +maintainers: + - Krishnakumar Kesavan <kkesavan@axiado.com> + - Prasad Bolisetty <pbolisetty@axiado.com> + - Swark Yang <syang@axiado.com> + +description: + The Axiado mailbox controller provides inter-processor communication + channels between subsystems within the Axiado SoC. The hardware has + separate TX and RX register regions. Only the RX channels (channels 8-15) + generate interrupts; TX channels are purely poll/write-based. + +properties: + compatible: + const: axiado,ax3005-mailbox + + reg: + items: + - description: TX mailbox register region + - description: RX mailbox register region + + reg-names: + items: + - const: tx + - const: rx + + interrupts: + description: + One interrupt per RX channel. The hardware exposes eight RX interrupt + lines corresponding to channels 8 through 15. + maxItems: 8 + + interrupt-names: + description: + Named interrupt lines for each RX channel, from ch8 to ch15. + items: + - const: ch8 + - const: ch9 + - const: ch10 + - const: ch11 + - const: ch12 + - const: ch13 + - const: ch14 + - const: ch15 + + "#mbox-cells": + description: + Number of cells in a mailbox specifier. A single cell encodes the + channel index as seen by the client. + const: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + mailbox@330f2000 { + compatible = "axiado,ax3005-mailbox"; + reg = <0x0 0x330f2000 0x0 0x2000>, + <0x0 0x331b0000 0x0 0x1000>; + reg-names = "tx", "rx"; + /* Only RX channels (8-15) have IRQs */ + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + interrupt-parent = <&gic500>; + #mbox-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml index e249db4c1fbc..c109c1f7af24 100644 --- a/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml @@ -20,7 +20,9 @@ description: properties: compatible: - const: google,gs101-mbox + enum: + - google,gs101-mbox + - samsung,exynos850-mbox reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index f40dc9048327..39bc374300c3 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - qcom,ipq5018-apcs-apps-global + - qcom,ipq5210-apcs-apps-global - qcom,ipq5332-apcs-apps-global - qcom,ipq5424-apcs-apps-global - qcom,ipq8074-apcs-apps-global @@ -49,6 +50,7 @@ properties: - qcom,qcs615-apss-shared - qcom,sc7180-apss-shared - qcom,sc8180x-apss-shared + - qcom,shikra-apss-shared - qcom,sm7150-apss-shared - qcom,sm8150-apss-shared - const: qcom,sdm845-apss-shared diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 90bfde66cc4a..03359479d926 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -19,7 +19,9 @@ properties: - items: - enum: - qcom,glymur-cpucp-mbox + - qcom,hawi-cpucp-mbox - qcom,kaanapali-cpucp-mbox + - qcom,nord-cpucp-mbox - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index f5c584cf2146..a378fe8c7148 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -26,8 +26,11 @@ properties: - enum: - qcom,eliza-ipcc - qcom,glymur-ipcc + - qcom,hawi-ipcc - qcom,kaanapali-ipcc + - qcom,maili-ipcc - qcom,milos-ipcc + - qcom,nord-ipcc - qcom,qcs8300-ipcc - qcom,qdu1000-ipcc - qcom,sa8255p-ipcc diff --git a/Documentation/devicetree/bindings/mailbox/st,sti-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/st,sti-mailbox.yaml index a023c28dff49..662ab7f617ac 100644 --- a/Documentation/devicetree/bindings/mailbox/st,sti-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/st,sti-mailbox.yaml @@ -42,7 +42,7 @@ additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - mailbox0: mailbox@8f00000 { + mailbox@8f00000 { compatible = "st,stih407-mailbox"; reg = <0x8f00000 0x1000>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; diff --git a/Documentation/devicetree/bindings/mailbox/ti,k2g-message-manager.yaml b/Documentation/devicetree/bindings/mailbox/ti,k2g-message-manager.yaml new file mode 100644 index 000000000000..481b7c8c0e96 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/ti,k2g-message-manager.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/ti,k2g-message-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Message Manager + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +description: + The Texas Instruments Message Manager is a mailbox controller that has + configurable queues selectable at SoC (System on Chip) integration. The + Message manager is broken up into queues in different address regions + that are called "proxies" - each instance is unidirectional and is + instantiated at SoC integration level to indicate receive or transmit path. + +properties: + compatible: + const: ti,k2g-message-manager + + reg: + maxItems: 2 + + reg-names: + items: + - const: queue_proxy_region + - const: queue_state_debug_region + + "#mbox-cells": + const: 2 + description: + Contains the queue ID and proxy ID in that order referring to the + transfer path. + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: rx_005 + - const: rx_057 + +required: + - compatible + - reg + - reg-names + - "#mbox-cells" + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + msgmgr@2a00000 { + compatible = "ti,k2g-message-manager"; + #mbox-cells = <2>; + reg-names = "queue_proxy_region", "queue_state_debug_region"; + reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; + interrupt-names = "rx_005", "rx_057"; + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt b/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt deleted file mode 100644 index ebf0e3710cee..000000000000 --- a/Documentation/devicetree/bindings/mailbox/ti,message-manager.txt +++ /dev/null @@ -1,50 +0,0 @@ -Texas Instruments' Message Manager Driver -======================================== - -The Texas Instruments' Message Manager is a mailbox controller that has -configurable queues selectable at SoC(System on Chip) integration. The Message -manager is broken up into queues in different address regions that are called -"proxies" - each instance is unidirectional and is instantiated at SoC -integration level to indicate receive or transmit path. - -Message Manager Device Node: -=========================== -Required properties: --------------------- -- compatible: Shall be: "ti,k2g-message-manager" -- reg-names queue_proxy_region - Map the queue proxy region. - queue_state_debug_region - Map the queue state debug - region. -- reg: Contains the register map per reg-names. -- #mbox-cells Shall be 2. Contains the queue ID and proxy ID in that - order referring to the transfer path. -- interrupt-names: Contains interrupt names matching the rx transfer path - for a given SoC. Receive interrupts shall be of the - format: "rx_<QID>". - For ti,k2g-message-manager, this shall contain: - "rx_005", "rx_057" -- interrupts: Contains the interrupt information corresponding to - interrupt-names property. - -Example(K2G): ------------- - - msgmgr: msgmgr@2a00000 { - compatible = "ti,k2g-message-manager"; - #mbox-cells = <2>; - reg-names = "queue_proxy_region", "queue_state_debug_region"; - reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; - interrupt-names = "rx_005", "rx_057"; - interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; - }; - - pmmc: pmmc { - [...] - mbox-names = "rx", "tx"; - # RX queue ID is 5, proxy ID is 2 - # TX queue ID is 0, proxy ID is 0 - mboxes= <&msgmgr 5 2>, - <&msgmgr 0 0>; - [...] - }; diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml index 42dfe22ad5f1..18b28feacf83 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml @@ -16,9 +16,10 @@ allOf: properties: compatible: oneOf: - - const: allwinner,sun4i-a10-ir - - const: allwinner,sun5i-a13-ir - - const: allwinner,sun6i-a31-ir + - enum: + - allwinner,sun4i-a10-ir + - allwinner,sun5i-a13-ir + - allwinner,sun6i-a31-ir - items: - enum: - allwinner,suniv-f1c100s-ir @@ -27,6 +28,7 @@ properties: - allwinner,sun50i-a64-ir - allwinner,sun50i-h6-ir - allwinner,sun50i-h616-ir + - allwinner,sun55i-a523-ir - const: allwinner,sun6i-a31-ir reg: diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml index 541325f900a1..01f2afa023f0 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml @@ -63,6 +63,16 @@ properties: CMA pool to use for buffers allocation instead of the default CMA pool. + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnects: + maxItems: 1 + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnect-names: + const: dma-mem + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml index 1aa5775ba2bc..978ef2dc0ae7 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml @@ -40,6 +40,12 @@ properties: resets: maxItems: 1 + interconnects: + maxItems: 1 + + interconnect-names: + const: dma-mem + port: $ref: /schemas/graph.yaml#/$defs/port-base description: Parallel input port, connect to a parallel sensor diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml index 3ea4a4290f23..c0d7accc7bbe 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml @@ -36,6 +36,12 @@ properties: resets: maxItems: 1 + interconnects: + maxItems: 1 + + interconnect-names: + const: dma-mem + ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml b/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml index 582c6c9cae48..21118e4bae0f 100644 --- a/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml +++ b/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml @@ -14,7 +14,7 @@ description: | hooked up to a pull-up GPIO line and - optionally - the HPD line is hooked up to another GPIO line. - Please note:: the maximum voltage for the CEC line is 3.63V, for the HPD and + Please note: the maximum voltage for the CEC line is 3.63V, for the HPD and 5V lines it is 5.3V. So you may need some sort of level conversion circuitry when connecting them to a GPIO line. diff --git a/Documentation/devicetree/bindings/media/cnm,wave521c.yaml b/Documentation/devicetree/bindings/media/cnm,wave521c.yaml index 6a11c1d11fb5..6cd33dfd095d 100644 --- a/Documentation/devicetree/bindings/media/cnm,wave521c.yaml +++ b/Documentation/devicetree/bindings/media/cnm,wave521c.yaml @@ -37,7 +37,7 @@ properties: maxItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: The VPU uses the SRAM to store some of the reference data instead of storing it on DMA memory. It is mainly used for the purpose of reducing diff --git a/Documentation/devicetree/bindings/media/i2c/onnn,mt9m114.yaml b/Documentation/devicetree/bindings/media/i2c/onnn,mt9m114.yaml index e896f4db2421..2b39614f5cbf 100644 --- a/Documentation/devicetree/bindings/media/i2c/onnn,mt9m114.yaml +++ b/Documentation/devicetree/bindings/media/i2c/onnn,mt9m114.yaml @@ -15,6 +15,9 @@ description: |- an I2C interface and outputs image data over a 8-bit parallel or 1-lane MIPI CSI-2 connection. +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + properties: compatible: enum: @@ -90,7 +93,7 @@ required: - vaa-supply - port -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx355.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx355.yaml index 6050d7e7dcfe..d9cdfda699bf 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx355.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx355.yaml @@ -50,8 +50,15 @@ properties: properties: data-lanes: - minItems: 4 - maxItems: 4 + oneOf: + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - items: + - const: 1 + - const: 2 required: - link-frequencies diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx678.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx678.yaml new file mode 100644 index 000000000000..098f72544216 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx678.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2026 Ideas on Board Oy +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/sony,imx678.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sony IMX678 Sensor + +maintainers: + - Jai Luthra <jai.luthra@ideasonboard.com> + +description: + Sony IMX678 diagonal 8.86 mm (Type 1/1.8) CMOS active pixel type solid-state + image sensor with a square pixel array and 8.40M (3856x2180) effective pixels. + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + items: + - enum: + - sony,imx678-aamr + - sony,imx678-aaqr + - const: sony,imx678 + description: + The IMX678 sensor exists in a colour variant (IMX678-AAQR) and a mono + variant (IMX678-AAMR). The variant-specific compatible describes the + exact sensor variant, with the generic IMX678 compatible as a fallback. + + reg: + maxItems: 1 + + clocks: + description: | + Input clock (INCK). Only the rates listed in the datasheet are supported: + 13.5, 18, 24, 27, 36, 37.125, 72, and 74.25 MHz. + maxItems: 1 + + avdd-supply: + description: Analog power supply (3.3V) + + ovdd-supply: + description: Interface power supply (1.8V) + + dvdd-supply: + description: Digital power supply (1.1V) + + reset-gpios: + description: Sensor RESETN (XCLR) GPIO + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + oneOf: + - items: + - const: 1 + - const: 2 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + - const: 5 + - const: 6 + - const: 7 + - const: 8 + + required: + - data-lanes + - link-frequencies + + required: + - endpoint + +required: + - compatible + - reg + - clocks + - avdd-supply + - ovdd-supply + - dvdd-supply + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx678-aaqr", "sony,imx678"; + reg = <0x1a>; + clocks = <&imx678_clk>; + + avdd-supply = <&camera_avdd_3v3>; + ovdd-supply = <&camera_ovdd_1v8>; + dvdd-supply = <&camera_dvdd_1v1>; + + reset-gpios = <&gpio 0 GPIO_ACTIVE_LOW>; + + port { + imx678: endpoint { + remote-endpoint = <&cam>; + data-lanes = <1 2 3 4>; + link-frequencies = /bits/ 64 <720000000>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml b/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml index 060ac6829b66..58b1f9e85a9d 100644 --- a/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml +++ b/Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml @@ -27,9 +27,10 @@ properties: compatible: enum: - st,vd55g1 + - st,vd55g4 - st,vd65g4 description: - VD55G1 is the monochrome variant, while VD65G4 is the color one. + VD55G1 and VD55G4 are monochrome variants, while VD65G4 is a color one. reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml index ebc615584f92..4505e66876a2 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -160,7 +160,7 @@ examples: vcodec_enc_vp8: vcodec@19002000 { compatible = "mediatek,mt8173-vcodec-enc-vp8"; - reg = <0x19002000 0x1000>; /* VENC_LT_SYS */ + reg = <0x19002000 0x1000>; /* VENC_LT_SYS */ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, <&iommu M4U_PORT_VENC_REC_FRM_SET2>, diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index bf8082d87ac0..d1d209cbbd43 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -232,7 +232,7 @@ examples: #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0x16000000 0 0x40000>; - reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ video-codec@10000 { compatible = "mediatek,mtk-vcodec-lat"; reg = <0 0x10000 0 0x800>; diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml b/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml index b59c4ce30b8b..279c9cd3034a 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml @@ -117,7 +117,9 @@ allOf: compatible: not: contains: - const: fsl,imx91-isi + enum: + - fsl,imx8ulp-isi + - fsl,imx91-isi then: required: - fsl,blk-ctrl diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml index 18cc6315a821..6ba668aa633d 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml @@ -56,10 +56,10 @@ properties: maxItems: 5 # Wrapper and 4 slots sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: - Optional phandle to a reserved on-chip SRAM regions. The SRAM can - be used for descriptor storage, which may improve bus utilization. + The SRAM can be used for descriptor storage, which may improve bus + utilization. required: - compatible diff --git a/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml b/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml new file mode 100644 index 000000000000..b0b0355ad52e --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,milos-iris.yaml @@ -0,0 +1,166 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,milos-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos SoC Iris video encoder and decoder + +maintainers: + - Alexander Koskovich <akoskovich@pm.me> + +description: + The Iris video processing unit on Qualcomm Milos SoC is a video encode and + decode accelerator. + +properties: + compatible: + enum: + - qcom,milos-iris + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + iommus: + maxItems: 2 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 4 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: cx + - const: mx + + resets: + maxItems: 2 + + reset-names: + items: + - const: bus + - const: core + +required: + - compatible + - dma-coherent + - interconnects + - interconnect-names + - iommus + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,milos-gcc.h> + #include <dt-bindings/clock/qcom,milos-videocc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,milos-rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + video-codec@aa00000 { + compatible = "qcom,milos-iris"; + reg = <0x0aa00000 0xf0000>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", + "core", + "vcodec0_core"; + + dma-coherent; + iommus = <&apps_smmu 0x1960 0>, + <&apps_smmu 0x1967 0>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + operating-points-v2 = <&iris_opp_table>; + + memory-region = <&video_mem>; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "venus", + "vcodec0", + "cx", + "mx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_CLK_ARES>; + reset-names = "bus", + "core"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-552000000 { + opp-hz = /bits/ 64 <552000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_nom>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,msm8939-venus.yaml b/Documentation/devicetree/bindings/media/qcom,msm8939-venus.yaml new file mode 100644 index 000000000000..10a50a410748 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,msm8939-venus.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,msm8939-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8939 Venus video encode and decode accelerators + +maintainers: + - André Apitzsch <git@apitzsch.eu> + - Erikas Bitovtas <xerikasxx@gmail.com> + +description: + The Venus IP is a video encode and decode accelerator present + on Qualcomm platforms + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + const: qcom,msm8939-venus + + power-domains: + maxItems: 3 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: vcodec1 + + clocks: + maxItems: 5 + + clock-names: + items: + - const: core + - const: iface + - const: bus + - const: vcodec0_core + - const: vcodec1_core + + iommus: + maxItems: 1 + +required: + - compatible + - iommus + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/qcom,gcc-msm8939.h> + + video-codec@1d00000 { + compatible = "qcom,msm8939-venus"; + reg = <0x01d00000 0xff000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>, + <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_CORE1_VCODEC0_CLK>; + clock-names = "core", + "iface", + "bus", + "vcodec0_core", + "vcodec1_core"; + power-domains = <&gcc VENUS_GDSC>, + <&gcc VENUS_CORE0_GDSC>, + <&gcc VENUS_CORE1_GDSC>; + power-domain-names = "venus", "vcodec0", "vcodec1"; + iommus = <&apps_iommu 5>; + memory-region = <&venus_mem>; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml index 391d0f6f67ef..490a7f3a8c5f 100644 --- a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml @@ -14,7 +14,11 @@ description: properties: compatible: - const: qcom,qcm2290-camss + oneOf: + - items: + - const: qcom,shikra-camss + - const: qcom,qcm2290-camss + - const: qcom,qcm2290-camss reg: maxItems: 9 @@ -76,7 +80,14 @@ properties: - const: sf_mnoc iommus: - maxItems: 4 + oneOf: + - items: + - description: S1 HLOS VFE non-protected (VFE only) + - items: + - description: S1 HLOS VFE non-protected + - description: S1 HLOS CDM non-protected + - description: S1 HLOS OPE read non-protected + - description: S1 HLOS OPE write non-protected power-domains: items: diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml index 7e6dc410c2d2..5977e7d0a71b 100644 --- a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml @@ -18,7 +18,11 @@ allOf: properties: compatible: - const: qcom,qcm2290-venus + oneOf: + - items: + - const: qcom,sm6115-venus + - const: qcom,qcm2290-venus + - const: qcom,qcm2290-venus power-domains: maxItems: 3 diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml index bfd8b1ad4731..b21bed314848 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml @@ -91,6 +91,21 @@ properties: deprecated: true additionalProperties: false + video-firmware: + type: object + additionalProperties: false + + description: | + Firmware subnode is needed when the platform does not + have TrustZone. + + properties: + iommus: + maxItems: 1 + + required: + - iommus + required: - compatible - power-domain-names diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml index 413c5b4ee650..9725fcb761dc 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml @@ -43,8 +43,7 @@ properties: - const: vcodec_bus iommus: - minItems: 1 - maxItems: 2 + maxItems: 1 interconnects: maxItems: 2 @@ -120,12 +119,7 @@ examples: <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "cpu-cfg", "video-mem"; - iommus = <&apps_smmu 0x2180 0x20>, - <&apps_smmu 0x2184 0x20>; + iommus = <&apps_smmu 0x2180 0x20>; memory-region = <&video_mem>; - - video-firmware { - iommus = <&apps_smmu 0x21a2 0x0>; - }; }; diff --git a/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml new file mode 100644 index 000000000000..96974d90d8c4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml @@ -0,0 +1,471 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm6350-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Camera Subsystem (CAMSS) + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm6350-camss + + reg: + maxItems: 24 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite + - const: a5_csr + - const: a5_qgic + - const: a5_sierra + - const: bps + - const: camnoc + - const: core_top_csr_tcsr + - const: cpas_cdm + - const: cpas_top + - const: ipe + - const: jpeg_dma + - const: jpeg_enc + - const: lrme + + clocks: + maxItems: 39 + + clock-names: + items: + - const: cam_axi + - const: soc_ahb + - const: camnoc_axi + - const: core_ahb + - const: cpas_ahb + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe0_csid + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe1_csid + - const: vfe2_axi + - const: vfe2 + - const: vfe2_cphy_rx + - const: vfe2_csid + - const: vfe_lite + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: bps + - const: bps_ahb + - const: bps_areg + - const: bps_axi + - const: icp + - const: ipe0 + - const: ipe0_ahb + - const: ipe0_areg + - const: ipe0_axi + - const: jpeg + - const: lrme + + interrupts: + maxItems: 18 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite + - const: a5 + - const: cpas + - const: cpas_cdm + - const: jpeg_dma + - const: jpeg_enc + - const: lrme + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 14 + + power-domains: + maxItems: 6 + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + - const: bps + - const: ipe + + vdd-csiphy0-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY0. + + vdd-csiphy0-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY0. + + vdd-csiphy1-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY1. + + vdd-csiphy1-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY1. + + vdd-csiphy2-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY2. + + vdd-csiphy2-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY2. + + vdd-csiphy3-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY3. + + vdd-csiphy3-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY3. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sm6350.h> + #include <dt-bindings/clock/qcom,sm6350-camcc.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,sm6350.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/media/video-interfaces.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb3000 { + compatible = "qcom,sm6350-camss"; + + reg = <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc1000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0ac65000 0x0 0x1000>, + <0x0 0x0ac66000 0x0 0x1000>, + <0x0 0x0ac67000 0x0 0x1000>, + <0x0 0x0ac68000 0x0 0x1000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acbd000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0ac18000 0x0 0x3000>, + <0x0 0x0ac00000 0x0 0x6000>, + <0x0 0x0ac10000 0x0 0x8000>, + <0x0 0x0ac6f000 0x0 0x8000>, + <0x0 0x0ac42000 0x0 0x4600>, + <0x0 0x01fc0000 0x0 0x40000>, + <0x0 0x0ac48000 0x0 0x1000>, + <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac87000 0x0 0xa000>, + <0x0 0x0ac52000 0x0 0x4000>, + <0x0 0x0ac4e000 0x0 0x4000>, + <0x0 0x0ac6b000 0x0 0xa00>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite", + "a5_csr", + "a5_qgic", + "a5_sierra", + "bps", + "camnoc", + "core_top_csr_tcsr", + "cpas_cdm", + "cpas_top", + "ipe", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + clocks = <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CORE_AHB_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_CLK>, + <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_CSID_CLK>, + <&camcc CAMCC_BPS_CLK>, + <&camcc CAMCC_BPS_AHB_CLK>, + <&camcc CAMCC_BPS_AREG_CLK>, + <&camcc CAMCC_BPS_AXI_CLK>, + <&camcc CAMCC_ICP_CLK>, + <&camcc CAMCC_IPE_0_CLK>, + <&camcc CAMCC_IPE_0_AHB_CLK>, + <&camcc CAMCC_IPE_0_AREG_CLK>, + <&camcc CAMCC_IPE_0_AXI_CLK>, + <&camcc CAMCC_JPEG_CLK>, + <&camcc CAMCC_LRME_CLK>; + clock-names = "cam_axi", + "soc_ahb", + "camnoc_axi", + "core_ahb", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "bps", + "bps_ahb", + "bps_areg", + "bps_axi", + "icp", + "ipe0", + "ipe0_ahb", + "ipe0_areg", + "ipe0_axi", + "jpeg", + "lrme"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 473 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 472 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite", + "a5", + "cpas", + "cpas_cdm", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x820 0xc0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0xc0>, + <&apps_smmu 0x880 0x0>, + <&apps_smmu 0xc40 0x20>, + <&apps_smmu 0xc60 0x20>, + <&apps_smmu 0xc80 0x0>, + <&apps_smmu 0xca2 0x0>, + <&apps_smmu 0xcc0 0x20>, + <&apps_smmu 0xce0 0x20>, + <&apps_smmu 0xd00 0x20>, + <&apps_smmu 0xd20 0x20>, + <&apps_smmu 0xd40 0x20>, + <&apps_smmu 0xd60 0x20>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc TITAN_TOP_GDSC>, + <&camcc BPS_GDSC>, + <&camcc IPE_0_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top", + "bps", + "ipe"; + + vdd-csiphy0-0p9-supply = <&vreg_l18a>; + vdd-csiphy0-1p25-supply = <&vreg_l22a>; + vdd-csiphy1-0p9-supply = <&vreg_l18a>; + vdd-csiphy1-1p25-supply = <&vreg_l22a>; + vdd-csiphy2-0p9-supply = <&vreg_l18a>; + vdd-csiphy2-1p25-supply = <&vreg_l22a>; + vdd-csiphy3-0p9-supply = <&vreg_l18a>; + vdd-csiphy3-1p25-supply = <&vreg_l22a>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy0_ep: endpoint { + data-lanes = <0 1 2 3>; + bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml index da54493220c9..aca748e42aca 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml @@ -10,19 +10,25 @@ maintainers: - Stanimir Varbanov <stanimir.varbanov@linaro.org> description: | - The Venus IP is a video encode and decode accelerator present - on Qualcomm platforms + The Iris v2.xx IP is a video encode and decode accelerator present on + Qualcomm platforms allOf: - $ref: qcom,venus-common.yaml# properties: compatible: - const: qcom,sm8250-venus + oneOf: + - const: qcom,sm8250-venus + - items: + - enum: + - qcom,sc8280xp-iris + - qcom,sm8350-iris + - const: qcom,sm8250-venus power-domains: minItems: 2 - maxItems: 3 + maxItems: 4 power-domain-names: minItems: 2 @@ -30,6 +36,7 @@ properties: - const: venus - const: vcodec0 - const: mx + - const: mmcx clocks: maxItems: 3 @@ -114,8 +121,12 @@ examples: interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&videocc MVS0C_GDSC>, <&videocc MVS0_GDSC>, - <&rpmhpd RPMHPD_MX>; - power-domain-names = "venus", "vcodec0", "mx"; + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mx", + "mmcx"; clocks = <&gcc GCC_VIDEO_AXI0_CLK>, <&videocc VIDEO_CC_MVS0C_CLK>, diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index 9c4b760508b5..0400ca1bff05 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -26,6 +26,7 @@ properties: - qcom,qcs8300-iris - qcom,sm8550-iris - qcom,sm8650-iris + - qcom,x1p42100-iris reg: maxItems: 1 @@ -41,13 +42,16 @@ properties: - const: mmcx clocks: - maxItems: 3 + minItems: 3 + maxItems: 4 clock-names: + minItems: 3 items: - const: iface - const: core - const: vcodec0_core + - const: vcodec0_bse firmware-name: maxItems: 1 @@ -115,6 +119,23 @@ allOf: maxItems: 1 reset-names: maxItems: 1 + - if: + properties: + compatible: + enum: + - qcom,x1p42100-iris + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + else: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml index 3153d91f9d18..59a3fde846d2 100644 --- a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml +++ b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml @@ -47,21 +47,6 @@ properties: minItems: 1 maxItems: 4 - video-firmware: - type: object - additionalProperties: false - - description: | - Firmware subnode is needed when the platform does not - have TrustZone. - - properties: - iommus: - maxItems: 1 - - required: - - iommus - required: - reg - clocks diff --git a/Documentation/devicetree/bindings/media/rc.yaml b/Documentation/devicetree/bindings/media/rc.yaml index dedc5a4b81ec..43d84296e70d 100644 --- a/Documentation/devicetree/bindings/media/rc.yaml +++ b/Documentation/devicetree/bindings/media/rc.yaml @@ -122,10 +122,10 @@ properties: - rc-proteus-2309 - rc-purpletv - rc-pv951 - - rc-rc5-tv - rc-rc6-mce - rc-real-audio-220-32-keys - rc-reddo + - rc-siemens-gigaset-rc20 - rc-snapstream-firefly - rc-streamzap - rc-su3000 @@ -147,11 +147,11 @@ properties: - rc-tt-1500 - rc-twinhan-dtv-cab-ci - rc-twinhan1027 + - rc-vega-s9x - rc-videomate-k100 - rc-videomate-s350 - rc-videomate-tv-pvr - rc-videostrong-kii-pro - - rc-vega-s9x - rc-wetek-hub - rc-wetek-play2 - rc-winfast diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.yaml b/Documentation/devicetree/bindings/media/renesas,fcp.yaml index b5eff6fec8a9..cbb16a7a5481 100644 --- a/Documentation/devicetree/bindings/media/renesas,fcp.yaml +++ b/Documentation/devicetree/bindings/media/renesas,fcp.yaml @@ -30,8 +30,12 @@ properties: - renesas,r9a07g043u-fcpvd # RZ/G2UL - renesas,r9a07g044-fcpvd # RZ/G2{L,LC} - renesas,r9a07g054-fcpvd # RZ/V2L + - renesas,r9a08g046-fcpvd # RZ/G3L + - renesas,r9a09g047-fcpvd # RZ/G3E - renesas,r9a09g056-fcpvd # RZ/V2N - renesas,r9a09g057-fcpvd # RZ/V2H(P) + - renesas,r9a09g077-fcpvd # RZ/T2H + - renesas,r9a09g087-fcpvd # RZ/N2H - const: renesas,fcpv # Generic FCP for VSP fallback reg: @@ -64,7 +68,6 @@ required: - reg - clocks - power-domains - - resets additionalProperties: false @@ -77,8 +80,12 @@ allOf: - renesas,r9a07g043u-fcpvd - renesas,r9a07g044-fcpvd - renesas,r9a07g054-fcpvd + - renesas,r9a08g046-fcpvd + - renesas,r9a09g047-fcpvd - renesas,r9a09g056-fcpvd - renesas,r9a09g057-fcpvd + - renesas,r9a09g077-fcpvd + - renesas,r9a09g087-fcpvd then: properties: clocks: @@ -90,6 +97,19 @@ allOf: clocks: maxItems: 1 clock-names: false + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g077-fcpvd + - renesas,r9a09g087-fcpvd + then: + properties: + resets: false + else: + required: + - resets examples: # R8A7795 (R-Car H3) FCP for VSP-D1 diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml index 07a97dd87a5b..a28632165804 100644 --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml @@ -25,8 +25,12 @@ properties: - enum: - renesas,r9a07g043u-vsp2 # RZ/G2UL - renesas,r9a07g054-vsp2 # RZ/V2L + - renesas,r9a08g046-vsp2 # RZ/G3L + - renesas,r9a09g047-vsp2 # RZ/G3E - renesas,r9a09g056-vsp2 # RZ/V2N - renesas,r9a09g057-vsp2 # RZ/V2H(P) + - renesas,r9a09g077-vsp2 # RZ/T2H + - renesas,r9a09g087-vsp2 # RZ/N2H - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback reg: @@ -65,7 +69,6 @@ required: - interrupts - clocks - power-domains - - resets additionalProperties: false @@ -99,6 +102,20 @@ allOf: maxItems: 1 clock-names: false + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g077-vsp2 + - renesas,r9a09g087-vsp2 + then: + properties: + resets: false + else: + required: + - resets + examples: # R8A7790 (R-Car H2) VSP1-S - | diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml index 4ac4a3b6f406..8bfad0fca3b7 100644 --- a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml @@ -16,9 +16,15 @@ description: properties: compatible: - enum: - - fsl,imx93-mipi-csi2 - - rockchip,rk3568-mipi-csi2 + oneOf: + - enum: + - fsl,imx93-mipi-csi2 + - fsl,imx95-mipi-csi2 + - rockchip,rk3568-mipi-csi2 + - items: + - enum: + - rockchip,rk3588-mipi-csi2 + - const: rockchip,rk3568-mipi-csi2 reg: maxItems: 1 @@ -135,6 +141,21 @@ allOf: clock-names: minItems: 2 + - if: + properties: + compatible: + contains: + const: fsl,imx95-mipi-csi2 + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: false + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + examples: - | #include <dt-bindings/clock/rk3568-cru.h> diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml index 18cd0a5a5318..080b64503b1b 100644 --- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml @@ -15,9 +15,15 @@ description: the data from camera sensors, video decoders, or other companion ICs and transfers it into system main memory by AXI bus. + The Rockchip RK3588 Video Capture (VICAP) is similar to its RK3568 + counterpart, but features six MIPI CSI-2 ports and additional connections + to the image signal processor (ISP) blocks. + properties: compatible: - const: rockchip,rk3568-vicap + enum: + - rockchip,rk3568-vicap + - rockchip,rk3588-vicap reg: maxItems: 1 @@ -26,11 +32,8 @@ properties: maxItems: 1 clocks: - items: - - description: ACLK - - description: HCLK - - description: DCLK - - description: ICLK + minItems: 4 + maxItems: 5 clock-names: items: @@ -38,25 +41,19 @@ properties: - const: hclk - const: dclk - const: iclk + - const: iclk1 + minItems: 4 iommus: maxItems: 1 resets: - items: - - description: ARST - - description: HRST - - description: DRST - - description: PRST - - description: IRST + minItems: 5 + maxItems: 9 reset-names: - items: - - const: arst - - const: hrst - - const: drst - - const: prst - - const: irst + minItems: 5 + maxItems: 9 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -67,8 +64,15 @@ properties: ports: $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + port@0: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false @@ -100,13 +104,75 @@ properties: port@1: $ref: /schemas/graph.yaml#/properties/port - description: Port connected to the MIPI CSI-2 receiver output. + description: Port connected to the MIPI CSI-2 receiver 0 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 1 output. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 2 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 3 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@5: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 4 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 5 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@10: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the ISP0 input. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@11: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the ISP1 input. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false required: - compatible - reg @@ -114,6 +180,75 @@ required: - clocks - ports +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-vicap + then: + properties: + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + maxItems: 5 + + reset-names: + items: + - const: arst + - const: hrst + - const: drst + - const: prst + - const: irst + + ports: + properties: + port@2: false + + port@3: false + + port@4: false + + port@5: false + + port@6: false + + port@10: false + + port@11: false + + - if: + properties: + compatible: + contains: + const: rockchip,rk3588-vicap + then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + + resets: + minItems: 9 + + reset-names: + items: + - const: arst + - const: hrst + - const: drst + - const: irst0 + - const: irst1 + - const: irst2 + - const: irst3 + - const: irst4 + - const: irst5 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml index 42022401d0ff..4f38a0ef29d8 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml @@ -91,9 +91,8 @@ properties: maxItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle - description: | - phandle to a reserved on-chip SRAM regions. + maxItems: 1 + description: Some SoCs, like rk3588 provide on-chip SRAM to store temporary buffers during decoding. diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.yaml b/Documentation/devicetree/bindings/media/rockchip-rga.yaml index ac17cda65191..7bd92f733666 100644 --- a/Documentation/devicetree/bindings/media/rockchip-rga.yaml +++ b/Documentation/devicetree/bindings/media/rockchip-rga.yaml @@ -9,7 +9,11 @@ title: Rockchip 2D raster graphic acceleration controller (RGA) description: RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D graphics operations, such as point/line drawing, image scaling, rotation, - BitBLT, alpha blending and image blur/sharpness. + BitBLT, alpha blending and image blur/sharpness. There exist many versions + of this unit that differ in the supported inputs/output formats, + the attached IOMMU and the supported operations on the input. As some SoCs + include multiple RGA units with different versions, a more specific + compatible name to differentiate the concrete unit is used for them. maintainers: - Jacob Chen <jacob-chen@iotwrt.com> @@ -20,6 +24,7 @@ properties: oneOf: - const: rockchip,rk3288-rga - const: rockchip,rk3399-rga + - const: rockchip,rk3588-rga3 - items: - enum: - rockchip,rk3228-rga @@ -45,6 +50,9 @@ properties: power-domains: maxItems: 1 + iommus: + maxItems: 1 + resets: maxItems: 3 diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index d9fbb90b0977..7c2ddd27780f 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -47,10 +47,10 @@ properties: maxItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: - phandle to a reserved SRAM region which is used as temporary - storage memory between DMA and MDMA engines. + SRAM region which is used as temporary storage memory between DMA and + MDMA engines. port: $ref: /schemas/graph.yaml#/$defs/port-base diff --git a/Documentation/devicetree/bindings/media/ti,am437x-vpfe.yaml b/Documentation/devicetree/bindings/media/ti,am437x-vpfe.yaml new file mode 100644 index 000000000000..983e705ab1e8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,am437x-vpfe.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,am437x-vpfe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments AM437x CAMERA Video Processing Front End (VPFE) + +maintainers: + - Benoit Parrot <bparrot@ti.com> + - Bhargav Joshi <j.bhargav.u@gmail.com> + +description: + The Video Processing Front End (VPFE) is a key component for image capture + applications. The capture module provides the system interface and the + processing capability to connect RAW image-sensor modules and video decoders + to the AM437x device. + +properties: + compatible: + const: ti,am437x-vpfe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + A single parallel input port connecting to an external image sensor or + video decoder. The VPFE supports only one input port per instance. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + ti,am437x-vpfe-interface: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4] + description: + Selects the VPFE input interface type can be one of following + 0 - Raw Bayer (VPFE_RAW_BAYER) + 1 - BT.656 8-bit (VPFE_BT656) + 2 - BT.656 10-bit (VPFE_BT656_10BIT) + 3 - YCbCr 8-bit sync (VPFE_YCBCR_SYNC_8) + 4 - YCbCr 16-bit sync (VPFE_YCBCR_SYNC_16) + + bus-width: + minimum: 8 + maximum: 16 + + required: + - remote-endpoint + - ti,am437x-vpfe-interface + - bus-width + +required: + - compatible + - reg + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + vpfe@48328000{ + compatible = "ti,am437x-vpfe"; + reg = <0x48328000 0x2000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&vpfe_pins_default>; + pinctrl-1 = <&vpfe_pins_sleep>; + + port { + vpfe0_ep: endpoint { + remote-endpoint = <&ov2659_1>; + ti,am437x-vpfe-interface = <0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/ti,da850-vpif.txt b/Documentation/devicetree/bindings/media/ti,da850-vpif.txt deleted file mode 100644 index e47c7ccc57f1..000000000000 --- a/Documentation/devicetree/bindings/media/ti,da850-vpif.txt +++ /dev/null @@ -1,106 +0,0 @@ -Texas Instruments VPIF ----------------------- - -The TI Video Port InterFace (VPIF) is the primary component for video -capture and display on the DA850/AM18x family of TI DaVinci/Sitara -SoCs. - -TI Document reference: SPRUH82C, Chapter 35 -http://www.ti.com/lit/pdf/spruh82 - -Required properties: -- compatible: must be "ti,da850-vpif" -- reg: physical base address and length of the registers set for the device; -- interrupts: should contain IRQ line for the VPIF - -Video Capture: - -VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a -single 16-bit channel. It should contain one or two port child nodes -with child 'endpoint' node. If there are two ports then port@0 must -describe the input and port@1 output channels. Please refer to the -bindings defined in -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example using 2 8-bit input channels, one of which is connected to an -I2C-connected TVP5147 decoder: - - vpif: vpif@217000 { - compatible = "ti,da850-vpif"; - reg = <0x217000 0x1000>; - interrupts = <92>; - - port@0 { - vpif_input_ch0: endpoint@0 { - reg = <0>; - bus-width = <8>; - remote-endpoint = <&composite_in>; - }; - - vpif_input_ch1: endpoint@1 { - reg = <1>; - bus-width = <8>; - data-shift = <8>; - }; - }; - - port@1 { - vpif_output_ch0: endpoint { - bus-width = <8>; - remote-endpoint = <&composite_out>; - }; - }; - }; - -[ ... ] - -&i2c0 { - - tvp5147@5d { - compatible = "ti,tvp5147"; - reg = <0x5d>; - - port { - composite_in: endpoint { - hsync-active = <1>; - vsync-active = <1>; - pclk-sample = <0>; - - /* VPIF channel 0 (lower 8-bits) */ - remote-endpoint = <&vpif_input_ch0>; - bus-width = <8>; - }; - }; - }; - - adv7343@2a { - compatible = "adi,adv7343"; - reg = <0x2a>; - - port { - composite_out: endpoint { - adi,dac-enable = <1 1 1>; - adi,sd-dac-enable = <1>; - - remote-endpoint = <&vpif_output_ch0>; - bus-width = <8>; - }; - }; - }; -}; - - -Alternatively, an example when the bus is configured as a single -16-bit input (e.g. for raw-capture mode): - - vpif: vpif@217000 { - compatible = "ti,da850-vpif"; - reg = <0x217000 0x1000>; - interrupts = <92>; - - port { - vpif_ch0: endpoint { - bus-width = <16>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/media/ti,da850-vpif.yaml b/Documentation/devicetree/bindings/media/ti,da850-vpif.yaml new file mode 100644 index 000000000000..77de70be807a --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,da850-vpif.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,da850-vpif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DA850/AM18x Video Port Interface (VPIF) + +maintainers: + - Lad, Prabhakar <prabhakar.csengg@gmail.com> + +description: + The Video Port Interface (VPIF) is the primary component for video capture + and display on the DA850/AM18x family of TI DaVinci/Sitara SoCs. + + TI Document reference:- SPRUH82C, Chapter 35 + https://www.ti.com/lit/pdf/spruh82 + +properties: + compatible: + const: ti,da850-vpif + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + VPIF port when the bus is configured as a single 16-bit input + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-width: + enum: [8, 16] + +patternProperties: + ^port@[0-1]$: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a + single 16-bit channel. It should contain one or two port child nodes + with child 'endpoint' node. If there are two ports then port@0 must + describe the input and port@1 output channels. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + bus-width: + enum: [8, 16] + + endpoint@0: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + description: + First 8-bit channel using the lower data lines [7:0]. + + properties: + bus-width: + const: 8 + + data-shift: + const: 0 + + endpoint@1: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + description: + Second 8-bit channel using the upper data lines [15:8]. + + properties: + bus-width: + const: 8 + + data-shift: + const: 8 + + anyOf: + - properties: + endpoint@0: false + endpoint@1: false + - properties: + endpoint: false + +required: + - compatible + - reg + - interrupts + +oneOf: + - properties: + port@0: false + port@1: false + - properties: + port: false + +additionalProperties: false + +examples: + - | + vpif@217000 { + compatible = "ti,da850-vpif"; + reg = <0x217000 0x1000>; + interrupts = <92>; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + vpif_input_ch0: endpoint@0 { + reg = <0>; + bus-width = <8>; + remote-endpoint = <&composite_in>; + }; + + vpif_input_ch1: endpoint@1 { + reg = <1>; + bus-width = <8>; + data-shift = <8>; + }; + }; + + port@1 { + reg = <1>; + + vpif_output_ch0: endpoint { + bus-width = <8>; + remote-endpoint = <&composite_out>; + }; + }; + }; + + - | + vpif@217000 { + compatible = "ti,da850-vpif"; + reg = <0x217000 0x1000>; + interrupts = <92>; + + port { + vpif_ch0: endpoint { + bus-width = <16>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml index b9f033f2f3ce..bf62998b0445 100644 --- a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml @@ -20,11 +20,44 @@ properties: const: ti,j721e-csi2rx-shim dmas: - maxItems: 1 + minItems: 1 + maxItems: 32 dma-names: + minItems: 1 items: - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - const: rx4 + - const: rx5 + - const: rx6 + - const: rx7 + - const: rx8 + - const: rx9 + - const: rx10 + - const: rx11 + - const: rx12 + - const: rx13 + - const: rx14 + - const: rx15 + - const: rx16 + - const: rx17 + - const: rx18 + - const: rx19 + - const: rx20 + - const: rx21 + - const: rx22 + - const: rx23 + - const: rx24 + - const: rx25 + - const: rx26 + - const: rx27 + - const: rx28 + - const: rx29 + - const: rx30 + - const: rx31 reg: maxItems: 1 @@ -62,8 +95,8 @@ examples: ti_csi2rx0: ticsi2rx@4500000 { compatible = "ti,j721e-csi2rx-shim"; - dmas = <&main_udmap 0x4940>; - dma-names = "rx0"; + dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>; + dma-names = "rx0", "rx1"; reg = <0x4500000 0x1000>; power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/media/ti-am437x-vpfe.txt b/Documentation/devicetree/bindings/media/ti-am437x-vpfe.txt deleted file mode 100644 index 3932e766553a..000000000000 --- a/Documentation/devicetree/bindings/media/ti-am437x-vpfe.txt +++ /dev/null @@ -1,61 +0,0 @@ -Texas Instruments AM437x CAMERA (VPFE) --------------------------------------- - -The Video Processing Front End (VPFE) is a key component for image capture -applications. The capture module provides the system interface and the -processing capability to connect RAW image-sensor modules and video decoders -to the AM437x device. - -Required properties: -- compatible: must be "ti,am437x-vpfe" -- reg: physical base address and length of the registers set for the device; -- interrupts: should contain IRQ line for the VPFE; -- ti,am437x-vpfe-interface: can be one of the following, - 0 - Raw Bayer Interface. - 1 - 8 Bit BT656 Interface. - 2 - 10 Bit BT656 Interface. - 3 - YCbCr 8 Bit Interface. - 4 - YCbCr 16 Bit Interface. - -VPFE supports a single port node with parallel bus. It should contain one -'port' child node with child 'endpoint' node. Please refer to the bindings -defined in Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - vpfe: vpfe@f0034000 { - compatible = "ti,am437x-vpfe"; - reg = <0x48328000 0x2000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&vpfe_pins_default>; - pinctrl-1 = <&vpfe_pins_sleep>; - - port { - #address-cells = <1>; - #size-cells = <0>; - - vpfe0_ep: endpoint { - remote-endpoint = <&ov2659_1>; - ti,am437x-vpfe-interface = <0>; - bus-width = <8>; - hsync-active = <0>; - vsync-active = <0>; - }; - }; - }; - - i2c1: i2c@4802a000 { - - ov2659@30 { - compatible = "ti,ov2659"; - reg = <0x30>; - - port { - ov2659_1: endpoint { - remote-endpoint = <&vpfe0_ep>; - bus-width = <8>; - mclk-frequency = <12000000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index f5f03bf36413..9398aae49093 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -16,7 +16,9 @@ description: | properties: compatible: - const: nvidia,tegra124-emc + enum: + - nvidia,tegra114-emc + - nvidia,tegra124-emc reg: maxItems: 1 @@ -29,6 +31,9 @@ properties: items: - const: emc + interrupts: + maxItems: 1 + "#interconnect-cells": const: 0 @@ -164,153 +169,12 @@ patternProperties: nvidia,emc-configuration: description: EMC timing characterization data. These are the registers (see - section "15.6.2 EMC Registers" in the TRM) whose values need to + section "20.11.2 EMC Registers" in the Tegra114 TRM or section + "15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to be specified, according to the board documentation. $ref: /schemas/types.yaml#/definitions/uint32-array - items: - - description: EMC_RC - - description: EMC_RFC - - description: EMC_RFC_SLR - - description: EMC_RAS - - description: EMC_RP - - description: EMC_R2W - - description: EMC_W2R - - description: EMC_R2P - - description: EMC_W2P - - description: EMC_RD_RCD - - description: EMC_WR_RCD - - description: EMC_RRD - - description: EMC_REXT - - description: EMC_WEXT - - description: EMC_WDV - - description: EMC_WDV_MASK - - description: EMC_QUSE - - description: EMC_QUSE_WIDTH - - description: EMC_IBDLY - - description: EMC_EINPUT - - description: EMC_EINPUT_DURATION - - description: EMC_PUTERM_EXTRA - - description: EMC_PUTERM_WIDTH - - description: EMC_PUTERM_ADJ - - description: EMC_CDB_CNTL_1 - - description: EMC_CDB_CNTL_2 - - description: EMC_CDB_CNTL_3 - - description: EMC_QRST - - description: EMC_QSAFE - - description: EMC_RDV - - description: EMC_RDV_MASK - - description: EMC_REFRESH - - description: EMC_BURST_REFRESH_NUM - - description: EMC_PRE_REFRESH_REQ_CNT - - description: EMC_PDEX2WR - - description: EMC_PDEX2RD - - description: EMC_PCHG2PDEN - - description: EMC_ACT2PDEN - - description: EMC_AR2PDEN - - description: EMC_RW2PDEN - - description: EMC_TXSR - - description: EMC_TXSRDLL - - description: EMC_TCKE - - description: EMC_TCKESR - - description: EMC_TPD - - description: EMC_TFAW - - description: EMC_TRPAB - - description: EMC_TCLKSTABLE - - description: EMC_TCLKSTOP - - description: EMC_TREFBW - - description: EMC_FBIO_CFG6 - - description: EMC_ODT_WRITE - - description: EMC_ODT_READ - - description: EMC_FBIO_CFG5 - - description: EMC_CFG_DIG_DLL - - description: EMC_CFG_DIG_DLL_PERIOD - - description: EMC_DLL_XFORM_DQS0 - - description: EMC_DLL_XFORM_DQS1 - - description: EMC_DLL_XFORM_DQS2 - - description: EMC_DLL_XFORM_DQS3 - - description: EMC_DLL_XFORM_DQS4 - - description: EMC_DLL_XFORM_DQS5 - - description: EMC_DLL_XFORM_DQS6 - - description: EMC_DLL_XFORM_DQS7 - - description: EMC_DLL_XFORM_DQS8 - - description: EMC_DLL_XFORM_DQS9 - - description: EMC_DLL_XFORM_DQS10 - - description: EMC_DLL_XFORM_DQS11 - - description: EMC_DLL_XFORM_DQS12 - - description: EMC_DLL_XFORM_DQS13 - - description: EMC_DLL_XFORM_DQS14 - - description: EMC_DLL_XFORM_DQS15 - - description: EMC_DLL_XFORM_QUSE0 - - description: EMC_DLL_XFORM_QUSE1 - - description: EMC_DLL_XFORM_QUSE2 - - description: EMC_DLL_XFORM_QUSE3 - - description: EMC_DLL_XFORM_QUSE4 - - description: EMC_DLL_XFORM_QUSE5 - - description: EMC_DLL_XFORM_QUSE6 - - description: EMC_DLL_XFORM_QUSE7 - - description: EMC_DLL_XFORM_ADDR0 - - description: EMC_DLL_XFORM_ADDR1 - - description: EMC_DLL_XFORM_ADDR2 - - description: EMC_DLL_XFORM_ADDR3 - - description: EMC_DLL_XFORM_ADDR4 - - description: EMC_DLL_XFORM_ADDR5 - - description: EMC_DLL_XFORM_QUSE8 - - description: EMC_DLL_XFORM_QUSE9 - - description: EMC_DLL_XFORM_QUSE10 - - description: EMC_DLL_XFORM_QUSE11 - - description: EMC_DLL_XFORM_QUSE12 - - description: EMC_DLL_XFORM_QUSE13 - - description: EMC_DLL_XFORM_QUSE14 - - description: EMC_DLL_XFORM_QUSE15 - - description: EMC_DLI_TRIM_TXDQS0 - - description: EMC_DLI_TRIM_TXDQS1 - - description: EMC_DLI_TRIM_TXDQS2 - - description: EMC_DLI_TRIM_TXDQS3 - - description: EMC_DLI_TRIM_TXDQS4 - - description: EMC_DLI_TRIM_TXDQS5 - - description: EMC_DLI_TRIM_TXDQS6 - - description: EMC_DLI_TRIM_TXDQS7 - - description: EMC_DLI_TRIM_TXDQS8 - - description: EMC_DLI_TRIM_TXDQS9 - - description: EMC_DLI_TRIM_TXDQS10 - - description: EMC_DLI_TRIM_TXDQS11 - - description: EMC_DLI_TRIM_TXDQS12 - - description: EMC_DLI_TRIM_TXDQS13 - - description: EMC_DLI_TRIM_TXDQS14 - - description: EMC_DLI_TRIM_TXDQS15 - - description: EMC_DLL_XFORM_DQ0 - - description: EMC_DLL_XFORM_DQ1 - - description: EMC_DLL_XFORM_DQ2 - - description: EMC_DLL_XFORM_DQ3 - - description: EMC_DLL_XFORM_DQ4 - - description: EMC_DLL_XFORM_DQ5 - - description: EMC_DLL_XFORM_DQ6 - - description: EMC_DLL_XFORM_DQ7 - - description: EMC_XM2CMDPADCTRL - - description: EMC_XM2CMDPADCTRL4 - - description: EMC_XM2CMDPADCTRL5 - - description: EMC_XM2DQPADCTRL2 - - description: EMC_XM2DQPADCTRL3 - - description: EMC_XM2CLKPADCTRL - - description: EMC_XM2CLKPADCTRL2 - - description: EMC_XM2COMPPADCTRL - - description: EMC_XM2VTTGENPADCTRL - - description: EMC_XM2VTTGENPADCTRL2 - - description: EMC_XM2VTTGENPADCTRL3 - - description: EMC_XM2DQSPADCTRL3 - - description: EMC_XM2DQSPADCTRL4 - - description: EMC_XM2DQSPADCTRL5 - - description: EMC_XM2DQSPADCTRL6 - - description: EMC_DSR_VTTGEN_DRV - - description: EMC_TXDSRVTTGEN - - description: EMC_FBIO_SPARE - - description: EMC_ZCAL_WAIT_CNT - - description: EMC_MRS_WAIT_CNT2 - - description: EMC_CTT - - description: EMC_CTT_DURATION - - description: EMC_CFG_PIPE - - description: EMC_DYN_SELF_REF_CONTROL - - description: EMC_QPOP + minItems: 97 + maxItems: 143 required: - clock-frequency @@ -318,9 +182,7 @@ patternProperties: - nvidia,emc-auto-cal-config2 - nvidia,emc-auto-cal-config3 - nvidia,emc-auto-cal-interval - - nvidia,emc-bgbias-ctl0 - nvidia,emc-cfg - - nvidia,emc-cfg-2 - nvidia,emc-ctt-term-ctrl - nvidia,emc-mode-1 - nvidia,emc-mode-2 @@ -344,6 +206,22 @@ required: - "#interconnect-cells" - operating-points-v2 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-emc + then: + patternProperties: + "^emc-timings-[0-9]+$": + patternProperties: + "^timing-[0-9]+$": + required: + - nvidia,emc-bgbias-ctl0 + - nvidia,emc-cfg-2 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 7b18b4d11e0a..f8747cebb680 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -19,7 +19,9 @@ description: | properties: compatible: - const: nvidia,tegra124-mc + enum: + - nvidia,tegra114-mc + - nvidia,tegra124-mc reg: maxItems: 1 @@ -64,29 +66,12 @@ patternProperties: nvidia,emem-configuration: $ref: /schemas/types.yaml#/definitions/uint32-array - description: | + description: Values to be written to the EMEM register block. See section - "15.6.1 MC Registers" in the TRM. - items: - - description: MC_EMEM_ARB_CFG - - description: MC_EMEM_ARB_OUTSTANDING_REQ - - description: MC_EMEM_ARB_TIMING_RCD - - description: MC_EMEM_ARB_TIMING_RP - - description: MC_EMEM_ARB_TIMING_RC - - description: MC_EMEM_ARB_TIMING_RAS - - description: MC_EMEM_ARB_TIMING_FAW - - description: MC_EMEM_ARB_TIMING_RRD - - description: MC_EMEM_ARB_TIMING_RAP2PRE - - description: MC_EMEM_ARB_TIMING_WAP2PRE - - description: MC_EMEM_ARB_TIMING_R2R - - description: MC_EMEM_ARB_TIMING_W2W - - description: MC_EMEM_ARB_TIMING_R2W - - description: MC_EMEM_ARB_TIMING_W2R - - description: MC_EMEM_ARB_DA_TURNS - - description: MC_EMEM_ARB_DA_COVERS - - description: MC_EMEM_ARB_MISC0 - - description: MC_EMEM_ARB_MISC1 - - description: MC_EMEM_ARB_RING1_THROTTLE + "20.11.1 MC Registers" in the Tegea114 TRM or + "15.6.1 MC Registers" in the Tegra124 TRM. + minItems: 18 + maxItems: 19 required: - clock-frequency diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 7b03b589168b..6c374e2b1543 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -32,6 +32,7 @@ properties: - nvidia,tegra186-mc - nvidia,tegra194-mc - nvidia,tegra234-mc + - nvidia,tegra238-mc - nvidia,tegra264-mc reg: @@ -269,6 +270,36 @@ allOf: - if: properties: compatible: + const: nvidia,tegra238-mc + then: + properties: + reg: + minItems: 10 + maxItems: 10 + description: 9 memory controller channels and 1 for stream-id registers + + reg-names: + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + + interrupts: + items: + - description: MC general interrupt + + interrupt-names: false + + - if: + properties: + compatible: const: nvidia,tegra264-mc then: properties: diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml index 55caf6905399..a33913fcd11f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml @@ -66,8 +66,8 @@ examples: - | memory-controller@7000f000 { compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400>, /* Controller registers */ - <0x58000000 0x02000000>; /* GART aperture */ + reg = <0x7000f000 0x400>, /* Controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ clocks = <&clock_controller 32>; clock-names = "mc"; diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml index 8e3822314b25..30ad2a858844 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml @@ -13,7 +13,7 @@ description: | Renesas SoCs contain one or more memory controllers. These memory controllers differ from one SoC variant to another, and are called by different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller - (DBSC3)", or "SDRAM Bus State Controller (SBSC)"). + (DBSC3)", or "SDRAM Bus State Controller (SBSC)". properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml index 7a84f5bb7284..cdeca4c795f3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml @@ -30,6 +30,8 @@ properties: - enum: - renesas,r9a09g056-xspi # RZ/V2N - renesas,r9a09g057-xspi # RZ/V2H(P) + - renesas,r9a09g077-xspi # RZ/T2H + - renesas,r9a09g087-xspi # RZ/N2H - const: renesas,r9a09g047-xspi reg: @@ -53,28 +55,38 @@ properties: - const: err_pulse clocks: - items: - - description: AHB clock - - description: AXI clock - - description: SPI clock - - description: Double speed SPI clock + oneOf: + - items: + - description: AHB clock + - description: AXI clock + - description: SPI clock + - description: Double speed SPI clock + - items: + - description: AHB clock + - description: SPI clock clock-names: - items: - - const: ahb - - const: axi - - const: spi - - const: spix2 + oneOf: + - items: + - const: ahb + - const: axi + - const: spi + - const: spix2 + - items: + - const: ahb + - const: spi power-domains: maxItems: 1 resets: + minItems: 1 items: - description: Hardware reset - description: AXI reset reset-names: + minItems: 1 items: - const: hresetn - const: aresetn @@ -109,6 +121,34 @@ required: - '#address-cells' - '#size-cells' +if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g077-xspi + - renesas,r9a09g087-xspi +then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + resets: + maxItems: 1 + reset-names: + maxItems: 1 +else: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + resets: + minItems: 2 + reset-names: + minItems: 2 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml index 783ac984d898..4cd5af38abce 100644 --- a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -128,7 +128,7 @@ examples: "mout_mx_mspll_ccore", "mout_mclk_cdrex"; operating-points-v2 = <&dmc_opp_table>; - devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; diff --git a/Documentation/devicetree/bindings/mfd/apple,smc.yaml b/Documentation/devicetree/bindings/mfd/apple,smc.yaml index 0410e712c900..34ce048619f5 100644 --- a/Documentation/devicetree/bindings/mfd/apple,smc.yaml +++ b/Documentation/devicetree/bindings/mfd/apple,smc.yaml @@ -49,6 +49,9 @@ properties: rtc: $ref: /schemas/rtc/apple,smc-rtc.yaml + hwmon: + $ref: /schemas/hwmon/apple,smc-hwmon.yaml + additionalProperties: false required: @@ -89,5 +92,38 @@ examples: nvmem-cells = <&rtc_offset>; nvmem-cell-names = "rtc_offset"; }; + + hwmon { + compatible = "apple,smc-hwmon"; + + current-ID0R { + apple,key-id = "ID0R"; + label = "AC Input Current"; + }; + + fan-F0Ac { + apple,key-id = "F0Ac"; + apple,fan-minimum = "F0Mn"; + apple,fan-maximum = "F0Mx"; + apple,fan-target = "F0Tg"; + apple,fan-mode = "F0Md"; + label = "Fan 1"; + }; + + power-PSTR { + apple,key-id = "PSTR"; + label = "Total System Power"; + }; + + temperature-TW0P { + apple,key-id = "TW0P"; + label = "WiFi/BT Module Temperature"; + }; + + voltage-VD0R { + apple,key-id = "VD0R"; + label = "AC Input Voltage"; + }; + }; }; }; diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index a87f31fce019..948ba92ef49b 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -46,6 +46,18 @@ properties: '#reset-cells': const: 1 + memory-region: + items: + - description: Region mapped through the first SSP address window. + - description: Region mapped through the second SSP address window. + - description: Region mapped through the TSP address window. + + memory-region-names: + items: + - const: ssp-0 + - const: ssp-1 + - const: tsp + patternProperties: '^p2a-control@[0-9a-f]+$': description: > @@ -87,6 +99,8 @@ patternProperties: - aspeed,ast2400-pinctrl - aspeed,ast2500-pinctrl - aspeed,ast2600-pinctrl + - aspeed,ast2700-soc0-pinctrl + - aspeed,ast2700-soc1-pinctrl required: - compatible @@ -156,6 +170,30 @@ required: - '#clock-cells' - '#reset-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - aspeed,ast2700-scu0 + - aspeed,ast2700-scu1 + then: + patternProperties: + '^p2a-control@[0-9a-f]+$': false + '^smp-memram@[0-9a-f]+$': false + + - if: + not: + properties: + compatible: + contains: + const: aspeed,ast2700-scu0 + then: + properties: + memory-region: false + memory-region-names: false + additionalProperties: false examples: @@ -180,4 +218,81 @@ examples: reg = <0x7c 0x4>, <0x150 0x8>; }; }; + + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssp_region_0: memory@400000000 { + reg = <0x4 0x00000000 0x0 0x01000000>; + no-map; + }; + + ssp_region_1: memory@401000000 { + reg = <0x4 0x01000000 0x0 0x01000000>; + no-map; + }; + + tsp_region: memory@402000000 { + reg = <0x4 0x02000000 0x0 0x01000000>; + no-map; + }; + }; + + bus { + #address-cells = <2>; + #size-cells = <2>; + + syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0 0x12c02000 0 0x1000>; + ranges = <0x0 0x0 0x12c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + memory-region = <&ssp_region_0>, <&ssp_region_1>, + <&tsp_region>; + memory-region-names = "ssp-0", "ssp-1", "tsp"; + + silicon-id@0 { + compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg = <0x0 0x4>; + }; + + interrupt-controller@1b0 { + compatible = "aspeed,ast2700-scu-ic0"; + reg = <0x1b0 0x4>; + #interrupt-cells = <1>; + interrupts-extended = <&intc0 97>; + interrupt-controller; + }; + + interrupt-controller@1e0 { + compatible = "aspeed,ast2700-scu-ic1"; + reg = <0x1e0 0x4>; + #interrupt-cells = <1>; + interrupts-extended = <&intc0 98>; + interrupt-controller; + }; + + pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + emmc-state { + function = "EMMC"; + groups = "EMMCG1"; + }; + }; + }; + }; + }; + ... diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml new file mode 100644 index 000000000000..6f28f472e0f5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/hisilicon,hi655x-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi655x Power Management Integrated Circuit + +maintainers: + - Chen Feng <puck.chen@hisilicon.com> + - Daniel Lezcano <daniel.lezcano@kernel.org> + +description: + The hardware layout for access PMIC Hi655x from AP SoC Hi6220. + Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. + We can use memory-mapped I/O to communicate. + +properties: + compatible: + const: hisilicon,hi655x-pmic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + pmic-gpios: + maxItems: 1 + description: The GPIO used by PMIC IRQ + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + + patternProperties: + '^LDO(2|7|10|13|14|15|17|19|21|22)$': + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - pmic-gpios + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + pmic: pmic@f8000000 { + compatible = "hisilicon,hi655x-pmic"; + reg = <0xf8000000 0x1000>; + #clock-cells = <0>; + interrupt-controller; + #interrupt-cells = <2>; + pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + + regulators { + ldo2: LDO2 { + regulator-name = "LDO2_2V8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt deleted file mode 100644 index 9630ac0e4b56..000000000000 --- a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hi655x Power Management Integrated Circuit (PMIC) - -The hardware layout for access PMIC Hi655x from AP SoC Hi6220. -Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. -We can use memory-mapped I/O to communicate. - -+----------------+ +-------------+ -| | | | -| Hi6220 | SSI bus | Hi655x | -| |-------------| | -| |(REGMAP_MMIO)| | -+----------------+ +-------------+ - -Required properties: -- compatible: Should be "hisilicon,hi655x-pmic". -- reg: Base address of PMIC on Hi6220 SoC. -- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain). -- pmic-gpios: The GPIO used by PMIC IRQ. -- #clock-cells: From common clock binding; shall be set to 0 - -Optional properties: -- clock-output-names: From common clock binding to override the - default output clock name - -Example: - pmic: pmic@f8000000 { - compatible = "hisilicon,hi655x-pmic"; - reg = <0x0 0xf8000000 0x0 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - #clock-cells = <0>; - } diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml index 084960fd5a1f..c6f91e7bc8aa 100644 --- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml +++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - khadas,mcu # MCU revision is discoverable + - khadas,vim4-mcu # Different MCU variant, not discoverable "#cooling-cells": # Only needed for boards having FAN control feature const: 2 @@ -25,10 +26,26 @@ properties: reg: maxItems: 1 + fan-supply: + description: Phandle to the regulator that powers the fan. + required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + const: khadas,vim4-mcu + then: + required: + - fan-supply + else: + properties: + fan-supply: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml b/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml index 92a72a99fd79..940262898353 100644 --- a/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml +++ b/Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml @@ -29,7 +29,7 @@ properties: type: object additionalProperties: false patternProperties: - "^(ldo(1[0-6]|[1-9])|buck[1-5])$": + "^(ldo(1[0-6]|[1-9])|buck[1-5]|vbus)$": type: object $ref: /schemas/regulator/regulator.yaml# description: LDO or buck regulator. diff --git a/Documentation/devicetree/bindings/mfd/maxim,max77620.yaml b/Documentation/devicetree/bindings/mfd/maxim,max77620.yaml index 602711865274..ac063c2bab73 100644 --- a/Documentation/devicetree/bindings/mfd/maxim,max77620.yaml +++ b/Documentation/devicetree/bindings/mfd/maxim,max77620.yaml @@ -311,7 +311,7 @@ examples: in-sd3-supply = <&vdd_5v0_vbus>; in-ldo0-1-supply = <&vdd_1v8_vio>; - in-ldo2-supply = <&vdd_3v3_vbat>; + in-ldo2-supply = <&vdd_3v3_vbat>; in-ldo3-5-supply = <&vdd_3v3_vbat>; in-ldo4-6-supply = <&vdd_3v3_vbat>; in-ldo7-8-supply = <&vdd_1v8_vio>; diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 05c121b0cb3d..3cbc0dc12c31 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -44,6 +44,10 @@ properties: - enum: - mediatek,mt6366 - const: mediatek,mt6358 + - items: + - enum: + - mediatek,mt6365 + - const: mediatek,mt6359 interrupts: maxItems: 1 @@ -70,6 +74,8 @@ properties: - mediatek,mt6397-rtc - items: - enum: + - mediatek,mt6359-rtc + - mediatek,mt6365-rtc - mediatek,mt6366-rtc - const: mediatek,mt6358-rtc @@ -98,6 +104,10 @@ properties: - enum: - mediatek,mt6366-regulator - const: mediatek,mt6358-regulator + - items: + - enum: + - mediatek,mt6365-regulator + - const: mediatek,mt6359-regulator required: - compatible @@ -124,6 +134,10 @@ properties: - enum: - mediatek,mt6366-sound - const: mediatek,mt6358-sound + - items: + - enum: + - mediatek,mt6365-codec + - const: mediatek,mt6359-codec required: - compatible @@ -225,12 +239,62 @@ properties: description: Pin controller + vsys-smps-supply: + description: Supply for regulator control logic + +patternProperties: + "^vsys-v[a-z]+[0-9]*-supply$": + description: Supplies for PMIC buck regulators + "^vs(ys|[12])-ldo[1-9]-supply$": + description: Supplies for PMIC LDO regulators + required: - compatible - regulators additionalProperties: false +allOf: + - if: + properties: + "compatible": + contains: + const: mediatek,mt6359 + then: + properties: + vsys-ldo1-supply: + description: Supply for LDOs vcn33_[12], vio28, vfe28, vibr + vsys-ldo2-supply: + description: Supply for LDOs vaux18, vbif28, vxo22, vrfck, vrfck_1, + vemc, vsim1, vsim2, vusb + vsys-vcore-supply: + description: Supply for buck regulator vcore + vsys-vgpu11-supply: + description: Supply for buck regulator vgpu11 + vsys-vmodem-supply: + description: Supply for buck regulator vmodem + vsys-vpa-supply: + description: Supply for buck regulator vpa + vsys-vproc1-supply: + description: Supply for buck regulator vproc1 + vsys-vproc2-supply: + description: Supply for buck regulator vproc2 + vsys-vpu-supply: + description: Supply for buck regulator vpu + vsys-vs1-supply: + description: Supply for buck regulator vs1 + vsys-vs2-supply: + description: Supply for buck regulator vs2 + vs1-ldo1-supply: + description: Supply for LDOs vaud18, vcamio, vm18, vufs + vs1-ldo2-supply: + description: Supply for LDOs vcn18, vefuse, vio18, vrf18 + vs2-ldo1-supply: + description: + Supply for LDOs vsram_proc1, vsram_proc2, vsram_others, vsram_md + vs2-ldo2-supply: + description: Supply for LDOs va09, va12, vcn13, vrf12 + examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml index 4cafa381979b..9f073d0c28ef 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8183-scpsys - mediatek,mt8186-scpsys - mediatek,mt8188-scpsys + - mediatek,mt8189-scpsys - mediatek,mt8192-scpsys - mediatek,mt8195-scpsys - mediatek,mt8365-scpsys diff --git a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt b/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt deleted file mode 100644 index c58d70437fce..000000000000 --- a/Documentation/devicetree/bindings/mfd/omap-usb-tll.txt +++ /dev/null @@ -1,27 +0,0 @@ -OMAP HS USB Host TLL (Transceiver-Less Interface) - -Required properties: - -- compatible : should be "ti,usbhs-tll" -- reg : should contain one register range i.e. start and length -- interrupts : should contain the TLL module's interrupt -- ti,hwmod : must contain "usb_tll_hs" - -Optional properties: - -- clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. - -- clock-names: should include: - * "usb_tll_hs_usb_ch0_clk" - USB TLL channel 0 clock - * "usb_tll_hs_usb_ch1_clk" - USB TLL channel 1 clock - * "usb_tll_hs_usb_ch2_clk" - USB TLL channel 2 clock - -Example: - - usbhstll: usbhstll@4a062000 { - compatible = "ti,usbhs-tll"; - reg = <0x4a062000 0x1000>; - interrupts = <78>; - ti,hwmods = "usb_tll_hs"; - }; diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index 644c42b5e2e5..5e0ed30a9a46 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -80,6 +80,7 @@ properties: - qcom,pmcx0102 - qcom,pmd8028 - qcom,pmd9635 + - qcom,pmg1110 - qcom,pmh0101 - qcom,pmh0104 - qcom,pmh0110 @@ -165,6 +166,10 @@ patternProperties: type: object $ref: /schemas/pinctrl/qcom,pmic-gpio.yaml# + "^haptics@[0-9a-f]+$": + type: object + $ref: /schemas/input/qcom,spmi-haptics.yaml# + "^led-controller@[0-9a-f]+$": type: object $ref: /schemas/leds/qcom,spmi-flash-led.yaml# @@ -193,6 +198,10 @@ patternProperties: type: object $ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml# + "^temperature-sensor@[0-9a-f]+$": + type: object + $ref: /schemas/thermal/qcom,pm8775-mbg-tm.yaml# + "^typec@[0-9a-f]+$": type: object $ref: /schemas/usb/qcom,pmic-typec.yaml# diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 14ae3f00ef7e..c3889f974ed3 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -17,8 +17,11 @@ properties: compatible: items: - enum: + - qcom,hawi-tcsr + - qcom,maili-tcsr - qcom,msm8976-tcsr - qcom,msm8998-tcsr + - qcom,nord-tcsr - qcom,qcm2290-tcsr - qcom,qcs404-tcsr - qcom,qcs615-tcsr @@ -33,6 +36,7 @@ properties: - qcom,sdx55-tcsr - qcom,sdx65-tcsr - qcom,sdx75-tcsr + - qcom,shikra-tcsr - qcom,sm4450-tcsr - qcom,sm6115-tcsr - qcom,sm8150-tcsr @@ -42,12 +46,14 @@ properties: - qcom,tcsr-apq8064 - qcom,tcsr-apq8084 - qcom,tcsr-ipq5018 + - qcom,tcsr-ipq5210 - qcom,tcsr-ipq5332 - qcom,tcsr-ipq5424 - qcom,tcsr-ipq6018 - qcom,tcsr-ipq8064 - qcom,tcsr-ipq8074 - qcom,tcsr-ipq9574 + - qcom,tcsr-ipq9650 - qcom,tcsr-mdm9615 - qcom,tcsr-msm8226 - qcom,tcsr-msm8660 diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml index 0676890f101e..a58d9455a1a5 100644 --- a/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml @@ -44,8 +44,7 @@ properties: description: Telling whether or not this PMIC is controlling the system power. - wakeup-source: - type: boolean + wakeup-source: true vcc1-supply: description: diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml b/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml new file mode 100644 index 000000000000..aff68c035b38 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mu005-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MU005 Power Management IC + +maintainers: + - Kaustabh Chakraborty <kauschluss@disroot.org> + +description: | + The S2MU005 is a companion power management IC which includes subdevices for + a charger controller, an MUIC (Micro USB Interface Controller), and flash and + RGB LED controllers. + +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + +properties: + compatible: + const: samsung,s2mu005-pmic + + flash: + $ref: /schemas/leds/samsung,s2mu005-flash.yaml# + description: + Child node describing flash LEDs. + + interrupts: + maxItems: 1 + + muic: + $ref: /schemas/extcon/samsung,s2mu005-muic.yaml# + description: + Child node describing MUIC device. + + multi-led: + type: object + + allOf: + - $ref: /schemas/leds/leds-class-multicolor.yaml# + + properties: + compatible: + const: samsung,s2mu005-rgb + + required: + - compatible + + unevaluatedProperties: false + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@3d { + compatible = "samsung,s2mu005-pmic"; + reg = <0x3d>; + interrupt-parent = <&gpa2>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + monitored-battery = <&battery>; + + flash { + compatible = "samsung,s2mu005-flash"; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_FLASH; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_WHITE>; + function = LED_FUNCTION_FLASH; + function-enumerator = <1>; + }; + }; + + muic { + compatible = "samsung,s2mu005-muic"; + + connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; + + port { + muic_to_usb: endpoint { + remote-endpoint = <&usb_to_muic>; + }; + }; + }; + + multi-led { + compatible = "samsung,s2mu005-rgb"; + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "pattern"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml b/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml index b023e1ef8d3c..e74ec4970994 100644 --- a/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml +++ b/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml @@ -54,7 +54,9 @@ properties: regulators: type: object - $ref: /schemas/regulator/sprd,sc2731-regulator.yaml# + oneOf: + - $ref: /schemas/regulator/sprd,sc2730-regulator.yaml# + - $ref: /schemas/regulator/sprd,sc2731-regulator.yaml# patternProperties: "^adc@[0-9a-f]+$": diff --git a/Documentation/devicetree/bindings/mfd/st,stmpe.yaml b/Documentation/devicetree/bindings/mfd/st,stmpe.yaml index df43878fbe18..ddb27ae64ba3 100644 --- a/Documentation/devicetree/bindings/mfd/st,stmpe.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stmpe.yaml @@ -20,7 +20,7 @@ allOf: properties: compatible: enum: - - st,stmpe601 + - st,stmpe610 - st,stmpe801 - st,stmpe811 - st,stmpe1600 @@ -127,6 +127,10 @@ properties: "#pwm-cells": const: 2 + required: + - compatible + - "#pwm-cells" + touchscreen: type: object $ref: /schemas/input/touchscreen/touchscreen.yaml# diff --git a/Documentation/devicetree/bindings/mfd/syscon-common.yaml b/Documentation/devicetree/bindings/mfd/syscon-common.yaml index 14a08e7bc8bd..2d5eef5add54 100644 --- a/Documentation/devicetree/bindings/mfd/syscon-common.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon-common.yaml @@ -32,6 +32,7 @@ properties: compatible: contains: const: syscon + # Always require a specific compatible for syscon minItems: 2 maxItems: 5 # Should be enough @@ -52,11 +53,44 @@ allOf: contains: const: simple-mfd then: + # Always require a specific compatible for syscon with simple-mfd properties: compatible: minItems: 3 maxItems: 5 + - if: + properties: + compatible: + contains: + const: simple-bus + then: + # simple-bus conflicts with syscon - if a device is a system controller + # with miscellaneous registers, then it has at least one dedicated + # function thus it is not a simple bus. Allow existing exceptions. + if: + properties: + compatible: + not: + contains: + # This list CANNOT grow + enum: + - cznic,turris1x-cpld + - img,pistachio-cr-periph + - ti,am3352-scm-conf + - ti,am4372-scm-conf + - ti,dm814-scm-conf + - ti,dm8168-scm-conf + - ti,dra7-scm-conf + - ti,omap2-scm-conf + - ti,omap3-scm-conf + - ti,omap4-sysc-padconf-global + - ti,omap5-scm-wkup-conf + - ti,omap5-sysc-padconf-global + then: + required: + - incorrect-usage-of-simple-bus-and-syscon + additionalProperties: true examples: diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index e22867088063..945a168b613d 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -19,122 +19,6 @@ description: | maintainers: - Lee Jones <lee@kernel.org> -# Need a select with all compatibles listed for compatibility with older -# dtschema (<2024.02), so this will not be selected for other schemas having -# syscon fallback. -select: - properties: - compatible: - contains: - enum: - - airoha,en7581-pbus-csr - - al,alpine-sysfabric-service - - allwinner,sun8i-a83t-system-controller - - allwinner,sun8i-h3-system-controller - - allwinner,sun8i-v3s-system-controller - - allwinner,sun50i-a64-system-controller - - altr,l3regs - - altr,sdr-ctl - - amd,pensando-elba-syscon - - amlogic,meson-mx-assist - - amlogic,meson-mx-bootrom - - amlogic,meson8-analog-top - - amlogic,meson8b-analog-top - - amlogic,meson8-pmu - - amlogic,meson8b-pmu - - apm,merlin-poweroff-mailbox - - apm,mustang-poweroff-mailbox - - apm,xgene-csw - - apm,xgene-efuse - - apm,xgene-mcb - - apm,xgene-rb - - apm,xgene-scu - - atmel,sama5d2-sfrbu - - atmel,sama5d3-nfc-io - - atmel,sama5d3-sfrbu - - atmel,sama5d4-sfrbu - - axis,artpec6-syscon - - brcm,cru-clkset - - brcm,sr-cdru - - brcm,sr-mhb - - cirrus,ep7209-syscon1 - - cirrus,ep7209-syscon2 - - cirrus,ep7209-syscon3 - - cnxt,cx92755-uc - - econet,en751221-chip-scu - - freecom,fsg-cs2-system-controller - - fsl,imx93-aonmix-ns-syscfg - - fsl,imx93-wakeupmix-syscfg - - fsl,ls1088a-reset - - fsl,vf610-anatop - - fsl,vf610-mscm-cpucfg - - hisilicon,dsa-subctrl - - hisilicon,hi6220-sramctrl - - hisilicon,hip04-ppe - - hisilicon,pcie-sas-subctrl - - hisilicon,peri-subctrl - - hpe,gxp-sysreg - - loongson,ls1b-syscon - - loongson,ls1c-syscon - - lsi,axxia-syscon - - marvell,armada-3700-cpu-misc - - marvell,armada-3700-nb-pm - - marvell,armada-3700-avs - - marvell,armada-3700-usb2-host-device-misc - - marvell,armada-3700-usb2-host-misc - - marvell,dove-global-config - - mediatek,mt2701-pctl-a-syscfg - - mediatek,mt2712-pctl-a-syscfg - - mediatek,mt6397-pctl-pmic-syscfg - - mediatek,mt7981-topmisc - - mediatek,mt7988-topmisc - - mediatek,mt8135-pctl-a-syscfg - - mediatek,mt8135-pctl-b-syscfg - - mediatek,mt8173-pctl-a-syscfg - - mediatek,mt8365-syscfg - - microchip,lan966x-cpu-syscon - - microchip,mpfs-control-scb - - microchip,mpfs-sysreg-scb - - microchip,sam9x60-sfr - - microchip,sama7d65-ddr3phy - - microchip,sama7d65-sfrbu - - microchip,sama7g5-ddr3phy - - mscc,ocelot-cpu-syscon - - mstar,msc313-pmsleep - - nuvoton,ma35d1-sys - - nuvoton,wpcm450-shm - - nxp,s32g2-gpr - - nxp,s32g3-gpr - - qcom,apq8064-mmss-sfpb - - qcom,apq8064-sps-sic - - rockchip,px30-qos - - rockchip,rk3036-qos - - rockchip,rk3066-qos - - rockchip,rk3128-qos - - rockchip,rk3228-qos - - rockchip,rk3288-qos - - rockchip,rk3368-qos - - rockchip,rk3399-qos - - rockchip,rk3528-qos - - rockchip,rk3562-qos - - rockchip,rk3568-qos - - rockchip,rk3576-qos - - rockchip,rk3588-qos - - rockchip,rv1126-qos - - st,spear1340-misc - - stericsson,nomadik-pmu - - starfive,jh7100-sysmain - - ti,am62-opp-efuse-table - - ti,am62-usb-phy-ctrl - - ti,am625-dss-oldi-io-ctrl - - ti,am62p-cpsw-mac-efuse - - ti,am654-dss-oldi-io-ctrl - - ti,j784s4-acspcie-proxy-ctrl - - ti,j784s4-pcie-ctrl - - ti,keystone-pllctrl - required: - - compatible - properties: compatible: oneOf: @@ -175,6 +59,7 @@ properties: - cirrus,ep7209-syscon3 - cnxt,cx92755-uc - econet,en751221-chip-scu + - eswin,eic7700-syscfg - freecom,fsg-cs2-system-controller - fsl,imx93-aonmix-ns-syscfg - fsl,imx93-wakeupmix-syscfg @@ -189,6 +74,7 @@ properties: - hpe,gxp-sysreg - loongson,ls1b-syscon - loongson,ls1c-syscon + - loongson,ls2k0300-chipid-syscon - lsi,axxia-syscon - marvell,armada-3700-cpu-misc - marvell,armada-3700-nb-pm diff --git a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml index ba14663c9266..cdce83f05804 100644 --- a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml @@ -4,17 +4,16 @@ $id: http://devicetree.org/schemas/mfd/ti,bq25703a.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: BQ25703A Charger Manager/Buck/Boost Converter +title: BQ257xx Charger Manager/Buck/Boost Converter maintainers: - Chris Morgan <macromorgan@hotmail.com> -allOf: - - $ref: /schemas/power/supply/power-supply.yaml# - properties: compatible: - const: ti,bq25703a + enum: + - ti,bq25703a + - ti,bq25792 reg: const: 0x6b @@ -25,7 +24,6 @@ properties: powering the device. minimum: 50000 maximum: 6400000 - default: 3250000 interrupts: maxItems: 1 @@ -57,11 +55,11 @@ properties: minimum: 0 maximum: 6350000 regulator-min-microvolt: - minimum: 4480000 - maximum: 20800000 + minimum: 2800000 + maximum: 22000000 regulator-max-microvolt: - minimum: 4480000 - maximum: 20800000 + minimum: 2800000 + maximum: 22000000 enable-gpios: description: The BQ25703 may require both a register write and a GPIO @@ -74,6 +72,61 @@ properties: - regulator-min-microvolt - regulator-max-microvolt +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + - if: + properties: + compatible: + const: ti,bq25703a + then: + properties: + input-current-limit-microamp: + minimum: 50000 + maximum: 6400000 + default: 3250000 + regulators: + properties: + vbus: + properties: + regulator-min-microamp: + minimum: 0 + maximum: 6350000 + regulator-max-microamp: + minimum: 0 + maximum: 6350000 + regulator-min-microvolt: + minimum: 4480000 + maximum: 20800000 + regulator-max-microvolt: + minimum: 4480000 + maximum: 20800000 + - if: + properties: + compatible: + const: ti,bq25792 + then: + properties: + input-current-limit-microamp: + minimum: 100000 + maximum: 3300000 + default: 3000000 + regulators: + properties: + vbus: + properties: + regulator-min-microamp: + minimum: 0 + maximum: 3320000 + regulator-max-microamp: + minimum: 0 + maximum: 3320000 + regulator-min-microvolt: + minimum: 2800000 + maximum: 22000000 + regulator-max-microvolt: + minimum: 2800000 + maximum: 22000000 + unevaluatedProperties: false required: diff --git a/Documentation/devicetree/bindings/mfd/ti,usbhs-tll.yaml b/Documentation/devicetree/bindings/mfd/ti,usbhs-tll.yaml new file mode 100644 index 000000000000..78f7a109392c --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/ti,usbhs-tll.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,usbhs-tll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP HS USB Host TLL (Transceiver-Less Interface) + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +properties: + compatible: + const: ti,usbhs-tll + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ti,hwmods: + description: Name of the hwmod associated with the USB TLL. + $ref: /schemas/types.yaml#/definitions/string + const: usb_tll_hs + + clocks: + minItems: 1 + maxItems: 3 + description: A list of phandles and clock-specifier pairs. + + clock-names: + minItems: 1 + items: + - const: usb_tll_hs_usb_ch0_clk + - const: usb_tll_hs_usb_ch1_clk + - const: usb_tll_hs_usb_ch2_clk + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + usb-tll@4a062000 { + compatible = "ti,usbhs-tll"; + reg = <0x4a062000 0x1000>; + interrupts = <78>; + ti,hwmods = "usb_tll_hs"; + }; diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml index df45ff56d444..801f305e0374 100644 --- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml +++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml @@ -166,7 +166,7 @@ examples: */ ranges = <0x0 0x0 0x8 0x0c000000 0x4000000 0x1 0x0 0x8 0x18000000 0x8000000>; - + /* define map for ICIDs 23-64 */ iommu-map = <23 &smmu 23 41>; /* define msi map for ICIDs 23-64 */ diff --git a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml index ca830dd06de2..49d2a5e8ba39 100644 --- a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml +++ b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml @@ -25,6 +25,9 @@ properties: - items: - enum: - qcom,glymur-fastrpc + - qcom,hawi-fastrpc + - qcom,maili-fastrpc + - qcom,nord-fastrpc - const: qcom,kaanapali-fastrpc label: @@ -34,6 +37,8 @@ properties: - sdsp - cdsp - cdsp1 + - cdsp2 + - cdsp3 - gdsp0 - gdsp1 diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 9f3b1edacaa0..9e9610bb1eda 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -56,7 +56,9 @@ properties: - const: allwinner,sun50i-h616-mmc - const: allwinner,sun50i-a100-mmc - items: - - const: allwinner,sun55i-a523-mmc + - enum: + - allwinner,sun55i-a523-mmc + - allwinner,sun60i-a733-mmc - const: allwinner,sun20i-d1-mmc reg: diff --git a/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml index 41c9b22523e7..e447579e0f22 100644 --- a/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml @@ -39,10 +39,11 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array description: | DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path. - It is integrated into CRG core on the SoC and has to be controlled during tuning. + It is integrated into CRG core on the SoC and has to be controlled during tuning items: - - description: A phandle pointed to the CRG syscon node - - description: Sample DLL register offset in CRG address space + - items: + - description: A phandle pointed to the CRG syscon node + - description: Sample DLL register offset in CRG address space required: - compatible diff --git a/Documentation/devicetree/bindings/mmc/mmc-card.yaml b/Documentation/devicetree/bindings/mmc/mmc-card.yaml index a61d6c96df75..042289450847 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-card.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-card.yaml @@ -38,7 +38,9 @@ patternProperties: properties: compatible: contains: - const: fixed-partitions + enum: + - fixed-partitions + - fixed-layout required: - compatible @@ -86,6 +88,25 @@ examples: read-only; }; }; + + partitions-boot2 { + compatible = "fixed-layout"; + + #address-cells = <1>; + #size-cells = <1>; + + mac-addr@4400 { + compatible = "mac-base"; + reg = <0x4400 0x6>; + #nvmem-cell-cells = <1>; + }; + + bd-addr@5400 { + compatible = "mac-base"; + reg = <0x5400 0x6>; + #nvmem-cell-cells = <1>; + }; + }; }; }; diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index eb3755bdfdf7..a4d032224dce 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -193,7 +193,6 @@ allOf: - mediatek,mt8183-mmc - mediatek,mt8186-mmc - mediatek,mt8188-mmc - - mediatek,mt8189-mmc - mediatek,mt8195-mmc - mediatek,mt8196-mmc - mediatek,mt8516-mmc @@ -348,6 +347,34 @@ allOf: - const: axi_cg - const: ahb_cg + - if: + properties: + compatible: + contains: + const: mediatek,mt8189-mmc + then: + properties: + clocks: + minItems: 6 + items: + - description: source clock + - description: HCLK which used for host + - description: independent source clock gate + - description: bus clock used for internal register access + - description: peripheral bus clock gate + - description: AXI bus clock gate + - description: crypto clock used for data encrypt/decrypt (optional) + clock-names: + minItems: 6 + items: + - const: source + - const: hclk + - const: source_cg + - const: bus_clk + - const: pclk_cg + - const: axi_cg + - const: crypto + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index 72987f0326a1..3cac067c7c98 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -39,6 +39,12 @@ properties: - nvidia,tegra234-sdhci - const: nvidia,tegra186-sdhci + - items: + - enum: + - nvidia,tegra238-sdhci + - nvidia,tegra264-sdhci + - const: nvidia,tegra194-sdhci + reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml index 695a95e8f35d..b3fcc1673c10 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml# +$id: http://devicetree.org/schemas/mmc/qcom,sdhci-msm.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm SDHCI controller (sdhci-msm) @@ -37,6 +37,8 @@ properties: - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 - items: - enum: + - qcom,eliza-sdhci + - qcom,hawi-sdhci - qcom,ipq5018-sdhci - qcom,ipq5210-sdhci - qcom,ipq5332-sdhci @@ -62,6 +64,7 @@ properties: - qcom,sdx55-sdhci - qcom,sdx65-sdhci - qcom,sdx75-sdhci + - qcom,shikra-sdhci - qcom,sm6115-sdhci - qcom,sm6125-sdhci - qcom,sm6350-sdhci @@ -142,6 +145,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: platform specific settings for DLL_CONFIG reg. + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the Inline Crypto Engine (ICE) hardware block for this controller. + iommus: minItems: 1 maxItems: 8 @@ -195,35 +203,69 @@ allOf: enum: - qcom,sdhci-msm-v4 then: - properties: - reg: - minItems: 2 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 2 - items: - - const: hc - - const: core - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + else: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice else: - properties: - reg: - minItems: 1 - items: - - description: Host controller register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 1 - items: - - const: hc - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 64fac0d11329..4d66966ce290 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -52,6 +52,7 @@ properties: - renesas,sdhi-r8a77980 # R-Car V3H - renesas,sdhi-r8a77990 # R-Car E3 - renesas,sdhi-r8a77995 # R-Car D3 + - renesas,sdhi-r8a779md # R-Car M3Le - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 - items: - enum: diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml index 4965bb518c54..21ecfaa454f4 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml @@ -43,6 +43,7 @@ properties: - rockchip,rk3562-dw-mshc - rockchip,rk3568-dw-mshc - rockchip,rk3588-dw-mshc + - rockchip,rv1106-dw-mshc - rockchip,rv1108-dw-mshc - rockchip,rv1126-dw-mshc - const: rockchip,rk3288-dw-mshc diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index 27c4060f2f91..223fcc9f651f 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -85,7 +85,7 @@ properties: description: | The value of CIU TX and RX clock phase shift value for HS400 mode operation. - Valid values for SDR and DDR CIU clock timing:: + Valid values for SDR and DDR CIU clock timing: - valid value for tx phase shift and rx phase shift is 0 to 7. - when CIU clock divider value is set to 3, all possible 8 phase shift values can be used. diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt deleted file mode 100644 index ccf82b4ee838..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt +++ /dev/null @@ -1,110 +0,0 @@ -* STMicroelectronics sdhci-st MMC/SD controller - -This file documents the differences between the core properties in -Documentation/devicetree/bindings/mmc/mmc.txt and the properties -used by the sdhci-st driver. - -Required properties: -- compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407" - to set the internal glue logic used for configuring the MMC - subsystem (mmcss) inside the FlashSS (available in STiH407 SoC - family). - -- clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory) - See: Documentation/devicetree/bindings/resource-names.txt -- clocks: Phandle to the clock. - See: Documentation/devicetree/bindings/clock/clock-bindings.txt - -- interrupts: One mmc interrupt should be described here. -- interrupt-names: Should be "mmcirq". - -- pinctrl-names: A pinctrl state names "default" must be defined. -- pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller. - See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -- reg: This must provide the host controller base address and it can also - contain the FlashSS Top register for TX/RX delay used by the driver - to configure DLL inside the flashSS, if so reg-names must also be - specified. - -Optional properties: -- reg-names: Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional - for eMMC on stih407 family silicon to configure DLL inside FlashSS. - -- non-removable: Non-removable slot. Also used for configuring mmcss in STiH407 SoC - family. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- bus-width: Number of data lines. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for - configuring the CCONFIG3 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- resets: Phandle and reset specifier pair to softreset line of HC IP. - See: Documentation/devicetree/bindings/reset/reset.txt - -- vqmmc-supply: Phandle to the regulator dt node, mentioned as the vcc/vdd - supply in eMMC/SD specs. - -- sd-uhs-sdr50: To enable the SDR50 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- sd-uhs-sdr104: To enable the SDR104 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -- sd-uhs-ddr50: To enable the DDR50 in the mmcss. - See: Documentation/devicetree/bindings/mmc/mmc.txt. - -Example: - -/* Example stih416e eMMC configuration */ - -mmc0: sdhci@fe81e000 { - compatible = "st,sdhci"; - reg = <0xfe81e000 0x1000>; - interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_a1_ls 1>; - bus-width = <8> - -/* Example SD stih407 family configuration */ - -mmc1: sdhci@9080000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - reg = <0x09080000 0x7ff>; - reg-names = "mmc"; - interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1>; - clock-names = "mmc"; - clocks = <&clk_s_c0_flexgen CLK_MMC_1>; - resets = <&softreset STIH407_MMC1_SOFTRESET>; - bus-width = <4>; -}; - -/* Example eMMC stih407 family configuration */ - -mmc0: sdhci@9060000 { - compatible = "st,sdhci-stih407", "st,sdhci"; - reg = <0x09060000 0x7ff>, <0x9061008 0x20>; - reg-names = "mmc", "top-mmc-delay"; - interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; - interrupt-names = "mmcirq"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc0>; - clock-names = "mmc"; - clocks = <&clk_s_c0_flexgen CLK_MMC_0>; - vqmmc-supply = <&vmmc_reg>; - max-frequency = <200000000>; - bus-width = <8>; - non-removable; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; -}; diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml index 9a055d963a7f..34d202af909f 100644 --- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml @@ -44,6 +44,18 @@ properties: - const: axi - const: sdh + pinctrl-names: + minItems: 1 + items: + - const: default + - const: uhs + + pinctrl-0: + description: Default pinctrl state for 3.3V operation + + pinctrl-1: + description: Optional pinctrl state for 1.8V UHS operation with "uhs" name + required: - compatible - reg @@ -62,4 +74,7 @@ examples: interrupt-parent = <&plic>; clocks = <&clk_apmu 10>, <&clk_apmu 13>; clock-names = "core", "io"; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&sdhci_default_cfg>; + pinctrl-1 = <&sdhci_uhs_cfg>; }; diff --git a/Documentation/devicetree/bindings/mmc/st,sdhci.yaml b/Documentation/devicetree/bindings/mmc/st,sdhci.yaml new file mode 100644 index 000000000000..798af599d374 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/st,sdhci.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/st,sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics SDHCI-ST MMC/SD Controller + +maintainers: + - Peter Griffin <peter.griffin@linaro.org> + +description: + The STMicroelectronics SDHCI-ST MMC/SD host controller is compliant with + the SD Host Controller Interface (SDHCI) specification and is used to + interface with MMC, SD and SDIO cards. The ST SDHCI controller extends the + standard SDHCI capabilities with platform-specific configurations such as + additional register regions, clock inputs, and delay control mechanisms + required for signal timing adjustments to support high-speed modes across + different ST SoCs. + +allOf: + - $ref: mmc-controller.yaml# + - if: + properties: + reg: + minItems: 2 + required: + - reg + then: + required: + - reg-names + +properties: + compatible: + oneOf: + - const: st,sdhci + - items: + - const: st,sdhci-stih407 + - const: st,sdhci + + reg: + minItems: 1 + items: + - description: MMC controller base registers + - description: FlashSS Top registers for TX/RX DLL delay configuration + + reg-names: + minItems: 1 + items: + - const: mmc + - const: top-mmc-delay + + clocks: + minItems: 1 + items: + - description: Clock for the MMC controller + - description: Interconnect (ICN) clock + + clock-names: + minItems: 1 + items: + - const: mmc + - const: icn + + interrupts: + maxItems: 1 + + interrupt-names: + const: mmcirq + + resets: + maxItems: 1 + + max-frequency: + enum: [200000000, 100000000, 50000000] + default: 50000000 + +required: + - reg + - compatible + - clocks + - clock-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/stih407-clks.h> + mmc@9060000 { + compatible = "st,sdhci-stih407", "st,sdhci"; + reg = <0x09060000 0x7ff>, <0x9061008 0x20>; + reg-names = "mmc", "top-mmc-delay"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc", "icn"; + clocks = <&clk_s_c0_flexgen CLK_MMC_0>, + <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; + bus-width = <8>; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/ti,omap2420-mmc.yaml b/Documentation/devicetree/bindings/mmc/ti,omap2420-mmc.yaml new file mode 100644 index 000000000000..794d5ec0b58e --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/ti,omap2420-mmc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/ti,omap2420-mmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments MMC host controller for OMAP1 and 2420 + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +description: | + The MMC Host Controller on TI OMAP1 and 2420 family provides + an interface for MMC, SD, and SDIO types of memory cards. + +allOf: + - $ref: /schemas/mmc/mmc-controller.yaml# + +properties: + compatible: + const: ti,omap2420-mmc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ti,hwmods: + description: | + Name of the hwmod associated to the MMC controller. Must be + "msdi<n>" where n is the controller instance starting from 1. + $ref: /schemas/types.yaml#/definitions/string + pattern: "^msdi([1-9]|[1-9][0-9]+)$" + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + mmc@4809c000 { + compatible = "ti,omap2420-mmc"; + ti,hwmods = "msdi1"; + reg = <0x4809c000 0x80>; + interrupts = <83>; + dmas = <&sdma 61 &sdma 62>; + dma-names = "tx", "rx"; + }; diff --git a/Documentation/devicetree/bindings/mmc/ti-omap.txt b/Documentation/devicetree/bindings/mmc/ti-omap.txt deleted file mode 100644 index 02fd31cf361d..000000000000 --- a/Documentation/devicetree/bindings/mmc/ti-omap.txt +++ /dev/null @@ -1,26 +0,0 @@ -* TI MMC host controller for OMAP1 and 2420 - -The MMC Host Controller on TI OMAP1 and 2420 family provides -an interface for MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the omap mmc driver. - -Note that this driver will not work with omap2430 or later omaps, -please see the omap hsmmc driver for the current omaps. - -Required properties: -- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers -- ti,hwmods: For 2420, must be "msdi<n>", where n is controller - instance starting 1 - -Examples: - - msdi1: mmc@4809c000 { - compatible = "ti,omap2420-mmc"; - ti,hwmods = "msdi1"; - reg = <0x4809c000 0x80>; - interrupts = <83>; - dmas = <&sdma 61 &sdma 62>; - dma-names = "tx", "rx"; - }; diff --git a/Documentation/devicetree/bindings/mtd/nand-chip.yaml b/Documentation/devicetree/bindings/mtd/nand-chip.yaml index 8800d1d07266..effdc4f99017 100644 --- a/Documentation/devicetree/bindings/mtd/nand-chip.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-chip.yaml @@ -23,6 +23,15 @@ properties: description: Contains the chip-select IDs. + nand-randomizer: + description: | + Control the data randomizer feature. + 0: Disable randomizer. + 1: Enable randomizer. + If absent, the current hardware state is left unchanged. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + required: - reg diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml index 5511389960f0..a916cac53af6 100644 --- a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml +++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml @@ -22,17 +22,20 @@ properties: - qcom,ipq4019-nand - qcom,ipq6018-nand - qcom,ipq8074-nand + - qcom,mdm9607-nand - qcom,sdx55-nand reg: maxItems: 1 clocks: + minItems: 1 items: - description: Core Clock - description: Always ON Clock clock-names: + minItems: 1 items: - const: core - const: aon @@ -101,6 +104,27 @@ allOf: items: - const: rxtx + # On MDM9607, the OS can only control a single clock. + # The 3 hardware clocks (core, aon, ahb) are invisible to the OS. + - if: + properties: + compatible: + contains: + enum: + - qcom,mdm9607-nand + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + else: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + - if: properties: compatible: @@ -121,6 +145,7 @@ allOf: - qcom,ipq4019-nand - qcom,ipq6018-nand - qcom,ipq8074-nand + - qcom,mdm9607-nand - qcom,sdx55-nand then: diff --git a/Documentation/devicetree/bindings/net/adi,ad3306.yaml b/Documentation/devicetree/bindings/net/adi,ad3306.yaml new file mode 100644 index 000000000000..785d05c995db --- /dev/null +++ b/Documentation/devicetree/bindings/net/adi,ad3306.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/adi,ad3306.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADI ADIN1140 10BASE-T1S MAC-PHY + +maintainers: + - Ciprian Regus <ciprian.regus@analog.com> + +description: | + The ADIN1140 (also called AD3306) is a low power single port + 10BASE-T1S MAC-PHY. It integrates an Ethernet PHY with a MAC + and all the associated analog circuitry. + The device tries to implement the Open Alliance TC6 10BASE-T1x MAC-PHY + Serial Interface specification and is compliant with the + IEEE 802.3cg-2019 Ethernet standard for 10 Mbps single pair + Ethernet (SPE). The device has a 4-wire SPI interface for + communication between the MAC and host processor. + +allOf: + - $ref: /schemas/net/ethernet-controller.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - items: + - const: adi,adin1140 + - const: adi,ad3306 + - const: adi,ad3306 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + interrupts: + maxItems: 1 + description: Interrupt from the MAC-PHY for receive data available + and error conditions + +required: + - compatible + - reg + - interrupts + - spi-max-frequency + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + ethernet@0 { + compatible = "adi,ad3306"; + reg = <0>; + spi-max-frequency = <23000000>; + + interrupt-parent = <&gpio>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + + local-mac-address = [ 00 11 22 33 44 55 ]; + }; + }; diff --git a/Documentation/devicetree/bindings/net/airoha,an8801.yaml b/Documentation/devicetree/bindings/net/airoha,an8801.yaml new file mode 100644 index 000000000000..d6e5a60a6b20 --- /dev/null +++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/airoha,an8801.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8801R Series PHY + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: + The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver + with Single-port serdes interface for 1000Base-X/RGMII; this chip is + compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3(u,ab) + and supports Energy Efficient Ethernet (802.3az), Full Duplex Control + Flow (802.3x), auto-negotiation, crossover detect and autocorrection, + Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9 Kilobytes. + This PHY also supports up to three user-configurable LEDs, which are + usually used for LAN Activity, 100M, 1000M indication. + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + enum: + - ethernet-phy-idc0ff.0421 + + reg: + maxItems: 1 + + leds: + type: object + description: + Describes the LEDs associated to the PHY + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-2]$": + type: object + description: PHY LEDs + $ref: /schemas/leds/common.yaml# + + properties: + reg: + enum: [0, 1, 2] + + function-enumerator: + enum: [0, 1, 2] + description: | + Specifies a function for offloading LED functionality to the PHY: + 0 - No offloading + 1 - Link Availability + 2 - Network Activity + + required: + - reg + + unevaluatedProperties: false + + additionalProperties: false + + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enable Wake-on-LAN support + +required: + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-idc0ff.0421"; + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml index fbe2ddcdd909..17fe2edf4886 100644 --- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml @@ -130,6 +130,42 @@ patternProperties: maximum: 4 description: GMAC port identifier + allOf: + - if: + properties: + reg: + contains: + items: + - enum: + - 3 + - 4 + then: + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + "^ethernet@[0-5]$": + type: object + unevaluatedProperties: false + $ref: ethernet-controller.yaml# + description: External ethernet port ID available on the GDM port + + properties: + compatible: + const: airoha,eth-port + + reg: + maximum: 5 + description: External ethernet port identifier + + required: + - reg + - compatible + required: - reg - compatible @@ -191,9 +227,27 @@ examples: #address-cells = <1>; #size-cells = <0>; - mac: ethernet@1 { + ethernet@1 { compatible = "airoha,eth-mac"; reg = <1>; }; + + ethernet@4 { + compatible = "airoha,eth-mac"; + reg = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + ethernet@0 { + compatible = "airoha,eth-port"; + reg = <0>; + }; + + ethernet@1 { + compatible = "airoha,eth-port"; + reg = <1>; + }; + }; }; }; diff --git a/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml index aafb6447b6c2..cfb53080dba2 100644 --- a/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml +++ b/Documentation/devicetree/bindings/net/altr,gmii-to-sgmii-2.0.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera GMII to SGMII Converter maintainers: - - Matthew Gerlach <matthew.gerlach@altera.com> + - Maxime Chevallier <maxime.chevallier@bootlin.com> description: This binding describes the Altera GMII to SGMII converter. diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index fc445ad5a1f1..db93436c96fa 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera SOCFPGA SoC DWMAC controller maintainers: - - Matthew Gerlach <matthew.gerlach@altera.com> + - Maxime Chevallier <maxime.chevallier@bootlin.com> description: This binding describes the Altera SOCFPGA SoC implementation of the @@ -63,11 +63,29 @@ properties: - const: ptp_ref interrupts: - maxItems: 1 + minItems: 1 + maxItems: 17 interrupt-names: + minItems: 1 items: - const: macirq + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: tx-queue-4 + - const: tx-queue-5 + - const: tx-queue-6 + - const: tx-queue-7 + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: rx-queue-4 + - const: rx-queue-5 + - const: rx-queue-6 + - const: rx-queue-7 iommus: minItems: 1 @@ -149,10 +167,36 @@ required: - clocks - clock-names - altr,sysmgr-syscon + - interrupts + - interrupt-names allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: altr,socfpga-stmmac-agilex5 + then: + properties: + interrupts: + minItems: 17 + + interrupt-names: + minItems: 17 + + dma-coherent: true + else: + properties: + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + dma-coherent: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml index 45630067d3c8..0beda26ae8bb 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml @@ -50,9 +50,6 @@ properties: description: VDD_RFA_1P7 supply regulator handle deprecated: true - vddrfa1p8-supply: - description: VDD_RFA_1P8 supply regulator handle - vddrfacmn-supply: description: VDD_RFA_CMN supply regulator handle @@ -68,7 +65,7 @@ required: - vddbtcmx-supply - vddrfa0p8-supply - vddrfa1p2-supply - - vddrfa1p8-supply + - vddrfa1p7-supply - vddrfacmn-supply - vddwlcx-supply - vddwlmx-supply @@ -91,7 +88,7 @@ examples: vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; diff --git a/Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml b/Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml index a077c0330013..81e2b6dfeb02 100644 --- a/Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml +++ b/Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml @@ -16,7 +16,9 @@ allOf: properties: compatible: oneOf: - - const: rockchip,rk3568v2-canfd + - enum: + - rockchip,rk3568v2-canfd + - rockchip,rk3588-canfd - items: - const: rockchip,rk3568v3-canfd - const: rockchip,rk3568v2-canfd diff --git a/Documentation/devicetree/bindings/net/can/ti,am3517-hecc.yaml b/Documentation/devicetree/bindings/net/can/ti,am3517-hecc.yaml new file mode 100644 index 000000000000..7874e9e49224 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/ti,am3517-hecc.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/ti,am3517-hecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments High End CAN Controller (HECC) + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + const: ti,am3517-hecc + + reg: + maxItems: 3 + + reg-names: + items: + - const: hecc + - const: hecc-ram + - const: mbx + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + ti,use-hecc1int: + type: boolean + description: + If provided, configures HECC to produce all interrupts on the + HECC1INT interrupt line. By default, the HECC0INT interrupt line + will be used. + default: false + + xceiver-supply: + description: Regulator that powers the CAN transceiver. + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + can@5c050000 { + compatible = "ti,am3517-hecc"; + reg = <0x5c050000 0x80>, + <0x5c053000 0x180>, + <0x5c052000 0x200>; + reg-names = "hecc", "hecc-ram", "mbx"; + interrupts = <24>; + clocks = <&hecc_ck>; + }; diff --git a/Documentation/devicetree/bindings/net/can/ti_hecc.txt b/Documentation/devicetree/bindings/net/can/ti_hecc.txt deleted file mode 100644 index e0f0a7cfe329..000000000000 --- a/Documentation/devicetree/bindings/net/can/ti_hecc.txt +++ /dev/null @@ -1,32 +0,0 @@ -Texas Instruments High End CAN Controller (HECC) -================================================ - -This file provides information, what the device node -for the hecc interface contains. - -Required properties: -- compatible: "ti,am3517-hecc" -- reg: addresses and lengths of the register spaces for 'hecc', 'hecc-ram' - and 'mbx' -- reg-names :"hecc", "hecc-ram", "mbx" -- interrupts: interrupt mapping for the hecc interrupts sources -- clocks: clock phandles (see clock bindings for details) - -Optional properties: -- ti,use-hecc1int: if provided configures HECC to produce all interrupts - on HECC1INT interrupt line. By default HECC0INT interrupt - line will be used. -- xceiver-supply: regulator that powers the CAN transceiver - -Example: - -For am3517evm board: - hecc: can@5c050000 { - compatible = "ti,am3517-hecc"; - reg = <0x5c050000 0x80>, - <0x5c053000 0x180>, - <0x5c052000 0x200>; - reg-names = "hecc", "hecc-ram", "mbx"; - interrupts = <24>; - clocks = <&hecc_ck>; - }; diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml index 40835497050a..18015e60fd6d 100644 --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml @@ -8,7 +8,7 @@ title: Xilinx CAN and CANFD controller maintainers: - - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> + - Harini T <harini.t@amd.com> properties: compatible: @@ -53,6 +53,9 @@ properties: $ref: /schemas/types.yaml#/definitions/flag description: CAN TX_OL, TX_TL and RX FIFOs have ECC support(AXI CAN) + phys: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/dptel,dap8211r.yaml b/Documentation/devicetree/bindings/net/dptel,dap8211r.yaml new file mode 100644 index 000000000000..4cd0f9730d95 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dptel,dap8211r.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dptel,dap8211r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DAPU Telecom DAP8211R(I) Gigabit Ethernet PHY + +maintainers: + - Artem Shimko <a.shimko.dev@gmail.com> + +description: | + The DAP8211R(I) is a Gigabit Ethernet PHY with RGMII interface, + supporting IEEE 802.3az Energy Efficient Ethernet, IEEE 1588 SyncE, + and an internal packet generator for diagnostics. + + Specifications: + - 10BASE-Te, 100BASE-TX, 1000BASE-T + - RGMII with configurable TX/RX clock delays (150 ps steps, 0-2250 ps) + - IEEE 802.3az-2010 Energy Efficient Ethernet + - IEEE 1588 SyncE support + - Internal packet generator and checker for link diagnostics + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + const: ethernet-phy-id0008.011b + + reg: + maxItems: 1 + + rx-internal-delay-ps: + description: + RGMII RX clock delay in picoseconds (0 to maximum). + multipleOf: 150 + maximum: 2250 + default: 1950 + + tx-internal-delay-ps: + description: + RGMII TX clock delay in picoseconds (0 to maximum). + multipleOf: 150 + maximum: 2250 + default: 1950 + +unevaluatedProperties: false + +examples: + - | + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + compatible = "ethernet-phy-id0008.011b"; + reg = <1>; + rx-internal-delay-ps = <1950>; + tx-internal-delay-ps = <1950>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt deleted file mode 100644 index dab208b5c7c7..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/dsa.txt +++ /dev/null @@ -1,4 +0,0 @@ -Distributed Switch Architecture Device Tree Bindings ----------------------------------------------------- - -See Documentation/devicetree/bindings/net/dsa/dsa.yaml for the documentation. diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documentation/devicetree/bindings/net/dsa/dsa.yaml index 2abd036578d1..801e1411e5c2 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -28,7 +28,11 @@ properties: A two element list indicates which DSA cluster, and position within the cluster a switch takes. <0 0> is cluster 0, switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1, switch 0. A switch not part of any cluster - (single device hanging off a CPU port) must not specify this property + (single device hanging off a CPU port) does not usually need to specify + this property, and then it becomes cluster 0, switch 0. For a topology + aware switch, its switch index can be specified through this property, + even if it is not part of any cluster. Also, topology-unaware switches + must always be defined as index 0 of their cluster. $ref: /schemas/types.yaml#/definitions/uint32-array additionalProperties: true diff --git a/Documentation/devicetree/bindings/net/dsa/lan9303.txt b/Documentation/devicetree/bindings/net/dsa/lan9303.txt deleted file mode 100644 index 46a732087f5c..000000000000 --- a/Documentation/devicetree/bindings/net/dsa/lan9303.txt +++ /dev/null @@ -1,100 +0,0 @@ -SMSC/MicroChip LAN9303 three port ethernet switch -------------------------------------------------- - -Required properties: - -- compatible: should be - - "smsc,lan9303-i2c" for I2C managed mode - or - - "smsc,lan9303-mdio" for mdio managed mode - -Optional properties: - -- reset-gpios: GPIO to be used to reset the whole device -- reset-duration: reset duration in milliseconds, defaults to 200 ms - -Subnodes: - -The integrated switch subnode should be specified according to the binding -described in dsa/dsa.txt. The CPU port of this switch is always port 0. - -Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is -configured to use 1/2/3 instead. This hardware configuration will be -auto-detected and mapped accordingly. - -Example: - -I2C managed mode: - - master: masterdevice@X { - - fixed-link { /* RMII fixed link to LAN9303 */ - speed = <100>; - full-duplex; - }; - }; - - switch: switch@a { - compatible = "smsc,lan9303-i2c"; - reg = <0xa>; - reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - reset-duration = <200>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { /* RMII fixed link to master */ - reg = <0>; - ethernet = <&master>; - }; - - port@1 { /* external port 1 */ - reg = <1>; - label = "lan1"; - }; - - port@2 { /* external port 2 */ - reg = <2>; - label = "lan2"; - }; - }; - }; - -MDIO managed mode: - - master: masterdevice@X { - phy-handle = <&switch>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch: switch-phy@0 { - compatible = "smsc,lan9303-mdio"; - reg = <0>; - reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - reset-duration = <100>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - ethernet = <&master>; - }; - - port@1 { /* external port 1 */ - reg = <1>; - label = "lan1"; - }; - - port@2 { /* external port 2 */ - reg = <2>; - label = "lan2"; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml index 815a90808901..90b3582b7619 100644 --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml @@ -100,6 +100,10 @@ properties: Built-in switch of the Airoha AN7583 SoC const: airoha,an7583-switch + - description: + Built-in switch of the EcoNet EN7528 SoC + const: econet,en7528-switch + reg: maxItems: 1 @@ -318,6 +322,7 @@ allOf: - mediatek,mt7988-switch - airoha,en7581-switch - airoha,an7583-switch + - econet,en7528-switch then: $ref: "#/$defs/builtin-dsa-port" properties: diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7628-esw.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7628-esw.yaml new file mode 100644 index 000000000000..e0e7ffef6648 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7628-esw.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/mediatek,mt7628-esw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT7628 Embedded Ethernet Switch + +maintainers: + - Joris Vaisvila <joey@tinyisr.com> + +description: + The MT7628 SoC's built-in Ethernet Switch has five user ports and one + internally connected CPU port. The user ports are all connected to the SoC's + integrated Fast Ethernet PHYs. The switch registers are directly mapped in + the SoC's memory. + +allOf: + - $ref: dsa.yaml#/$defs/ethernet-ports + +properties: + compatible: + const: mediatek,mt7628-esw + + reg: + maxItems: 1 + + resets: + items: + - description: internal switch block reset + - description: internal phy package reset + + reset-names: + items: + - const: esw + - const: ephy + +required: + - compatible + - reg + - resets + - reset-names + - ethernet-ports + +unevaluatedProperties: false + +examples: + - | + switch@10110000 { + compatible = "mediatek,mt7628-esw"; + reg = <0x10110000 0x8000>; + + resets = <&sysc 23>, <&sysc 24>; + reset-names = "esw", "ephy"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + phy-mode = "internal"; + }; + + ethernet-port@1 { + reg = <1>; + phy-mode = "internal"; + }; + + ethernet-port@2 { + reg = <2>; + phy-mode = "internal"; + }; + + ethernet-port@3 { + reg = <3>; + phy-mode = "internal"; + }; + + ethernet-port@4 { + reg = <4>; + phy-mode = "internal"; + }; + + ethernet-port@6 { + reg = <6>; + phy-mode = "internal"; + ethernet = <ðernet>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml b/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml new file mode 100644 index 000000000000..1b35e4cbd049 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/nxp,netc-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NETC Switch family + +description: > + The NETC presents itself as a multi-function PCIe Root Complex Integrated + Endpoint (RCiEP) and provides full 802.1Q Ethernet switch functionality, + advanced QoS with 8 traffic classes and 4 drop resilience levels, and a + full range of TSN standards capabilities. + + The CPU port of the switch connects to an internal ENETC. The switch and + the internal ENETC are fully integrated into the NETC IP, a back-to-back + MAC is not required. Instead, a light-weight "pseudo MAC" provides the + delineation between the switch and ENETC. This translates to lower power + (less logic and memory) and lower delay (as there is no serialization + delay across this link). + +maintainers: + - Wei Fang <wei.fang@nxp.com> + +properties: + compatible: + enum: + - pci1131,eef2 + + reg: + maxItems: 1 + + dsa,member: + description: > + The property indicates DSA cluster and switch index. For NETC switch, + the valid range of the switch index is 1 ~ 7, the index is reflected + in the switch tag as an indication of the switch ID where the frame + originated. The value 0 is reserved for ENETC VEPA switch, whose ID + is hardwired to zero. + items: + - true + - minimum: 1 + maximum: 7 + + ethernet-ports: + type: object + patternProperties: + "^ethernet-port@[0-9a-f]$": + type: object + $ref: dsa-port.yaml# + + properties: + clocks: + items: + - description: MAC transmit/receive reference clock. + + clock-names: + items: + - const: ref + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: + Optional child node for switch port, otherwise use NETC EMDIO. + + unevaluatedProperties: false + +required: + - compatible + - reg + - dsa,member + - ethernet-ports + +allOf: + - $ref: /schemas/pci/pci-device.yaml + - $ref: dsa.yaml# + +unevaluatedProperties: false + +examples: + - | + pcie { + #address-cells = <3>; + #size-cells = <2>; + + ethernet-switch@0,2 { + compatible = "pci1131,eef2"; + reg = <0x200 0 0 0 0>; + dsa,member = <0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + phy-handle = <ðphy0>; + phy-mode = "mii"; + }; + + ethernet-port@1 { + reg = <1>; + phy-handle = <ðphy1>; + phy-mode = "mii"; + }; + + ethernet-port@2 { + reg = <2>; + clocks = <&scmi_clk 103>; + clock-names = "ref"; + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + }; + + ethernet-port@3 { + reg = <3>; + ethernet = <&enetc3>; + phy-mode = "internal"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/dsa/smsc,lan9303.yaml b/Documentation/devicetree/bindings/net/dsa/smsc,lan9303.yaml new file mode 100644 index 000000000000..42f8473538a0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/smsc,lan9303.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/smsc,lan9303.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SMSC/MicroChip LAN9303 three port ethernet switch + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + The LAN9303 is a three port ethernet switch with integrated PHYs for the + two external ports. The third port is an RMII/MII interface to a host + processor. The device can be managed via I2C or MDIO. + + Note - always use 'reg = <0/1/2>;' for the three DSA ports, even if the + device is configured to use 1/2/3 instead. This hardware configuration + will be auto-detected and mapped accordingly. + +properties: + compatible: + enum: + - smsc,lan9303-i2c + - smsc,lan9303-mdio + + reg: + maxItems: 1 + + reset-gpios: + description: + GPIO to be used to reset the whole device + maxItems: 1 + + reset-duration: + description: + Reset duration in milliseconds + default: 200 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + +unevaluatedProperties: false + +allOf: + - $ref: dsa.yaml# + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + /* I2C managed mode */ + i2c { + #address-cells = <1>; + #size-cells = <0>; + + switch@a { + compatible = "smsc,lan9303-i2c"; + reg = <0xa>; + reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + reset-duration = <200>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&master>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + }; + }; + }; + + - | + #include <dt-bindings/gpio/gpio.h> + + /* MDIO managed mode */ + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "smsc,lan9303-mdio"; + reg = <0>; + reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + reset-duration = <100>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&master>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index 91e8cd1db67b..ba49fd6a086c 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -20,16 +20,37 @@ select: contains: enum: - eswin,eic7700-qos-eth + - eswin,eic7700-qos-eth-clk-inversion required: - compatible allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: eswin,eic7700-qos-eth + then: + properties: + tx-internal-delay-ps: + maximum: 2540 + - if: + properties: + compatible: + contains: + const: eswin,eic7700-qos-eth-clk-inversion + then: + properties: + tx-internal-delay-ps: + minimum: 2000 properties: compatible: items: - - const: eswin,eic7700-qos-eth + - enum: + - eswin,eic7700-qos-eth + - eswin,eic7700-qos-eth-clk-inversion - const: snps,dwmac-5.20 reg: @@ -63,25 +84,41 @@ properties: - const: stmmaceth rx-internal-delay-ps: - enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + minimum: 0 + maximum: 2540 + multipleOf: 20 tx-internal-delay-ps: - enum: [0, 200, 600, 1200, 1600, 1800, 2000, 2200, 2400] + minimum: 0 + maximum: 4540 + multipleOf: 20 eswin,hsp-sp-csr: description: HSP CSR is to control and get status of different high-speed peripherals (such as Ethernet, USB, SATA, etc.) via register, which can tune board-level's parameters of PHY, etc. + + Additional background information about the High-Speed Subsystem + and the HSP CSR block is available in Chapter 10 ("High-Speed Interface") + of the EIC7700X SoC Technical Reference Manual, Part 4 + (EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is + publicly available at + https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases + + This reference is provided for background information only. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - items: + - minItems: 4 + items: - description: Phandle to HSP(High-Speed Peripheral) device - description: Offset of phy control register for internal or external clock selection - description: Offset of AXI clock controller Low-Power request register - description: Offset of register controlling TX/RX clock delay + - description: Optional offset of register controlling TXD delay + - description: Optional offset of register controlling RXD delay required: - compatible @@ -93,8 +130,6 @@ required: - phy-mode - resets - reset-names - - rx-internal-delay-ps - - tx-internal-delay-ps - eswin,hsp-sp-csr unevaluatedProperties: false @@ -104,26 +139,51 @@ examples: ethernet@50400000 { compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; reg = <0x50400000 0x10000>; - clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, - <&d0_clock 193>; - clock-names = "axi", "cfg", "stmmaceth", "tx"; interrupt-parent = <&plic>; interrupts = <61>; interrupt-names = "macirq"; - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; + clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 193>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; resets = <&reset 95>; reset-names = "stmmaceth"; - rx-internal-delay-ps = <200>; - tx-internal-delay-ps = <200>; - eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118>; - snps,axi-config = <&stmmac_axi_setup>; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; snps,aal; snps,fixed-burst; snps,tso; + snps,axi-config = <&stmmac_axi_setup>; + stmmac_axi_setup: stmmac-axi-config { snps,blen = <0 0 0 0 16 8 4>; snps,rd_osr_lmt = <2>; snps,wr_osr_lmt = <2>; }; }; + + ethernet@50410000 { + compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20"; + reg = <0x50410000 0x10000>; + interrupt-parent = <&plic>; + interrupts = <70>; + interrupt-names = "macirq"; + clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>, + <&d0_clock 194>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + resets = <&reset 94>; + reset-names = "stmmaceth"; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>; + phy-handle = <&gmac1_phy0>; + phy-mode = "rgmii-id"; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config = <&stmmac_axi_setup_gmac1>; + + stmmac_axi_setup_gmac1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 21a1a63506f0..c3ebb3af8b52 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -106,10 +106,13 @@ properties: by software. clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 description: - External clock connected to the PHY. If not specified it is assumed - that the PHY uses a fixed crystal or an internal oscillator. + External clock connected to the PHY or RX and TX clocks that the PHY + requires to enable explicitly. If not specified it is assumed + that the PHY uses a fixed crystal or an internal oscillator or that the + RX/TX clocks are hardware enabled by default. enet-phy-lane-swap: $ref: /schemas/types.yaml#/definitions/flag diff --git a/Documentation/devicetree/bindings/net/fsl,gianfar.yaml b/Documentation/devicetree/bindings/net/fsl,gianfar.yaml index 0d8909770ccb..e2543b683bd4 100644 --- a/Documentation/devicetree/bindings/net/fsl,gianfar.yaml +++ b/Documentation/devicetree/bindings/net/fsl,gianfar.yaml @@ -234,7 +234,7 @@ examples: <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; }; - queue-group@2d14000 { + queue-group@2d14000 { reg = <0x0 0x2d14000 0x0 0x1000>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, diff --git a/Documentation/devicetree/bindings/net/mdio.txt b/Documentation/devicetree/bindings/net/mdio.txt deleted file mode 100644 index cf8a0105488e..000000000000 --- a/Documentation/devicetree/bindings/net/mdio.txt +++ /dev/null @@ -1 +0,0 @@ -This file has moved to mdio.yaml. diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index cc346946291a..6bbd83c6aaf7 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -67,8 +67,7 @@ properties: - const: ppe sram: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to mmio SRAM + maxItems: 1 mediatek,ethsys: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/net/microchip,lan7800.yaml b/Documentation/devicetree/bindings/net/microchip,lan7800.yaml new file mode 100644 index 000000000000..cb3927215dfc --- /dev/null +++ b/Documentation/devicetree/bindings/net/microchip,lan7800.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/microchip,lan7800.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip LAN7800/LAN7801/LAN7850 Gigabit Ethernet controller + +maintainers: + - Thangaraj Samynathan <Thangaraj.S@microchip.com> + - Rengarajan Sundararajan <Rengarajan.S@microchip.com> + +description: + The LAN7800/LAN7801/LAN7850 devices are usually configured by + programming their OTP or with an external EEPROM, but some + platforms (e.g. Raspberry Pi 3 B+) have neither. The Device Tree + properties, if present, override the OTP and EEPROM. + +allOf: + - $ref: /schemas/usb/usb-device.yaml# + - $ref: /schemas/net/ethernet-controller.yaml# + +properties: + compatible: + enum: + - usb424,7800 + - usb424,7801 + - usb424,7850 + + reg: + maxItems: 1 + description: USB port number + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + + patternProperties: + "^ethernet-phy(@[0-9a-f]+)?$": + $ref: /schemas/net/ethernet-phy.yaml# + unevaluatedProperties: false + type: object + + properties: + microchip,led-modes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + description: + Array of LED mode values for each of up to 4 LEDs. + Omitted LEDs are turned off. Allowed values are defined + in include/dt-bindings/net/microchip-lan78xx.h. + + required: + - reg + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/net/microchip-lan78xx.h> + + usb { + #address-cells = <1>; + #size-cells = <0>; + + ethernet@1 { + compatible = "usb424,7800"; + reg = <1>; + local-mac-address = [00 11 22 33 44 55]; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethernet-phy@1 { + reg = <1>; + microchip,led-modes = < + LAN78XX_LINK_1000_ACTIVITY + LAN78XX_LINK_10_100_ACTIVITY + >; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/net/microchip,lan78xx.txt b/Documentation/devicetree/bindings/net/microchip,lan78xx.txt deleted file mode 100644 index 11a679530ae6..000000000000 --- a/Documentation/devicetree/bindings/net/microchip,lan78xx.txt +++ /dev/null @@ -1,53 +0,0 @@ -Microchip LAN78xx Gigabit Ethernet controller - -The LAN78XX devices are usually configured by programming their OTP or with -an external EEPROM, but some platforms (e.g. Raspberry Pi 3 B+) have neither. -The Device Tree properties, if present, override the OTP and EEPROM. - -Required properties: -- compatible: Should be one of "usb424,7800", "usb424,7801" or "usb424,7850". - -The MAC address will be determined using the optional properties -defined in ethernet.txt. - -Optional properties of the embedded PHY: -- microchip,led-modes: a 0..4 element vector, with each element configuring - the operating mode of an LED. Omitted LEDs are turned off. Allowed values - are defined in "include/dt-bindings/net/microchip-lan78xx.h". - -Example: - -/* Based on the configuration for a Raspberry Pi 3 B+ */ -&usb { - usb-port@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - usb-port@1 { - compatible = "usb424,2514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - ethernet: ethernet@1 { - compatible = "usb424,7800"; - reg = <1>; - local-mac-address = [ 00 11 22 33 44 55 ]; - - mdio { - #address-cells = <0x1>; - #size-cells = <0x0>; - eth_phy: ethernet-phy@1 { - reg = <1>; - microchip,led-modes = < - LAN78XX_LINK_1000_ACTIVITY - LAN78XX_LINK_10_100_ACTIVITY - >; - }; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/microchip,lan8650.yaml b/Documentation/devicetree/bindings/net/microchip,lan8650.yaml index 61e11d4a07c4..766ff58147ae 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan8650.yaml +++ b/Documentation/devicetree/bindings/net/microchip,lan8650.yaml @@ -67,7 +67,7 @@ examples: pinctrl-names = "default"; pinctrl-0 = <ð0_pins>; interrupt-parent = <&gpio>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; local-mac-address = [04 05 06 01 02 03]; spi-max-frequency = <15000000>; }; diff --git a/Documentation/devicetree/bindings/net/microchip,lan95xx.yaml b/Documentation/devicetree/bindings/net/microchip,lan95xx.yaml index accff93d38f8..2bf6be9807a7 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan95xx.yaml +++ b/Documentation/devicetree/bindings/net/microchip,lan95xx.yaml @@ -20,6 +20,8 @@ properties: compatible: items: - enum: + - usb424,7500 # SMSC LAN7500 USB Ethernet Device + - usb424,7505 # SMSC LAN7505 USB Ethernet Device - usb424,9500 # SMSC9500 USB Ethernet Device - usb424,9505 # SMSC9505 USB Ethernet Device - usb424,9530 # SMSC LAN9530 USB Ethernet Device @@ -33,7 +35,7 @@ properties: - usb424,9906 # SMSC9505A USB Ethernet Device (HAL) - usb424,9907 # SMSC9500 USB Ethernet Device (Alternate ID) - usb424,9908 # SMSC9500A USB Ethernet Device (Alternate ID) - - usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Device ID) + - usb424,9909 # SMSC9512/9514 USB Hub & Ethernet Device - usb424,9e00 # SMSC9500A USB Ethernet Device - usb424,9e01 # SMSC9505A USB Ethernet Device - usb424,9e08 # SMSC LAN89530 USB Ethernet Device diff --git a/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml b/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml index 306ef9ecf2b9..b4efa2f6036a 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml @@ -17,7 +17,7 @@ description: | properties: $nodename: - pattern: "^switch@[0-9a-f]+$" + pattern: "^(ethernet-)?switch@[0-9a-f]+$" compatible: const: microchip,lan966x-switch @@ -70,7 +70,7 @@ properties: additionalProperties: false patternProperties: - "^port@[0-9a-f]+$": + "^(ethernet-)?port@[0-9a-f]+$": type: object $ref: /schemas/net/ethernet-controller.yaml# @@ -138,10 +138,10 @@ additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - switch: switch@e0000000 { + switch: ethernet-switch@e0000000 { compatible = "microchip,lan966x-switch"; - reg = <0xe0000000 0x0100000>, - <0xe2000000 0x0800000>; + reg = <0xe0000000 0x0100000>, + <0xe2000000 0x0800000>; reg-names = "cpu", "gcb"; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "xtr"; @@ -151,14 +151,14 @@ examples: #address-cells = <1>; #size-cells = <0>; - port0: port@0 { + port0: ethernet-port@0 { reg = <0>; phy-handle = <&phy0>; phys = <&serdes 0 0>; phy-mode = "gmii"; }; - port1: port@1 { + port1: ethernet-port@1 { reg = <1>; sfp = <&sfp_eth1>; managed = "in-band-status"; diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index 75c7c8d1f411..9de8eeb8c6a4 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -210,9 +210,9 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> switch: switch@600000000 { compatible = "microchip,sparx5-switch"; - reg = <0 0x401000>, - <0x10004000 0x7fc000>, - <0x11010000 0xaf0000>; + reg = <0 0x401000>, + <0x10004000 0x7fc000>, + <0x11010000 0xaf0000>; reg-names = "cpu", "devices", "gcb"; interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "xtr"; diff --git a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml index ca61cc37a790..ca4200afa793 100644 --- a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml +++ b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml @@ -22,6 +22,10 @@ properties: reg: maxItems: 1 + disable-ports-gpios: + description: GPIO pin to disable PoE on all ports + maxItems: 1 + vdd-supply: description: Regulator that provides 3.3V VDD power supply. diff --git a/Documentation/devicetree/bindings/net/pse-pd/realtek,pse-mcu-gen1.yaml b/Documentation/devicetree/bindings/net/pse-pd/realtek,pse-mcu-gen1.yaml new file mode 100644 index 000000000000..3bb32349c28c --- /dev/null +++ b/Documentation/devicetree/bindings/net/pse-pd/realtek,pse-mcu-gen1.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pse-pd/realtek,pse-mcu-gen1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek PSE MCU + +maintainers: + - Jonas Jelonek <jelonek.jonas@gmail.com> + +description: | + A microcontroller (MCU) that manages the PSE (Power Sourcing Equipment) + hardware on a range of managed PoE switches. The host CPU talks only to + this MCU - over I2C/SMBus or UART - using a small message-based protocol; + the PSE silicon it drives sits behind the MCU and is never accessed + directly. For example, on the Zyxel GS1900-10HP the SoC reaches the MCU + over UART, and the MCU manages the on-board PSE chip. + + This binding describes the MCU together with its Realtek firmware: the + firmware and its host protocol, which are stable across boards. The + microcontroller silicon is a general-purpose part that varies, and the + PSE silicon behind the MCU (Realtek RTL823x/RTL8239* or Broadcom + BCM59xxx) is reported by the MCU and detected at runtime - neither is + named here. + + Two protocol generations exist, both Realtek's: + gen1 older boards, where the MCU fronts Broadcom PSE silicon + gen2 the altered protocol used with Realtek's own PSE silicon + + On an I2C attachment the framing the MCU firmware expects is part of the + compatible: '-smbus' (reads carry a leading command byte and a repeated + start) or '-i2c' (bare block writes and reads). A UART attachment carries + no framing suffix; the transport is given by the parent 'serial' node. + + Each board additionally carries a device-specific compatible that falls + back to one of the protocol compatibles above. Drivers bind on the + protocol compatible; the device-specific string identifies the board and + reserves a place for a future per-board quirk without having to retrofit + device trees already in the field. + +properties: + compatible: + oneOf: + # UART + - items: + - enum: + - zyxel,gs1900-10hp-a1-pse + - const: realtek,pse-mcu-gen1 + + # I2C, SMBus framing + - items: + - enum: + - zyxel,gs1920-24hp-v2-pse + - const: realtek,pse-mcu-gen1-smbus + + # UART + - items: + - enum: + - zyxel,gs1900-10hp-b1-pse + - zyxel,xmg1915-10ep-pse + - const: realtek,pse-mcu-gen2 + + # I2C, SMBus framing + - items: + - enum: + - zyxel,xs1930-12hp-pse + - const: realtek,pse-mcu-gen2-smbus + + # I2C, raw framing + - items: + - enum: + - linksys,lgs328mpc-v2-pse + - const: realtek,pse-mcu-gen2-i2c + + reg: + maxItems: 1 + + reset-gpios: + description: Reset line of the MCU. + maxItems: 1 + + disable-ports-gpios: + description: + Hardware gate that forces all ports into admin-disabled state while + asserted. + maxItems: 1 + +required: + - compatible + +allOf: + - $ref: pse-controller.yaml# + # A '-smbus'/'-i2c' compatible is an I2C attachment: it has 'reg' and + # cannot carry serial bus properties. A bare gen compatible is a UART + # attachment: no 'reg', the transport comes from the parent serial node. + - if: + properties: + compatible: + contains: + enum: + - realtek,pse-mcu-gen1-smbus + - realtek,pse-mcu-gen2-smbus + - realtek,pse-mcu-gen2-i2c + then: + required: + - reg + properties: + current-speed: false + max-speed: false + else: + allOf: + - $ref: /schemas/serial/serial-peripheral-props.yaml# + + properties: + reg: false + +unevaluatedProperties: false + +examples: + # SMBus-framed I2C attachment + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-pse@20 { + compatible = "zyxel,xs1930-12hp-pse", "realtek,pse-mcu-gen2-smbus"; + reg = <0x20>; + + pse-pis { + #address-cells = <1>; + #size-cells = <0>; + + pse-pi@0 { + reg = <0>; + #pse-cells = <0>; + }; + }; + }; + }; + + # Raw-I2C-framed attachment + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-pse@20 { + compatible = "linksys,lgs328mpc-v2-pse", "realtek,pse-mcu-gen2-i2c"; + reg = <0x20>; + + pse-pis { + #address-cells = <1>; + #size-cells = <0>; + + pse-pi@0 { + reg = <0>; + #pse-cells = <0>; + }; + }; + }; + }; + + # UART attachment + - | + serial { + ethernet-pse { + compatible = "zyxel,gs1900-10hp-a1-pse", "realtek,pse-mcu-gen1"; + current-speed = <19200>; + + pse-pis { + #address-cells = <1>; + #size-cells = <0>; + + pse-pi@0 { + reg = <0>; + #pse-cells = <0>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml index 7ae5110e7aa2..53f648c4135f 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -28,6 +28,16 @@ allOf: reg: const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC + clocks: + items: + - description: RX clock + - description: TX clock + + clock-names: + items: + - const: rx + - const: tx + resets: items: - description: @@ -42,6 +52,11 @@ allOf: of this PHY are directly connected to an RJ45 connector. type: boolean + required: + - clocks + - clock-names + - resets + properties: compatible: enum: @@ -162,6 +177,7 @@ examples: }; }; - | + #include <dt-bindings/clock/qcom,gcc-ipq5018.h> #include <dt-bindings/reset/qcom,gcc-ipq5018.h> mdio { @@ -172,6 +188,9 @@ examples: compatible = "ethernet-phy-id004d.d0c0"; reg = <7>; + clocks = <&gcc GCC_GEPHY_RX_CLK>, + <&gcc GCC_GEPHY_TX_CLK>; + clock-names = "rx", "tx"; resets = <&gcc GCC_GEPHY_MISC_ARES>; }; }; diff --git a/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml b/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml index b30544410d09..33746c238513 100644 --- a/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml +++ b/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml @@ -42,7 +42,19 @@ properties: description: State bits used by the AP to signal the modem. items: - description: Power control + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 - description: Power control acknowledgment + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: Names for the state bits used by the AP to signal the modem. diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Documentation/devicetree/bindings/net/qcom,ipa.yaml index fdeaa81b9645..68ec76fe4473 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -128,7 +128,19 @@ properties: description: State bits used in by the AP to signal the modem. items: - description: Whether the "ipa-clock-enabled" state bit is valid + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 - description: Whether the IPA clock is enabled (if valid) + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml index 753f370b7605..6d0b21a10732 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm IPQ packet process engine (PPE) maintainers: - - Luo Jie <quic_luoj@quicinc.com> + - Luo Jie <jie.luo@oss.qualcomm.com> - Lei Wei <quic_leiwei@quicinc.com> - Suruchi Agarwal <quic_suruchia@quicinc.com> - Pavithra R <quic_pavir@quicinc.com> diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml index 02e4e33e9969..271e05bae9c5 100644 --- a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml @@ -18,7 +18,14 @@ properties: - realtek,rtl9302c-mdio - realtek,rtl9303-mdio - const: realtek,rtl9301-mdio - - const: realtek,rtl9301-mdio + - items: + - enum: + - realtek,rtl9312-mdio + - realtek,rtl9313-mdio + - const: realtek,rtl9311-mdio + - enum: + - realtek,rtl9301-mdio + - realtek,rtl9311-mdio '#address-cells': const: 1 diff --git a/Documentation/devicetree/bindings/net/renesas,ether.yaml b/Documentation/devicetree/bindings/net/renesas,ether.yaml index f0a52f47f95a..dd7187f12a67 100644 --- a/Documentation/devicetree/bindings/net/renesas,ether.yaml +++ b/Documentation/devicetree/bindings/net/renesas,ether.yaml @@ -121,8 +121,7 @@ examples: #size-cells = <0>; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index 2125b5ddf73d..c8f76c8e7584 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -254,10 +254,10 @@ examples: ethernet@15c30000 { compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", "snps,dwmac-5.20"; reg = <0x15c30000 0x10000>; - clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, - <&ptp_clock>, <&cpg CPG_MOD 0xb8>, - <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>, - <&cpg CPG_MOD 0xbb>; + clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, + <&ptp_clock>, <&cpg CPG_MOD 0xb8>, + <&cpg CPG_MOD 0xb9>, <&cpg CPG_MOD 0xba>, + <&cpg CPG_MOD 0xbb>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "rx", "tx-180", "rx-180"; resets = <&cpg 0xb0>; diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml index 313a15331661..fdcc61c65f87 100644 --- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml @@ -31,7 +31,7 @@ properties: - const: starfive,jh7110-dwmac - const: snps,dwmac-5.20 - items: - - const: starfive,jh8100-dwmac + - const: starfive,jhb100-dwmac - const: starfive,jh7110-dwmac - const: snps,dwmac-5.20 @@ -39,20 +39,24 @@ properties: maxItems: 1 clocks: + minItems: 5 items: - description: GMAC main clock - description: GMAC AHB clock - description: PTP clock - description: TX clock - description: GTX clock + - description: SGMII RX clock clock-names: + minItems: 5 items: - const: stmmaceth - const: pclk - const: ptp_ref - const: tx - const: gtx + - const: sgmii_rx starfive,tx-use-rgmii-clk: description: @@ -111,22 +115,19 @@ allOf: contains: const: starfive,jh7110-dwmac then: - properties: - interrupts: - minItems: 3 - maxItems: 3 - - interrupt-names: - minItems: 3 - maxItems: 3 - if: properties: compatible: contains: - const: starfive,jh8100-dwmac + const: starfive,jhb100-dwmac then: properties: + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + resets: maxItems: 1 @@ -134,6 +135,14 @@ allOf: const: stmmaceth else: properties: + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + minItems: 3 + maxItems: 3 + resets: minItems: 2 diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml index c296e5711848..883033b19b8f 100644 --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml @@ -21,7 +21,7 @@ properties: - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0 sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: phandle to MSMC SRAM node diff --git a/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml index a98ad45ca66f..9370c43bc66a 100644 --- a/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml +++ b/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml @@ -24,7 +24,7 @@ properties: - ti,am3359-prueth # for AM33x SoC family sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: phandle to OCMC SRAM node diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml index c21d66c7cd55..e667d78b3ab3 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml @@ -158,7 +158,13 @@ properties: description: State bits used by the AP to signal the WLAN Q6. items: - description: Signal bits used to enable/disable low power mode - on WCN in the case of WoW (Wake on Wireless). + on WCN in the case of WoW (Wake on Wireless). + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output. @@ -384,22 +390,22 @@ examples: <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi0", - "msi1", - "msi2", - "msi3", - "msi4", - "msi5", - "msi6", - "msi7", - "msi8", - "msi9", - "msi10", - "msi11", - "msi12", - "msi13", - "msi14", - "msi15", - "legacy"; + interrupt-names = "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "msi8", + "msi9", + "msi10", + "msi11", + "msi12", + "msi13", + "msi14", + "msi15", + "legacy"; ieee80211-freq-limit = <5470000 5875000>; }; diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml index 0cc1dbf2beef..d4aa56e2f823 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml @@ -80,7 +80,13 @@ properties: description: State bits used by the AP to signal the WLAN Q6. items: - description: Signal bits used to enable/disable low power mode - on WCN6750 in the case of WoW (Wake on Wireless). + on WCN6750 in the case of WoW (Wake on Wireless). + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output. diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml index 37d8a0da7780..18cd91e2728c 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml @@ -168,8 +168,26 @@ properties: description: States used by the AP to signal the remote processor items: - description: Shutdown WCSS pd + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 - description: Stop WCSS pd + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 - description: Spawn WCSS pd + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: diff --git a/Documentation/devicetree/bindings/net/wireless/st,stlc4560.yaml b/Documentation/devicetree/bindings/net/wireless/st,stlc4560.yaml new file mode 100644 index 000000000000..a32265c07350 --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/st,stlc4560.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/st,stlc4560.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST/Intersil/Conexant stlc45xx/p54spi/cx3110x SPI wireless device + +maintainers: + - Christian Lamparter <chunkeey@gmail.com> + +description: + The SPI variant of the Intersil Prism54 wireless device was sold + under a variety of names, including Conexant CX3110x and + ST Microelectronics STLC5460. + +allOf: + - $ref: ieee80211.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - const: st,stlc4560 + - items: + - enum: + - cnxt,3110x + - isil,p54spi + - st,stlc4550 + - const: st,stlc4560 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + powerdown-gpios: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + wifi@0 { + compatible = "st,stlc4560"; + reg = <0>; + spi-max-frequency = <48000000>; + interrupts-extended = <&gpio 23>; + powerdown-gpios = <&gpio 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml b/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml new file mode 100644 index 000000000000..c52f8d4bec39 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/airoha,smc-efuses.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/airoha,smc-efuses.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha SMC eFuses + +description: | + Airoha new SoC AN7581 expose banks of eFuse accessible + via specific SMC commands. + + 2 different bank of eFuse or 64 cells of 32 bit are exposed + read-only used to give information on HW Revision, PHY Calibration, + Device Model, Private Key... + +maintainers: + - Christian Marangi <ansuelsmth@gmail.com> + +properties: + compatible: + enum: + - airoha,an7581-efuses + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + '^efuse-bank@[0-1]$': + type: object + + allOf: + - $ref: nvmem.yaml# + + properties: + reg: + description: Identify the eFuse bank. + enum: [0, 1] + + required: + - reg + + unevaluatedProperties: false + +required: + - compatible + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + efuse { + compatible = "airoha,an7581-efuses"; + #address-cells = <1>; + #size-cells = <0>; + + efuse-bank@0 { + reg = <0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml b/Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml index f97c6beb4766..c03e96afe564 100644 --- a/Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml +++ b/Documentation/devicetree/bindings/nvmem/microchip,lan9662-otpc.yaml @@ -25,6 +25,7 @@ properties: - const: microchip,lan9662-otpc - enum: - microchip,lan9662-otpc + - microchip,lan9691-otpc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml b/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml index a26633bf52db..45836308c724 100644 --- a/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml +++ b/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml @@ -16,6 +16,8 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array description: List of phandle to the nvmem providers. + items: + maxItems: 1 nvmem-cells: $ref: /schemas/types.yaml#/definitions/phandle-array diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 2ab047f2bb69..bc0a0898b9e4 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -19,14 +19,19 @@ properties: - enum: - qcom,apq8064-qfprom - qcom,apq8084-qfprom + - qcom,glymur-qfprom + - qcom,hawi-qfprom - qcom,ipq5018-qfprom + - qcom,ipq5210-qfprom - qcom,ipq5332-qfprom - qcom,ipq5424-qfprom - qcom,ipq6018-qfprom - qcom,ipq8064-qfprom - qcom,ipq8074-qfprom - qcom,ipq9574-qfprom + - qcom,ipq9650-qfprom - qcom,kaanapali-qfprom + - qcom,milos-qfprom - qcom,msm8226-qfprom - qcom,msm8916-qfprom - qcom,msm8917-qfprom @@ -48,6 +53,7 @@ properties: - qcom,sdm630-qfprom - qcom,sdm670-qfprom - qcom,sdm845-qfprom + - qcom,shikra-qfprom - qcom,sm6115-qfprom - qcom,sm6350-qfprom - qcom,sm6375-qfprom diff --git a/Documentation/devicetree/bindings/opp/opp-v2.yaml b/Documentation/devicetree/bindings/opp/opp-v2.yaml index 10000a758572..ce0fa82bce98 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2.yaml @@ -293,9 +293,9 @@ examples: opp-microvolt = <970000>, /* Supply 0 */ <960000>, /* Supply 1 */ <960000>; /* Supply 2 */ - opp-microamp = <70000>, /* Supply 0 */ - <70000>, /* Supply 1 */ - <70000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <70000>, /* Supply 1 */ + <70000>; /* Supply 2 */ clock-latency-ns = <300000>; }; @@ -306,9 +306,9 @@ examples: opp-microvolt = <975000 970000 985000>, /* Supply 0 */ <965000 960000 975000>, /* Supply 1 */ <965000 960000 975000>; /* Supply 2 */ - opp-microamp = <70000>, /* Supply 0 */ - <70000>, /* Supply 1 */ - <70000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <70000>, /* Supply 1 */ + <70000>; /* Supply 2 */ clock-latency-ns = <300000>; }; @@ -317,11 +317,11 @@ examples: opp-1000000002 { opp-hz = /bits/ 64 <1000000002>; opp-microvolt = <975000 970000 985000>, /* Supply 0 */ - <965000 960000 975000>, /* Supply 1 */ - <965000 960000 975000>; /* Supply 2 */ - opp-microamp = <70000>, /* Supply 0 */ - <0>, /* Supply 1 doesn't need this */ - <70000>; /* Supply 2 */ + <965000 960000 975000>, /* Supply 1 */ + <965000 960000 975000>; /* Supply 2 */ + opp-microamp = <70000>, /* Supply 0 */ + <0>, /* Supply 1 doesn't need this */ + <70000>; /* Supply 2 */ clock-latency-ns = <300000>; }; }; @@ -405,8 +405,8 @@ examples: opp-hz = /bits/ 64 <1000000000>; opp-microvolt-slow = <915000 900000 925000>; opp-microvolt-fast = <975000 970000 985000>; - opp-microamp-slow = <70000>; - opp-microamp-fast = <71000>; + opp-microamp-slow = <70000>; + opp-microamp-fast = <71000>; }; opp-1200000000 { @@ -415,7 +415,7 @@ examples: <925000 910000 935000>; /* Supply vcc1 */ opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */ <965000 960000 975000>; /* Supply vcc1 */ - opp-microamp = <70000>; /* Will be used for both slow/fast */ + opp-microamp = <70000>; /* Will be used for both slow/fast */ }; }; diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 812ef5957cfc..328b8156cd94 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -214,7 +214,7 @@ examples: dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>, <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>; brcm,enable-ssc; - brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; + brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>; /* PCIe bridge, Root Port */ pci@0,0 { diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 9d1349855b42..4f56e8e4f100 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -58,24 +58,48 @@ properties: items: - description: builtin MSI controller. - description: builtin DMA controller. + - description: PCIe event interrupt. + - description: builtin AER SPI standalone interrupt line. + - description: builtin PME SPI standalone interrupt line. interrupt-names: minItems: 1 items: - const: msi - const: dma + - const: intr + - const: aer + - const: pme reset-gpio: + deprecated: true description: Should specify the GPIO for controlling the PCI bus device reset signal. It's not polarity aware and defaults to active-low reset sequence (L=reset state, H=operation state) (optional required). + This property is deprecated, instead of referencing this property from the + host bridge node, use the reset-gpios property from the root port node. reset-gpio-active-high: + deprecated: true description: If present then the reset sequence using the GPIO specified in the "reset-gpio" property is reversed (H=reset state, L=operation state) (optional required). + This property is deprecated along with the reset-gpio property above, use + the reset-gpios property from the root port node. type: boolean + pcie@0: + description: + Describe the i.MX6 PCIe Root Port. + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + unevaluatedProperties: false + required: - compatible - reg @@ -231,11 +255,31 @@ allOf: - const: ref - const: extref # Optional + - if: + properties: + compatible: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + - fsl,imx8mq-pcie + - fsl,imx8q-pcie + then: + properties: + interrupts: + maxItems: 2 + interrupt-names: + maxItems: 2 + unevaluatedProperties: false examples: - | #include <dt-bindings/clock/imx6qdl-clock.h> + #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> pcie: pcie@1ffc000 { @@ -262,5 +306,18 @@ examples: <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_REF_125M>; clock-names = "pcie", "pcie_bus", "pcie_phy"; + + pcie_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; }; ... diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml index 54e2890ae631..394bb46b38e6 100644 --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml @@ -27,16 +27,20 @@ properties: - const: snps,dw-pcie reg: + minItems: 3 items: - description: Controller control and status registers. - description: PCIe configuration registers. - description: Controller application registers. + - description: Internal Address Translation Unit (iATU) registers. reg-names: + minItems: 3 items: - const: dbi - const: config - const: app + - const: atu ranges: maxItems: 1 @@ -95,8 +99,9 @@ examples: #size-cells = <2>; reg = <0xd0e00000 0x1000>, <0xd2000000 0x800000>, - <0xd0a41000 0x1000>; - reg-names = "dbi", "config", "app"; + <0xd0a41000 0x1000>, + <0xd0ec0000 0x1000>; + reg-names = "dbi", "config", "app", "atu"; linux,pci-domain = <0>; max-link-speed = <4>; bus-range = <0x00 0x08>; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 4db700fc36ba..b88717dec1fa 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -51,6 +51,7 @@ properties: - mediatek,mt7981-pcie - mediatek,mt7986-pcie - mediatek,mt8188-pcie + - mediatek,mt8189-pcie - mediatek,mt8195-pcie - const: mediatek,mt8192-pcie - items: @@ -115,6 +116,10 @@ properties: power-domains: maxItems: 1 + memory-region: + maxItems: 1 + description: phandle to restricted DMA buffer + mediatek,pbus-csr: $ref: /schemas/types.yaml#/definitions/phandle-array items: @@ -193,6 +198,7 @@ allOf: contains: enum: - mediatek,mt8188-pcie + - mediatek,mt8189-pcie - mediatek,mt8195-pcie then: properties: diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml index e33bcc216e30..542252168388 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml @@ -125,8 +125,8 @@ examples: phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>, /* I/O space */ - <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>, /* I/O space */ + <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ pcie@0,0 { device_type = "pci"; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml index 0b8c78ec4f91..c009a7a52bc6 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - airoha,an7583-pcie + - econet,en7528-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -226,6 +227,31 @@ allOf: mediatek,pbus-csr: false + - if: + properties: + compatible: + contains: + const: econet,en7528-pcie + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + resets: false + + reset-names: false + + power-domains: false + + mediatek,pbus-csr: false + + required: + - phys + - phy-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml index dc4f8725c9f5..f0114defc04e 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml @@ -10,32 +10,23 @@ maintainers: - Thierry Reding <thierry.reding@gmail.com> - Jon Hunter <jonathanh@nvidia.com> +description: | + Of the six PCIe controllers found on Tegra264, one (C0) is used for the + internal GPU and the other five (C1-C5) are routed to connectors such as + PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1 + through C5, but not for C0. + properties: compatible: const: nvidia,tegra264-pcie reg: - description: | - Of the six PCIe controllers found on Tegra264, one (C0) is used for the - internal GPU and the other five (C1-C5) are routed to connectors such as - PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1 - through C5, but not for C0. minItems: 4 - items: - - description: ECAM-compatible configuration space - - description: application layer registers - - description: transaction layer registers - - description: privileged transaction layer registers - - description: data link/physical layer registers (not available on C0) + maxItems: 5 reg-names: minItems: 4 - items: - - const: ecam - - const: xal - - const: xtl - - const: xtl-pri - - const: xpl + maxItems: 5 interrupts: minItems: 1 @@ -61,6 +52,49 @@ properties: - description: PCIe controller ID maximum: 5 +patternProperties: + '^pcie@': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + unevaluatedProperties: false + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - oneOf: + - description: C0 controller (no UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: ecam + + - description: C1-C5 controllers (with UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: data link/physical layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: xpl + - const: ecam + required: - interrupt-map - interrupt-map-mask @@ -68,9 +102,6 @@ required: - msi-map - nvidia,bpmp -allOf: - - $ref: /schemas/pci/pci-host-bridge.yaml# - unevaluatedProperties: false examples: @@ -81,11 +112,11 @@ examples: pci@c000000 { compatible = "nvidia,tegra264-pcie"; - reg = <0xd0 0xb0000000 0x0 0x10000000>, - <0x00 0x0c000000 0x0 0x00004000>, + reg = <0x00 0x0c000000 0x0 0x00004000>, <0x00 0x0c004000 0x0 0x00001000>, - <0x00 0x0c005000 0x0 0x00001000>; - reg-names = "ecam", "xal", "xtl", "xtl-pri"; + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names = "xal", "xtl", "xtl-pri", "ecam"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -105,9 +136,18 @@ examples: ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; - bus-range = <0x0 0xff>; nvidia,bpmp = <&bpmp 0>; + + pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; @@ -118,12 +158,12 @@ examples: pci@8400000 { compatible = "nvidia,tegra264-pcie"; - reg = <0xa8 0xb0000000 0x0 0x10000000>, - <0x00 0x08400000 0x0 0x00004000>, + reg = <0x00 0x08400000 0x0 0x00004000>, <0x00 0x08404000 0x0 0x00001000>, <0x00 0x08405000 0x0 0x00001000>, - <0x00 0x08410000 0x0 0x00010000>; - reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -142,8 +182,17 @@ examples: ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>, <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; - bus-range = <0x00 0xff>; nvidia,bpmp = <&bpmp 1>; + + pcie@0 { + device_type = "pci"; + compatible = "pciclass,0604"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml new file mode 100644 index 000000000000..aba89b599155 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml @@ -0,0 +1,201 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hawi PCI Express Root Complex + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Manivannan Sadhasivam <mani@kernel.org> + +description: + Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on + the Synopsys DesignWare PCIe IP. + +properties: + compatible: + oneOf: + - const: qcom,hawi-pcie + - items: + - enum: + - qcom,maili-pcie + - const: qcom,hawi-pcie + + reg: + items: + - description: Qualcomm specific registers + - description: DesignWare PCIe registers + - description: External local bus interface registers + - description: ATU address space + - description: PCIe configuration space + - description: MHI registers + + reg-names: + items: + - const: parf + - const: dbi + - const: elbi + - const: atu + - const: config + - const: mhi + + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe Configuration clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe Aggre NoC AXI clock + - description: PCIe Config NoC AXI clock + + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: noc_aggr + - const: cnoc_sf_axi + + interrupts: + minItems: 9 + maxItems: 9 + + interrupt-names: + items: + - const: msi0 + - const: msi1 + - const: msi2 + - const: msi3 + - const: msi4 + - const: msi5 + - const: msi6 + - const: msi7 + - const: global + + resets: + items: + - description: PCIe core reset + - description: PCIe link down reset + + reset-names: + items: + - const: pci + - const: link_down + +required: + - power-domains + - resets + - reset-names + +allOf: + - $ref: qcom,pcie-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1c00000 { + compatible = "qcom,hawi-pcie"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>; + + bus-range = <0x00 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&gcc_pcie_0_aux_clk>, + <&gcc_pcie_0_cfg_ahb_clk>, + <&gcc_pcie_0_mstr_axi_clk>, + <&gcc_pcie_0_slv_axi_clk>, + <&gcc_pcie_0_slv_q2a_axi_clk>, + <&gcc_aggre_noc_pcie_axi_clk>, + <&gcc_cnoc_pcie_sf_axi_clk>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "noc_aggr", + "cnoc_sf_axi"; + + dma-coherent; + + interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", "global"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + interconnects = <&pcie_anoc_master_pcie_0 QCOM_ICC_TAG_ALWAYS + &mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main_slave_pcie_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &apps_smmu 0x1000 0x1>, + <0x100 &apps_smmu 0x1001 0x1>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + power-domains = <&gcc_pcie_0_phy_gdsc>; + + resets = <&gcc_pcie_0_bcr>, + <&gcc_pcie_0_link_down_bcr>; + reset-names = "pci", "link_down"; + + msi-map = <0x0 &gic_its 0x1000 0x1>, + <0x100 &gic_its 0x1001 0x1>; + msi-map-mask = <0xff00>; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + phys = <&pcie0_phy>; + wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml index 4be342cc04e1..533079811881 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ipq9574.yaml @@ -17,8 +17,10 @@ properties: - qcom,pcie-ipq9574 - items: - enum: + - qcom,pcie-ipq5210 - qcom,pcie-ipq5332 - qcom,pcie-ipq5424 + - qcom,pcie-ipq9650 - const: qcom,pcie-ipq9574 reg: @@ -82,6 +84,19 @@ required: allOf: - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-ipq5210 + - qcom,pcie-ipq9650 + then: + properties: + interrupts: + minItems: 9 + interrupt-names: + minItems: 9 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index 3a94a9c1bb15..fb706b1397a3 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -20,6 +20,7 @@ properties: - const: qcom,pcie-sm8550 - items: - enum: + - qcom,eliza-pcie - qcom,kaanapali-pcie - qcom,sar2130p-pcie - qcom,pcie-sm8650 @@ -91,6 +92,55 @@ required: allOf: - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + const: qcom,eliza-pcie + then: + properties: + reg: + minItems: 6 + reg-names: + minItems: 6 + + - if: + properties: + compatible: + contains: + const: qcom,eliza-pcie + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + minItems: 8 + maxItems: 8 + + - if: + properties: + compatible: + contains: + const: qcom,eliza-pcie + then: + properties: + interrupts: + minItems: 9 + interrupt-names: + minItems: 9 + + - if: + properties: + compatible: + contains: + const: qcom,eliza-pcie + then: + properties: + resets: + minItems: 2 + reset-names: + minItems: 2 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml index bb3f843c59d9..64f456c6a75a 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -66,6 +66,9 @@ properties: max-link-speed: maximum: 4 + msi-parent: + maxItems: 1 + num-lanes: maximum: 4 diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml index 065b7508d288..1f0ab9ccd1dd 100644 --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -155,7 +155,7 @@ examples: #include <dt-bindings/clock/r8a7790-cpg-mssr.h> #include <dt-bindings/power/r8a7790-sysc.h> - pci@ee090000 { + pci@ee090000 { compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; device_type = "pci"; reg = <0xee090000 0xc00>, diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml index a67108c48feb..09d78bd1a577 100644 --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -4,21 +4,28 @@ $id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G3S PCIe host controller +title: Renesas RZ/G3S PCIe host controller (and similar SoCs) maintainers: - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> -description: - Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe - Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and - up to 8 GT/s (Gen3) for RZ/G3E. +description: | + PCIe host controller found in Renesas RZ/G3S and similar SoCs complies + with PCIe Base Specification 4.0 and supports different link speeds + depending on the SoC variant: + - Gen2 (5 GT/s): RZ/G3S + - Gen3 (8 GT/s): RZ/G3E, RZ/V2H(P), RZ/V2N properties: compatible: - enum: - - renesas,r9a08g045-pcie # RZ/G3S - - renesas,r9a09g047-pcie # RZ/G3E + oneOf: + - enum: + - renesas,r9a08g045-pcie # RZ/G3S + - renesas,r9a09g047-pcie # RZ/G3E + - renesas,r9a09g057-pcie # RZ/V2H(P) + - items: + - const: renesas,r9a09g056-pcie # RZ/V2N + - const: renesas,r9a09g047-pcie reg: maxItems: 1 @@ -133,7 +140,13 @@ properties: - clkl1pm clock request state - power off information in L2 state - errors (fatal, non-fatal, correctable) - $ref: /schemas/types.yaml#/definitions/phandle + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to system controller + - description: PCIe controller index + enum: [0, 1] + minItems: 1 patternProperties: "^pcie@0,[0-0]$": @@ -152,6 +165,7 @@ patternProperties: enum: - 0x0033 - 0x0039 + - 0x003b clocks: items: @@ -213,7 +227,9 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g047-pcie + enum: + - renesas,r9a09g047-pcie + - renesas,r9a09g057-pcie then: properties: interrupts: @@ -228,6 +244,25 @@ allOf: maxItems: 1 reset-names: maxItems: 1 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-pcie + then: + properties: + num-lanes: + enum: [2, 4] + renesas,sysc: + items: + - minItems: 2 + required: + - num-lanes + else: + properties: + renesas,sysc: + items: + - maxItems: 1 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index f20ed7e709f7..57a8f163dda5 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -109,7 +109,7 @@ examples: num-lanes = <1>; num-viewport = <3>; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; vdd10-supply = <&ldo6_reg>; vdd18-supply = <&ldo7_reg>; diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml index f8b7ca57fff1..ab482488b047 100644 --- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml @@ -30,6 +30,8 @@ properties: device-id: const: 0x2042 + dma-coherent: true + msi-parent: true allOf: @@ -60,5 +62,6 @@ examples: vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; }; diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml index 74195c1f5292..afde18c5a4fa 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml @@ -63,10 +63,10 @@ examples: pcie0_ep: pcie-ep@5500000 { compatible = "ti,am654-pcie-ep"; - reg = <0x5500000 0x1000>, - <0x5501000 0x1000>, - <0x10000000 0x8000000>, - <0x5506000 0x1000>; + reg = <0x5500000 0x1000>, + <0x5501000 0x1000>, + <0x10000000 0x8000000>, + <0x5506000 0x1000>; reg-names = "app", "dbics", "addr_space", "atu"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; ti,syscon-pcie-mode = <&scm_conf 0x4060>; diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 98f6c7f1b1a6..db92125a2f2d 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -121,12 +121,12 @@ examples: pcie0_rc: pcie@5500000 { compatible = "ti,am654-pcie-rc"; - reg = <0x5500000 0x1000>, - <0x5501000 0x1000>, - <0x10000000 0x2000>, - <0x5506000 0x1000>, - <0x2900000 0x1000>, - <0x2908000 0x1000>; + reg = <0x5500000 0x1000>, + <0x5501000 0x1000>, + <0x10000000 0x2000>, + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; reg-names = "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells = <3>; diff --git a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml index fae466064780..f084830c6d0c 100644 --- a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml +++ b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml @@ -49,11 +49,12 @@ properties: A phandle to the parent I2C node and the slave address of the device used to configure tc9563 to change FTS, tx amplitude etc. items: - - description: Phandle to the I2C controller node - - description: I2C slave address + - items: + - description: Phandle to the I2C controller node + - description: I2C slave address patternProperties: - "^pcie@[1-3],0$": + "^pcie@[1-2],0$": description: child nodes describing the internal downstream ports of the tc9563 switch. @@ -63,6 +64,21 @@ patternProperties: - $ref: /schemas/pci/pci-pci-bridge.yaml# unevaluatedProperties: false + "^pcie@[3],0$": + description: + child node describing the internal downstream port connected to the + integrated Ethernet MAC endpoint of the tc9563 switch. + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + properties: + n-fts: false + patternProperties: + "^ethernet@0,[0-1]$": + type: object + properties: + n-fts: false + unevaluatedProperties: false + $defs: tc9563-node: type: object @@ -153,6 +169,8 @@ examples: device_type = "pci"; ranges; bus-range = <0x04 0xff>; + + toshiba,tx-amplitude-microvolt = <10>; }; pcie@3,0 { @@ -164,8 +182,6 @@ examples: ranges; bus-range = <0x05 0xff>; - toshiba,tx-amplitude-microvolt = <10>; - ethernet@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; }; diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml new file mode 100644 index 000000000000..d9d1488e915a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 PCIe Host Controller + +description: + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. + +maintainers: + - Xincheng Zhang <zhangxincheng@ultrarisc.com> + - Jia Wang <wangjia@ultrarisc.com> + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: ultrarisc,dp1000-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: config + + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [4, 16] + description: Number of lanes to use. + + interrupts: + items: + - description: MSI interrupt + - description: Legacy INTA interrupt + - description: Legacy INTB interrupt + - description: Legacy INTC interrupt + - description: Legacy INTD interrupt + + clocks: + items: + - description: PCIe core clock + - description: Data Bus Interface (DBI) clock + - description: Auxiliary clock + + clock-names: + items: + - const: core + - const: dbi + - const: aux + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@21000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x21000000 0x0 0x01000000>, + <0x0 0x4fff0000 0x0 0x00010000>; + reg-names = "dbi", "config"; + clocks = <&clkc 9>, <&clkc 7>, <&clkc 10>; + clock-names = "core", "dbi", "aux"; + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <16>; + interrupt-parent = <&plic>; + interrupts = <43>, <44>, <45>, <46>, <47>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + }; + }; diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml index a18dd0a8c43a..f2f0d6b61eac 100644 --- a/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-ddr.yaml @@ -4,16 +4,22 @@ $id: http://devicetree.org/schemas/perf/marvell-cn10k-ddr.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Marvell CN10K DDR performance monitor +title: Marvell CN10K / CN20K DDR performance monitor + +description: + Performance Monitoring Unit (PMU) for the DDR controller on Marvell + CN10K and CN20K SoCs. The block is accessed via a dedicated MMIO region. maintainers: - Bharat Bhushan <bbhushan2@marvell.com> + - Geetha sowjanya <gakula@marvell.com> properties: compatible: items: - enum: - marvell,cn10k-ddr-pmu + - marvell,cn20k-ddr-pmu reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml new file mode 100644 index 000000000000..61700b80e93f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/axiado,ax3000-emmc-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axiado AX3000 Arasan eMMC PHY + +maintainers: + - SriNavmani A <srinavmani@axiado.com> + - Tzu-Hao Wei <twei@axiado.com> + - Prasad Bolisetty <pbolisetty@axiado.com> + +properties: + compatible: + const: axiado,ax3000-emmc-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@80801c00 { + compatible = "axiado,ax3000-emmc-phy"; + reg = <0x80801c00 0x1000>; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml new file mode 100644 index 000000000000..987d396c1c64 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528 + +maintainers: + - Caleb James DeLisle <cjd@cjdns.fr> + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen1 and + Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while + port 1 is Gen1/Gen2 capable. + +properties: + compatible: + enum: + - econet,en751221-pcie-gen1 + - econet,en751221-pcie-gen2 + - econet,en7528-pcie-gen1 + - econet,en7528-pcie-gen2 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + pcie-phy@1faf2000 { + compatible = "econet,en7528-pcie-gen1"; + reg = <0x1faf2000 0x1000>; + #phy-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml new file mode 100644 index 000000000000..2e7d0abfa71a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Lynx 10G SerDes PHY + +maintainers: + - Vladimir Oltean <vladimir.oltean@nxp.com> + +description: + The 10G Lynx is a multi-protocol SerDes block which handles networking, PCIe, + SATA and other high-speed interfaces. It is present on most QorIQ and + Layerscape SoCs. The register map is common, but the integration is + SoC-specific, with the differences consisting in register endianness, the + number of lanes, protocol converters available per lane and their location in + the PCCR registers. Some SoCs have multiple SerDes blocks and those differ in + their protocol capabilities per lane. + +properties: + compatible: + enum: + - fsl,ls1028a-serdes + - fsl,ls1046a-serdes1 + - fsl,ls1046a-serdes2 + - fsl,ls1088a-serdes1 + - fsl,ls1088a-serdes2 + - fsl,ls2088a-serdes1 + - fsl,ls2088a-serdes2 + + reg: + maxItems: 1 + + big-endian: true + + "#phy-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^phy@[0-7]$": + type: object + description: SerDes lane (single RX/TX differential pair) + + properties: + reg: + minimum: 0 + maximum: 7 + description: Lane index as seen in register map + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - "#phy-cells" + - "#address-cells" + - "#size-cells" + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,ls1028a-serdes + - fsl,ls1046a-serdes1 + - fsl,ls1046a-serdes2 + - fsl,ls1088a-serdes1 + - fsl,ls1088a-serdes2 + then: + patternProperties: + "^phy@[0-7]$": + properties: + reg: + minimum: 0 + maximum: 3 + - if: + properties: + compatible: + enum: + - fsl,ls1046a-serdes1 + - fsl,ls1046a-serdes2 + then: + required: + - big-endian + else: + properties: + big-endian: false + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + serdes@1ea0000 { + compatible = "fsl,ls1028a-serdes"; + reg = <0x0 0x1ea0000 0x0 0xffff>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + + phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml index e96229c2f8fb..d73591315d4b 100644 --- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml @@ -9,10 +9,37 @@ title: Freescale Lynx 28G SerDes PHY maintainers: - Ioana Ciornei <ioana.ciornei@nxp.com> +description: + The Lynx 28G is a multi-lane, multi-protocol SerDes (PCIe, SATA, Ethernet) + present in multiple instances on NXP LX2160A and LX2162A SoCs. All instances + share a common register map and programming model, however they differ in + supported protocols per lane in a way that is not detectable by said + programming model without prior knowledge. The distinction is made through + the compatible string. + properties: compatible: - enum: - - fsl,lynx-28g + oneOf: + - const: fsl,lynx-28g + deprecated: true + description: + Legacy compatibility string for Lynx 28G SerDes. Any assumption + regarding whether a certain lane supports a certain protocol may + be incorrect. Deprecated except when used as a fallback. Use + device-specific strings instead. + - items: + - const: fsl,lx2160a-serdes1 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2160a-serdes2 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2162a-serdes1 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2162a-serdes2 + - const: fsl,lynx-28g + - const: fsl,lx2160a-serdes3 reg: maxItems: 1 @@ -51,6 +78,21 @@ required: - reg - "#phy-cells" +allOf: + # LX2162A SerDes 1 has fewer lanes than the others + - if: + properties: + compatible: + contains: + const: fsl,lx2162a-serdes1 + then: + patternProperties: + "^phy@[0-7]$": + properties: + reg: + minimum: 4 + maximum: 7 + additionalProperties: false examples: @@ -60,7 +102,7 @@ examples: #size-cells = <2>; serdes@1ea0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g"; reg = <0x0 0x1ea0000 0x0 0x1e30>; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml index c6d0bbdbe0e2..9df1dbe1253b 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml @@ -39,6 +39,7 @@ properties: - const: mediatek,mt2701-mipi-tx - const: mediatek,mt8173-mipi-tx - const: mediatek,mt8183-mipi-tx + - const: mediatek,mt8196-mipi-tx reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml b/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml new file mode 100644 index 000000000000..fb068f7d774f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nxp,tja1145.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TJA1145 CAN transceiver + +maintainers: + - Dimitri Fedrau <dimitri.fedrau@liebherr.com> + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: nxp,tja1145 + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + spi-cpha: true + + spi-max-frequency: + maximum: 4000000 + + spi-cs-setup-delay-ns: + minimum: 50 + default: 50 + + spi-cs-hold-delay-ns: + minimum: 50 + default: 50 + + spi-cs-inactive-delay-ns: + minimum: 250 + default: 250 + + vcc-supply: + description: + CAN transceiver supply voltage + + vio-supply: + description: + Supply voltage for I/O level adaptor + + vbat-supply: + description: + Battery supply voltage + +required: + - compatible + - reg + - "#phy-cells" + - spi-cpha + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + can-phy@0 { + compatible = "nxp,tja1145"; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + #phy-cells = <0>; + spi-cpha; + spi-max-frequency = <4000000>; + spi-cs-setup-delay-ns = <50>; + spi-cs-hold-delay-ns = <50>; + spi-cs-inactive-delay-ns = <250>; + vcc-supply = <®_5v0>; + vio-supply = <®_3v3>; + vbat-supply = <®_24v0>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml index 966c70d746aa..f397ba3fa84a 100644 --- a/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml @@ -20,6 +20,7 @@ properties: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,kaanapali-dsi-phy-3nm + - qcom,milos-dsi-phy-4nm - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 4a1daae3d8d4..0bf8bf4f66ac 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -74,6 +74,7 @@ allOf: compatible: enum: - qcom,glymur-dp-phy + - qcom,sa8775p-edp-phy - qcom,x1e80100-dp-phy then: properties: diff --git a/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml new file mode 100644 index 000000000000..759f7f979dc6 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,glymur-qmp-gen5x8-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PCIe multiple link-mode PHY controller (PCIe, Glymur) + +maintainers: + - Qiang Yu <qiang.yu@oss.qualcomm.com> + - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> + +description: | + The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the + PCIe3a/PCIe3b controllers. This block supports two link modes, selected + at runtime via a TCSR syscon register: + + 1. x8 - a single 8-lane PHY instance is exposed (PCIe3a only) + 2. x4+x4 - two independent 4-lane PHY instances are exposed (PCIe3a and + PCIe3b) + + The node always describes both PHY instances ("port a" and "port b"), + regardless of which link mode is active on the board. + +properties: + compatible: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + + reg: + maxItems: 2 + + reg-names: + items: + - const: port_a + - const: port_b + + clocks: + maxItems: 10 + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: phy_b_aux + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: pipediv2_b + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: port_a + - const: port_b + + resets: + maxItems: 4 + + reset-names: + items: + - const: port_a + - const: port_a_nocsr + - const: port_b + - const: port_b_nocsr + + vdda-phy-supply: true + + vdda-pll-supply: true + + vdda-refgen0p9-supply: true + + vdda-refgen1p2-supply: true + + qcom,link-mode: + description: + Reference to a register in the TCSR syscon that reports the link + mode the PCIe PHY is currently configured for, either a single x8 + link or two independent x4 links. The link mode is programmed by + firmware before Linux boots; this property is only used to read + the active link mode, specified as a phandle to the syscon and + the register offset. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of link mode register + + "#clock-cells": + const: 1 + + clock-output-names: + items: + - description: Name of the PHY A pipe clock output. + - description: Name of the PHY B pipe clock output. + + "#phy-cells": + const: 1 + description: + The cell is the index of the sub-PHY within the active link + mode, e.g. on Glymur, 0 for "port a" and 1 for "port b" in + x4x4 mode, and only index 0 (the single wide PHY) is valid in + x8 mode. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - vdda-refgen0p9-supply + - vdda-refgen1p2-supply + - qcom,link-mode + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,glymur-gcc.h> + #include <dt-bindings/clock/qcom,glymur-tcsr.h> + + phy@f00000 { + compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; + reg = <0x00f00000 0x10000>, <0x00f10000 0x10000>; + reg-names = "port_a", "port_b"; + + clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_3_CLKREF_EN>, + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3A_PIPE_CLK>, + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, + <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_3B_PIPE_CLK>, + <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", + "phy_b_aux", "cfg_ahb_b", "rchng_b", "pipe_b", + "pipediv2_b"; + + resets = <&gcc GCC_PCIE_3A_PHY_BCR>, + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, + <&gcc GCC_PCIE_3B_PHY_BCR>, + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; + reset-names = "port_a", "port_a_nocsr", "port_b", "port_b_nocsr"; + + power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>, + <&gcc GCC_PCIE_3B_PHY_GDSC>; + power-domain-names = "port_a", "port_b"; + + vdda-phy-supply = <&vreg_l3c>; + vdda-pll-supply = <&vreg_l2c>; + + vdda-refgen0p9-supply = <&vreg_l3c>; + vdda-refgen1p2-supply = <&vreg_l2c>; + + qcom,link-mode = <&tcsr 0x5000>; + + #clock-cells = <1>; + clock-output-names = "pcie3a_pipe_clk", "pcie3b_pipe_clk"; + + #phy-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index f60804687412..d602588a9178 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -17,17 +17,21 @@ properties: compatible: oneOf: - enum: + - qcom,ipq5210-qmp-gen3x1-pcie-phy - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy - qcom,ipq9574-qmp-gen3x1-pcie-phy - qcom,ipq9574-qmp-gen3x2-pcie-phy + - qcom,ipq9650-qmp-gen3x1-pcie-phy + - qcom,ipq9650-qmp-gen3x2-pcie-phy - items: - enum: - qcom,ipq5424-qmp-gen3x1-pcie-phy - const: qcom,ipq9574-qmp-gen3x1-pcie-phy - items: - enum: + - qcom,ipq5210-qmp-gen3x2-pcie-phy - qcom,ipq5424-qmp-gen3x2-pcie-phy - const: qcom,ipq9574-qmp-gen3x2-pcie-phy @@ -61,6 +65,8 @@ properties: "#phy-cells": const: 0 + refgen-supply: true + required: - compatible - reg @@ -72,6 +78,21 @@ required: - clock-output-names - "#phy-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9650-qmp-gen3x1-pcie-phy + - qcom,ipq9650-qmp-gen3x2-pcie-phy + then: + required: + - refgen-supply + else: + properties: + refgen-supply: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml index cd6b84213a7c..c0e7e2963ce6 100644 --- a/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,m31-eusb2-phy.yaml @@ -19,6 +19,7 @@ properties: - items: - enum: - qcom,glymur-m31-eusb2-phy + - qcom,hawi-m31-eusb2-phy - qcom,kaanapali-m31-eusb2-phy - const: qcom,sm8750-m31-eusb2-phy - const: qcom,sm8750-m31-eusb2-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml index efb465c71c1b..98397006fa62 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,qcs615-qmp-usb3-dp-phy + - qcom,shikra-qmp-usb3-dp-phy reg: maxItems: 1 @@ -33,12 +34,15 @@ properties: - const: pipe resets: - maxItems: 2 + minItems: 2 + maxItems: 3 reset-names: + minItems: 2 items: - const: phy_phy - const: dp_phy + - const: phy vdda-phy-supply: true @@ -63,6 +67,22 @@ properties: - description: offset of the PHY mode register description: Clamp and PHY mode register present in the TCSR + orientation-switch: + description: + Flag the PHY as possible handler of USB Type-C orientation switching + type: boolean + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the PHY + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB controller + required: - compatible - reg @@ -78,6 +98,33 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,shikra-qmp-usb3-dp-phy + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs615-qmp-usb3-dp-phy + then: + properties: + resets: + maxItems: 2 + reset-names: + maxItems: 2 + examples: - | #include <dt-bindings/clock/qcom,qcs615-gcc.h> diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 39851ba9de43..001fd0ccc985 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -28,10 +28,15 @@ properties: - qcom,qcm2290-qusb2-phy - qcom,qcs615-qusb2-phy - qcom,sdm660-qusb2-phy + - qcom,shikra-qusb2-phy - qcom,sm4250-qusb2-phy - qcom,sm6115-qusb2-phy - items: - enum: + - qcom,ipq5210-qusb2-phy + - const: qcom,ipq6018-qusb2-phy + - items: + - enum: - qcom,sc7180-qusb2-phy - qcom,sdm670-qusb2-phy - qcom,sdm845-qusb2-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml index 90fc8c039219..e573abcb937d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml @@ -35,6 +35,17 @@ properties: phy-supply: description: Phandle to a regulator that provides power to the PHY. + deprecated: true + + vdda-0p9-supply: + description: + Phandle to a 0.9V regulator supply to the PHY, which draws a peak + current of 46 mA. + + vdda-1p2-supply: + description: + Phandle to a 1.2V regulator supply to the PHY, which draws a peak + current of 15 mA. "#phy-cells": const: 0 diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 3a35120a77ec..b353b7bfb839 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -16,8 +16,12 @@ description: properties: compatible: enum: + - qcom,eliza-qmp-gen3x1-pcie-phy + - qcom,eliza-qmp-gen3x2-pcie-phy - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,hawi-qmp-gen3x2-pcie-phy + - qcom,hawi-qmp-gen4x1-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -41,6 +45,7 @@ properties: - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen4x2-pcie-phy + - qcom,sm8475-qmp-gen3x1-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy @@ -136,8 +141,6 @@ allOf: items: - description: port a - description: port b - required: - - qcom,4ln-config-sel else: properties: reg: @@ -148,6 +151,17 @@ allOf: compatible: contains: enum: + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy + then: + required: + - qcom,4ln-config-sel + + - if: + properties: + compatible: + contains: + enum: - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,sar2130p-qmp-gen3x2-pcie-phy @@ -164,6 +178,7 @@ allOf: - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen3x2-pcie-phy + - qcom,sm8475-qmp-gen3x1-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy @@ -181,8 +196,12 @@ allOf: compatible: contains: enum: + - qcom,eliza-qmp-gen3x1-pcie-phy + - qcom,eliza-qmp-gen3x2-pcie-phy - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,hawi-qmp-gen3x2-pcie-phy + - qcom,hawi-qmp-gen4x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy @@ -206,8 +225,12 @@ allOf: compatible: contains: enum: + - qcom,eliza-qmp-gen3x1-pcie-phy + - qcom,eliza-qmp-gen3x2-pcie-phy - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,hawi-qmp-gen3x2-pcie-phy + - qcom,hawi-qmp-gen4x1-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 9616c736b6d4..4efe40c0dc97 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -31,12 +31,14 @@ properties: - items: - enum: - qcom,eliza-qmp-ufs-phy + - qcom,nord-qmp-ufs-phy - const: qcom,sm8650-qmp-ufs-phy - items: - enum: - qcom,kaanapali-qmp-ufs-phy - const: qcom,sm8750-qmp-ufs-phy - enum: + - qcom,hawi-qmp-ufs-phy - qcom,milos-qmp-ufs-phy - qcom,msm8996-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy @@ -107,6 +109,7 @@ allOf: compatible: contains: enum: + - qcom,hawi-qmp-ufs-phy - qcom,milos-qmp-ufs-phy - qcom,msm8998-qmp-ufs-phy - qcom,sa8775p-qmp-ufs-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index 623c2f8c7d22..01342823e57f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -15,26 +15,32 @@ description: properties: compatible: - enum: - - qcom,glymur-qmp-usb3-uni-phy - - qcom,ipq5424-qmp-usb3-phy - - qcom,ipq6018-qmp-usb3-phy - - qcom,ipq8074-qmp-usb3-phy - - qcom,ipq9574-qmp-usb3-phy - - qcom,msm8996-qmp-usb3-phy - - qcom,qcs8300-qmp-usb3-uni-phy - - qcom,qdu1000-qmp-usb3-uni-phy - - qcom,sa8775p-qmp-usb3-uni-phy - - qcom,sc8180x-qmp-usb3-uni-phy - - qcom,sc8280xp-qmp-usb3-uni-phy - - qcom,sdm845-qmp-usb3-uni-phy - - qcom,sdx55-qmp-usb3-uni-phy - - qcom,sdx65-qmp-usb3-uni-phy - - qcom,sdx75-qmp-usb3-uni-phy - - qcom,sm8150-qmp-usb3-uni-phy - - qcom,sm8250-qmp-usb3-uni-phy - - qcom,sm8350-qmp-usb3-uni-phy - - qcom,x1e80100-qmp-usb3-uni-phy + oneOf: + - items: + - enum: + - qcom,glymur-qmp-usb3-uni-phy + - qcom,ipq5424-qmp-usb3-phy + - qcom,ipq6018-qmp-usb3-phy + - qcom,ipq8074-qmp-usb3-phy + - qcom,ipq9574-qmp-usb3-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,qcs8300-qmp-usb3-uni-phy + - qcom,qdu1000-qmp-usb3-uni-phy + - qcom,sa8775p-qmp-usb3-uni-phy + - qcom,sc8180x-qmp-usb3-uni-phy + - qcom,sc8280xp-qmp-usb3-uni-phy + - qcom,sdm845-qmp-usb3-uni-phy + - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy + - qcom,sdx75-qmp-usb3-uni-phy + - qcom,sm8150-qmp-usb3-uni-phy + - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-usb3-uni-phy + - qcom,x1e80100-qmp-usb3-uni-phy + - items: + - enum: + - qcom,ipq5210-qmp-usb3-phy + - const: qcom,ipq9574-qmp-usb3-phy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 3d537b7f9985..8adfc78108fe 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -18,10 +18,15 @@ properties: oneOf: - items: - enum: + - qcom,eliza-qmp-usb3-dp-phy + - const: qcom,sm8650-qmp-usb3-dp-phy + - items: + - enum: - qcom,kaanapali-qmp-usb3-dp-phy - const: qcom,sm8750-qmp-usb3-dp-phy - enum: - qcom,glymur-qmp-usb3-dp-phy + - qcom,hawi-qmp-usb3-dp-phy - qcom,sar2130p-qmp-usb3-dp-phy - qcom,sc7180-qmp-usb3-dp-phy - qcom,sc7280-qmp-usb3-dp-phy @@ -33,6 +38,7 @@ properties: - qcom,sm8250-qmp-usb3-dp-phy - qcom,sm8350-qmp-usb3-dp-phy - qcom,sm8450-qmp-usb3-dp-phy + - qcom,sm8475-qmp-usb3-dp-phy - qcom,sm8550-qmp-usb3-dp-phy - qcom,sm8650-qmp-usb3-dp-phy - qcom,sm8750-qmp-usb3-dp-phy @@ -205,6 +211,7 @@ allOf: contains: enum: - qcom,glymur-qmp-usb3-dp-phy + - qcom,hawi-qmp-usb3-dp-phy - qcom,sar2130p-qmp-usb3-dp-phy - qcom,sc8280xp-qmp-usb43dp-phy - qcom,sm6350-qmp-usb3-dp-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml index 854f70af0a6c..096f6b546632 100644 --- a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml @@ -17,6 +17,7 @@ properties: oneOf: - items: - enum: + - qcom,eliza-snps-eusb2-phy - qcom,milos-snps-eusb2-phy - qcom,sar2130p-snps-eusb2-phy - qcom,sdx75-snps-eusb2-phy diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml index 9740e5b335f9..d6b9d08ceec6 100644 --- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml @@ -16,6 +16,7 @@ properties: - enum: - renesas,usb2-phy-r8a77470 # RZ/G1C - renesas,usb2-phy-r9a08g045 # RZ/G3S + - renesas,usb2-phy-r9a08g046 # RZ/G3L - renesas,usb2-phy-r9a09g057 # RZ/V2H(P) - items: @@ -132,6 +133,7 @@ allOf: enum: - renesas,usb2-phy-r9a09g057 - renesas,usb2-phy-r9a08g045 + - renesas,usb2-phy-r9a08g046 - renesas,rzg2l-usb2-phy then: properties: diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index 58e735b5dd05..f50fc69fbbe4 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -20,6 +20,7 @@ properties: - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy + - rockchip,rk3528-usb2phy - rockchip,rk3562-usb2phy - rockchip,rk3568-usb2phy - rockchip,rk3576-usb2phy @@ -41,11 +42,15 @@ properties: maxItems: 3 clock-names: - minItems: 1 - items: + oneOf: - const: phyclk - - const: aclk - - const: aclk_slv + - items: + - const: phyclk + - const: pclk + - items: + - const: phyclk + - const: aclk + - const: aclk_slv assigned-clocks: description: @@ -65,6 +70,9 @@ properties: description: Muxed interrupt for both ports maxItems: 1 + power-domains: + maxItems: 1 + resets: maxItems: 2 @@ -150,6 +158,21 @@ allOf: compatible: contains: enum: + - rockchip,rk3528-usb2phy + - rockchip,rk3568-usb2phy + - rockchip,rv1108-usb2phy + then: + required: + - rockchip,usbgrf + else: + properties: + rockchip,usbgrf: false + + - if: + properties: + compatible: + contains: + enum: - rockchip,rk3568-usb2phy - rockchip,rk3588-usb2phy @@ -209,6 +232,19 @@ allOf: compatible: contains: enum: + - rockchip,rk3528-usb2phy + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + + - if: + properties: + compatible: + contains: + enum: - rockchip,rk3576-usb2phy then: properties: diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 03950b3cad08..913aa688c0ae 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -56,6 +56,16 @@ properties: description: Some additional phy settings are access through GRF regs. + rockchip,clk-lane-phase: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 3 + description: + Clock lane sampling phase selection (hardware tap index 0–7). Each step + corresponds to an approximately 40 ps delay as described in the hardware + specification. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml index 16967ef8e9ec..87b6a35b2626 100644 --- a/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml @@ -13,14 +13,14 @@ maintainers: description: | For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the - PHY specifier identifies the PHY and its meaning is as follows:: + PHY specifier identifies the PHY and its meaning is as follows: 0 - MIPI CSIS 0, 1 - MIPI DSIM 0, 2 - MIPI CSIS 1, 3 - MIPI DSIM 1. samsung,exynos5420-mipi-video-phy and samsung,exynos5433-mipi-video-phy - support additional fifth PHY:: + support additional fifth PHY: 4 - MIPI CSIS 2. properties: diff --git a/Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml index d9f22a801cbf..7db7605a82e2 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml @@ -14,7 +14,7 @@ maintainers: description: | The first phandle argument in the PHY specifier identifies the PHY, its meaning is compatible dependent. For the currently supported SoCs (Exynos4210 - and Exynos4212) it is as follows:: + and Exynos4212) it is as follows: 0 - USB device ("device"), 1 - USB host ("host"), 2 - HSIC0 ("hsic0"), diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 4562e0468f4f..a1b3d9e6a094 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -14,7 +14,7 @@ maintainers: description: | For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy compatible PHYs, the second cell in the PHY specifier identifies the - PHY id, which is interpreted as follows:: + PHY id, which is interpreted as follows: 0 - UTMI+ type phy, 1 - PIPE3 type phy. diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml new file mode 100644 index 000000000000..ed820cf697b8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,k3-combo-phy.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spacemit K3 PCIE/USB3 Comb PHY + +maintainers: + - Inochi Amaoto <inochiama@gmail.com> + +properties: + compatible: + const: spacemit,k3-combo-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 2 + description: + The first one is phy id, the second one is phy type. This + only supports types are PCIe and USB . + + spacemit,apb-spare: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to APB SPARE system controller interface, used for + PHY calibration. + + spacemit,apmu: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of APMU syscon + - description: configuration of the PHY lanes + description: | + Phandle to control PHY mux configuration. The configuration + is described as follows: + bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode + bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode + bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode + bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode + bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode + + The bit[3:0] is only valid when bit 4 is 1. + + This mux control does not affect the PHY for PCIe E, it is always + in PCIe mode. + +required: + - compatible + - reg + - "#phy-cells" + - spacemit,apb-spare + - spacemit,apmu + +additionalProperties: false + +examples: + - | + phy@81d00000 { + compatible = "spacemit,k3-combo-phy"; + reg = <0x81d00000 0x600000>; + #phy-cells = <2>; + spacemit,apb-spare = <&apb_spare>; + spacemit,apmu = <&apmu 0x00>; + }; diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml index 43eaca90d88c..18025e5f60d6 100644 --- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SpacemiT K1 SoC USB 2.0 PHY +title: SpacemiT K1/K3 SoC USB 2.0 PHY maintainers: - Ze Huang <huang.ze@linux.dev> properties: compatible: - const: spacemit,k1-usb2-phy + enum: + - spacemit,k1-usb2-phy + - spacemit,k3-usb2-phy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/ti,ds125df111.yaml b/Documentation/devicetree/bindings/phy/ti,ds125df111.yaml new file mode 100644 index 000000000000..ca4605f1d664 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,ds125df111.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/ti,ds125df111.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DS125DF111 Retimer PHY + +description: + This binding describes the TI DS125DF111 multi-protocol Retimer PHY. + +maintainers: + - Ioana Ciornei <ioana.ciornei@nxp.com> + +properties: + compatible: + const: ti,ds125df111 + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: | + The phandle's argument in the PHY specifier selects one of the two + channels of the retimer + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + phy@18 { + compatible = "ti,ds125df111"; + reg = <0x18>; + #phy-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml index be41b4547ec6..60b644a4c639 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml @@ -47,15 +47,20 @@ description: | properties: compatible: - enum: - - ti,am3352-phy-gmii-sel - - ti,dra7xx-phy-gmii-sel - - ti,am43xx-phy-gmii-sel - - ti,dm814-phy-gmii-sel - - ti,am654-phy-gmii-sel - - ti,j7200-cpsw5g-phy-gmii-sel - - ti,j721e-cpsw9g-phy-gmii-sel - - ti,j784s4-cpsw9g-phy-gmii-sel + oneOf: + - enum: + - ti,am3352-phy-gmii-sel + - ti,dra7xx-phy-gmii-sel + - ti,am43xx-phy-gmii-sel + - ti,dm814-phy-gmii-sel + - ti,am654-phy-gmii-sel + - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel + - items: + - enum: + - ti,j722s-phy-gmii-sel + - const: ti,am654-phy-gmii-sel reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 3f16ff14484d..0653252c18d8 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -12,13 +12,18 @@ maintainers: properties: compatible: - enum: - - ti,j721e-wiz-16g - - ti,j721e-wiz-10g - - ti,j721s2-wiz-10g - - ti,am64-wiz-10g - - ti,j7200-wiz-10g - - ti,j784s4-wiz-10g + oneOf: + - enum: + - ti,j721e-wiz-16g + - ti,j721e-wiz-10g + - ti,j721s2-wiz-10g + - ti,am64-wiz-10g + - ti,j7200-wiz-10g + - ti,j784s4-wiz-10g + - items: + - enum: + - ti,j722s-wiz-10g + - const: ti,am64-wiz-10g power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml new file mode 100644 index 000000000000..6d186ebe4a41 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7563-pinctrl.yaml @@ -0,0 +1,350 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,an7563-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7563 Pin Controller + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The Airoha's AN7563 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,an7563-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, sipo, mdio, uart, jtag, pcm, spi, pnand, gpio, + pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0, + phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [hsuart, hsuart_cts_rts] + maxItems: 2 + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pnand + then: + properties: + groups: + enum: [pnand] + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio28, gpio29, gpio30, gpio31, gpio32, + gpio33, gpio34, gpio35, gpio36, gpio37] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio36, gpio37] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio4, gpio5, gpio6, gpio7] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio4, gpio5, gpio6, gpio7] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio4, gpio5, gpio6, gpio7] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio4, gpio5, gpio6, gpio7] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, + pcie_reset0, pcie_reset1, i2c_scl, i2c_sda, spi_clk, + spi_cs, spi_mosi, spi_miso, uart_txd, uart_rxd] + minItems: 1 + maxItems: 38 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl { + compatible = "airoha,an7563-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&pinctrl 0 0 38>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + hsuart-pins { + mux { + function = "uart"; + groups = "hsuart", "hsuart_cts_rts"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml index 79910214d9b5..aad2e9880ec6 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml @@ -60,8 +60,8 @@ patternProperties: function: description: A string containing the name of the function to mux to the group. - enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, - pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + enum: [pon, olt, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1] @@ -81,7 +81,15 @@ patternProperties: then: properties: groups: - enum: [pon] + enum: [pon, pon_alt] + - if: + properties: + function: + const: olt + then: + properties: + groups: + enum: [olt] - if: properties: function: @@ -115,7 +123,7 @@ patternProperties: groups: items: enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, - uart4, uart5] + uart4, uart5, npu_uart] maxItems: 2 - if: properties: @@ -124,7 +132,7 @@ patternProperties: then: properties: groups: - enum: [i2c1] + enum: [i2c0, i2c1] - if: properties: function: @@ -159,33 +167,34 @@ patternProperties: properties: groups: items: - enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, - pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4] - maxItems: 7 + enum: [pcm_spi, pcm_spi_rst, pcm_spi_cs1] + maxItems: 3 - if: properties: function: - const: i2c + const: emmc then: properties: groups: - enum: [i2s] + enum: [emmc] - if: properties: function: - const: emmc + const: pnand then: properties: groups: - enum: [emmc] + enum: [pnand] - if: properties: function: - const: pnand + const: gpio then: properties: groups: - enum: [pnand] + enum: [gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, + gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, + gpio51, gpio52] - if: properties: function: @@ -207,7 +216,8 @@ patternProperties: gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, - gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47, + gpio48, gpio49, gpio50, gpio51] - if: properties: function: @@ -288,17 +298,16 @@ patternProperties: description: An array of strings. Each string contains the name of a pin. items: - enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk, - spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4, - gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, - gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, - gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, - gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, - gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40, - gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, - pcie_reset0, pcie_reset1, pcie_reset2] + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, + gpio29, gpio30, gpio31, gpio32, gpio33, gpio34, gpio35, + gpio36, gpio37, gpio38, i2c0_scl, i2c0_sda, i2c1_scl, + i2c1_sda, spi_clk, spi_cs, spi_mosi, spi_miso, uart_txd, + uart_rxd, pcie_reset0, pcie_reset1, mdc_0, mdio_0] minItems: 1 - maxItems: 58 + maxItems: 53 bias-disable: true @@ -346,6 +355,8 @@ examples: interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 2 53>; + pcie1-rst-pins { conf { pins = "pcie_reset1"; diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml new file mode 100644 index 000000000000..599f80e94432 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7523-pinctrl.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,en7523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7523 Pin Controller + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The Airoha's EN7523 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,en7523-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - gpio-ranges + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, i2s, gpio, pcie_reset, pwm, phy1_led0, + phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, + phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: tod_1pps + then: + properties: + groups: + enum: [pon_tod_1pps, gsw_tod_1pps] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart2, npu_uart] + maxItems: 2 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c1] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pcm_spi + then: + properties: + groups: + items: + enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, + pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3, + pcm_spi_cs4] + maxItems: 7 + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio28, gpio29] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio22, gpio23, gpio24, gpio25] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio22, gpio23, gpio24, gpio25] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio22, gpio23, gpio24, gpio25] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio22, gpio23, gpio24, gpio25] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio7, gpio6, gpio5, gpio4] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio7, gpio6, gpio5, gpio4] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio7, gpio6, gpio5, gpio4] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio7, gpio6, gpio5, gpio4] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [i2c_sda, i2c_scl, spi_cs0, spi_clk, spi_mosi, spi_miso, + uart1_txd, uart1_rxd, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, + gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, pcie_reset0, pcie_reset1] + minItems: 1 + maxItems: 38 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl { + compatible = "airoha,en7523-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&pinctrl 0 12 30>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml index 21fd4f1ba78b..0cf1826c691f 100644 --- a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml @@ -61,7 +61,7 @@ patternProperties: description: A string containing the name of the function to mux to the group. enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, - pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + pcm_spi, i2s, emmc, pnand, gpio, pcie_reset, pwm, phy1_led0, phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, phy3_led1, phy4_led1] @@ -166,7 +166,7 @@ patternProperties: - if: properties: function: - const: i2c + const: i2s then: properties: groups: @@ -190,6 +190,14 @@ patternProperties: - if: properties: function: + const: gpio + then: + properties: + groups: + enum: [gpio47, gpio48, gpio49] + - if: + properties: + function: const: pcie_reset then: properties: @@ -208,7 +216,8 @@ patternProperties: gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, - gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47, + gpio48, gpio49] - if: properties: function: @@ -347,6 +356,8 @@ examples: interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pinctrl 0 13 50>; + pcie1-rst-pins { conf { pins = "pcie_reset1"; diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml index 154e03da8ce9..f87b8274cc37 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -34,7 +34,7 @@ properties: interrupts: minItems: 2 - maxItems: 10 + maxItems: 11 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. @@ -61,7 +61,7 @@ properties: bank found in the controller $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 - maxItems: 10 + maxItems: 11 patternProperties: # It's pretty scary, but the basic idea is that: @@ -130,8 +130,8 @@ allOf: then: properties: interrupts: - minItems: 10 - maxItems: 10 + minItems: 11 + maxItems: 11 - if: properties: diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 6ba66c2033b4..b69db1b95345 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -17,6 +17,7 @@ properties: oneOf: - enum: - amlogic,pinctrl-a4 + - amlogic,pinctrl-a9 - amlogic,pinctrl-s6 - amlogic,pinctrl-s7 - items: diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 41073176bc69..f08d2c4f5784 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -20,6 +20,8 @@ properties: - items: - enum: - apple,t6020-pinctrl + - apple,t6030-pinctrl + - apple,t6031-pinctrl - apple,t8122-pinctrl - const: apple,t8103-pinctrl - items: diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml new file mode 100644 index 000000000000..407a64f28d49 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC0 Pin Controller + +maintainers: + - Billy Tsai <billy_tsai@aspeedtech.com> + +description: > + The AST2700 features a dual-SoC architecture with two interconnected SoCs, + each having its own System Control Unit (SCU) for independent pin control. + This pin controller manages the pin multiplexing for SoC0. + + The SoC0 pin controller manages pin functions including eMMC, VGA DDC, + dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces. + +properties: + compatible: + const: aspeed,ast2700-soc0-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-state$': + description: | + Pin control state. + + If 'function' is present, the node describes a pinmux state and must + specify 'groups'. + + For pin configuration, exactly one of 'groups' or 'pins' must be + specified in each state node. Group-level configuration applies to all + pins in the group. Pin-level configuration may be supplied in a + separate state node for individual pins; when both group-level and + pin-level configuration apply to the same pin, the pin-level + configuration takes precedence. + + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + - if: + required: + - function + then: + required: + - groups + - oneOf: + - required: + - groups + - required: + - pins + + additionalProperties: false + + properties: + function: + enum: + - EMMC + - JTAGDDR + - JTAGM0 + - JTAGPCIEA + - JTAGPCIEB + - JTAGPSP + - JTAGSSP + - JTAGTSP + - JTAGUSB3A + - JTAGUSB3B + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2AD0 + - USB2AD1 + - USB2AH + - USB2AHP + - USB2AHPD0 + - USB2AXH + - USB2AXH2B + - USB2AXHD1 + - USB2AXHP + - USB2AXHP2B + - USB2AXHPD1 + - USB2BD0 + - USB2BD1 + - USB2BH + - USB2BHP + - USB2BHPD0 + - USB2BXH + - USB2BXH2A + - USB2BXHD1 + - USB2BXHP + - USB2BXHP2A + - USB2BXHPD1 + - USB3AXH + - USB3AXH2B + - USB3AXHD + - USB3AXHP + - USB3AXHP2B + - USB3AXHPD + - USB3BXH + - USB3BXH2A + - USB3BXHD + - USB3BXHP + - USB3BXHP2A + - USB3BXHPD + - VB + - VGADDC + + groups: + enum: + - EMMCCDN + - EMMCG1 + - EMMCG4 + - EMMCG8 + - EMMCWPN + - JTAG0 + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2A + - USB2AAP + - USB2ABP + - USB2ADAP + - USB2AH + - USB2AHAP + - USB2B + - USB2BAP + - USB2BBP + - USB2BDBP + - USB2BH + - USB2BHBP + - USB3A + - USB3AAP + - USB3ABP + - USB3B + - USB3BAP + - USB3BBP + - VB0 + - VB1 + - VGADDC + + pins: + enum: + - AB13 + - AB14 + - AC13 + - AC14 + - AD13 + - AD14 + - AE13 + - AE14 + - AE15 + - AF13 + - AF14 + - AF15 + + drive-strength: + enum: [3, 6, 8, 11, 16, 18, 20, 23, 30, 32, 33, 35, 37, 38, 39, 41] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + emmc-state { + function = "EMMC"; + groups = "EMMCG1"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml new file mode 100644 index 000000000000..fe7cef4fef6a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml @@ -0,0 +1,761 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC1 Pin Controller + +maintainers: + - Billy Tsai <billy_tsai@aspeedtech.com> + +description: + The AST2700 features a dual-SoC architecture with two interconnected SoCs, + each having its own System Control Unit (SCU) for independent pin control. + This pin controller manages the pin multiplexing for SoC1. + + The SoC1 pin controller manages pin functions including eSPI, LPC and I2C, + among others. + +properties: + compatible: + const: aspeed,ast2700-soc1-pinctrl + reg: + maxItems: 1 + +patternProperties: + '-state$': + description: | + Pin control state. + + If `function` is present, the node describes a pinmux state and must + specify `groups`. + + For pin configuration, exactly one of `groups` or `pins` must be + specified in each state node. Group-level configuration applies to all + pins in the group. Pin-level configuration may be supplied in a + separate state node for individual pins; when both group-level and + pin-level configuration apply to the same pin, the pin-level + configuration takes precedence. + + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + - if: + required: + - function + then: + required: + - groups + - oneOf: + - required: + - groups + - required: + - pins + additionalProperties: false + + properties: + function: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - AUXPWRGOOD0 + - AUXPWRGOOD1 + - CANBUS + - ESPI0 + - ESPI1 + - FSI0 + - FSI1 + - FSI2 + - FSI3 + - FWQSPI + - FWSPIABR + - FWWPN + - HBLED + - I2C0 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I2CF0 + - I2CF1 + - I2CF2 + - I3C0 + - I3C1 + - I3C10 + - I3C11 + - I3C12 + - I3C13 + - I3C14 + - I3C15 + - I3C2 + - I3C3 + - I3C4 + - I3C5 + - I3C6 + - I3C7 + - I3C8 + - I3C9 + - JTAGM1 + - LPC0 + - LPC1 + - LTPI + - MACLINK0 + - MACLINK1 + - MACLINK2 + - MDIO0 + - MDIO1 + - MDIO2 + - NCTS0 + - NCTS1 + - NCTS5 + - NCTS6 + - NDCD0 + - NDCD1 + - NDCD5 + - NDCD6 + - NDSR0 + - NDSR1 + - NDSR5 + - NDSR6 + - NDTR0 + - NDTR1 + - NDTR5 + - NDTR6 + - NRI0 + - NRI1 + - NRI5 + - NRI6 + - NRTS0 + - NRTS1 + - NRTS5 + - NRTS6 + - OSCCLK + - PCIERC + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - QSPI0 + - QSPI1 + - QSPI2 + - RGMII0 + - RGMII1 + - RMII0 + - RMII0RCLKO + - RMII1 + - RMII1RCLKO + - SALT0 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD + - SGMII + - SGPM0 + - SGPM1 + - SGPS + - SIOONCTRLN0 + - SIOONCTRLN1 + - SIOPBIN0 + - SIOPBIN1 + - SIOPBON0 + - SIOPBON1 + - SIOPWREQN0 + - SIOPWREQN1 + - SIOPWRGD1 + - SIOS3N0 + - SIOS3N1 + - SIOS5N0 + - SIOS5N1 + - SIOSCIN0 + - SIOSCIN1 + - SMON0 + - SMON1 + - SPI0 + - SPI0ABR + - SPI0CS1 + - SPI0WPN + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WPN + - SPI2 + - SPI2CS1 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - UART0 + - UART1 + - UART10 + - UART11 + - UART2 + - UART3 + - UART5 + - UART6 + - UART7 + - UART8 + - UART9 + - USB2C + - USB2D + - USBUART + - VGA + - VPI + - WDTRST0N + - WDTRST1N + - WDTRST2N + - WDTRST3N + - WDTRST4N + - WDTRST5N + - WDTRST6N + - WDTRST7N + + groups: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - AUXPWRGOOD0 + - AUXPWRGOOD1 + - CANBUS + - DI2C0 + - DI2C1 + - DI2C10 + - DI2C11 + - DI2C12 + - DI2C13 + - DI2C14 + - DI2C15 + - DI2C2 + - DI2C3 + - DI2C8 + - DI2C9 + - DSGPM0 + - ESPI0 + - ESPI1 + - FSI0 + - FSI1 + - FSI2 + - FSI3 + - FWQSPI + - FWSPIABR + - FWWPN + - HBLED + - HVI3C0 + - HVI3C1 + - HVI3C12 + - HVI3C13 + - HVI3C14 + - HVI3C15 + - HVI3C2 + - HVI3C3 + - I2C0 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I2CF0 + - I2CF1 + - I2CF2 + - I3C10 + - I3C11 + - I3C4 + - I3C5 + - I3C6 + - I3C7 + - I3C8 + - I3C9 + - JTAGM1 + - JTAGM1TRST + - LPC0 + - LPC1 + - LTPI + - LTPI_PS_I2C0 + - LTPI_PS_I2C1 + - LTPI_PS_I2C2 + - LTPI_PS_I2C3 + - MACLINK0 + - MACLINK1 + - MACLINK2 + - MDIO0 + - MDIO1 + - MDIO2 + - NCTS0 + - NCTS1 + - NCTS5 + - NCTS6 + - NDCD0 + - NDCD1 + - NDCD5 + - NDCD6 + - NDSR0 + - NDSR1 + - NDSR5 + - NDSR6 + - NDTR0 + - NDTR1 + - NDTR5 + - NDTR6 + - NRI0 + - NRI1 + - NRI5 + - NRI6 + - NRTS0 + - NRTS1 + - NRTS5 + - NRTS6 + - OSCCLK + - PE2SGRSTN + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - QSPI0 + - QSPI1 + - QSPI2 + - RGMII0 + - RGMII1 + - RMII0 + - RMII0RCLKO + - RMII1 + - RMII1RCLKO + - SALT0 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD + - SGMII + - SGPM0 + - SGPM1 + - SGPS + - SIOONCTRLN0 + - SIOONCTRLN1 + - SIOPBIN0 + - SIOPBIN1 + - SIOPBON0 + - SIOPBON1 + - SIOPWREQN0 + - SIOPWREQN1 + - SIOPWRGD1 + - SIOS3N0 + - SIOS3N1 + - SIOS5N0 + - SIOS5N1 + - SIOSCIN0 + - SIOSCIN1 + - SMON0 + - SMON1 + - SPI0 + - SPI0ABR + - SPI0CS1 + - SPI0WPN + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WPN + - SPI2 + - SPI2CS1 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - UART0 + - UART1 + - UART10 + - UART11 + - UART2 + - UART3 + - UART5 + - UART6 + - UART7 + - UART8 + - UART9 + - USB2CD + - USB2CH + - USB2CU + - USB2CUD + - USB2DD + - USB2DH + - USBUART + - VGA + - VPI + - WDTRST0N + - WDTRST1N + - WDTRST2N + - WDTRST3N + - WDTRST4N + - WDTRST5N + - WDTRST6N + - WDTRST7N + + pins: + enum: + - A14 + - A15 + - A18 + - A19 + - A21 + - A22 + - A23 + - A24 + - A25 + - A26 + - A6 + - A7 + - A8 + - AA12 + - AA13 + - AA14 + - AA15 + - AA16 + - AA17 + - AA18 + - AA20 + - AA21 + - AA22 + - AA23 + - AA24 + - AA25 + - AA26 + - AB15 + - AB16 + - AB17 + - AB18 + - AB19 + - AB20 + - AB21 + - AB22 + - AB23 + - AB24 + - AB25 + - AB26 + - AC15 + - AC16 + - AC17 + - AC18 + - AC19 + - AC20 + - AC22 + - AC24 + - AC25 + - AC26 + - AD15 + - AD16 + - AD17 + - AD18 + - AD19 + - AD20 + - AD22 + - AD25 + - AD26 + - AE16 + - AE17 + - AE18 + - AE19 + - AE20 + - AE21 + - AE23 + - AE25 + - AE26 + - AF16 + - AF17 + - AF18 + - AF19 + - AF20 + - AF21 + - AF23 + - AF25 + - AF26 + - B10 + - B11 + - B12 + - B13 + - B14 + - B15 + - B16 + - B18 + - B19 + - B21 + - B22 + - B23 + - B24 + - B25 + - B26 + - B6 + - B7 + - B8 + - B9 + - C10 + - C11 + - C12 + - C13 + - C14 + - C15 + - C16 + - C17 + - C18 + - C19 + - C20 + - C23 + - C26 + - C6 + - C7 + - C8 + - C9 + - D10 + - D12 + - D14 + - D15 + - D19 + - D20 + - D24 + - D26 + - D7 + - D8 + - D9 + - E10 + - E11 + - E12 + - E13 + - E14 + - E26 + - E7 + - E8 + - E9 + - F10 + - F11 + - F12 + - F13 + - F14 + - F26 + - F7 + - F8 + - F9 + - G10 + - G11 + - G7 + - G8 + - G9 + - H10 + - H11 + - H7 + - H8 + - H9 + - J10 + - J11 + - J12 + - J13 + - J9 + - K12 + - K13 + - L12 + - M13 + - M14 + - M15 + - M16 + - N13 + - N14 + - N15 + - N25 + - N26 + - P13 + - P14 + - P25 + - P26 + - R14 + - R25 + - R26 + - T23 + - T24 + - U21 + - U22 + - U25 + - U26 + - V14 + - V16 + - V17 + - V18 + - V19 + - V20 + - V21 + - V22 + - V23 + - V24 + - W14 + - W16 + - W17 + - W18 + - W20 + - W21 + - W22 + - W25 + - W26 + - Y11 + - Y15 + - Y16 + - Y17 + - Y18 + - Y20 + - Y21 + - Y22 + - Y23 + - Y24 + - Y25 + - Y26 + + drive-strength: + enum: [4, 8, 12, 16] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + pinctrl@400 { + compatible = "aspeed,ast2700-soc1-pinctrl"; + reg = <0x400 0x2A0>; + sgpm0-state { + function = "SGPM0"; + groups = "SGPM0"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index aa71398cf522..1468c6f87cfa 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -17,6 +17,7 @@ properties: enum: - mediatek,mt2701-pinctrl - mediatek,mt2712-pinctrl + - mediatek,mt6392-pinctrl - mediatek,mt6397-pinctrl - mediatek,mt7623-pinctrl - mediatek,mt8127-pinctrl diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index 68e91c05f122..9a937f414cc9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -152,6 +152,14 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] + slew-rate: + description: | + Set the slew rate. Valid arguments are described as below: + 0: Normal slew rate + 1: Slower slew + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + required: - pinmux diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml new file mode 100644 index 000000000000..9b834e87afde --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6858-pinctrl.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6858-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6858 Pin Controller + +maintainers: + - Nikolai Burov <nikolai.burov@jolla.com> + +description: + The MediaTek's MT6858 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6858-pinctrl + + reg: + items: + - description: gpio base + - description: lm group IO + - description: rb group IO + - description: bm2 group IO + - description: bm group IO + - description: bm1 group IO + - description: lt group IO + - description: lt1 group IO + - description: rt group IO + - description: rt1 group IO + - description: eint south group IO + - description: eint west group IO + - description: eint east group IO + - description: eint center group IO + + reg-names: + items: + - const: base + - const: lm + - const: rb + - const: bm2 + - const: bm + - const: bm1 + - const: lt + - const: lt1 + - const: rt + - const: rt1 + - const: eint0 + - const: eint1 + - const: eint2 + - const: eint3 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in arch/arm64/boot/dts/mediatek/mt6858-pinfunc.h + for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt65xx.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #define PINMUX_GPIO149__FUNC_SCL5 (MTK_PIN_NO(149) | 1) + #define PINMUX_GPIO150__FUNC_SDA5 (MTK_PIN_NO(150) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6858-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11b20000 0x1000>, + <0x11c10000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11ed0000 0x1000>, + <0x11ee0000 0x1000>, + <0x11b00000 0x1000>, + <0x11e60000 0x1000>, + <0x11e80000 0x1000>, + <0x1c01e000 0x1000>; + reg-names = "base", "lm", "rb", "bm2", "bm", "bm1", "lt", "lt1", + "rt", "rt1", "eint0", "eint1", "eint2", "eint3"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 197>; + interrupt-controller; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + i2c5-pins { + pins { + pinmux = <PINMUX_GPIO149__FUNC_SCL5>, + <PINMUX_GPIO150__FUNC_SDA5>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 6b925c5099cc..021307b6d801 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -65,6 +65,11 @@ then: - "#interrupt-cells" patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + '-pins(-[a-z]+)?$': type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml index 1f31b520cb43..a33f1fd277c9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml @@ -573,7 +573,7 @@ examples: uart0_pins: uart0-pins { mux { function = "uart"; - groups = "uart0"; + groups = "uart0"; }; }; }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml index e994b0c70dbf..1cf06e46f7bb 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -67,6 +67,11 @@ properties: # PIN CONFIGURATION NODES patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + '-pins$': type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt deleted file mode 100644 index 51efd2085113..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt +++ /dev/null @@ -1,60 +0,0 @@ -* Microchip PIC32 Pin Controller - -Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and -../interrupt-controller/interrupts.txt for generic information regarding -pin controller, GPIO, and interrupt bindings. - -PIC32 'pin configuration node' is a node of a group of pins which can be -used for a specific device or function. This node represents configurations of -pins, optional function, and optional mux related configuration. - -Required properties for pin controller node: - - compatible: "microchip,pic32mada-pinctrl" - - reg: Address range of the pinctrl registers. - - clocks: Clock specifier (see clock bindings for details) - -Required properties for pin configuration sub-nodes: - - pins: List of pins to which the configuration applies. - -Optional properties for pin configuration sub-nodes: ----------------------------------------------------- - - function: Mux function for the specified pins. - - bias-pull-up: Enable weak pull-up. - - bias-pull-down: Enable weak pull-down. - - input-enable: Set the pin as an input. - - output-low: Set the pin as an output level low. - - output-high: Set the pin as an output level high. - - microchip,digital: Enable digital I/O. - - microchip,analog: Enable analog I/O. - -Example: - -pic32_pinctrl: pinctrl@1f801400{ - #address-cells = <1>; - #size-cells = <1>; - compatible = "microchip,pic32mzda-pinctrl"; - reg = <0x1f801400 0x400>; - clocks = <&rootclk PB1CLK>; - - pinctrl_uart2: pinctrl_uart2 { - uart2-tx { - pins = "G9"; - function = "U2TX"; - microchip,digital; - output-low; - }; - uart2-rx { - pins = "B0"; - function = "U2RX"; - microchip,digital; - input-enable; - }; - }; -}; - -uart2: serial@1f822200 { - compatible = "microchip,pic32mzda-uart"; - reg = <0x1f822200 0x50>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32mzda-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic32mzda-pinctrl.yaml new file mode 100644 index 000000000000..dcaa87d9a30b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32mzda-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,pic32mzda-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 Pin Controller + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: + PIC32 pin configuration node is a node of a group of pins which can be used + for a specific device or function. This node represents configurations of + pins, optional function, and optional mux related configuration. + +properties: + compatible: + const: microchip,pic32mzda-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +$defs: + pin-node: + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + properties: + pins: + description: List of pins to which the configuration applies. + items: + type: string + minItems: 1 + + function: true + + bias-pull-up: true + bias-pull-down: true + input-enable: true + output-low: true + output-high: true + + microchip,digital: + description: Enable digital I/O. + type: boolean + + microchip,analog: + description: Enable analog I/O. + type: boolean + + required: + - pins + + unevaluatedProperties: false + +additionalProperties: + oneOf: + - additionalProperties: + $ref: '#/$defs/pin-node' + - $ref: '#/$defs/pin-node' + +required: + - compatible + - reg + - clocks + +examples: + - | + #include <dt-bindings/clock/microchip,pic32-clock.h> + #include <dt-bindings/interrupt-controller/irq.h> + + pic32_pinctrl: pinctrl@1f801400 { + compatible = "microchip,pic32mzda-pinctrl"; + reg = <0x1f801400 0x400>; + clocks = <&rootclk PB1CLK>; + + pinctrl_uart2: pinctrl_uart2 { + uart2-tx { + pins = "G9"; + function = "U2TX"; + microchip,digital; + output-low; + }; + + uart2-rx { + pins = "B0"; + function = "U2RX"; + microchip,digital; + input-enable; + }; + }; + }; + + uart2: serial@1f822200 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822200 0x50>; + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>, + <146 IRQ_TYPE_LEVEL_HIGH>, + <147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rootclk PB2CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml index db8224dfba2c..4910dc8e8aeb 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -58,7 +58,11 @@ patternProperties: drive_soc_gpio27_pee6, drive_ao_retention_n_pee2, drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ] -unevaluatedProperties: false +required: + - compatible + - reg + +additionalProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml index f5a3a881dec4..52b3d40e8839 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -115,7 +115,11 @@ patternProperties: drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3, drive_sdmmc1_dat0_pj2 ] -unevaluatedProperties: false +required: + - compatible + - reg + +additionalProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file mode 100644 index 000000000000..2b2e1a82880e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 AON Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra238-pinmux-aon + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra238-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2, + pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5, + soc_gpio25_paa6, soc_gpio26_paa7, + hdmi_cec_pbb0, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, + gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1, + gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4, + dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7, + pwm3_pee0, pwm7_pee1, soc_gpio49_pee2, + soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5, + soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2, + soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5, + soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0, + soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3, + uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6, + uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1, + uart5_cts_phh2, soc_gpio86_phh3, + # drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH) + drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1, + drive_vcomp_alert_paa2, drive_pwm1_paa3, + drive_batt_oc_paa4, drive_soc_gpio04_paa5, + drive_soc_gpio25_paa6, drive_soc_gpio26_paa7, + drive_hdmi_cec_pbb0, + drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, + drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3, + drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5, + drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7, + drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1, + drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3, + drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5, + drive_soc_gpio19_pdd6, drive_pwm2_pdd7, + drive_pwm3_pee0, drive_pwm7_pee1, + drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, + drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, + drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, + drive_soc_gpio86_phh3, drive_soc_gpio72_pff3, + drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, + drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, + drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, + drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0, + drive_uart5_tx_pgg7, drive_uart5_rx_phh0, + drive_uart2_tx_pgg2, drive_uart2_rx_pgg3, + drive_uart2_cts_pgg5, drive_uart2_rts_pgg4, + drive_uart5_cts_phh2, drive_uart5_rts_phh1 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@c300000 { + compatible = "nvidia,tegra238-pinmux-aon"; + reg = <0x0c300000 0x4000>; + + pinctrl-names = "cec"; + pinctrl-0 = <&cec_state>; + + cec_state: pinmux-cec { + cec { + nvidia,pins = "hdmi_cec_pbb0"; + nvidia,function = "hdmi_cec"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml new file mode 100644 index 000000000000..5c7608981f2d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +$ref: nvidia,tegra-pinmux-common.yaml + +properties: + nvidia,function: + enum: [ dca_vsync, dca_hsync, displaya, rsvd0, i2c7_clk, i2c7_dat, + i2c4_dat, i2c4_clk, i2c9_dat, i2c9_clk, usb_vbus_en0, + usb_vbus_en1, spi3_din, spi1_cs0, spi3_cs0, spi1_din, + spi3_cs1, spi1_sck, spi3_sck, spi1_cs1, spi1_dout, spi3_dout, + gp_pwm5, gp_pwm6, extperiph2_clk, extperiph1_clk, i2c3_dat, + i2c3_clk, extperiph4_clk, extperiph3_clk, dmic2_dat, + dmic2_clk, uarta_cts, uarta_rts, uarta_rxd, uarta_txd, + i2c5_clk, i2c5_dat, uartd_cts, uartd_rts, uartd_rxd, + uartd_txd, i2c1_clk, i2c1_dat, sdmmc1_cd, i2s2_sclk, + i2s2_sdata_out, i2s2_sdata_in, i2s2_lrck, i2s4_sclk, + i2s4_sdata_out, i2s4_sdata_in, i2s4_lrck, i2s1_sclk, + i2s1_sdata_out, i2s1_sdata_in, i2s1_lrck, aud_mclk, + i2s3_lrck, i2s3_sclk, i2s3_sdata_in, i2s3_sdata_out, + pe2_clkreq_l, pe1_clkreq_l, pe1_rst_l, pe0_clkreq_l, + pe0_rst_l, pe2_rst_l, pe3_clkreq_l, pe3_rst_l, + dp_aux_ch0_hpd, qspi0_io0, qspi0_io1, qspi0_sck, qspi0_cs_n, + uartg_cts, uartg_rts, uartg_txd, uartg_rxd, sdmmc1_clk, + sdmmc1_cmd, sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, + sdmmc1_dat1, sdmmc1_dat0, ufs0, soc_therm_oc1, hdmi_cec, + gp_pwm4, uartc_rxd, uartc_txd, i2c8_dat, i2c8_clk, + spi2_dout, i2c2_clk, spi2_cs0, i2c2_dat, spi2_sck, spi2_din, + ppc_mode_1, ppc_ready, ppc_mode_2, ppc_cc, ppc_mode_0, + ppc_int_n, uarte_txd, uarte_rxd, uartb_txd, uartb_rxd, + uartb_cts, uartb_rts, uarte_cts, uarte_rts, gp_pwm7, + gp_pwm2, gp_pwm3, gp_pwm1, spi2_cs1, dmic1_clk, dmic1_dat, + rsvd1, dcb_hsync, dcb_vsync, soc_therm_oc4, gp_pwm8, + nv_therm_fan_tach0, wdt_reset_outa, ccla_la_trigger_mux, + dspk1_dat, dspk1_clk, nv_therm_fan_tach1, dspk0_dat, + dspk0_clk, i2s5_sclk, i2s6_lrck, i2s6_sdata_in, i2s6_sclk, + i2s6_sdata_out, i2s5_lrck, i2s5_sdata_out, i2s5_sdata_in, + sdmmc1_pe3_rst_l, sdmmc1_pe3_clkreq_l, touch_clk, + ppc_i2c_dat, wdt_reset_outb, spi5_cs1, ppc_rst_n, + ppc_i2c_clk, spi4_cs1, soc_therm_oc3, spi5_sck, spi5_miso, + spi4_sck, spi4_miso, spi4_cs0, spi4_mosi, spi5_cs0, + spi5_mosi, led_blink, rsvd2, dmic3_clk, dmic3_dat, + dmic4_clk, dmic4_dat, tsc_edge_out0, tsc_edge_out3, + tsc_edge_out1, tsc_edge_out2, dmic5_clk, dmic5_dat, rsvd3, + sdmmc1_wp, tsc_edge_out0a, tsc_edge_out0d, tsc_edge_out0b, + tsc_edge_out0c, soc_therm_oc2 ] + + # out of the common properties, only these are allowed for Tegra238 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + +required: + - nvidia,pins + +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml new file mode 100644 index 000000000000..92d276634d76 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra238-pinmux + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra238-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ gpu_pwr_req_pa0, gp_pwm5_pa1, gp_pwm6_pa2, spi3_sck_pa3, + spi3_miso_pa4, spi3_mosi_pa5, spi3_cs0_pa6, spi3_cs1_pa7, + spi1_sck_pb0, spi1_miso_pb1, spi1_mosi_pb2, spi1_cs0_pb3, + spi1_cs1_pb4, pwr_i2c_scl_pc0, pwr_i2c_sda_pc1, + extperiph1_clk_pc2, extperiph2_clk_pc3, cam_i2c_scl_pc4, + cam_i2c_sda_pc5, soc_gpio23_pc6, soc_gpio24_pc7, + soc_gpio27_pd0, soc_gpio55_pd1, soc_gpio29_pd2, + soc_gpio33_pd3, soc_gpio32_pd4, soc_gpio35_pd5, + soc_gpio37_pd6, soc_gpio56_pd7, uart1_tx_pe0, + uart1_rx_pe1, uart1_rts_pe2, uart1_cts_pe3, + soc_gpio13_pf0, soc_gpio14_pf1, soc_gpio15_pf2, + soc_gpio16_pf3, soc_gpio17_pf4, soc_gpio18_pf5, + soc_gpio20_pf6, soc_gpio21_pf7, soc_gpio22_pg0, + soc_gpio06_pg1, uart4_tx_pg2, uart4_rx_pg3, + uart4_rts_pg4, uart4_cts_pg5, soc_gpio41_pg6, + soc_gpio42_pg7, soc_gpio43_ph0, soc_gpio44_ph1, + gen1_i2c_scl_ph2, gen1_i2c_sda_ph3, cpu_pwr_req_ph4, + soc_gpio07_ph5, dap3_clk_pj0, dap3_dout_pj1, + dap3_din_pj2, dap3_fs_pj3, soc_gpio57_pj4, + soc_gpio58_pj5, soc_gpio59_pj6, soc_gpio60_pj7, + soc_gpio45_pk0, soc_gpio46_pk1, soc_gpio47_pk2, + soc_gpio48_pk3, qspi0_sck_pl0, qspi0_io0_pl1, + qspi0_io1_pl2, qspi0_cs_n_pl3, soc_gpio152_pl4, + soc_gpio153_pl5, soc_gpio154_pl6, soc_gpio155_pl7, + soc_gpio156_pm0, soc_gpio157_pm1, soc_gpio158_pm2, + soc_gpio159_pm3, soc_gpio160_pm4, soc_gpio161_pm5, + soc_gpio162_pm6, uart7_tx_pm7, uart7_rx_pn0, + uart7_rts_pn1, uart7_cts_pn2, soc_gpio167_pp0, + soc_gpio168_pp1, soc_gpio169_pp2, soc_gpio170_pp3, + dap4_sclk_pp4, dap4_dout_pp5, dap4_din_pp6, dap4_fs_pp7, + soc_gpio171_pq0, soc_gpio172_pq1, soc_gpio173_pq2, + soc_gpio61_pr0, soc_gpio62_pr1, soc_gpio63_pr2, + soc_gpio64_pr3, soc_gpio65_pr4, soc_gpio66_pr5, + soc_gpio67_pr6, soc_gpio68_pr7, gen4_i2c_scl_ps0, + gen4_i2c_sda_ps1, soc_gpio75_ps2, gen7_i2c_scl_ps3, + gen7_i2c_sda_ps4, soc_gpio78_ps5, gen9_i2c_scl_ps6, + gen9_i2c_sda_ps7, soc_gpio81_pt0, soc_gpio36_pt1, + soc_gpio53_pt2, soc_gpio38_pt3, soc_gpio40_pt4, + soc_gpio34_pt5, usb_vbus_en0_pt6, usb_vbus_en1_pt7, + sdmmc1_clk_pu0, sdmmc1_cmd_pu1, sdmmc1_dat0_pu2, + sdmmc1_dat1_pu3, sdmmc1_dat2_pu4, sdmmc1_dat3_pu5, + ufs0_ref_clk_pv0, ufs0_rst_n_pv1, pex_l0_clkreq_n_pw0, + pex_l0_rst_n_pw1, pex_l1_clkreq_n_pw2, + pex_l1_rst_n_pw3, pex_l2_clkreq_n_pw4, + pex_l2_rst_n_pw5, pex_l3_clkreq_n_pw6, + pex_l3_rst_n_pw7, pex_wake_n_px0, dp_aux_ch0_hpd_px1, + bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2, + pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5, + soc_gpio25_paa6, soc_gpio26_paa7, hdmi_cec_pbb0, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, + gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3, + dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6, + pwm2_pdd7, pwm3_pee0, pwm7_pee1, soc_gpio49_pee2, + soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5, + soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2, + soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5, + soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0, + soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3, + uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6, + uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1, + uart5_cts_phh2, soc_gpio86_phh3, sdmmc1_comp, + # drive groups + drive_soc_gpio36_pt1, drive_soc_gpio53_pt2, + drive_soc_gpio38_pt3, drive_soc_gpio40_pt4, + drive_soc_gpio75_ps2, drive_soc_gpio81_pt0, + drive_soc_gpio78_ps5, drive_soc_gpio34_pt5, + drive_gen7_i2c_scl_ps3, drive_gen7_i2c_sda_ps4, + drive_gen4_i2c_sda_ps1, drive_gen4_i2c_scl_ps0, + drive_gen9_i2c_sda_ps7, drive_gen9_i2c_scl_ps6, + drive_usb_vbus_en0_pt6, drive_usb_vbus_en1_pt7, + drive_soc_gpio61_pr0, drive_soc_gpio62_pr1, + drive_soc_gpio63_pr2, drive_soc_gpio64_pr3, + drive_soc_gpio65_pr4, drive_soc_gpio66_pr5, + drive_soc_gpio67_pr6, drive_soc_gpio68_pr7, + drive_spi3_miso_pa4, drive_spi1_cs0_pb3, + drive_spi3_cs0_pa6, drive_spi1_miso_pb1, + drive_spi3_cs1_pa7, drive_spi1_sck_pb0, + drive_spi3_sck_pa3, drive_spi1_cs1_pb4, + drive_spi1_mosi_pb2, drive_spi3_mosi_pa5, + drive_gpu_pwr_req_pa0, drive_gp_pwm5_pa1, + drive_gp_pwm6_pa2, drive_extperiph2_clk_pc3, + drive_extperiph1_clk_pc2, drive_cam_i2c_sda_pc5, + drive_cam_i2c_scl_pc4, drive_soc_gpio23_pc6, + drive_soc_gpio24_pc7, drive_soc_gpio27_pd0, + drive_soc_gpio29_pd2, drive_soc_gpio32_pd4, + drive_soc_gpio33_pd3, drive_soc_gpio35_pd5, + drive_soc_gpio37_pd6, drive_soc_gpio56_pd7, + drive_soc_gpio55_pd1, drive_uart1_cts_pe3, + drive_uart1_rts_pe2, drive_uart1_rx_pe1, + drive_uart1_tx_pe0, drive_pwr_i2c_scl_pc0, + drive_pwr_i2c_sda_pc1, drive_cpu_pwr_req_ph4, + drive_uart4_cts_pg5, drive_uart4_rts_pg4, + drive_uart4_rx_pg3, drive_uart4_tx_pg2, + drive_gen1_i2c_scl_ph2, drive_gen1_i2c_sda_ph3, + drive_soc_gpio20_pf6, drive_soc_gpio21_pf7, + drive_soc_gpio22_pg0, drive_soc_gpio13_pf0, + drive_soc_gpio14_pf1, drive_soc_gpio15_pf2, + drive_soc_gpio16_pf3, drive_soc_gpio17_pf4, + drive_soc_gpio18_pf5, drive_soc_gpio41_pg6, + drive_soc_gpio42_pg7, drive_soc_gpio43_ph0, + drive_soc_gpio44_ph1, drive_soc_gpio06_pg1, + drive_soc_gpio07_ph5, drive_dap4_sclk_pp4, + drive_dap4_dout_pp5, drive_dap4_din_pp6, + drive_dap4_fs_pp7, drive_soc_gpio167_pp0, + drive_soc_gpio168_pp1, drive_soc_gpio169_pp2, + drive_soc_gpio170_pp3, drive_soc_gpio171_pq0, + drive_soc_gpio172_pq1, drive_soc_gpio173_pq2, + drive_soc_gpio45_pk0, drive_soc_gpio46_pk1, + drive_soc_gpio47_pk2, drive_soc_gpio48_pk3, + drive_soc_gpio57_pj4, drive_soc_gpio58_pj5, + drive_soc_gpio59_pj6, drive_soc_gpio60_pj7, + drive_dap3_fs_pj3, drive_dap3_clk_pj0, + drive_dap3_din_pj2, drive_dap3_dout_pj1, + drive_pex_l2_clkreq_n_pw4, drive_pex_wake_n_px0, + drive_pex_l1_clkreq_n_pw2, drive_pex_l1_rst_n_pw3, + drive_pex_l0_clkreq_n_pw0, drive_pex_l0_rst_n_pw1, + drive_pex_l2_rst_n_pw5, drive_pex_l3_clkreq_n_pw6, + drive_pex_l3_rst_n_pw7, drive_dp_aux_ch0_hpd_px1, + drive_qspi0_io0_pl1, drive_qspi0_io1_pl2, + drive_qspi0_sck_pl0, drive_qspi0_cs_n_pl3, + drive_soc_gpio156_pm0, drive_soc_gpio155_pl7, + drive_soc_gpio160_pm4, drive_soc_gpio154_pl6, + drive_soc_gpio152_pl4, drive_soc_gpio153_pl5, + drive_soc_gpio161_pm5, drive_soc_gpio162_pm6, + drive_soc_gpio159_pm3, drive_soc_gpio157_pm1, + drive_soc_gpio158_pm2, drive_uart7_cts_pn2, + drive_uart7_rts_pn1, drive_uart7_tx_pm7, + drive_uart7_rx_pn0, drive_sdmmc1_clk_pu0, + drive_sdmmc1_cmd_pu1, drive_sdmmc1_dat3_pu5, + drive_sdmmc1_dat2_pu4, drive_sdmmc1_dat1_pu3, + drive_sdmmc1_dat0_pu2, drive_ufs0_rst_n_pv1, + drive_ufs0_ref_clk_pv0, drive_batt_oc_paa4, + drive_bootv_ctl_n_paa0, drive_vcomp_alert_paa2, + drive_hdmi_cec_pbb0, drive_touch_clk_pdd3, + drive_uart3_rx_pcc6, drive_uart3_tx_pcc5, + drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1, + drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7, + drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0, + drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, + drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, + drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, + drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, + drive_soc_gpio00_paa1, drive_soc_gpio19_pdd6, + drive_soc_gpio86_phh3, drive_soc_gpio72_pff3, + drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, + drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, + drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, + drive_soc_gpio04_paa5, drive_soc_gpio85_pgg6, + drive_soc_gpio69_pff0, drive_soc_gpio25_paa6, + drive_soc_gpio26_paa7, drive_uart5_tx_pgg7, + drive_uart5_rx_phh0, drive_uart2_tx_pgg2, + drive_uart2_rx_pgg3, drive_uart2_cts_pgg5, + drive_uart2_rts_pgg4, drive_uart5_cts_phh2, + drive_uart5_rts_phh1, drive_pwm7_pee1, + drive_pwm2_pdd7, drive_pwm3_pee0, drive_pwm1_paa3, + drive_spi2_cs1_pcc4, drive_dmic1_clk_pdd4, + drive_dmic1_dat_pdd5, drive_sdmmc1_comp ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@2430000 { + compatible = "nvidia,tegra238-pinmux"; + reg = <0x2430000 0x17000>; + + pinctrl-names = "pex_rst"; + pinctrl-0 = <&pex_rst_c5_out_state>; + + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { + pexrst { + nvidia,pins = "pex_l3_rst_n_pw7"; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml new file mode 100644 index 000000000000..682e6510ed45 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 AON Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra264-pinmux-aon + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2, + batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5, + hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0, + soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1, + gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4, + uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7, + spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2, + soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5, + soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0, + soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3, + drive_ao_retention_n_paa2, drive_batt_oc_paa3, + drive_power_on_paa5, drive_vcomp_alert_paa1, + drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0, + drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0, + drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6, + drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1, + drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3, + drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5, + drive_uart0_rx_pcc6, drive_spi2_sck_pcc7, + drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1, + drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3, + drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5, + drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7, + drive_soc_gpio26_pee0, drive_soc_gpio27_pee1, + drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@c7a2000 { + compatible = "nvidia,tegra264-pinmux-aon"; + reg = <0xc7a2000 0x2000>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux-default { + uart0 { + nvidia,pins = "uart0_tx_pcc5"; + nvidia,function = "uarta_txd"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml new file mode 100644 index 000000000000..d644c496d8a5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 Pinmux Common Properties + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +$ref: nvidia,tegra-pinmux-common.yaml + +properties: + nvidia,function: + enum: [ dca_vsync, dca_hsync, rsvd0, dp_aux_ch0_hpd, dp_aux_ch1_hpd, + dp_aux_ch2_hpd, dp_aux_ch3_hpd, gp_pwm2, gp_pwm3, i2c7_clk, + i2c7_dat, i2c9_clk, i2c9_dat, uartk_cts, uartk_rts, uartk_rxd, + uartk_txd, spi3_cs0, spi3_cs3, spi3_din, spi3_dout, spi3_sck, + uartf_cts, uartf_rts, uartf_rxd, uartf_txd, spi1_cs0, spi1_cs1, + spi1_din, spi1_dout, spi1_sck, extperiph2_clk, extperiph1_clk, + i2c12_clk, i2c12_dat, nv_therm_fan_tach0, gp_pwm9, uartj_cts, + uartj_rts, uartj_rxd, uartj_txd, i2c0_clk, i2c0_dat, i2c1_clk, + i2c1_dat, i2s2_lrck, i2s2_sclk, i2s2_sdata_out, i2s2_sdata_in, + gp_pwm10, uarte_cts, uarte_rts, uarte_rxd, uarte_txd, i2c5_dat, + i2c5_clk, i2s6_sdata_in, i2s6_sdata_out, i2s6_lrck, i2s6_sclk, + i2s4_sdata_out, i2s4_sclk, i2s4_sdata_in, i2s4_lrck, spi5_cs0, + spi5_din, spi5_dout, spi5_sck, aud_mclk, i2s1_sclk, i2s1_sdata_in, + i2s1_sdata_out, i2s1_lrck, i2c11_clk, i2c11_dat, xhalt_trig, + gp_pwm1, gp_pwm6, gp_pwm7, gp_pwm8, ufs0, pe1_clkreq_l, pe1_rst_l, + pe2_rst_l, pe2_clkreq_l, pe3_clkreq_l, pe3_rst_l, sgmii0_sma_mdio, + sgmii0_sma_mdc, usb_vbus_en0, usb_vbus_en1, eth1_mdio, pe4_clkreq_l, + pe4_rst_l, pe5_clkreq_l, pe5_rst_l, eth0_mdio, eth0_mdc, eth1_mdc, + eth2_mdio, eth2_mdc, eth3_mdio, eth3_mdc, qspi0_cs_n, qspi0_io0, + qspi0_io1, qspi0_io2, qspi0_io3, qspi0_sck, sdmmc1_clk, sdmmc1_cmd, + sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, sdmmc1_dat1, sdmmc1_dat0, + qspi3_sck, qspi3_cs0, qspi3_io0, qspi3_io1, dcb_vsync, dcb_hsync, + dsa_lspii, dce_vsync, dce_hsync, dch_vsync, dch_hsync, bl_en, + bl_pwm_dim0, rsvd1, soc_therm_oc3, i2s5_sclk, i2s5_sdata_in, + extperiph3_clk, extperiph4_clk, i2s5_sdata_out, i2s5_lrck, + sdmmc1_cd, i2s7_sdata_in, spi4_sck, spi4_din, spi4_dout, spi4_cs0, + spi4_cs1, gp_pwm5, i2c14_clk, i2c14_dat, i2s8_sclk, i2s8_sdata_out, + i2s8_lrck, i2s8_sdata_in, i2c16_clk, i2c16_dat, i2s3_sclk, + i2s3_sdata_out, i2s3_sdata_in, i2s3_lrck, pm_trig1, pm_trig0, + qspi2_sck, qspi2_cs0, qspi2_io0, qspi2_io1, dcc_vsync, dcc_hsync, + rsvd2, dcf_vsync, dcf_hsync, soundwire1_clk, soundwire1_dat0, + soundwire1_dat1, soundwire1_dat2, dmic2_clk, dmic2_dat, + nv_therm_fan_tach1, i2c15_clk, i2c15_dat, i2s7_lrck, + ccla_la_trigger_mux, i2s7_sclk, i2s7_sdata_out, dmic1_dat, + dmic1_clk, dcd_vsync, dcd_hsync, rsvd3, dcg_vsync, dcg_hsync, + dspk1_clk, dspk1_dat, soc_therm_oc2, istctrl_ist_done_n, + soc_therm_oc1, tsc_edge_out0c, tsc_edge_out0d, tsc_edge_out0a, + tsc_edge_out0b, touch_clk, hdmi_cec, i2c2_clk, i2c2_dat, i2c3_clk, + i2c3_dat, gp_pwm4, uarta_txd, uarta_rxd, spi2_sck, spi2_din, + spi2_dout, spi2_cs0, tsc_sync1, tsc_edge_out3, tsc_edge_out0, + tsc_edge_out1, tsc_sync0, soundwire0_clk, soundwire0_dat0, + l0l1_rst_out_n, l2_rst_out_n, uartl_txd, uartl_rxd, i2s9_sclk, + i2s9_sdata_out, i2s9_sdata_in, i2s9_lrck, dmic5_dat, dmic5_clk, + tsc_edge_out2 ] + + # out of the common properties, only these are allowed for Tegra264 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + +required: + - nvidia,pins + +# We would typically use unevaluatedProperties here but that has the +# downside that all the properties in the common bindings become valid +# for all chip generations. In this case, however, we want the per-SoC +# bindings to be able to override which of the common properties are +# allowed, since not all pinmux generations support the same sets of +# properties. This way, the common bindings define the format of the +# properties but the per-SoC bindings define which of them apply to a +# given chip. +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml new file mode 100644 index 000000000000..01db762e82bc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-main.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 Main Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra264-pinmux-main + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, ufs0_ref_clk_pa4, + ufs0_rst_n_pa5, soc_gpio250_pf0, soc_gpio251_pf1, + soc_gpio252_pf2, dp_aux_ch0_hpd_pf3, dp_aux_ch1_hpd_pf4, + dp_aux_ch2_hpd_pf5, dp_aux_ch3_hpd_pf6, pwm2_pf7, pwm3_pg0, + gen7_i2c_scl_pg1, gen7_i2c_sda_pg2, gen9_i2c_scl_pg3, + gen9_i2c_sda_pg4, sdmmc1_clk_px0, sdmmc1_cmd_px1, + sdmmc1_dat0_px2, sdmmc1_dat1_px3, sdmmc1_dat2_px4, + sdmmc1_dat3_px5, sdmmc1_comp, soc_gpio124_pl0, + soc_gpio125_pl1, fan_tach0_pl2, soc_gpio127_pl3, + soc_gpio128_pl4, soc_gpio129_pl5, soc_gpio130_pl6, + soc_gpio131_pl7, gp_pwm9_pm0, soc_gpio133_pm1, uart9_tx_pm2, + uart9_rx_pm3, uart9_rts_n_pm4, uart9_cts_n_pm5, + soc_gpio170_pu0, soc_gpio171_pu1, soc_gpio172_pu2, + soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5, + soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0, + pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4, + uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pw0, dap2_dout_pv7, + dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3, + gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6, + pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1, + dap6_sclk_pp2, dap6_dout_pp3, dap6_din_pp4, dap6_fs_pp5, + dap4_sclk_pp6, dap4_dout_pp7, dap4_din_pq0, dap4_fs_pq1, + spi5_sck_pq2, spi5_miso_pq3, spi5_mosi_pq4, spi5_cs0_pq5, + soc_gpio152_pq6, soc_gpio153_pq7, aud_mclk_pr0, + soc_gpio155_pr1, dap1_sclk_pr2, dap1_out_pr3, dap1_in_pr4, + dap1_fs_pr5, gen11_i2c_scl_pr6, gen11_i2c_sda_pr7, + soc_gpio350_ps0, soc_gpio351_ps1, qspi0_sck_pt0, + qspi0_cs_n_pt1, qspi0_io0_pt2, qspi0_io1_pt3, qspi0_io2_pt4, + qspi0_io3_pt5, soc_gpio192_pt6, soc_gpio270_py0, + soc_gpio271_py1, soc_gpio272_py2, soc_gpio273_py3, + soc_gpio274_py4, soc_gpio275_py5, soc_gpio276_py6, + soc_gpio277_py7, soc_gpio278_pz0, soc_gpio279_pz1, + xhalt_trig_pz2, soc_gpio281_pz3, soc_gpio282_pz4, + soc_gpio283_pz5, soc_gpio284_pz6, soc_gpio285_pz7, + soc_gpio286_pal0, soc_gpio287_pal1, soc_gpio288_pal2, + cpu_pwr_req_ph0, gpu_pwr_req_ph1, uart10_tx_ph2, + uart10_rx_ph3, uart10_rts_n_ph4, uart10_cts_n_ph5, + spi3_sck_ph6, spi3_miso_ph7, spi3_mosi_pj0, spi3_cs0_pj1, + spi3_cs3_pj2, uart5_tx_pj3, uart5_rx_pj4, uart5_rts_n_pj5, + uart5_cts_n_pj6, spi1_sck_pj7, spi1_miso_pk0, spi1_mosi_pk1, + spi1_cs0_pk2, spi1_cs1_pk3, extperiph1_clk_pk4, + extperiph2_clk_pk5, gen12_i2c_scl_pk6, gen12_i2c_sda_pk7, + drive_cpu_pwr_req_ph0, drive_gpu_pwr_req_ph1, + drive_uart10_cts_n_ph5, drive_uart10_rts_n_ph4, + drive_uart10_rx_ph3, drive_uart10_tx_ph2, + drive_spi3_cs0_pj1, drive_spi3_cs3_pj2, + drive_spi3_miso_ph7, drive_spi3_mosi_pj0, + drive_spi3_sck_ph6, drive_uart5_cts_n_pj6, + drive_uart5_rts_n_pj5, drive_uart5_rx_pj4, + drive_uart5_tx_pj3, drive_spi1_cs0_pk2, + drive_spi1_cs1_pk3, drive_spi1_miso_pk0, + drive_spi1_mosi_pk1, drive_spi1_sck_pj7, + drive_extperiph2_clk_pk5, drive_extperiph1_clk_pk4, + drive_gen12_i2c_scl_pk6, drive_gen12_i2c_sda_pk7, + drive_soc_gpio124_pl0, drive_soc_gpio125_pl1, + drive_fan_tach0_pl2, drive_soc_gpio127_pl3, + drive_soc_gpio128_pl4, drive_soc_gpio129_pl5, + drive_soc_gpio130_pl6, drive_soc_gpio131_pl7, + drive_gp_pwm9_pm0, drive_soc_gpio133_pm1, + drive_uart9_cts_n_pm5, drive_uart9_rts_n_pm4, + drive_uart9_rx_pm3, drive_uart9_tx_pm2, + drive_sdmmc1_clk_px0, drive_sdmmc1_cmd_px1, + drive_sdmmc1_dat3_px5, drive_sdmmc1_dat2_px4, + drive_sdmmc1_dat1_px3, drive_sdmmc1_dat0_px2, + drive_qspi0_cs_n_pt1, drive_qspi0_io0_pt2, + drive_qspi0_io1_pt3, drive_qspi0_io2_pt4, + drive_qspi0_io3_pt5, drive_qspi0_sck_pt0, + drive_soc_gpio192_pt6, drive_soc_gpio138_pp0, + drive_soc_gpio139_pp1, drive_dap6_din_pp4, + drive_dap6_dout_pp3, drive_dap6_fs_pp5, + drive_dap6_sclk_pp2, drive_dap4_dout_pp7, + drive_dap4_sclk_pp6, drive_dap4_din_pq0, + drive_dap4_fs_pq1, drive_spi5_cs0_pq5, + drive_spi5_miso_pq3, drive_spi5_mosi_pq4, + drive_spi5_sck_pq2, drive_soc_gpio152_pq6, + drive_soc_gpio153_pq7, drive_soc_gpio155_pr1, + drive_aud_mclk_pr0, drive_dap1_sclk_pr2, + drive_dap1_in_pr4, drive_dap1_out_pr3, + drive_dap1_fs_pr5, drive_gen11_i2c_scl_pr6, + drive_gen11_i2c_sda_pr7, drive_soc_gpio350_ps0, + drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4, + drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2, + drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1, + drive_dap2_clk_pv6, drive_dap2_din_pw0, + drive_dap2_dout_pv7, drive_pwm10_pv1, + drive_soc_gpio170_pu0, drive_soc_gpio171_pu1, + drive_soc_gpio172_pu2, drive_soc_gpio173_pu3, + drive_soc_gpio174_pu4, drive_soc_gpio175_pu5, + drive_soc_gpio176_pu6, drive_soc_gpio177_pu7, + drive_soc_gpio178_pv0, drive_uart4_cts_n_pv5, + drive_uart4_rts_n_pv4, drive_uart4_rx_pv3, + drive_uart4_tx_pv2, drive_pwr_i2c_sda_pw7, + drive_pwr_i2c_scl_pw6, drive_soc_gpio250_pf0, + drive_soc_gpio251_pf1, drive_soc_gpio252_pf2, + drive_dp_aux_ch0_hpd_pf3, drive_dp_aux_ch1_hpd_pf4, + drive_dp_aux_ch2_hpd_pf5, drive_dp_aux_ch3_hpd_pf6, + drive_pwm2_pf7, drive_pwm3_pg0, + drive_gen7_i2c_scl_pg1, drive_gen7_i2c_sda_pg2, + drive_gen9_i2c_scl_pg3, drive_gen9_i2c_sda_pg4, + drive_soc_gpio270_py0, drive_soc_gpio271_py1, + drive_soc_gpio272_py2, drive_soc_gpio273_py3, + drive_soc_gpio274_py4, drive_soc_gpio275_py5, + drive_soc_gpio276_py6, drive_soc_gpio277_py7, + drive_soc_gpio278_pz0, drive_soc_gpio279_pz1, + drive_soc_gpio282_pz4, drive_soc_gpio283_pz5, + drive_soc_gpio284_pz6, drive_soc_gpio285_pz7, + drive_soc_gpio286_pal0, drive_soc_gpio287_pal1, + drive_soc_gpio288_pal2, drive_xhalt_trig_pz2, + drive_soc_gpio281_pz3 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@c281000 { + compatible = "nvidia,tegra264-pinmux-main"; + reg = <0xc281000 0xc000>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux-default { + sdmmc1 { + nvidia,pins = "sdmmc1_clk_px0"; + nvidia,function = "sdmmc1_cd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml new file mode 100644 index 000000000000..9a54795d9cc5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 UPHY Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra264-pinmux-uphy + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1, + pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4, + eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3, + eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0, + pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3, + pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5, + sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6, + soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, + ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0, + drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1, + drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3, + drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1, + drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6, + drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0, + drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2, + drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2, + drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5, + drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1, + drive_soc_gpio113_pb6, drive_soc_gpio114_pb7, + drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2, + drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@82e0000 { + compatible = "nvidia,tegra264-pinmux-uphy"; + reg = <0x82e0000 0x4000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: pinmux-default { + pex { + nvidia,pins = "pex_l1_rst_n_pb1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml index a24286e4def6..36f2393fa406 100644 --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright 2022 NXP +# Copyright 2022, 2026 NXP %YAML 1.2 --- $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml# @@ -17,8 +17,10 @@ description: | SIUL2_0 @ 0x4009c000 SIUL2_1 @ 0x44010000 - Every SIUL2 region has multiple register types, and here only MSCR and - IMCR registers need to be revealed for kernel to configure pinmux. + Every SIUL2 region has multiple register types. MSCR and IMCR registers + need to be revealed for kernel to configure pinmux. PGPDO and PGPDI + registers are used for GPIO output/input operations. EIRQ registers + are used for external interrupt configuration. Please note that some register indexes are reserved in S32G2, such as MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429. @@ -29,14 +31,22 @@ properties: - nxp,s32g2-siul2-pinctrl reg: + minItems: 6 description: | - A list of MSCR/IMCR register regions to be reserved. + A list of MSCR/IMCR/PGPDO/PGPDI/EIRQ register regions to be reserved. - MSCR (Multiplexed Signal Configuration Register) An MSCR register can configure the associated pin as either a GPIO pin or a function output pin depends on the selected signal source. - IMCR (Input Multiplexed Signal Configuration Register) An IMCR register can configure the associated pin as function input pin depends on the selected signal source. + - PGPDO (Parallel GPIO Pad Data Out Register) + A PGPDO register is used to set the output value of a GPIO pin. + - PGPDI (Parallel GPIO Pad Data In Register) + A PGPDI register is used to read the input value of a GPIO pin. + - EIRQ (External Interrupt Request) + EIRQ registers are used to configure and manage external interrupts. + items: - description: MSCR registers group 0 in SIUL2_0 - description: MSCR registers group 1 in SIUL2_1 @@ -44,6 +54,28 @@ properties: - description: IMCR registers group 0 in SIUL2_0 - description: IMCR registers group 1 in SIUL2_1 - description: IMCR registers group 2 in SIUL2_1 + - description: PGPDO registers in SIUL2_0 + - description: PGPDI registers in SIUL2_0 + - description: PGPDO registers in SIUL2_1 + - description: PGPDI registers in SIUL2_1 + - description: EIRQ registers in SIUL2_1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 4 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 patternProperties: '-pins$': @@ -86,11 +118,38 @@ required: - compatible - reg +oneOf: + - description: Legacy pinctrl-only node + properties: + reg: + maxItems: 6 + + gpio-controller: false + "#gpio-cells": false + gpio-ranges: false + interrupt-controller: false + "#interrupt-cells": false + interrupts: false + + - description: Pinctrl node with GPIO and external interrupt support + required: + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - "#interrupt-cells" + - interrupts + properties: + reg: + minItems: 11 + additionalProperties: false examples: - | - pinctrl@4009c240 { + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -104,7 +163,26 @@ examples: /* IMCR119-IMCR397 registers on siul2_1 */ <0x44010c1c 0x45c>, /* IMCR430-IMCR495 registers on siul2_1 */ - <0x440110f8 0x108>; + <0x440110f8 0x108>, + /* PGPDO registers on siul2_0 */ + <0x4009d700 0x10>, + /* PGPDI registers on siul2_0 */ + <0x4009d740 0x10>, + /* PGPDO registers on siul2_1 */ + <0x44011700 0x18>, + /* PGPDI registers on siul2_1 */ + <0x44011740 0x18>, + /* EIRQ registers on siul2_1 */ + <0x44010010 0x34>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 102>, + <&pinctrl 112 112 79>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; llce-can0-pins { llce-can0-grp0 { diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml new file mode 100644 index 000000000000..2b0385ed879b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-multiplexer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic pinctrl device for on-board MUX Chips + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + Generic pinctrl device for on-board MUX Chips, which switch SoC signals + between different peripherals (e.g. MMC and UART). + + The MUX select lines are often driven by a I2C GPIO expander. + +properties: + compatible: + const: pinctrl-multiplexer + +patternProperties: + '-grp$': + type: object + additionalProperties: false + properties: + mux-states: + maxItems: 1 + + required: + - mux-states + +required: + - compatible + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + pinctrl-mux { + compatible = "pinctrl-multiplexer"; + + uart-grp { + mux-states = <&mux 0>; + }; + + spi-grp { + mux-states = <&mux 1>; + }; + + i2c-grp { + mux-states = <&mux 2>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml index 290438826c50..20176bf30747 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml @@ -27,7 +27,7 @@ description: | properties: $nodename: - pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$" + pattern: "^(pinctrl|pinmux)(@[0-9a-f]+|-[a-z0-9]+)?$" "#pinctrl-cells": description: > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index 282650426487..aaaeca8e7bb7 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -86,16 +86,22 @@ $defs: qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, qlink_big_request, qlink_little_enable, qlink_little_request, qlink_wmss, qspi0, qspi_clk, - qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, - qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, - qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, - qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, - sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, - tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, - tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, - uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, - uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, - vsense_trigger_mirnat, wcn_sw_ctrl ] + qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, + qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, + qup1_se3, qup1_se4_01, qup1_se4_23, + qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, + qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, + qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb, + qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5, + qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1, + sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ] required: - pins diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml index cc5de9f77680..de9a3e67e1bb 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml @@ -36,11 +36,6 @@ patternProperties: $ref: "#/$defs/qcom-ipq4019-tlmm-state" additionalProperties: false - "-hog(-[0-9]+)?$": - type: object - required: - - gpio-hog - $defs: qcom-ipq4019-tlmm-state: type: object diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml new file mode 100644 index 000000000000..549eaa6aa11b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9650-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ9650 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ9650 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq9650-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 54 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq9650-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq9650-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq9650-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char_start, atest_char_status0, atest_char_status1, + atest_char_status2, atest_char_status3, atest_tic_en, + audio_pri_mclk_in0, audio_pri_mclk_out0, audio_pri_mclk_in1, + audio_pri_mclk_out1, audio_pri, audio_sec, audio_sec_mclk_in0, + audio_sec_mclk_out0, audio_sec_mclk_in1, audio_sec_mclk_out1, + core_voltage_0, core_voltage_1, core_voltage_2, core_voltage_3, + core_voltage_4, cri_rng0, cri_rng1, cri_rng2, dbg_out_clk, + gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, + mdc_mst, mdc_slv0, mdc_slv1, mdio_mst, mdio_slv, mdio_slv0, + mdio_slv1, pcie0_clk_req_n, pcie0_wake, pcie1_clk_req_n, + pcie1_wake, pcie2_clk_req_n, pcie2_wake, pcie3_clk_req_n, + pcie3_wake, pcie4_clk_req_n, pcie4_wake, pll_bist_sync, + pll_test, pwm, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_data, + qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, qup_se3, + qup_se4, qup_se5, qup_se6, qup_se7, resout, rx_los0, rx_los1, + rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max, tsn ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9650-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart1-default-state { + pins = "gpio43", "gpio44"; + function = "qup_se6"; + drive-strength = <8>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml new file mode 100644 index 000000000000..64fe90b2391b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,maili-tlmm.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,maili-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Maili TLMM block + +maintainers: + - Jingyi Wang <jingyi.wang@oss.qualcomm.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Maili SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,maili-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 113 + + gpio-line-names: + maxItems: 226 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-maili-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-maili-tlmm-state" + additionalProperties: false + +$defs: + qcom-maili-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk, + audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1, + cci_i2c2, cci_i2c3, cci_timer, coex_espmi, coex_uart1_rx, + coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot, egpio, + gcc_gp, gnss_adc, host2wlan_sol, host_rst, i2chub0_se0, + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1, + ibi_i3c, ibi_i3c_qup5_se0, jitter_bist, mdp_esync0, mdp_esync1, + mdp_esync2, mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3, + nav_rffe, pcie0_clk_req_n, pcie1_clk_req_n, pcie1_rst_n, + phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink, qspi, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23, qup3_se0, + qup3_se1, qup3_se2, qup3_se3, qup3_se4, qup3_se5, qup4_se0, + qup4_se1, qup4_se2, qup4_se3_01, qup4_se3_23, qup4_se3_l3, + qup4_se4_01, qup4_se4_23, qup4_se4_l3, qup5_se0, rng_rosc, + sd_write_protect, sdc2_clk, sdc2_cmd, sdc2_data, sdc2_rclk, + sdc4_clk, sdc4_cmd, sdc4_data, sys_throttle, tb_trig_sdc, + tmess_rng, tsense_clm, tsense_pwm, uim0, uim1, usb0_hs, usb_phy, + vfr, vsense_trigger_mirnat, wcn_sw ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f100000 { + compatible = "qcom,maili-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 227>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml index 73e84f188591..86c1da0f577c 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml @@ -15,9 +15,12 @@ description: properties: compatible: - const: qcom,milos-lpass-lpi-pinctrl + enum: + - qcom,eliza-lpass-lpi-pinctrl + - qcom,milos-lpass-lpi-pinctrl reg: + minItems: 1 items: - description: LPASS LPI TLMM Control and Status registers - description: LPASS LPI MCC registers @@ -74,6 +77,19 @@ $defs: allOf: - $ref: qcom,lpass-lpi-common.yaml# + - if: + properties: + compatible: + const: qcom,eliza-lpass-lpi-pinctrl + then: + properties: + reg: + maxItems: 1 + else: + properties: + reg: + minItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml new file mode 100644 index 000000000000..56758a85ead8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA8797P TLMM block + +maintainers: + - Bartosz Golaszewski <brgl@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,nord-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 90 + + gpio-line-names: + maxItems: 181 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-nord-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-nord-tlmm-state" + additionalProperties: false + +$defs: + qcom-nord-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$" + - enum: [ ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, aoss_cti, atest_char, atest_usb20, atest_usb21, + aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws, + aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws, + aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws, + aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws, + aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws, + aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws, + aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws, + aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws, + aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws, + aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws, + aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws, + aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb, + aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1, + bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer, + clink_debug, dbg_out, dbg_out_clk, + ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop, + ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10, + dp_rx11, dp_rx1_mute, + edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, + edp3_hot, edp3_lcd, + emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg, + emac1_mdc, emac1_mdio, emac1_ptp, + gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk, + gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass, + mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e, + mdp_vsync_p, mdp_vsync_s, + pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n, + pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi, + qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, + qup1_se0, qup1_se1, qup1_se2_01, qup1_se2_23, qup1_se3_01, + qup1_se3_23, qup1_se4, qup1_se5, + qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4, + qup2_se5, qup2_se6, qup3_se0_mira, qup3_se0_mirb, + sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert, + smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0, + tmess_prng1, tsc_timer, tsense_pwm, usb0_hs, + usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy, + usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f100000 { + compatible = "qcom,nord-tlmm"; + reg = <0x0f100000 0xc0000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 181>; + wakeup-parent = <&pdc>; + + qup_uart15_default: qup-uart15-default-state { + pins = "gpio147", "gpio148"; + function = "qup2_se2"; + drive-strength = <2>; + bias-disable; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 386c31e9c52b..c27e24cb206f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -30,6 +30,7 @@ properties: - qcom,pm7550-gpio - qcom,pm7550ba-gpio - qcom,pm8005-gpio + - qcom,pm8010-gpio - qcom,pm8018-gpio - qcom,pm8019-gpio - qcom,pm8038-gpio @@ -61,6 +62,7 @@ properties: - qcom,pmc8380-gpio - qcom,pmcx0102-gpio - qcom,pmd8028-gpio + - qcom,pmg1110-gpio - qcom,pmh0101-gpio - qcom,pmh0104-gpio - qcom,pmh0110-gpio @@ -134,6 +136,7 @@ allOf: compatible: contains: enum: + - qcom,pm8010-gpio - qcom,pmi8950-gpio - qcom,pmr735d-gpio then: @@ -153,6 +156,7 @@ allOf: - qcom,pm8450-gpio - qcom,pm8916-gpio - qcom,pmd8028-gpio + - qcom,pmg1110-gpio - qcom,pmk8350-gpio - qcom,pmr735a-gpio - qcom,pmr735b-gpio @@ -465,6 +469,7 @@ $defs: - gpio1-gpio10 for pm7325 - gpio1-gpio8 for pm7550ba - gpio1-gpio4 for pm8005 + - gpio1-gpio2 for pm8010 - gpio1-gpio6 for pm8018 - gpio1-gpio12 for pm8038 - gpio1-gpio40 for pm8058 @@ -493,6 +498,7 @@ $defs: - gpio1-gpio22 for pma8084 - gpio1-gpio14 for pmcx0102 - gpio1-gpio4 for pmd8028 + - gpio1-gpio4 for pmg1110 - gpio1-gpio18 for pmh0101 - gpio1-gpio8 for pmh0104 - gpio1-gpio14 for pmh0110 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml index 4fcac2e55b55..3b33daedc018 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -42,11 +42,6 @@ patternProperties: $ref: "#/$defs/qcom-sdm845-tlmm-state" additionalProperties: false - "-hog(-[0-9]+)?$": - type: object - required: - - gpio-hog - $defs: qcom-sdm845-tlmm-state: type: object diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml new file mode 100644 index 000000000000..411c402f9044 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Shikra TLMM block + +maintainers: + - Komal Bajaj <komal.bajaj@oss.qualcomm.com> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,shikra-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 83 + + gpio-line-names: + maxItems: 166 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-shikra-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-shikra-tlmm-state" + additionalProperties: false + +$defs: + qcom-shikra-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc, + atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0, + cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib, + dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg, + emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, + emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1, + i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0, + mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte, + nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n, + phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0, + qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01, + qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6, + qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01, + qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig, + ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async, + tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps, + vfr, vsense_trigger_mirnat, wlan ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@500000 { + compatible = "qcom,shikra-tlmm"; + reg = <0x00500000 0x800000>; + + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 166>; + + qup-uart0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..4903b2d37d89 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 SoC LPASS LPI TLMM + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM6350 SoC. + +properties: + compatible: + const: qcom,sm6350-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6350-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6350-lpass-state" + additionalProperties: false + +$defs: + qcom-sm6350-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-4])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, gpio, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> + + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; + reg = <0x033c0000 0x20000>, + <0x03550000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + i2s1_active: i2s1-active-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index aae3dcf6cac8..aec72e8c0621 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -51,6 +51,12 @@ properties: should not be accessed by the OS. Please see the ../gpio/gpio.txt for more information. +patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + allOf: - $ref: pinctrl.yaml# diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml index 9562a043707e..adc5955a2047 100644 --- a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml @@ -110,7 +110,7 @@ patternProperties: input-schmitt-disable: true - input-voltage-microvolt: + input-threshold-voltage-microvolt: description: | Select the input receiver voltage domain for the pin. Valid arguments are: diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 00c05243b9a4..fb1fe1ea759f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a08g046-pinctrl # RZ/G3L - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) @@ -78,6 +79,26 @@ properties: - description: PFC main reset - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins + reset-names: + oneOf: + - items: + - const: rstn + - const: port + - const: spare + - items: + - const: main + - const: error + + renesas,clonech: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of clone channel control register + description: + Phandle and offset to the system controller containing the clone channel + control values. + additionalProperties: anyOf: - type: object @@ -144,6 +165,15 @@ allOf: properties: compatible: contains: + const: renesas,r9a08g046-pinctrl + then: + required: + - renesas,clonech + + - if: + properties: + compatible: + contains: enum: - renesas,r9a09g047-pinctrl - renesas,r9a09g056-pinctrl @@ -152,10 +182,14 @@ allOf: properties: resets: maxItems: 2 + reset-names: + maxItems: 2 else: properties: resets: minItems: 3 + reset-names: + minItems: 3 required: - compatible @@ -187,6 +221,7 @@ examples: resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; power-domains = <&cpg>; scif0_pins: serial0 { diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 9b3cbeb54fed..81747bb53056 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -51,6 +51,7 @@ properties: - rockchip,rk3576-pinctrl - rockchip,rk3588-pinctrl - rockchip,rv1103b-pinctrl + - rockchip,rv1106-pinctrl - rockchip,rv1108-pinctrl - rockchip,rv1126-pinctrl diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 2b88f25e80a6..802911e23aff 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -41,6 +41,7 @@ properties: - samsung,exynos7870-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint + - samsung,exynos8855-wakeup-eint - samsung,exynos8890-wakeup-eint - samsung,exynos8895-wakeup-eint - const: samsung,exynos7-wakeup-eint diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index 7b006009ca0e..1feb6a6fc690 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -18,7 +18,7 @@ description: | All the pin controller nodes should be represented in the aliases node using the following format 'pinctrl{n}' where n is a unique number for the alias. - The controller supports three types of interrupts:: + The controller supports three types of interrupts: - External GPIO interrupts (see interrupts property in pin controller node); - External wake-up interrupts - multiplexed (capable of waking up the system @@ -53,6 +53,7 @@ properties: - samsung,exynos7870-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl + - samsung,exynos8855-pinctrl - samsung,exynos8890-pinctrl - samsung,exynos8895-pinctrl - samsung,exynos9610-pinctrl diff --git a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt deleted file mode 100644 index 7f2980567c9f..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Pin configuration for TI DA850/OMAP-L138/AM18x - -These SoCs have a separate controller for setting bias (internal pullup/down). -Bias can only be selected for groups rather than individual pins. - -Required Properties: - - - compatible: Must be "ti,da850-pupd" - - reg: Base address and length of the memory resource used by the pullup/down - controller hardware module. - -The controller node also acts as a container for pin group configuration nodes. -The names of these groups are ignored. - -Pin Group Node Properties: - -- groups: An array of strings, each string containing the name of a pin group. - Valid names are "cp0".."cp31". - -The pin configuration parameters use the generic pinconf bindings defined in -pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down. - - -Example -------- - -In common dtsi file: - - pinconf: pin-controller@22c00c { - compatible = "ti,da850-pupd"; - reg = <0x22c00c 0x8>; - }; - -In board-specific file: - - &pinconf { - pinctrl-0 = <&pinconf_bias_groups>; - pinctrl-names = "default"; - - pinconf_bias_groups: bias-groups { - pull-up { - groups = "cp30", "cp31"; - bias-pull-up; - }; - pull-down { - groups = "cp29", "cp28"; - bias-pull-down; - }; - disable { - groups = "cp27", "cp26"; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.yaml b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.yaml new file mode 100644 index 000000000000..21d439e08d4b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ti,da850-pupd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DA850/OMAP-L138/AM18x Pin Configuration + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +description: + These SoCs have a separate controller for setting bias (internal pullup/down). + Bias can only be selected for groups rather than individual pins. + The controller node also acts as a container for pin group configuration nodes. + The names of these groups are ignored. + +properties: + compatible: + const: ti,da850-pupd + + reg: + maxItems: 1 + + pinctrl-0: true + pinctrl-names: true + +patternProperties: + "-groups$": + type: object + additionalProperties: false + patternProperties: + "^(disable|pull-(up|down))$": + $ref: /schemas/pinctrl/pincfg-node.yaml# + properties: + groups: + $ref: /schemas/types.yaml#/definitions/string-array + description: An array of strings containing the name of a pin group. + items: + pattern: "^cp([0-9]|[1-2][0-9]|3[0-1])$" + bias-disable: true + bias-pull-up: true + bias-pull-down: true + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinconf: pin-controller@22c00c { + compatible = "ti,da850-pupd"; + reg = <0x22c00c 0x8>; + pinctrl-0 = <&pinconf_bias_groups>; + pinctrl-names = "default"; + + pinconf_bias_groups: bias-groups { + pull-up { + groups = "cp30", "cp31"; + bias-pull-up; + }; + pull-down { + groups = "cp29", "cp28"; + bias-pull-down; + }; + disable { + groups = "cp27", "cp26"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml b/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml new file mode 100644 index 000000000000..a798552c1ac2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ti,dra7-iodelay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin configuration for TI IODELAY controller + +maintainers: + - Nishanth Menon <nm@ti.com> + - Bhargav Joshi <j.bhargav.u@gmail.com> + +description: + TI dra7 based SoCs such as am57xx have a controller for setting the IO delay + for each pin. For most part the IO delay values are programmed by the + bootloader, but some pins need to be configured dynamically by the kernel such + as the MMC pins. + +properties: + compatible: + const: ti,dra7-iodelay + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pinctrl-cells': + const: 2 + +patternProperties: + ^.*_conf$: + type: object + additionalProperties: false + + properties: + pinctrl-pin-array: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An array of 32-bit integers defining the pin delay configuration. + + required: + - pinctrl-pin-array + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - '#pinctrl-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/dra.h> + + padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + + mmc2_iodelay_3v3_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ + 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ + 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ + 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ + 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt deleted file mode 100644 index c3ed1232b6a3..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt +++ /dev/null @@ -1,47 +0,0 @@ -* Pin configuration for TI IODELAY controller - -TI dra7 based SoCs such as am57xx have a controller for setting the IO delay -for each pin. For most part the IO delay values are programmed by the bootloader, -but some pins need to be configured dynamically by the kernel such as the -MMC pins. - -Required Properties: - - - compatible: Must be "ti,dra7-iodelay" - - reg: Base address and length of the memory resource used - - #address-cells: Number of address cells - - #size-cells: Size of cells - - #pinctrl-cells: Number of pinctrl cells, must be 2. See also - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example -------- - -In the SoC specific dtsi file: - - dra7_iodelay_core: padconf@4844a000 { - compatible = "ti,dra7-iodelay"; - reg = <0x4844a000 0x0d1c>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <2>; - }; - -In board-specific file: - -&dra7_iodelay_core { - mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { - pinctrl-pin-array = < - 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ - 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ - 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ - 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ - 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ - 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ - 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ - 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ - 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ - 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ - >; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml new file mode 100644 index 000000000000..c2332e6e60c2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 Pin Controller + +maintainers: + - Jia Wang <wangjia@ultrarisc.com> + +description: | + UltraRISC RISC-V SoC DP1000 pin controller. + The controller manages ports A, B, C, D and LPC. Ports A-D default to + GPIO and provide additional SPI, UART, I2C, and PWM mux functions. + LPC pins default to the LPC interface and can be muxed to eSPI. + All pins also support pin configuration, including drive strength, + pull-up, and pull-down settings. + +properties: + compatible: + const: ultrarisc,dp1000-pinctrl + + reg: + items: + - description: pin controller registers + +required: + - compatible + - reg + +patternProperties: + '.*-pins$': + type: object + unevaluatedProperties: false + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + - if: + properties: + pins: + items: + minimum: 40 + maximum: 52 + then: + properties: + function: + enum: + - lpc + - espi + else: + properties: + pins: + items: + maximum: 39 + function: + enum: + - gpio + - i2c + - pwm + - spi + - uart + + properties: + pins: + description: | + List of pins affected by this state node, using numeric pin IDs. + Pins 0-39 correspond to ports A-D, and pins 40-52 correspond + to LPC0-LPC12. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + uniqueItems: true + items: + minimum: 0 + maximum: 52 + + function: + description: | + Mux function to select for the listed pins. Supported functions + depend on the selected pins and match the DP1000 hardware mux + table. + enum: + - gpio + - i2c + - pwm + - spi + - uart + - lpc + - espi + + bias-disable: true + bias-high-impedance: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + description: Output drive strength in mA. + enum: [20, 27, 33, 40] + + required: + - pins + - function + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@11081000 { + compatible = "ultrarisc,dp1000-pinctrl"; + reg = <0x0 0x11081000 0x0 0x1000>; + + i2c0-pins { + pins = <12 13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0-pins { + pins = <8 9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml index 12b71688dd34..e608a0c75961 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -22,6 +22,7 @@ properties: - amlogic,meson-s4-pwrc - amlogic,a4-pwrc - amlogic,a5-pwrc + - amlogic,a9-pwrc - amlogic,c3-pwrc - amlogic,t7-pwrc - amlogic,s6-pwrc diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index caf151880999..e269f433524e 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -43,7 +43,11 @@ properties: - apple,t6000-pmgr-pwrstate - const: apple,pmgr-pwrstate - items: - - const: apple,t6020-pmgr-pwrstate + - enum: + - apple,t6020-pmgr-pwrstate + - apple,t6030-pmgr-pwrstate + - apple,t6031-pmgr-pwrstate + - apple,t8122-pmgr-pwrstate - const: apple,t8103-pmgr-pwrstate reg: diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 07f046277f8a..d03e4a925163 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -25,6 +25,7 @@ properties: enum: - mediatek,mt6735-power-controller - mediatek,mt6795-power-controller + - mediatek,mt6858-power-controller - mediatek,mt6893-power-controller - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller @@ -34,6 +35,7 @@ properties: - mediatek,mt8189-power-controller - mediatek,mt8192-power-controller - mediatek,mt8195-power-controller + - mediatek,mt8196-hfrp-power-controller - mediatek,mt8196-hwv-hfrp-power-controller - mediatek,mt8196-hwv-scp-power-controller - mediatek,mt8196-power-controller @@ -55,7 +57,7 @@ properties: faults while enabling or disabling a power domain. For example, this may hold phandles to INFRACFG and SMI. minItems: 1 - maxItems: 3 + maxItems: 6 patternProperties: "^power-domain@[0-9a-f]+$": @@ -102,6 +104,7 @@ $defs: description: | Power domain index. Valid values are defined in: "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. + "include/dt-bindings/power/mediatek,mt6858-power.h" - for MT6858 type power domain. "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain. "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. @@ -160,6 +163,23 @@ allOf: compatible: contains: enum: + - mediatek,mt6858-power-controller + then: + properties: + access-controllers: + items: + - description: handle to INFRACFG register block + - description: handle to IMG_SUB0 register block + - description: handle to CAM_SUB1 register block + - description: handle to CAM_SUB0 register block + - description: handle to IPE_SUB0 register block + - description: handle to VLPCFG register block + + - if: + properties: + compatible: + contains: + enum: - mediatek,mt8183-power-controller - mediatek,mt8196-power-controller then: diff --git a/Documentation/devicetree/bindings/power/power-domain.yaml b/Documentation/devicetree/bindings/power/power-domain.yaml index b1147dbf2e73..163b0af158fd 100644 --- a/Documentation/devicetree/bindings/power/power-domain.yaml +++ b/Documentation/devicetree/bindings/power/power-domain.yaml @@ -68,6 +68,21 @@ properties: by the given provider should be subdomains of the domain specified by this binding. + power-domains-child-ids: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + An array of child domain IDs that correspond to the power-domains + property. This property is only applicable to power domain providers + with "#power-domain-cells" > 0 (i.e., providers that supply multiple + power domains). It specifies which of the provider's child domains + should be associated with each parent domain listed in the power-domains + property. The number of elements in this array must match the number of + phandles in the power-domains property. Each element specifies the child + domain ID (index) that should be made a child domain of the corresponding + parent domain. This enables hierarchical power domain structures where + different child domains from the same provider can have different + parent domains. + required: - "#power-domain-cells" @@ -133,3 +148,22 @@ examples: min-residency-us = <7000>; }; }; + + - | + // Example: SCMI domain 15 -> MAIN_PD, SCMI domain 19 -> WKUP_PD + MAIN_PD: power-controller-main { + compatible = "foo,power-controller"; + #power-domain-cells = <0>; + }; + + WKUP_PD: power-controller-wkup { + compatible = "foo,power-controller"; + #power-domain-cells = <0>; + }; + + scmi_pds: power-controller-scmi { + compatible = "foo,power-controller"; + #power-domain-cells = <1>; + power-domains = <&MAIN_PD>, <&WKUP_PD>; + power-domains-child-ids = <15>, <19>; + }; diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 0bf1e13a9964..0a45e1f55062 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -35,6 +35,7 @@ properties: - qcom,msm8994-rpmpd - qcom,msm8996-rpmpd - qcom,msm8998-rpmpd + - qcom,nord-rpmhpd - qcom,qcm2290-rpmpd - qcom,qcs404-rpmpd - qcom,qcs615-rpmhpd @@ -55,6 +56,7 @@ properties: - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd - qcom,sdx75-rpmhpd + - qcom,shikra-rpmpd - qcom,sm4450-rpmhpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd @@ -73,6 +75,10 @@ properties: - enum: - qcom,msm8937-rpmpd - const: qcom,msm8917-rpmpd + - items: + - enum: + - qcom,maili-rpmhpd + - const: qcom,hawi-rpmhpd '#power-domain-cells': const: 1 diff --git a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml new file mode 100644 index 000000000000..1dba1e1b1c5b --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/renesas,r8a78000-mdlc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car X5H Module Controller + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + Each instance of the R-Car X5H Module Controller (MODULE CONTROL) provides + Power Gating for up to 64 Power Domains, and Module Standby and Reset for up + to 256 modules in the Power Domain of each Module hierarchy. + +properties: + compatible: + const: renesas,r8a78000-mdlc + + reg: + maxItems: 1 + + '#power-domain-cells': + description: | + - The first power domain specifier cell is the power domain part, and + must be either the Module Power Domain Gating (MPDG) register index + (0x00-0x3f) from the datasheet, for power domains which are backed by + MPDG bits and which can be controlled in that manner, or a Power + Domain number, as defined in + <dt-bindings/power/renesas,r8a78000-mdlc.h>, for power domains which + are always on, and for which there are no MPDG bits to control them. + + - The second power domain specifier cell is the module standby part, and + must be the module number (0x00-0xff), composed of the Module System + Reset (MSRES) register index in the high nibble, and the Module Reset + Destination bitfield index in the low nibble. + const: 2 + + '#reset-cells': + description: + The single reset specifier cell must be the module number (0x00-0xff), + and thus identical to the second power domain specifier cell. + const: 1 + +required: + - compatible + - reg + - '#power-domain-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + system-controller@c3060000 { + compatible = "renesas,r8a78000-mdlc"; + reg = <0xc3060000 0x1000>; + #power-domain-cells = <2>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index 347571e2545a..b67aa170b2c1 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -13,7 +13,7 @@ maintainers: description: | The R-Car (RZ/G) System Controller provides power management for the CPU cores and various coprocessors. - The power domain IDs for consumers are defined in header files:: + The power domain IDs for consumers are defined in header files: include/dt-bindings/power/r8*-sysc.h properties: diff --git a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt b/Documentation/devicetree/bindings/power/reset/keystone-reset.txt deleted file mode 100644 index c5c03789ed1e..000000000000 --- a/Documentation/devicetree/bindings/power/reset/keystone-reset.txt +++ /dev/null @@ -1,67 +0,0 @@ -* Device tree bindings for Texas Instruments keystone reset - -This node is intended to allow SoC reset in case of software reset -of selected watchdogs. - -The Keystone SoCs can contain up to 4 watchdog timers to reset -SoC. Each watchdog timer event input is connected to the Reset Mux -block. The Reset Mux block can be configured to cause reset or not. - -Additionally soft or hard reset can be configured. - -Required properties: - -- compatible: ti,keystone-reset - -- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to - access pll controller registers and the offset to use - reset control registers. - -- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to - access device state control registers and the offset - in order to use mux block registers for all watchdogs. - -Optional properties: - -- ti,soft-reset: Boolean option indicating soft reset. - By default hard reset is used. - -- ti,wdt-list: WDT list that can cause SoC reset. It's not related - to WDT driver, it's just needed to enable a SoC related - reset that's triggered by one of WDTs. The list is - in format: <0>, <2>; It can be in random order and - begins from 0 to 3, as keystone can contain up to 4 SoC - reset watchdogs and can be in random order. - -Example 1: -Setup keystone reset so that in case software reset or -WDT0 is triggered it issues hard reset for SoC. - -pllctrl: pll-controller@2310000 { - compatible = "ti,keystone-pllctrl", "syscon"; - reg = <0x02310000 0x200>; -}; - -devctrl: device-state-control@2620000 { - compatible = "ti,keystone-devctrl", "syscon"; - reg = <0x02620000 0x1000>; -}; - -rstctrl: reset-controller { - compatible = "ti,keystone-reset"; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>; -}; - -Example 2: -Setup keystone reset so that in case of software reset or -WDT0 or WDT2 is triggered it issues soft reset for SoC. - -rstctrl: reset-controller { - compatible = "ti,keystone-reset"; - ti,syscon-pll = <&pllctrl 0xe4>; - ti,syscon-dev = <&devctrl 0x328>; - ti,wdt-list = <0>, <2>; - ti,soft-reset; -}; diff --git a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml index 979a377cb4ff..3d07aa004eb6 100644 --- a/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml +++ b/Documentation/devicetree/bindings/power/reset/qcom,pon.yaml @@ -17,12 +17,16 @@ description: | properties: compatible: - enum: - - qcom,pm8916-pon - - qcom,pm8941-pon - - qcom,pms405-pon - - qcom,pm8998-pon - - qcom,pmk8350-pon + oneOf: + - enum: + - qcom,pm8916-pon + - qcom,pm8941-pon + - qcom,pms405-pon + - qcom,pm8998-pon + - qcom,pmk8350-pon + - items: + - const: qcom,pmm8654au-pon + - const: qcom,pmk8350-pon reg: description: | @@ -79,6 +83,10 @@ allOf: reg-names: items: - const: pon + patternProperties: + # Negative look-ahead to disallow unsupported modes. The '$' has to be + # part of lookahead group to work, instead of trailing outside of (). + "^mode-(?!(bootloader$|recovery$))": false else: patternProperties: "^mode-.*$": false diff --git a/Documentation/devicetree/bindings/power/reset/restart-handler.yaml b/Documentation/devicetree/bindings/power/reset/restart-handler.yaml index 965a834a3dbe..00c00ec5ec81 100644 --- a/Documentation/devicetree/bindings/power/reset/restart-handler.yaml +++ b/Documentation/devicetree/bindings/power/reset/restart-handler.yaml @@ -18,12 +18,12 @@ properties: priority: $ref: /schemas/types.yaml#/definitions/uint32 description: | - A priority ranging from 0 to 255 according to the following guidelines:: - 0:: Restart handler of last resort, with limited restart capabilities. - 128:: Typical, default restart handler; use if no other restart handler + A priority ranging from 0 to 255 according to the following guidelines: + 0: Restart handler of last resort, with limited restart capabilities. + 128: Typical, default restart handler; use if no other restart handler is expected to be available, and/or if restart functionality is sufficient to restart the entire system. - 255:: Highest priority restart handler, will preempt all other restart handlers. + 255: Highest priority restart handler, will preempt all other restart handlers. minimum: 0 maximum: 255 diff --git a/Documentation/devicetree/bindings/power/reset/ti,keystone-reset.yaml b/Documentation/devicetree/bindings/power/reset/ti,keystone-reset.yaml new file mode 100644 index 000000000000..ecc68d37f07e --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/ti,keystone-reset.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/ti,keystone-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone SoC Reset Controller + +maintainers: + - Andrew Davis <afd@ti.com> + +description: + This is intended to allow SoC reset in case of software reset of selected + watchdogs. The Keystone SoCs can contain up to 4 watchdog timers to reset + SoC. Each watchdog timer event input is connected to the Reset Mux block. The + Reset Mux block can be configured to cause reset or not. Additionally soft or + hard reset can be configured. + +properties: + compatible: + const: ti,keystone-reset + + reg: + maxItems: 1 + + ti,syscon-pll: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The phandle to syscon used to access pll controller registers and the + offset to use reset control registers. + items: + - items: + - description: phandle to pll controller syscon + - description: offset within pll controller register space + + ti,syscon-dev: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The phandle to syscon used to access device state control registers and + the offset in order to use mux block registers for all watchdogs. + items: + - items: + - description: phandle to device state control syscon + - description: offset within device state control register + + ti,soft-reset: + type: boolean + description: + Boolean option indicating soft reset. By default hard reset is used. + + ti,wdt-list: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + WDT list that can cause SoC reset. It's not related to WDT driver, it's + just needed to enable a SoC related reset that's triggered by one of + WDTs. The list is in format- <0>, <2>; It can be in random order and + begins from 0 to 3, as keystone can contain up to 4 SoC reset watchdogs + and can be in random order. + minItems: 1 + maxItems: 4 + items: + minimum: 0 + maximum: 3 + +required: + - compatible + - reg + - ti,syscon-pll + - ti,syscon-dev + +additionalProperties: false + +examples: + - | + reset-controller@328 { + compatible = "ti,keystone-reset"; + reg = <0x328 0x10>; + ti,syscon-pll = <&pllctrl 0xe4>; + ti,syscon-dev = <&devctrl 0x328>; + ti,wdt-list = <0>; + }; diff --git a/Documentation/devicetree/bindings/power/supply/maxim,max17042.yaml b/Documentation/devicetree/bindings/power/supply/maxim,max17042.yaml index 242b33f2bcba..2d9bad1c658c 100644 --- a/Documentation/devicetree/bindings/power/supply/maxim,max17042.yaml +++ b/Documentation/devicetree/bindings/power/supply/maxim,max17042.yaml @@ -44,13 +44,13 @@ properties: Defining this property enables current-sense functionality. maxim,cold-temp: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/int32 description: Temperature threshold to report battery as cold (in tenths of degree Celsius). Default is not to report cold events. maxim,over-heat-temp: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/int32 description: Temperature threshold to report battery as over heated (in tenths of degree Celsius). Default is not to report over heating events. @@ -67,13 +67,11 @@ properties: Voltage threshold to report battery as over voltage (in mV). Default is not to report over-voltage events. - power-supplies: true - required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/power/supply/maxim,max8903.yaml b/Documentation/devicetree/bindings/power/supply/maxim,max8903.yaml index 86af38378999..b3d8c0a5f214 100644 --- a/Documentation/devicetree/bindings/power/supply/maxim,max8903.yaml +++ b/Documentation/devicetree/bindings/power/supply/maxim,max8903.yaml @@ -44,9 +44,40 @@ properties: maxItems: 1 description: USB suspend pin (active high, output) + dc-current-limit-gpios: + minItems: 1 + maxItems: 4 + description: + GPIOs controlling DC input current limit via resistor mux. + Used with dc-current-limit-mapping to select charging current. + + dc-current-limit-mapping: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 2 + maxItems: 16 + description: | + Array of (current_microamps, gpio_bit_pattern) pairs defining available + DC current limits. The gpio_bit_pattern is applied to dc-current-limit-gpios + to select that current level. + items: + items: + - description: Current limit in microamps + - description: GPIO bit pattern value + + usb-current-limit-gpios: + maxItems: 1 + description: + GPIO driving the MAX8903 IUSB pin. IUSB is a silicon-fixed + two-state input - low selects 100 mA, high selects 500 mA. + Only the GPIO mapping is board-specific. + required: - compatible +dependentRequired: + dc-current-limit-gpios: [dc-current-limit-mapping] + dc-current-limit-mapping: [dc-current-limit-gpios] + anyOf: - required: - dok-gpios @@ -65,3 +96,25 @@ examples: chg-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; cen-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; }; + - | + /* Example with DC and USB current limit control */ + #include <dt-bindings/gpio/gpio.h> + charger { + compatible = "maxim,max8903"; + dok-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + flt-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + chg-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + cen-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; + dcm-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + + /* DC input current limit via IDC resistor mux */ + dc-current-limit-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>, + <&gpio1 1 GPIO_ACTIVE_HIGH>; + dc-current-limit-mapping = <750000 0>, /* GPIO[1:0]=0b00 */ + <900000 1>, /* GPIO[1:0]=0b01 */ + <1400000 3>, /* GPIO[1:0]=0b11 */ + <2000000 2>; /* GPIO[1:0]=0b10 */ + + /* USB current limit: IUSB pin, 100 mA (low) / 500 mA (high) */ + usb-current-limit-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/power/supply/sgmicro,sgm41542.yaml b/Documentation/devicetree/bindings/power/supply/sgmicro,sgm41542.yaml new file mode 100644 index 000000000000..af80fe528505 --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/sgmicro,sgm41542.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/sgmicro,sgm41542.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SGM41542 Battery Charger + +description: + The SGMicro SGM41542 is a single cell battery charger/boost controller. + +maintainers: + - Chris Morgan <macromorgan@hotmail.com> + - Xu Shengfei <xsf@rock-chips.com> + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + const: sgmicro,sgm41542 + + input-current-limit-microamp: + default: 2400000 + minimum: 100000 + maximum: 3800000 + + input-voltage-limit-microvolt: + default: 4500000 + minimum: 3900000 + maximum: 12000000 + + interrupts: + maxItems: 1 + + monitored-battery: + description: | + The charger uses the following battery properties + constant-charge-current-max-microamp (default 2040000) + constant-charge-voltage-max-microvolt (default 4208000) + charge-term-current-microamp (default 180000) + precharge-current-microamp (default 180000) + + reg: + maxItems: 1 + + regulators: + type: object + properties: + otg-vbus: + type: object + description: OTG boost regulator + $ref: /schemas/regulator/regulator.yaml + unevaluatedProperties: false + additionalProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + battery: battery { + compatible = "simple-battery"; + constant-charge-current-max-microamp = <10000000>; + constant-charge-voltage-max-microvolt = <4350000>; + precharge-current-microamp = <180000>; + charge-term-current-microamp = <300000>; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@3b { + compatible = "sgmicro,sgm41542"; + reg = <0x3b>; + input-current-limit-microamp = <3000000>; + input-voltage-limit-microvolt = <4500000>; + interrupt-parent = <&gpio0>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + monitored-battery = <&battery>; + + regulators { + otg-vbus { + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/power/supply/ti,bq25630.yaml b/Documentation/devicetree/bindings/power/supply/ti,bq25630.yaml new file mode 100644 index 000000000000..3f2904731c5a --- /dev/null +++ b/Documentation/devicetree/bindings/power/supply/ti,bq25630.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/ti,bq25630.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI BQ25630 battery charger + +maintainers: + - Waqar Hameed <waqar.hameed@axis.com> + +description: | + I2C controlled single cell Li-ion and Li-polymer 5A buck charger. + Datasheet: https://www.ti.com/lit/gpn/bq25630 + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + const: ti,bq25630 + + reg: + const: 0x6b + + interrupts: + maxItems: 1 + description: + Device sends active low 256 µs pulse. Type should therefore be + IRQ_TYPE_EDGE_FALLING. + +required: + - compatible + - reg + - interrupts + - monitored-battery + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@6b { + compatible = "ti,bq25630"; + reg = <0x6b>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + monitored-battery = <&bat>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/power/ti,smartreflex.yaml b/Documentation/devicetree/bindings/power/ti,smartreflex.yaml new file mode 100644 index 000000000000..7ca0a5eed9b2 --- /dev/null +++ b/Documentation/devicetree/bindings/power/ti,smartreflex.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/ti,smartreflex.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments SmartReflex + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +description: + SmartReflex is used to set and adjust the SoC operating points. + +properties: + compatible: + enum: + - ti,omap3-smartreflex-core + - ti,omap3-smartreflex-mpu-iva + - ti,omap4-smartreflex-core + - ti,omap4-smartreflex-mpu + - ti,omap4-smartreflex-iva + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ti,hwmods: + description: Shall contain the TI interconnect module name if needed by the SoC + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/power/ti-smartreflex.txt b/Documentation/devicetree/bindings/power/ti-smartreflex.txt deleted file mode 100644 index 21ef14d6af12..000000000000 --- a/Documentation/devicetree/bindings/power/ti-smartreflex.txt +++ /dev/null @@ -1,47 +0,0 @@ -Texas Instruments SmartReflex binding - -SmartReflex is used to set and adjust the SoC operating points. - - -Required properties: - -compatible: Shall be one of the following: - "ti,omap3-smartreflex-core" - "ti,omap3-smartreflex-mpu-iva" - "ti,omap4-smartreflex-core" - "ti,omap4-smartreflex-mpu" - "ti,omap4-smartreflex-iva" - -reg: Shall contain the device instance IO range - -interrupts: Shall contain the device instance interrupt - - -Optional properties: - -ti,hwmods: Shall contain the TI interconnect module name if needed - by the SoC - - -Example: - - smartreflex_iva: smartreflex@4a0db000 { - compatible = "ti,omap4-smartreflex-iva"; - reg = <0x4a0db000 0x80>; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "smartreflex_iva"; - }; - - smartreflex_core: smartreflex@4a0dd000 { - compatible = "ti,omap4-smartreflex-core"; - reg = <0x4a0dd000 0x80>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "smartreflex_core"; - }; - - smartreflex_mpu: smartreflex@4a0d9000 { - compatible = "ti,omap4-smartreflex-mpu"; - reg = <0x4a0d9000 0x80>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - ti,hwmods = "smartreflex_mpu"; - }; diff --git a/Documentation/devicetree/bindings/ptp/fsl,ptp.yaml b/Documentation/devicetree/bindings/ptp/fsl,ptp.yaml index 42ca895f3c4e..998f2ce8665f 100644 --- a/Documentation/devicetree/bindings/ptp/fsl,ptp.yaml +++ b/Documentation/devicetree/bindings/ptp/fsl,ptp.yaml @@ -146,11 +146,11 @@ examples: reg = <0x24e00 0xb0>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&ipic>; - fsl,cksel = <1>; + fsl,cksel = <1>; fsl,tclk-period = <10>; - fsl,tmr-prsc = <100>; - fsl,tmr-add = <0x999999a4>; - fsl,tmr-fiper1 = <0x3b9ac9f6>; - fsl,tmr-fiper2 = <0x00018696>; - fsl,max-adj = <659999998>; + fsl,tmr-prsc = <100>; + fsl,tmr-add = <0x999999a4>; + fsl,tmr-fiper1 = <0x3b9ac9f6>; + fsl,tmr-fiper2 = <0x00018696>; + fsl,max-adj = <659999998>; }; diff --git a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml index d8f4f9ffe884..dd95037ea5ee 100644 --- a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +++ b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml @@ -18,8 +18,11 @@ properties: - enum: - apple,t8103-fpwm - apple,t8112-fpwm + - apple,t8122-fpwm - apple,t6000-fpwm - apple,t6020-fpwm + - apple,t6030-fpwm + - apple,t6031-fpwm - const: apple,s5l-fpwm reg: diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml index 8df327e52810..f1422a401b6b 100644 --- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: contains: - const: spacemit,k1-pwm + enum: + - spacemit,k1-pwm + - spacemit,k3-pwm then: properties: "#pwm-cells": @@ -26,6 +28,26 @@ allOf: const: 1 description: | Used for specifying the period length in nanoseconds. + - if: + properties: + compatible: + contains: + enum: + - spacemit,k3-pwm + then: + required: + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 properties: compatible: @@ -36,7 +58,9 @@ properties: - marvell,pxa168-pwm - marvell,pxa910-pwm - items: - - const: spacemit,k1-pwm + - enum: + - spacemit,k1-pwm + - spacemit,k3-pwm - const: marvell,pxa910-pwm reg: @@ -47,7 +71,18 @@ properties: description: Number of cells in a pwm specifier. clocks: - maxItems: 1 + minItems: 1 + items: + - description: The function clock + - description: An optional bus clock + + clock-names: + minItems: 1 + maxItems: 2 + oneOf: + - items: + - const: func + - const: bus resets: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml index 41cea4979132..cb2f36e7b5d6 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml @@ -16,6 +16,7 @@ properties: - enum: - nvidia,tegra20-pwm - nvidia,tegra186-pwm + - nvidia,tegra264-pwm - items: - enum: diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml index bae993128981..40397bdf2d69 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml @@ -62,7 +62,7 @@ additionalProperties: false examples: - | - pwm: pwm@10020000 { + pwm@10020000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x10020000 0x1000>; clocks = <&tlclk>; diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 000000000000..f9f1f652e752 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - George Moussalem <george.moussalem@outlook.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,ipq5018-pwm + - qcom,ipq5332-pwm + - qcom,ipq9574-pwm + - const: qcom,ipq6018-pwm + - const: qcom,ipq6018-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq6018.h> + + pwm: pwm@1941010 { + compatible = "qcom,ipq6018-pwm"; + reg = <0x01941010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt b/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt deleted file mode 100644 index f401316e0248..000000000000 --- a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt +++ /dev/null @@ -1,18 +0,0 @@ -== ST STMPE PWM controller == - -This is a PWM block embedded in the ST Microelectronics STMPE -(ST Multi-Purpose Expander) chips. The PWM is registered as a -subdevices of the STMPE MFD device. - -Required properties: -- compatible: should be: - - "st,stmpe-pwm" -- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of - the cells format. - -Example: - -pwm0: pwm { - compatible = "st,stmpe-pwm"; - #pwm-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml b/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml index 69bae90fc4b2..b35b8f365b0f 100644 --- a/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml +++ b/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml @@ -23,6 +23,7 @@ properties: - silergy,syr827 - silergy,syr828 - tcs,tcs4525 + - tcs,tcs4526 - items: - const: rockchip,rk8601 - const: rockchip,rk8600 @@ -48,6 +49,12 @@ properties: VSEL0 register. When this pin is HIGH, VOUT is set by the VSEL1 register. maxItems: 1 + regulator-initial-mode: + enum: + [ 1, 2 ] + description: + Defined in include/dt-bindings/regulator/fcs,fan53555-regulator.h + required: - compatible - reg @@ -56,6 +63,7 @@ unevaluatedProperties: false examples: - | + #include <dt-bindings/regulator/fcs,fan53555-regulator.h> i2c { #address-cells = <1>; #size-cells = <0>; @@ -68,6 +76,7 @@ examples: regulator-max-microvolt = <1800000>; vin-supply = <&parent_reg>; fcs,suspend-voltage-selector = <1>; + regulator-initial-mode = <FAN53555_REGULATOR_MODE_FORCE_PWM>; }; }; ... diff --git a/Documentation/devicetree/bindings/regulator/lltc,ltc3589.yaml b/Documentation/devicetree/bindings/regulator/lltc,ltc3589.yaml new file mode 100644 index 000000000000..2c2755bb84eb --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/lltc,ltc3589.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/lltc,ltc3589.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Linear Technology LTC3589 PMIC + +maintainers: + - Frank Li <Frank.li@kernel.org> + +description: + Linear Technology LTC3589, LTC3589-1 and LTC3589-2 are PMICs + containing three buck regulators, one boost regulator and four + LDO regulators. + +properties: + compatible: + enum: + - lltc,ltc3589 + - lltc,ltc3589-1 + - lltc,ltc3589-2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + + patternProperties: + "^(sw1|sw2|sw3|bb-out|ldo1|ldo2)$": + type: object + unevaluatedProperties: false + $ref: regulator.yaml# + + properties: + lltc,fb-voltage-divider: + description: + Feedback voltage divider resistor values (R1, R2) in ohms. + Regulators sw1, sw2, sw3, and ldo2 can regulate the feedback + reference from 0.3625 V to 0.75 V in 12.5 mV steps. The output + voltage thus ranges between 0.3625 * (1 + R1/R2) V and + 0.75 * (1 + R1/R2) V. Regulators bb-out and ldo1 have a fixed + 0.8 V reference and thus output 0.8 * (1 + R1/R2) V. The ldo3 + regulator is fixed to 1.8 V on LTC3589 and to 2.8 V on + LTC3589-1,2. The ldo4 regulator can output between 1.8 V and + 3.3 V on LTC3589 and between 1.2 V and 3.2 V on LTC3589-1,2 in + four steps. The ldo1 standby regulator can not be disabled and + thus should have the regulator-always-on property set. + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: R1 in ohms + - description: R2 in ohms. + + required: + - lltc,fb-voltage-divider + + "^(ldo3|ldo4)$": + type: object + unevaluatedProperties: false + $ref: regulator.yaml# + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@34 { + compatible = "lltc,ltc3589-1"; + reg = <0x34>; + + regulators { + sw1 { + regulator-min-microvolt = <591930>; + regulator-max-microvolt = <1224671>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456803>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3 { + regulator-min-microvolt = <1341250>; + regulator-max-microvolt = <2775000>; + lltc,fb-voltage-divider = <270000 100000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + bb-out { + regulator-min-microvolt = <3387341>; + regulator-max-microvolt = <3387341>; + lltc,fb-voltage-divider = <511000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1 { + regulator-min-microvolt = <1306329>; + regulator-max-microvolt = <1306329>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456806>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + ldo4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3200000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/ltc3589.txt b/Documentation/devicetree/bindings/regulator/ltc3589.txt deleted file mode 100644 index 801053036146..000000000000 --- a/Documentation/devicetree/bindings/regulator/ltc3589.txt +++ /dev/null @@ -1,99 +0,0 @@ -Linear Technology LTC3589, LTC3589-1, and LTC3589-2 8-output regulators - -Required properties: -- compatible: "lltc,ltc3589", "lltc,ltc3589-1" or "lltc,ltc3589-2" -- reg: I2C slave address - -Required child node: -- regulators: Contains eight regulator child nodes sw1, sw2, sw3, bb-out, - ldo1, ldo2, ldo3, and ldo4, specifying the initialization data as - documented in Documentation/devicetree/bindings/regulator/regulator.txt. - -Each regulator is defined using the standard binding for regulators. The -nodes for sw1, sw2, sw3, bb-out, ldo1, and ldo2 additionally need to specify -the resistor values of their external feedback voltage dividers: - -Required properties (not on ldo3, ldo4): -- lltc,fb-voltage-divider: An array of two integers containing the resistor - values R1 and R2 of the feedback voltage divider in ohms. - -Regulators sw1, sw2, sw3, and ldo2 can regulate the feedback reference from -0.3625 V to 0.75 V in 12.5 mV steps. The output voltage thus ranges between -0.3625 * (1 + R1/R2) V and 0.75 * (1 + R1/R2) V. Regulators bb-out and ldo1 -have a fixed 0.8 V reference and thus output 0.8 * (1 + R1/R2) V. The ldo3 -regulator is fixed to 1.8 V on LTC3589 and to 2.8 V on LTC3589-1,2. The ldo4 -regulator can output between 1.8 V and 3.3 V on LTC3589 and between 1.2 V -and 3.2 V on LTC3589-1,2 in four steps. The ldo1 standby regulator can not -be disabled and thus should have the regulator-always-on property set. - -Example: - - ltc3589: pmic@34 { - compatible = "lltc,ltc3589-1"; - reg = <0x34>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <591930>; - regulator-max-microvolt = <1224671>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456803>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1341250>; - regulator-max-microvolt = <2775000>; - lltc,fb-voltage-divider = <270000 100000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - bb_out_reg: bb-out { - regulator-min-microvolt = <3387341>; - regulator-max-microvolt = <3387341>; - lltc,fb-voltage-divider = <511000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <1306329>; - regulator-max-microvolt = <1306329>; - lltc,fb-voltage-divider = <100000 158000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <704123>; - regulator-max-microvolt = <1456806>; - lltc,fb-voltage-divider = <180000 191000>; - regulator-ramp-delay = <7000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3200000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/maxim,max77802.yaml b/Documentation/devicetree/bindings/regulator/maxim,max77802.yaml index b704f05ea454..b886495c1396 100644 --- a/Documentation/devicetree/bindings/regulator/maxim,max77802.yaml +++ b/Documentation/devicetree/bindings/regulator/maxim,max77802.yaml @@ -22,13 +22,13 @@ description: | Certain regulators support "regulator-initial-mode" and "regulator-mode". The valid modes list is defined in the dt-bindings/regulator/maxim,max77802.h - and their meaning is:: + and their meaning is: 1 - Normal regulator voltage output mode. 3 - Low Power which reduces the quiescent current down to only 1uA The standard "regulator-mode" property can only be used for regulators that support changing their mode to Low Power Mode during suspend. These - regulators are:: bucks 2-4 and LDOs 1-35. Also, it only takes effect if the + regulators are: bucks 2-4 and LDOs 1-35. Also, it only takes effect if the regulator has been enabled for the given suspend state using "regulator-on-in-suspend" and has not been disabled for that state using "regulator-off-in-suspend". diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6311-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6311-regulator.yaml new file mode 100644 index 000000000000..f65ee2c90298 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6311-regulator.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6311-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6311 Regulator + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: + The MediaTek MT6311 is an I2C power management IC that provides one step-down + converter and one low-dropout regulator. The regulators are named VDVFS and + VBIASN, respectively. + +properties: + compatible: + const: mediatek,mt6311-regulator + + reg: + description: I2C slave address. + maxItems: 1 + + regulators: + type: object + description: List of regulators provided by this controller. + + patternProperties: + "^(VDVFS|VBIASN)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@6b { + compatible = "mediatek,mt6311-regulator"; + reg = <0x6b>; + + regulators { + VDVFS { + regulator-name = "VDVFS"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <10000>; + }; + + VBIASN { + regulator-name = "VBIASN"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <800000>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6358-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6358-regulator.yaml index c50402fcba72..4eb635179b6a 100644 --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6358-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6358-regulator.yaml @@ -145,7 +145,7 @@ allOf: then: patternProperties: # Old regulator node name scheme (with prefix and underscores) only - # ([^y-] is used to avoid matching -supply + # ([^y-]) is used to avoid matching -supply "^(?<!buck_)(?<!ldo_)v.*[^y-](?!-supply)$": false "^ldo_vsram-": false # vsram_core regulator doesn't exist on MT6358 diff --git a/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt deleted file mode 100644 index 84d544d8c1b1..000000000000 --- a/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek MT6311 Regulator - -Required properties: -- compatible: "mediatek,mt6311-regulator" -- reg: I2C slave address, usually 0x6b. -- regulators: List of regulators provided by this controller. It is named - to VDVFS and VBIASN. - The definition for each of these nodes is defined using the standard binding - for regulators at Documentation/devicetree/bindings/regulator/regulator.txt. - -The valid names for regulators are: -BUCK: - VDVFS -LDO: - VBIASN - -Example: - mt6311: pmic@6b { - compatible = "mediatek,mt6311-regulator"; - reg = <0x6b>; - - regulators { - mt6311_vcpu_reg: VDVFS { - regulator-name = "VDVFS"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <10000>; - }; - mt6311_ldo_reg: VBIASN { - regulator-name = "VBIASN"; - regulator-min-microvolt = <200000>; - regulator-max-microvolt = <800000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml index fe4ac9350ba0..e3c20412c8a7 100644 --- a/Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml @@ -18,84 +18,50 @@ patternProperties: "^buck_v(s1|gpu11|modem|pu|core|s2|pa|proc2|proc1|core_sshub)$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(s1|gpu11|modem|pu|core|s2|pa|proc2|proc1|core_sshub)$" - unevaluatedProperties: false "^ldo_v(ibr|rf12|usb|camio|efuse|xo22)$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(ibr|rf12|usb|camio|efuse|xo22)$" - unevaluatedProperties: false "^ldo_v(rfck|emc|a12|a09|ufs|bbck)$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(rfck|emc|a12|a09|ufs|bbck)$" - unevaluatedProperties: false - "^ldo_vcn(18|13|33_1_bt|13_1_wifi|33_2_bt|33_2_wifi)$": + "^ldo_vcn(18|13|33_[12])$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^vcn(18|13|33_1_bt|13_1_wifi|33_2_bt|33_2_wifi)$" - unevaluatedProperties: false "^ldo_vsram_(proc2|others|md|proc1|others_sshub)$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^vsram_(proc2|others|md|proc1|others_sshub)$" - unevaluatedProperties: false "^ldo_v(fe|bif|io)28$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(fe|bif|io)28$" - unevaluatedProperties: false "^ldo_v(aud|io|aux|rf|m)18$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(aud|io|aux|rf|m)18$" - unevaluatedProperties: false "^ldo_vsim[12]$": type: object $ref: regulator.yaml# + unevaluatedProperties: false - properties: - regulator-name: - pattern: "^vsim[12]$" - - required: - - regulator-name - + "^ldo_vcn33_[12]_(bt|wifi)$": + type: object + $ref: regulator.yaml# + description: + vcn33_[12]_(bt|wifi) are incorrect representations. + Use vcn33_[12] instead. + deprecated: true unevaluatedProperties: false additionalProperties: false @@ -246,13 +212,8 @@ examples: regulator-min-microvolt = <900000>; regulator-max-microvolt = <1300000>; }; - mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt { - regulator-name = "vcn33_1_bt"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; - }; - mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi { - regulator-name = "vcn33_1_wifi"; + mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1 { + regulator-name = "vcn33_1"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3500000>; }; @@ -313,13 +274,8 @@ examples: regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; }; - mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt { - regulator-name = "vcn33_2_bt"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; - }; - mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi { - regulator-name = "vcn33_2_wifi"; + mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2 { + regulator-name = "vcn33_2"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3500000>; }; diff --git a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml index 9c879bc3c360..cbb74e8e875d 100644 --- a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml @@ -17,6 +17,10 @@ properties: compatible: const: mediatek,mt6360-regulator + BUCK1_VIN-supply: + description: Input supply phandle(s) for BUCK1 + BUCK2_VIN-supply: + description: Input supply phandle(s) for BUCK2 LDO_VIN1-supply: description: Input supply phandle(s) for LDO1/2/3 LDO_VIN2-supply: diff --git a/Documentation/devicetree/bindings/regulator/nxp,pf8x00-regulator.yaml b/Documentation/devicetree/bindings/regulator/nxp,pf8x00-regulator.yaml index 894bdbca78a2..8ac77c1a9b9f 100644 --- a/Documentation/devicetree/bindings/regulator/nxp,pf8x00-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/nxp,pf8x00-regulator.yaml @@ -134,42 +134,42 @@ examples: regulator-always-on; regulator-boot-on; regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; }; reg_buck2: buck2 { regulator-always-on; regulator-boot-on; regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; }; reg_buck3: buck3 { regulator-always-on; regulator-boot-on; regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; }; reg_buck4: buck4 { regulator-always-on; regulator-boot-on; regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; }; reg_buck5: buck5 { regulator-always-on; regulator-boot-on; regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; }; reg_buck6: buck6 { regulator-always-on; regulator-boot-on; regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <400000>; + regulator-min-microvolt = <400000>; }; reg_buck7: buck7 { diff --git a/Documentation/devicetree/bindings/regulator/pbias-regulator.txt b/Documentation/devicetree/bindings/regulator/pbias-regulator.txt deleted file mode 100644 index acbcb452a69a..000000000000 --- a/Documentation/devicetree/bindings/regulator/pbias-regulator.txt +++ /dev/null @@ -1,32 +0,0 @@ -PBIAS internal regulator for SD card dual voltage i/o pads on OMAP SoCs. - -Required properties: -- compatible: - - should be "ti,pbias-dra7" for DRA7 - - should be "ti,pbias-omap2" for OMAP2 - - should be "ti,pbias-omap3" for OMAP3 - - should be "ti,pbias-omap4" for OMAP4 - - should be "ti,pbias-omap5" for OMAP5 - - "ti,pbias-omap" is deprecated -- reg: pbias register offset from syscon base and size of pbias register. -- syscon : phandle of the system control module -- regulator-name : should be - pbias_mmc_omap2430 for OMAP2430, OMAP3 SoCs - pbias_sim_omap3 for OMAP3 SoCs - pbias_mmc_omap4 for OMAP4 SoCs - pbias_mmc_omap5 for OMAP5 and DRA7 SoC - -Optional properties: -- Any optional property defined in bindings/regulator/regulator.txt - -Example: - - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0 0x4>; - syscon = <&omap5_padconf_global>; - pbias_mmc_reg: pbias_mmc_omap5 { - regulator-name = "pbias_mmc_omap5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; - }; diff --git a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml index 58bb0ad5dda4..eed2ce7fa861 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml @@ -47,10 +47,12 @@ description: | For PM8150, smps1 - smps10, ldo1 - ldo18 For PM8150L, smps1 - smps8, ldo1 - ldo11, bob, flash, rgb For PM8350, smps1 - smps12, ldo1 - ldo10 + For PM8350B, ldo1 For PM8350C, smps1 - smps10, ldo1 - ldo13, bob For PM8450, smps1 - smps6, ldo1 - ldo4 For PM8550, smps1 - smps6, ldo1 - ldo17, bob1 - bob2 For PM8998, smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2 + For PMAU0102, smps1 - smps8, ldo1 - ldo3 For PMH0101, ldo1 - ldo18, bob1 - bob2 For PMH0104, smps1 - smps4 For PMH0110, smps1 - smps10, ldo1 - ldo4 @@ -81,12 +83,14 @@ properties: - qcom,pm8150-rpmh-regulators - qcom,pm8150l-rpmh-regulators - qcom,pm8350-rpmh-regulators + - qcom,pm8350b-rpmh-regulators - qcom,pm8350c-rpmh-regulators - qcom,pm8450-rpmh-regulators - qcom,pm8550-rpmh-regulators - qcom,pm8550ve-rpmh-regulators - qcom,pm8550vs-rpmh-regulators - qcom,pm8998-rpmh-regulators + - qcom,pmau0102-rpmh-regulators - qcom,pmc8180-rpmh-regulators - qcom,pmc8180c-rpmh-regulators - qcom,pmc8380-rpmh-regulators @@ -339,6 +343,15 @@ allOf: properties: compatible: enum: + - qcom,pm8350b-rpmh-regulators + then: + properties: + vdd-l1-supply: true + + - if: + properties: + compatible: + enum: - qcom,pm8350c-rpmh-regulators then: properties: @@ -417,6 +430,7 @@ allOf: properties: compatible: enum: + - qcom,pmau0102-rpmh-regulators - qcom,pmc8380-rpmh-regulators - qcom,pm8550ve-rpmh-regulators then: diff --git a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml index 40f9223d4c27..0bbf7c806fbc 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml @@ -13,9 +13,6 @@ description: The REFGEN (reference voltage generator) regulator provides reference voltage for on-chip IPs (like PHYs) on some Qualcomm SoCs. -allOf: - - $ref: regulator.yaml# - properties: compatible: oneOf: @@ -39,16 +36,44 @@ properties: - const: qcom,sm8250-refgen-regulator - enum: + - qcom,ipq9650-refgen-regulator - qcom,sdm845-refgen-regulator - qcom,sm8250-refgen-regulator reg: maxItems: 1 + clocks: + items: + - description: Core reference clock + - description: AHB interface clock + + clock-names: + items: + - const: core + - const: hclk + required: - compatible - reg +allOf: + - $ref: regulator.yaml# + + - if: + properties: + compatible: + contains: + const: qcom,ipq9650-refgen-regulator + then: + required: + - clocks + - clock-names + else: + properties: + clocks: false + clock-names: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml index b7241ce975b9..0d8bc9bf996a 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -35,6 +35,12 @@ description: For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob + For pm8019, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l13, l14 + + For pm8150, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, l1, l2, l3, l4, l5, l6, + l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18 + For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1 @@ -91,6 +97,8 @@ properties: - qcom,rpm-pm6125-regulators - qcom,rpm-pm660-regulators - qcom,rpm-pm660l-regulators + - qcom,rpm-pm8019-regulators + - qcom,rpm-pm8150-regulators - qcom,rpm-pm8226-regulators - qcom,rpm-pm8841-regulators - qcom,rpm-pm8909-regulators diff --git a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml index fcefc722ee2a..024b34d0eb1a 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,usb-vbus-regulator.yaml @@ -14,17 +14,21 @@ description: | regulator will be enabled in situations where the device is required to provide power to the connected peripheral. -allOf: - - $ref: regulator.yaml# + The pm8150b variant uses an OTG current-limit selector, supporting limits + of 500 mA, 1000 mA, 1500 mA, 2000 mA, 2500 mA and 3000 mA. + + The pm4125 variant uses a different register layout with a 2-bit VBOOST + voltage selector supporting output voltages of 4.25 V, 4.5 V, 4.75 V + and 5.0 V. properties: compatible: oneOf: - enum: - qcom,pm8150b-vbus-reg + - qcom,pm4125-vbus-reg - items: - enum: - - qcom,pm4125-vbus-reg - qcom,pm6150-vbus-reg - qcom,pm7250b-vbus-reg - qcom,pmi632-vbus-reg @@ -34,11 +38,35 @@ properties: maxItems: 1 description: VBUS output base address +allOf: + - $ref: regulator.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8150b-vbus-reg + - qcom,pm6150-vbus-reg + - qcom,pm7250b-vbus-reg + - qcom,pmi632-vbus-reg + then: + required: + - regulator-min-microamp + - regulator-max-microamp + + - if: + properties: + compatible: + contains: + const: qcom,pm4125-vbus-reg + then: + required: + - regulator-min-microvolt + - regulator-max-microvolt + required: - compatible - reg - - regulator-min-microamp - - regulator-max-microamp unevaluatedProperties: false @@ -55,4 +83,16 @@ examples: regulator-max-microamp = <3000000>; }; }; + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + usb-vbus-regulator@1100 { + compatible = "qcom,pm4125-vbus-reg"; + reg = <0x1100>; + regulator-min-microvolt = <4250000>; + regulator-max-microvolt = <5000000>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml b/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml index 022c1f197364..4c3236be8709 100644 --- a/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml +++ b/Documentation/devicetree/bindings/regulator/richtek,rtq2208.yaml @@ -21,7 +21,7 @@ description: | conduction mode (FCCM). The definition of modes is in the datasheet which is available in below link - and their meaning is:: + and their meaning is: 0 - Auto mode for power saving, which reducing the switching frequency at light load condition to maintain high frequency. 1 - FCCM to meet the strict voltage regulation accuracy, which keeping constant switching frequency. @@ -42,11 +42,14 @@ properties: richtek,mtp-sel-high: type: boolean + deprecated: true description: vout register selection based on this boolean value. false - Using DVS0 register setting to adjust vout true - Using DVS1 register setting to adjust vout + The property is now deprecated. Will be identified by RG HW register. + regulators: type: object additionalProperties: false @@ -100,7 +103,6 @@ examples: compatible = "richtek,rtq2208"; reg = <0x10>; interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>; - richtek,mtp-sel-high; regulators { buck-a { diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml index cc4ceb32e9d6..68b5e579e2d3 100644 --- a/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71815-regulator.yaml @@ -38,7 +38,9 @@ patternProperties: type: object description: Properties for single LDO/BUCK regulator. - $ref: regulator.yaml# + allOf: + - $ref: regulator.yaml# + - $ref: rohm,pmic-states.yaml# properties: regulator-name: @@ -51,15 +53,6 @@ patternProperties: description: GPIO used to control ldo4 state (when ldo4 is controlled by GPIO). - rohm,dvs-run-voltage: - description: - PMIC "RUN" state voltage in uV when PMIC HW states are used. See - comments below for bucks/LDOs which support this. 0 means - regulator should be disabled at RUN state. - $ref: /schemas/types.yaml#/definitions/uint32 - minimum: 0 - maximum: 3300000 - rohm,dvs-snvs-voltage: description: Whether to keep regulator enabled at "SNVS" state or not. @@ -71,21 +64,15 @@ patternProperties: minimum: 0 maximum: 3300000 + rohm,dvs-run-voltage: + minimum: 0 + maximum: 3300000 + rohm,dvs-suspend-voltage: - description: - PMIC "SUSPEND" state voltage in uV when PMIC HW states are used. See - comments below for bucks/LDOs which support this. 0 means - regulator should be disabled at SUSPEND state. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-lpsr-voltage: - description: - PMIC "LPSR" state voltage in uV when PMIC HW states are used. See - comments below for bucks/LDOs which support this. 0 means - regulator should be disabled at LPSR state. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml index d898800d6bca..8cba397678a6 100644 --- a/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71828-regulator.yaml @@ -40,7 +40,9 @@ patternProperties: type: object description: Properties for single BUCK regulator. - $ref: regulator.yaml# + allOf: + - $ref: regulator.yaml# + - $ref: rohm,pmic-states.yaml# properties: regulator-name: @@ -49,34 +51,18 @@ patternProperties: should be "buck1", ..., "buck7" rohm,dvs-run-voltage: - description: - PMIC default "RUN" state voltage in uV. See below table for - bucks which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-idle-voltage: - description: - PMIC default "IDLE" state voltage in uV. See below table for - bucks which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-suspend-voltage: - description: - PMIC default "SUSPEND" state voltage in uV. See below table for - bucks which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-lpsr-voltage: - description: - PMIC default "LPSR" state voltage in uV. See below table for - bucks which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml index 29b350a4f88a..b886cb6d2fb9 100644 --- a/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.yaml @@ -44,7 +44,9 @@ patternProperties: "^BUCK[1-8]$": type: object - $ref: regulator.yaml# + allOf: + - $ref: regulator.yaml# + - $ref: rohm,pmic-states.yaml# description: Properties for single BUCK regulator. @@ -55,28 +57,16 @@ patternProperties: should be "buck1", ..., "buck8" rohm,dvs-run-voltage: - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1300000 - description: - PMIC default "RUN" state voltage in uV. See below table for - bucks which support this. 0 means disabled. rohm,dvs-idle-voltage: - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1300000 - description: - PMIC default "IDLE" state voltage in uV. See below table for - bucks which support this. 0 means disabled. rohm,dvs-suspend-voltage: - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1300000 - description: - PMIC default "SUSPEND" state voltage in uV. See below table for - bucks which support this. 0 means disabled. # Supported default DVS states: # @@ -108,8 +98,8 @@ patternProperties: # Setups where regulator (especially the buck8) output voltage is scaled # by adding external connection where some other regulator output is # connected to feedback-pin (over suitable resistors) is getting popular - # amongst users of BD71837. (This allows for example scaling down the - # buck8 voltages to suit lover GPU voltages for projects where buck8 is + # amongst users of BD71837. This allows for example scaling down the + # buck8 voltages to suit lower GPU voltages for projects where buck8 is # (ab)used to supply power for GPU. # # So we allow describing this external connection from DT and scale the diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml index 7ba4ccf723d8..f0846983f2e0 100644 --- a/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/rohm,bd71847-regulator.yaml @@ -43,7 +43,9 @@ patternProperties: "^BUCK[1-6]$": type: object - $ref: regulator.yaml# + allOf: + - $ref: regulator.yaml# + - $ref: rohm,pmic-states.yaml# description: Properties for single BUCK regulator. @@ -54,28 +56,16 @@ patternProperties: should be "buck1", ..., "buck6" rohm,dvs-run-voltage: - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1300000 - description: - PMIC default "RUN" state voltage in uV. See below table for - bucks which support this. 0 means disabled. rohm,dvs-idle-voltage: - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1300000 - description: - PMIC default "IDLE" state voltage in uV. See below table for - bucks which support this. 0 means disabled. rohm,dvs-suspend-voltage: - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 1300000 - description: - PMIC default "SUSPEND" state voltage in uV. See below table for - bucks which support this. 0 means disabled. # Supported default DVS states: # @@ -103,8 +93,8 @@ patternProperties: # Setups where regulator (especially the buck8) output voltage is scaled # by adding external connection where some other regulator output is # connected to feedback-pin (over suitable resistors) is getting popular - # amongst users of BD71837. (This allows for example scaling down the - # buck8 voltages to suit lover GPU voltages for projects where buck8 is + # amongst users of BD71837. This allows for example scaling down the + # buck8 voltages to suit lower GPU voltages for projects where buck8 is # (ab)used to supply power for GPU. # # So we allow describing this external connection from DT and scale the diff --git a/Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml b/Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml index 5518082129bd..76747bf2bbdd 100644 --- a/Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml @@ -26,41 +26,27 @@ patternProperties: type: object description: Properties for single LDO regulator. - $ref: regulator.yaml# + allOf: + - $ref: regulator.yaml# + - $ref: rohm,pmic-states.yaml# properties: regulator-name: pattern: "^ldo([1-9]|1[0-1])$" rohm,dvs-run-voltage: - description: - PMIC default "RUN" state voltage in uV. See below table for - LDOs which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-idle-voltage: - description: - PMIC default "IDLE" state voltage in uV. See below table for - LDOs which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-suspend-voltage: - description: - PMIC default "SUSPEND" state voltage in uV. See below table for - LDOs which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-lpsr-voltage: - description: - PMIC default "deep-idle" state voltage in uV. See below table for - LDOs which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 @@ -82,7 +68,9 @@ patternProperties: type: object description: Properties for single BUCK regulator. - $ref: regulator.yaml# + allOf: + - $ref: regulator.yaml# + - $ref: rohm,pmic-states.yaml# properties: regulator-name: @@ -97,34 +85,18 @@ patternProperties: maximum: 300000 rohm,dvs-run-voltage: - description: - PMIC default "RUN" state voltage in uV. See below table for - bucks which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-idle-voltage: - description: - PMIC default "IDLE" state voltage in uV. See below table for - bucks which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-suspend-voltage: - description: - PMIC default "SUSPEND" state voltage in uV. See below table for - bucks which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 rohm,dvs-lpsr-voltage: - description: - PMIC default "deep-idle" state voltage in uV. See below table for - bucks which support this. 0 means disabled. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 3300000 diff --git a/Documentation/devicetree/bindings/regulator/rohm,pmic-states.yaml b/Documentation/devicetree/bindings/regulator/rohm,pmic-states.yaml new file mode 100644 index 000000000000..f09f021bdde4 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/rohm,pmic-states.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/rohm,pmic-states.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM PMICs' hardware state machine descriptions + +maintainers: + - Matti Vaittinen <mazziesaccount@gmail.com> + +description: + Many of the ROHM PMICs have internal state-machine designed to provide + correct voltages for different SOC states. In many cases the states and + transitions are SOC specific, but ones described here can be found from a + few of the different ROHM PMICs. + +properties: + rohm,dvs-run-voltage: + description: + PMIC "RUN" state voltage in uV when PMIC HW states are used. 0 means the + regulator should be disabled at RUN state. Some regulators do not support + setting HW state specific voltage but do support enable/disable control. + For them any positive value means the regulator should be enabled without + touching the voltage. + $ref: /schemas/types.yaml#/definitions/uint32 + + rohm,dvs-suspend-voltage: + description: + PMIC "SUSPEND" state voltage in uV when PMIC HW states are used. 0 means + the regulator should be disabled at SUSPEND state. Some regulators do not + support setting HW state specific voltage but do support enable/disable + control. For them any positive value means the regulator should be + enabled without touching the voltage. + $ref: /schemas/types.yaml#/definitions/uint32 + + rohm,dvs-idle-voltage: + description: + PMIC "IDLE" state voltage in uV. 0 means the regulator should be disabled + at IDLE state. Some regulators do not support setting HW state specific + voltage but do support enable/disable control. For them any positive + value means the regulator should be enabled without touching the voltage. + $ref: /schemas/types.yaml#/definitions/uint32 + + rohm,dvs-lpsr-voltage: + description: + PMIC "LPSR" state voltage in uV when PMIC HW states are used. 0 means the + regulator should be disabled at LPSR state. Some regulators do not + support setting HW state specific voltage but do support enable/disable + control. For them any positive value means the regulator should be + enabled without touching the voltage. Some PMICs' documentation may refer + to this state as a "deep-idle state". + $ref: /schemas/types.yaml#/definitions/uint32 + +# The schema is expected to be reference by PMIC schemas, which may introduce +# other properties that must be allowed. +additionalProperties: true diff --git a/Documentation/devicetree/bindings/regulator/sgmicro,sgm3804.yaml b/Documentation/devicetree/bindings/regulator/sgmicro,sgm3804.yaml new file mode 100644 index 000000000000..3716eaf81aa9 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/sgmicro,sgm3804.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/sgmicro,sgm3804.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SG Micro SGM3804 Single Inductor Dual Output Buck/Boost Converter + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +description: + The SGM3804 is a dual voltage regulator, designed to support positive/negative + supply for driving LCD panels. It support software-configurable output + switching. The output voltages can be programmed via an I2C compatible interface. + +properties: + compatible: + const: sgmicro,sgm3804 + + reg: + maxItems: 1 + + vin-supply: true + +patternProperties: + "^(pos|neg)$": + type: object + $ref: regulator.yaml# + + properties: + enable-gpios: true + + unevaluatedProperties: false + + required: + - enable-gpios + +required: + - compatible + - reg + - pos + - neg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@3e { + compatible = "sgmicro,sgm3804"; + reg = <0x3e>; + + vin-supply = <&vin_reg>; + + pos { + regulator-name = "outpos"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + }; + + neg { + regulator-name = "outneg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + }; + }; + }; +... + diff --git a/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml b/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml new file mode 100644 index 000000000000..ab945c46b08e --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/sprd,sc2730-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc SC2730 Power Management IC regulators + +maintainers: + - Otto Pflüger <otto.pflueger@abscue.de> + +patternProperties: + "^dcdc-(core|cpu|gen[0-1]|gpu|mem|memq|modem|sram)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-avdd(12|18)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-vdd(18-dcxo|28)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-vdd(emmccore|kpled|ldo[0-2]|sd(core|io)|sim[0-2]|usb33|wcn|wifipa)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-vddcam(a0|a1|d0|d1|io|mot)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-vddrf(1v25|18)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/regulator/ti,pbias-omap.yaml b/Documentation/devicetree/bindings/regulator/ti,pbias-omap.yaml new file mode 100644 index 000000000000..4533f337963f --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/ti,pbias-omap.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/ti,pbias-omap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PBIAS internal regulator + +maintainers: + - Tony Lindgren <tony@atomide.com> + +properties: + compatible: + items: + - enum: + - ti,pbias-dra7 + - ti,pbias-omap2 + - ti,pbias-omap3 + - ti,pbias-omap4 + - ti,pbias-omap5 + - const: ti,pbias-omap + + reg: + maxItems: 1 + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle of the system control module + + pbias_mmc_omap2430: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + required: + - regulator-name + + pbias_sim_omap3: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + required: + - regulator-name + + pbias_mmc_omap4: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + required: + - regulator-name + + pbias_mmc_omap5: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + required: + - regulator-name + +required: + - compatible + - reg + - syscon + +allOf: + - if: + properties: + compatible: + contains: + const: ti,pbias-omap2 + then: + required: + - pbias_mmc_omap2430 + properties: + pbias_sim_omap3: false + pbias_mmc_omap4: false + pbias_mmc_omap5: false + + - if: + properties: + compatible: + contains: + const: ti,pbias-omap3 + then: + anyOf: + - required: + - pbias_mmc_omap2430 + - required: + - pbias_sim_omap3 + properties: + pbias_mmc_omap4: false + pbias_mmc_omap5: false + + - if: + properties: + compatible: + contains: + const: ti,pbias-omap4 + then: + required: + - pbias_mmc_omap4 + properties: + pbias_mmc_omap2430: false + pbias_sim_omap3: false + pbias_mmc_omap5: false + + - if: + properties: + compatible: + contains: + enum: + - ti,pbias-omap5 + - ti,pbias-dra7 + then: + required: + - pbias_mmc_omap5 + properties: + pbias_mmc_omap2430: false + pbias_sim_omap3: false + pbias_mmc_omap4: false + +additionalProperties: false + +examples: + - | + pbias_regulator@0 { + compatible = "ti,pbias-omap5", "ti,pbias-omap"; + reg = <0 0x4>; + syscon = <&omap5_padconf_global>; + pbias_mmc_omap5 { + regulator-name = "pbias_mmc_omap5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/ti,tps51632.yaml b/Documentation/devicetree/bindings/regulator/ti,tps51632.yaml new file mode 100644 index 000000000000..130fa9796f57 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/ti,tps51632.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/ti,tps51632.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TPS51632 Voltage regulators + +maintainers: + - Laxman Dewangan <ldewangan@nvidia.com> + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + const: ti,tps51632 + + reg: + maxItems: 1 + + ti,enable-pwm-dvfs: + description: Enable the DVFS voltage control through the PWM interface. + type: boolean + + ti,dvfs-step-20mV: + description: + The 20mV step voltage when PWM DVFS enabled. Missing this will set 10mV + step voltage in PWM DVFS mode. In normal mode, the voltage step is 10mV + as per datasheet. + type: boolean + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + tps51632@43 { + compatible = "ti,tps51632"; + reg = <0x43>; + regulator-name = "tps51632-vout"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + ti,enable-pwm-dvfs; + ti,dvfs-step-20mV; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt b/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt deleted file mode 100644 index 2f7e44a96414..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps51632-regulator.txt +++ /dev/null @@ -1,27 +0,0 @@ -TPS51632 Voltage regulators - -Required properties: -- compatible: Must be "ti,tps51632" -- reg: I2C slave address - -Optional properties: -- ti,enable-pwm-dvfs: Enable the DVFS voltage control through the PWM interface. -- ti,dvfs-step-20mV: The 20mV step voltage when PWM DVFS enabled. Missing this - will set 10mV step voltage in PWM DVFS mode. In normal mode, the voltage - step is 10mV as per datasheet. - -Any property defined as part of the core regulator binding, defined in -regulator.txt, can also be used. - -Example: - - tps51632 { - compatible = "ti,tps51632"; - reg = <0x43>; - regulator-name = "tps51632-vout"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - ti,enable-pwm-dvfs; - ti,dvfs-step-20mV; - }; diff --git a/Documentation/devicetree/bindings/regulator/tps65217.txt b/Documentation/devicetree/bindings/regulator/tps65217.txt deleted file mode 100644 index 4f05d208c95c..000000000000 --- a/Documentation/devicetree/bindings/regulator/tps65217.txt +++ /dev/null @@ -1,78 +0,0 @@ -TPS65217 family of regulators - -Required properties: -- compatible: "ti,tps65217" -- reg: I2C slave address -- regulators: list of regulators provided by this controller, must be named - after their hardware counterparts: dcdc[1-3] and ldo[1-4] -- regulators: This is the list of child nodes that specify the regulator - initialization data for defined regulators. Not all regulators for the given - device need to be present. The definition for each of these nodes is defined - using the standard binding for regulators found at - Documentation/devicetree/bindings/regulator/regulator.txt. - -Optional properties: -- ti,pmic-shutdown-controller: Telling the PMIC to shutdown on PWR_EN toggle. - - The valid names for regulators are: - tps65217: dcdc1, dcdc2, dcdc3, ldo1, ldo2, ldo3 and ldo4 - -Each regulator is defined using the standard binding for regulators. - -Example: - - tps: tps@24 { - compatible = "ti,tps65217"; - ti,pmic-shutdown-controller; - - regulators { - dcdc1_reg: dcdc1 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc2_reg: dcdc2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - dcdc3_reg: dcc3 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: ldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml new file mode 100644 index 000000000000..c0359f447ea8 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/amd,bram-rproc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/amd,bram-rproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD MicroBlaze/V BRAM-based Remote Processor + +maintainers: + - Ben Levinsky <ben.levinsky@amd.com> + +description: | + Soft-core processor subsystem instantiated in AMD programmable logic and + using dual-port BRAM for firmware storage and execution. + + Hardware Architecture: + + Host (PS) Programmable Logic (PL) + ========= ====================== + + AXI Interface -----------------> AXI BRAM Controller (Host Port) + | + | Port A + v + +-----------------+ + | Dual-Port BRAM | + | (shared memory) | + +-----------------+ + ^ + | Port B + | + AXI BRAM Controller (Soft-core Port) + ^ + | LMB + | + Soft-core CPU (MicroBlaze/V) + + GPIO --------------------------> Proc Sys Reset ----> CPU Reset Signal + + Clock -------------------------> Clock Distribution -> CPU Clock + + Memory Architecture: + + The dual-port BRAM allows simultaneous access from both processors: + - Port A: Connected to the host AXI BRAM controller for firmware loading + - Port B: Connected to the soft-core local memory bus for execution + + The reg property describes the executable BRAM window in the processor-local + address space. The parent bus node translates that window to the system + physical address space by using standard devicetree address translation + through ranges. A clock input and a reset GPIO control the subsystem. + +properties: + compatible: + oneOf: + - const: xlnx,zynqmp-bram-rproc + - items: + - enum: + - amd,versal2-bram-rproc + - xlnx,versal-bram-rproc + - xlnx,versal-net-bram-rproc + - const: xlnx,zynqmp-bram-rproc + + reg: + maxItems: 1 + description: + Processor-local address and size of the BRAM firmware memory window, + as seen by the soft-core processor (typically 0x0 for reset vector). + The parent bus ranges property must translate this window to the + corresponding system physical address. + + clocks: + maxItems: 1 + description: + Clock input for the soft-core processor subsystem. + + firmware-name: + maxItems: 1 + description: + Name of the firmware ELF file to load. + + reset-gpios: + maxItems: 1 + description: + GPIO specifier controlling the soft-core reset input. + +required: + - compatible + - reg + - clocks + - reset-gpios + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + remoteproc@0 { + compatible = "xlnx,zynqmp-bram-rproc"; + reg = <0x0 0x40000>; + clocks = <&pl_clk>; + firmware-name = "firmware.elf"; + reset-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; +... diff --git a/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml index 76e8ca44906a..4cd5121b9a4e 100644 --- a/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml @@ -25,7 +25,7 @@ properties: - const: amlogic,meson-mx-ao-arc firmware-name: - $ref: /schemas/types.yaml#/definitions/string + maxItems: 1 description: The name of the firmware which should be loaded for this remote processor. @@ -48,12 +48,7 @@ properties: minItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle - description: - phandles to a reserved SRAM region which is used as the memory of - the ARC core. The region should be defined as child nodes of the - AHB SRAM node as per the generic bindings in - Documentation/devicetree/bindings/sram/sram.yaml + maxItems: 1 amlogic,secbus2: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml index ce8ec0119469..c18f71b64889 100644 --- a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml @@ -28,6 +28,9 @@ properties: - fsl,imx8qxp-cm4 - fsl,imx8ulp-cm33 - fsl,imx93-cm33 + - fsl,imx94-cm33s + - fsl,imx94-cm70 + - fsl,imx94-cm71 - fsl,imx95-cm7 clocks: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml index 16a245fe2738..7e8ecae8e6cb 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml @@ -32,6 +32,14 @@ properties: reg: maxItems: 1 + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + cx-supply: true px-supply: @@ -49,6 +57,30 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - memory-region @@ -66,56 +98,6 @@ allOf: - qcom,msm8953-adsp-pil - qcom,msm8974-adsp-pil - qcom,msm8996-adsp-pil - - qcom,msm8996-slpi-pil - - qcom,msm8998-adsp-pas - - qcom,msm8998-slpi-pas - - qcom,sdm660-adsp-pas - - qcom,sdm660-cdsp-pas - - qcom,sdm845-adsp-pas - - qcom,sdm845-cdsp-pas - - qcom,sdm845-slpi-pas - then: - properties: - clocks: - items: - - description: XO clock - clock-names: - items: - - const: xo - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8226-adsp-pil - - qcom,msm8953-adsp-pil - - qcom,msm8974-adsp-pil - - qcom,msm8996-adsp-pil - - qcom,msm8996-slpi-pil - - qcom,msm8998-adsp-pas - - qcom,msm8998-slpi-pas - - qcom,sdm660-adsp-pas - - qcom,sdm660-cdsp-pas - - qcom,sdm845-adsp-pas - - qcom,sdm845-cdsp-pas - - qcom,sdm845-slpi-pas - then: - properties: - interrupts: - maxItems: 5 - interrupt-names: - maxItems: 5 - - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8226-adsp-pil - - qcom,msm8953-adsp-pil - - qcom,msm8974-adsp-pil - - qcom,msm8996-adsp-pil - qcom,msm8998-adsp-pas - qcom,sdm660-adsp-pas - qcom,sdm660-cdsp-pas diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,kaanapali-soccp-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,kaanapali-soccp-pas.yaml new file mode 100644 index 000000000000..e6c78d621d17 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,kaanapali-soccp-pas.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,kaanapali-soccp-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Kaanapali SoCCP Peripheral Authentication Service + +maintainers: + - Jingyi Wang <jingyi.wang@oss.qualcomm.com> + +description: + The SoC Control Processor (SoCCP) is a small RISC-V MCU that controls USB + Type-C, battery charging and various other functions on Qualcomm SoCs, somewhat + analogous to traditional PC Embedded Controllers. This document describes + the Peripheral Authentication Service that loads and boots firmware for SoCCP. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,hawi-soccp-pas + - qcom,maili-soccp-pas + - const: qcom,kaanapali-soccp-pas + - enum: + - qcom,glymur-soccp-pas + - qcom,kaanapali-soccp-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + power-domains: + items: + - description: CX power domain + - description: MX power domain + + power-domain-names: + items: + - const: cx + - const: mx + + firmware-name: + items: + - description: Firmware name of the SoC Control Processor + - description: Firmware name of the SoCCP Devicetree + + memory-region: + items: + - description: Memory region for main Firmware authentication + - description: Memory region for Devicetree Firmware authentication + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Pong interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: pong + + qcom,smem-states: + minItems: 2 + description: States used by the AP to signal the SoC Control Processor + + qcom,smem-state-names: + minItems: 2 + description: The names of the state bits used for SMP2P output + +required: + - compatible + - reg + - memory-region + - power-domains + - power-domain-names + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #define IPCC_MPROC_SOCCP + + remoteproc@d00000 { + compatible = "qcom,kaanapali-soccp-pas"; + reg = <0x00d00000 0x200000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "pong"; + + memory-region = <&soccp_mem>, + <&soccp_dtb_mem_mem>; + + firmware-name = "qcom/kaanapali/soccp.mbn", + "qcom/kaanapali/soccp_dtb.mbn"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + qcom,smem-states = <&soccp_smp2p_out 0>, + <&soccp_smp2p_out 8>; + qcom,smem-state-names = "stop", + "ping"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_SOCCP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "soccp"; + qcom,remote-pid = <19>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml index e5cce0d05fc6..b24e6f6eaf37 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,milos-pas.yaml @@ -16,7 +16,6 @@ description: properties: compatible: enum: - - qcom,eliza-adsp-pas - qcom,milos-adsp-pas - qcom,milos-cdsp-pas - qcom,milos-mpss-pas @@ -34,12 +33,22 @@ properties: - const: xo interrupts: - minItems: 6 - maxItems: 6 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt interrupt-names: - minItems: 6 - maxItems: 6 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack qcom,qmp: $ref: /schemas/types.yaml#/definitions/phandle @@ -59,6 +68,14 @@ properties: - description: Memory region for core Firmware authentication - description: Memory region for Devicetree Firmware authentication + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg @@ -70,7 +87,6 @@ allOf: properties: compatible: enum: - - qcom,eliza-adsp-pas - qcom,milos-adsp-pas - qcom,milos-cdsp-pas then: @@ -91,7 +107,6 @@ allOf: compatible: contains: enum: - - qcom,eliza-adsp-pas - qcom,milos-adsp-pas then: properties: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml index faf2712e3d27..4049157dd83d 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml @@ -108,6 +108,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: Names of the states used by the AP to signal the Hexagon core diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml index 1b65813cc8ad..4a1b439f985e 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml @@ -101,6 +101,13 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop modem + items: + - description: Phandle to the Shared Memory Point 2 Point or Shared + Memory Manager device handling the communication with a remote + processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: Names of the states used by the AP to signal the Hexagon core diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,nord-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,nord-pas.yaml new file mode 100644 index 000000000000..e90d2953ba69 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,nord-pas.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,nord-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Nord SoC Peripheral Authentication Service + +maintainers: + - Shawn Guo <shengchao.guo@oss.qualcomm.com> + +description: + Qualcomm Nord SoC Peripheral Authentication Service loads and boots firmware + on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,nord-adsp-pas + - qcom,nord-cdsp0-pas + - qcom,nord-cdsp1-pas + - qcom,nord-cdsp2-pas + - qcom,nord-cdsp3-pas + + power-domains: + minItems: 2 + items: + - description: CX power domain + - description: MX power domain + - description: NSP power domain + + power-domain-names: + minItems: 2 + items: + - const: cx + - const: mx + - const: nsp + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + qcom,qmp: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the AOSS side-channel message RAM. + + smd-edge: false + + firmware-name: + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + memory-region: + items: + - description: Memory region for main Firmware authentication + - description: Memory region for Devicetree Firmware authentication + + interrupts: + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + +required: + - compatible + - reg + - memory-region + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,nord-adsp-pas + then: + properties: + power-domains: + maxItems: 2 + power-domain-names: + maxItems: 2 + else: + properties: + power-domains: + minItems: 3 + power-domain-names: + minItems: 3 + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/mailbox/qcom-ipcc.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + #define IPCC_MPROC_ADSP0 + + remoteproc@4c00000 { + compatible = "qcom,nord-adsp-pas"; + reg = <0x04c00000 0x10000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interrupts-extended = <&intc GIC_SPI 159 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + memory-region = <&hpass_dsp0_mem>, <&hpass_dsp0_dtb_mem>; + + firmware-name = "qcom/nord/adsp.mbn", + "qcom/nord/adsp_dtb.mbn"; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names = "cx", + "mx"; + + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_MPROC_ADSP0 + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_MPROC_ADSP0 IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "adsp"; + qcom,remote-pid = <2>; + + /* ... */ + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index 68c17bf18987..11faf655f530 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -26,23 +26,11 @@ properties: interrupts: minItems: 5 - items: - - description: Watchdog interrupt - - description: Fatal interrupt - - description: Ready interrupt - - description: Handover interrupt - - description: Stop acknowledge interrupt - - description: Shutdown acknowledge interrupt + maxItems: 6 interrupt-names: minItems: 5 - items: - - const: wdog - - const: fatal - - const: ready - - const: handover - - const: stop-ack - - const: shutdown-ack + maxItems: 6 iommus: maxItems: 1 @@ -58,13 +46,29 @@ properties: qcom,smem-states: $ref: /schemas/types.yaml#/definitions/phandle-array description: States used by the AP to signal the Hexagon core + minItems: 1 items: - - description: Stop the modem + - description: Stop the remoteproc + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 + - description: Ping the remoteproc + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output + minItems: 1 items: - const: stop + - const: ping smd-edge: $ref: /schemas/remoteproc/qcom,smd-edge.yaml# diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml index bca59394aef4..e5f5f92987e1 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml @@ -92,6 +92,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml index ad45fd00ae34..bf9bf1af9ff1 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-pas.yaml @@ -32,10 +32,20 @@ properties: - const: xo interrupts: - maxItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt interrupt-names: - maxItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack power-domains: false power-domain-names: false @@ -49,6 +59,14 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml index 540bdfca53d9..823304afaa98 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml @@ -87,6 +87,7 @@ properties: - qcom,qcm2290-rpm-proc - qcom,qcs404-rpm-proc - qcom,sdm660-rpm-proc + - qcom,shikra-rpm-proc - qcom,sm6115-rpm-proc - qcom,sm6125-rpm-proc - qcom,sm6375-rpm-proc diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml index bcd2bcf96e24..dda2d144b720 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sa8775p-pas.yaml @@ -59,10 +59,28 @@ properties: - description: Memory region for main Firmware authentication interrupts: - maxItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt interrupt-names: - maxItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output required: - compatible diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml index 7c9accac92d0..21c82cd3be03 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml @@ -133,6 +133,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml index 66b455d0a8e3..b20780e5e26b 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-pas.yaml @@ -48,6 +48,34 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml index 94ca7a0cc203..23b8e3079f3b 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml @@ -91,6 +91,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml index f349c303fa07..43dfb90ac18d 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml @@ -147,6 +147,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml index f4118b2da5f6..f3f3432948ed 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml @@ -104,6 +104,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml index 8227527c1d77..4bbe4a986c7c 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc8280xp-pas.yaml @@ -45,6 +45,34 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml index a3c74871457f..9666ebf1e7b6 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml @@ -92,6 +92,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml index 8c4abde74915..8c16b01c53e4 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sdx55-pas.yaml @@ -30,10 +30,22 @@ properties: - const: xo interrupts: - minItems: 6 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt interrupt-names: - minItems: 6 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack power-domains: items: @@ -59,6 +71,14 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml new file mode 100644 index 000000000000..34a2f15e9361 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,shikra-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra SoC Peripheral Authentication Service + +maintainers: + - Bibek Kumar Patro <bibek.patro@oss.qualcomm.com> + - Komal Bajaj <komal.bajaj@oss.qualcomm.com> + +description: + Qualcomm Shikra SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,shikra-cdsp-pas + - qcom,shikra-lpaicp-pas + - qcom,shikra-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + memory-region: + minItems: 1 + maxItems: 2 + + smd-edge: false + + firmware-name: + minItems: 1 + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the remoteproc core. + unevaluatedProperties: false + + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop the remote processor + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output + items: + - const: stop + +required: + - compatible + - reg + - memory-region + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + + - if: + properties: + compatible: + enum: + - qcom,shikra-cdsp-pas + - qcom,shikra-mpss-pas + then: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + maxItems: 1 + firmware-name: + maxItems: 1 + power-domains: + items: + - description: CX power domain + power-domain-names: + items: + - const: cx + + - if: + properties: + compatible: + enum: + - qcom,shikra-lpaicp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + minItems: 2 + firmware-name: + minItems: 2 + power-domains: false + power-domain-names: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmcc.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,rpm-icc.h> + #include <dt-bindings/interconnect/qcom,shikra.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + remoteproc@b300000 { + compatible = "qcom,shikra-cdsp-pas"; + reg = <0x0b300000 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + power-domain-names = "cx"; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + firmware-name = "qcom/shikra/cdsp.mbn"; + + glink-edge { + interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 4>; + qcom,remote-pid = <5>; + label = "cdsp"; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml index eeb6a8aafeb9..454ba82bd6f1 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6115-pas.yaml @@ -51,6 +51,34 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml index c1a3cc308bdb..42e02c64347a 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6350-pas.yaml @@ -45,6 +45,34 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml index 7286b2baa19f..274f87880e2e 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm6375-pas.yaml @@ -39,8 +39,36 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + smd-edge: false + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml index a8cddf7e2fe1..5a7c5f8c92d1 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8150-pas.yaml @@ -61,6 +61,34 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml index 6d09823153fc..72d0db5698c5 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -55,6 +55,34 @@ properties: maxItems: 1 description: Firmware name for the Hexagon core + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 1e4db0c9fcf9..c58e8a6c7fe1 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,eliza-cdsp-pas - qcom,sdx75-mpss-pas - qcom,sm8550-adsp-pas - qcom,sm8550-cdsp-pas @@ -29,14 +30,19 @@ properties: - qcom,x1e80100-cdsp-pas - items: - enum: + - qcom,eliza-adsp-pas - qcom,glymur-adsp-pas + - qcom,hawi-adsp-pas - qcom,kaanapali-adsp-pas + - qcom,maili-adsp-pas - qcom,sm8750-adsp-pas - const: qcom,sm8550-adsp-pas - items: - enum: - qcom,glymur-cdsp-pas + - qcom,hawi-cdsp-pas - qcom,kaanapali-cdsp-pas + - qcom,maili-cdsp-pas - const: qcom,sm8550-cdsp-pas - items: - const: qcom,sm8750-cdsp-pas @@ -73,6 +79,34 @@ properties: - description: DSM Memory region 2 - description: Memory region for Qlink Logging + interrupts: + minItems: 5 + items: + - description: Watchdog interrupt + - description: Fatal interrupt + - description: Ready interrupt + - description: Handover interrupt + - description: Stop acknowledge interrupt + - description: Shutdown acknowledge interrupt + + interrupt-names: + minItems: 5 + items: + - const: wdog + - const: fatal + - const: ready + - const: handover + - const: stop-ack + - const: shutdown-ack + + qcom,smem-states: + maxItems: 1 + description: States used by the AP to signal the Hexagon core + + qcom,smem-state-names: + maxItems: 1 + description: The names of the state bits used for SMP2P output + required: - compatible - reg @@ -102,10 +136,15 @@ allOf: compatible: contains: enum: + - qcom,eliza-adsp-pas - qcom,glymur-adsp-pas - qcom,glymur-cdsp-pas + - qcom,hawi-adsp-pas + - qcom,hawi-cdsp-pas - qcom,kaanapali-adsp-pas - qcom,kaanapali-cdsp-pas + - qcom,maili-adsp-pas + - qcom,maili-cdsp-pas - qcom,sm8750-adsp-pas then: properties: @@ -135,6 +174,7 @@ allOf: compatible: contains: enum: + - qcom,eliza-cdsp-pas - qcom,sm8750-cdsp-pas then: properties: @@ -249,6 +289,25 @@ allOf: - const: mxc - const: nsp + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-cdsp-pas + then: + properties: + power-domains: + items: + - description: CX power domain + - description: MX power domain + - description: NSP power domain + power-domain-names: + items: + - const: cx + - const: mx + - const: nsp + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml index 117fb4d0c4ad..a55e55f5f014 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml @@ -84,6 +84,12 @@ properties: States used by the AP to signal the WCNSS core that it should shutdown items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/ti,am3352-wkup-m3.yaml b/Documentation/devicetree/bindings/remoteproc/ti,am3352-wkup-m3.yaml new file mode 100644 index 000000000000..9e8a03acdec4 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/ti,am3352-wkup-m3.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/ti,am3352-wkup-m3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM33xx/AM43xx Wakeup M3 Remote Processor + +maintainers: + - Suman Anna <s-anna@ti.com> + - Bhargav Joshi <j.bhargav.u@gmail.com> + +description: + The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor + (commonly referred to as Wakeup M3 or CM3) to help with various low power + tasks that cannot be controlled from the MPU. This CM3 processor requires a + firmware binary to accomplish this. A wkup_m3 device node is used to + represent the Wakeup M3 processor instance within the SoC. It is added as a + child node of the parent interconnect bus (l4_wkup) through which it is + accessible to the MPU. + +properties: + compatible: + enum: + - ti,am3352-wkup-m3 + - ti,am4372-wkup-m3 + + reg: + items: + - description: Address range for UMEM + - description: Address range for DMEM + + reg-names: + items: + - const: umem + - const: dmem + + ti,pm-firmware: + $ref: /schemas/types.yaml#/definitions/string + description: + Name of firmware file to be used for loading and booting the wkup_m3 + remote processor. + + resets: + maxItems: 1 + + reset-names: + items: + - const: rstctrl + + ti,hwmods: + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + description: + Name of the hwmod associated with the wkupm3 device. + +required: + - compatible + - reg + - reg-names + - ti,pm-firmware + +dependencies: + resets: [reset-names] + reset-names: [resets] + +additionalProperties: false + +examples: + - | + target-module@0 { + compatible = "ti,sysc-omap4", "ti,sysc"; + reg = <0x0 0x4>; + reg-names = "rev"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x00000000 0x4000>, + <0x00080000 0x00080000 0x2000>; + + cpu@0 { + compatible = "ti,am3352-wkup-m3"; + reg = <0x00000000 0x4000>, + <0x00080000 0x2000>; + reg-names = "umem", "dmem"; + resets = <&prm_wkup 3>; + reset-names = "rstctrl"; + ti,pm-firmware = "am335x-pm-firmware.elf"; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml index b51bb863d759..8b1ed384ef22 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml @@ -75,16 +75,8 @@ properties: # -------------------- sram: - $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 4 - items: - maxItems: 1 - description: | - phandles to one or more reserved on-chip SRAM regions. The regions - should be defined as child nodes of the respective SRAM node, and - should be defined as per the generic bindings in, - Documentation/devicetree/bindings/sram/sram.yaml allOf: - if: diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml index 775e9b3a1938..14e6b2f817b3 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml @@ -224,16 +224,8 @@ patternProperties: at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted. sram: - $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 4 - items: - maxItems: 1 - description: | - phandles to one or more reserved on-chip SRAM regions. The regions - should be defined as child nodes of the respective SRAM node, and - should be defined as per the generic bindings in, - Documentation/devicetree/bindings/sram/sram.yaml required: - compatible diff --git a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt index 91f0a3b0c0b2..847552133633 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt +++ b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt @@ -75,7 +75,7 @@ SoCs only: - clocks: Should contain the device's input clock, and should be defined as per the bindings in, - Documentation/devicetree/bindings/clock/keystone-gate.txt + Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml The following are mandatory properties for Keystone 2 66AK2G SoCs only: diff --git a/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml b/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml index 2811334515d1..591471e5f93a 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,pru-consumer.yaml @@ -30,7 +30,6 @@ properties: maxItems: 1 firmware-name: - $ref: /schemas/types.yaml#/definitions/string-array minItems: 1 maxItems: 6 description: | diff --git a/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt b/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt deleted file mode 100644 index 3a70073797eb..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/wkup_m3_rproc.txt +++ /dev/null @@ -1,52 +0,0 @@ -TI Wakeup M3 Remoteproc Driver -============================== - -The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor -(commonly referred to as Wakeup M3 or CM3) to help with various low power tasks -that cannot be controlled from the MPU. This CM3 processor requires a firmware -binary to accomplish this. The wkup_m3 remoteproc driver handles the loading of -the firmware and booting of the CM3. - -Wkup M3 Device Node: -==================== -A wkup_m3 device node is used to represent the Wakeup M3 processor instance -within the SoC. It is added as a child node of the parent interconnect bus -(l4_wkup) through which it is accessible to the MPU. - -Required properties: --------------------- -- compatible: Should be one of, - "ti,am3352-wkup-m3" for AM33xx SoCs - "ti,am4372-wkup-m3" for AM43xx SoCs -- reg: Should contain the address ranges for the two internal - memory regions, UMEM and DMEM. The parent node should - provide an appropriate ranges property for properly - translating these into bus addresses. -- reg-names: Contains the corresponding names for the two memory - regions. These should be named "umem" & "dmem". -- ti,hwmods: Name of the hwmod associated with the wkupm3 device. -- ti,pm-firmware: Name of firmware file to be used for loading and - booting the wkup_m3 remote processor. - -Example: --------- -/* AM33xx */ -ocp { - l4_wkup: l4_wkup@44c00000 { - compatible = "am335-l4-wkup", "simple-bus"; - ranges = <0 0x44c00000 0x400000>; - #address-cells = <1>; - #size-cells = <1>; - - wkup_m3: wkup_m3@100000 { - compatible = "ti,am3352-wkup-m3"; - reg = <0x100000 0x4000>, - <0x180000 0x2000>; - reg-names = "umem", "dmem"; - ti,hwmods = "wkup_m3"; - ti,pm-firmware = "am335x-pm-firmware.elf"; - }; - }; - - ... -}; diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml index ee63c03949c9..5ab19d70a344 100644 --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml @@ -106,20 +106,13 @@ patternProperties: - const: rx sram: - $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 8 - items: - maxItems: 1 - description: | + description: phandles to one or more reserved on-chip SRAM regions. Other than TCM, the RPU can execute instructions and access data from the OCM memory, the main DDR memory, and other system memories. - The regions should be defined as child nodes of the respective SRAM - node, and should be defined as per the generic bindings in - Documentation/devicetree/bindings/sram/sram.yaml - memory-region: description: | List of phandles to the reserved memory regions associated with the @@ -135,6 +128,10 @@ patternProperties: - description: vring1 additionalItems: true + firmware-name: + maxItems: 1 + description: default firmware to load + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml new file mode 100644 index 000000000000..4362bc058df4 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake up + secondary CPUs on Intel processors. It is an alternative to the INIT-!INIT- + SIPI sequence used on most x86 systems. + + The structure and operation of the mailbox is described in the Multiprocessor + Wakeup Structure of the ACPI specification version 6.6 section 5.2.12.19 [1]. + + The implementation of the mailbox in platform firmware is described in the + Intel TDX Virtual Firmware Design Guide section 4.3.5 [2]. + + 1: https://uefi.org/specs/ACPI/6.6/05_ACPI_Software_Programming_Model.html#multiprocessor-wakeup-structure + 2: https://www.intel.com/content/www/us/en/content-details/733585/intel-tdx-virtual-firmware-design-guide.html + +maintainers: + - Ricardo Neri <ricardo.neri-calderon@linux.intel.com> + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + + wakeup-mailbox@ffff0000 { + compatible = "intel,wakeup-mailbox"; + reg = <0x0 0xffff0000 0x1000>; + }; + }; diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml index 4380f622f9a9..6efadc5f8078 100644 --- a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Tegra CPU-NS - BPMP IPC reserved memory maintainers: - - Peter De Schrijver <pdeschrijver@nvidia.com> + - Thierry Reding <thierry.reding@kernel.org> + - Jonathan Hunter <jonathanh@nvidia.com> description: | Define a memory region used for communication between CPU-NS and BPMP. diff --git a/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml b/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml new file mode 100644 index 000000000000..bfad1d20e7cd --- /dev/null +++ b/Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/qcom,shikra-audiocore-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio Core CSR for Qualcomm Shikra SoC + +maintainers: + - Imran Shaik <imran.shaik@oss.qualcomm.com> + +description: | + Audio Core CSR module provides the resets on Qualcomm Shikra SoC platform. + + See also: + - include/dt-bindings/clock/qcom,shikra-audiocorecc.h + +properties: + compatible: + const: qcom,shikra-audiocore-csr + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + reset-controller@a0b4000 { + compatible = "qcom,shikra-audiocore-csr"; + reg = <0x0a0b4000 0x1000>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml index 41fd11f70a49..f9854ff43ac6 100644 --- a/Documentation/devicetree/bindings/riscv/canaan.yaml +++ b/Documentation/devicetree/bindings/riscv/canaan.yaml @@ -10,7 +10,7 @@ maintainers: - Damien Le Moal <dlemoal@kernel.org> description: - Canaan Kendryte K210 SoC-based boards + Canaan Kendryte SoC-based boards properties: $nodename: @@ -42,6 +42,12 @@ properties: - items: - const: canaan,kendryte-k210 + - items: + - enum: + - canaan,canmv-k230 + - canaan,k230-usip-lp3-evb + - const: canaan,kendryte-k230 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 5feeb2203050..0da219ae6769 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -117,8 +117,8 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: VLEN/8, the vector register length in bytes. This property is required on - thead systems where the vector register length is not identical on all harts, or - the vlenb CSR is not available. + thead systems where the vector register length is not identical on all + harts, or the vlenb CSR is not available. # RISC-V has multiple properties for cache op block sizes as the sizes # differ between individual CBO extensions @@ -151,8 +151,8 @@ anyOf: - riscv,isa-base dependencies: - riscv,isa-base: [ "riscv,isa-extensions" ] - riscv,isa-extensions: [ "riscv,isa-base" ] + riscv,isa-base: ["riscv,isa-extensions"] + riscv,isa-extensions: ["riscv,isa-base"] required: - interrupt-controller diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 2b0a8a93bb21..577d7ae5576b 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -181,6 +181,27 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smcdeleg + description: | + The standard Smcdeleg machine-level extension for the machine mode + to delegate the hpmcounters to supervisor mode so that they are + directly accessible in the supervisor mode as ratified in the + 20240213 version of the privileged ISA specification. + + - const: smcntrpmf + description: | + The standard Smcntrpmf machine-level extension for the machine mode + to enable privilege mode filtering for cycle and instret counters as + ratified in the 20240326 version of the privileged ISA specification. + + - const: smcsrind + description: | + The standard Smcsrind machine-level extension extends the + indirect CSR access mechanism defined by the Smaia extension. This + extension allows other ISA extensions to use indirect CSR access + mechanism in M-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as @@ -206,6 +227,14 @@ properties: behavioural changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: ssccfg + description: | + The standard Ssccfg supervisor-level extension for configuring + the delegated hpmcounters to be accessible directly in supervisor + mode as ratified in the 20240213 version of the privileged ISA + specification. This extension depends on Sscsrind, Smcdeleg, Zihpm, + Zicntr extensions. + - const: ssccptr description: | The standard Ssccptr extension for main memory (cacheability and @@ -226,12 +255,26 @@ properties: Profiles Version 1.0, with commit b1d806605f87 ("Updated to ratified state.") + - const: sscsrind + description: | + The standard Sscsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Ssaia extension. This + extension allows other ISA extensions to use indirect CSR access + mechanism in S-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: ssnpm description: | The standard Ssnpm extension for next-mode pointer masking as ratified at commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. + - const: ssqosid + description: | + The standard Ssqosid extension for Quality of Service ID is + ratified as v1.0 in commit d9c616497fde ("Merge pull + request #7 from ved-rivos/Ratified") of riscv-ssqosid. + - const: ssstateen description: | The standard Ssstateen extension for supervisor-mode view of the @@ -457,6 +500,13 @@ properties: merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed of zc.adoc to src tree."). + - const: zclsd + description: + The Zclsd extension implements the compressed (16-bit) version of the + Load/Store Pair for RV32. As with Zilsd, this extension was ratified + in commit f88abf1 ("Integrating load/store pair for RV32 with the + main manual") of riscv-isa-manual. + - const: zcmop description: The standard Zcmop extension version 1.0, as ratified in commit @@ -487,6 +537,22 @@ properties: in commit 64074bc ("Update version numbers for Zfh/Zfinx") of riscv-isa-manual. + - const: zicbom + description: + The standard Zicbom extension for base cache management operations as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + + - const: zicbop + description: + The standard Zicbop extension for cache-block prefetch instructions + as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of + riscv-CMOs. + + - const: zicboz + description: + The standard Zicboz extension for cache-block zeroing as ratified + in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + - const: ziccamoa description: The standard Ziccamoa extension for main memory (cacheability and @@ -514,6 +580,66 @@ properties: guarantee on LR/SC sequences, as ratified in commit b1d806605f87 ("Updated to ratified state.") of the riscv profiles specification. + - const: zicfilp + description: | + The standard Zicfilp extension for enforcing forward edge + control-flow integrity as ratified in commit 3f8e450 ("merge + pull request #227 from ved-rivos/0709") of riscv-cfi + github repo. + + - const: zicfiss + description: | + The standard Zicfiss extension for enforcing backward edge + control-flow integrity as ratified in commit 3f8e450 ("merge + pull request #227 from ved-rivos/0709") of riscv-cfi + github repo. + + - const: zicntr + description: + The standard Zicntr extension for base counters and timers, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 95cf1f9 + ("Add changes requested by Ved during signoff") of riscv-zicond. + + - const: zicsr + description: | + The standard Zicsr extension for control and status register + instructions, as ratified in the 20191213 version of the + unprivileged ISA specification. + + This does not include Chapter 10, "Counters", which documents + special case read-only CSRs, that were moved into the Zicntr and + Zihpm extensions after the ratification of the 20191213 version of + the unprivileged specification. + + - const: zifencei + description: + The standard Zifencei extension for instruction-fetch fence, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: zihintntl + description: + The standard Zihintntl extension for non-temporal locality hints, as + ratified in commit 0dc91f5 ("Zihintntl is ratified") of the + riscv-isa-manual. + + - const: zihintpause + description: + The standard Zihintpause extension for pause hints, as ratified in + commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. + + - const: zihpm + description: + The standard Zihpm extension for hardware performance counters, as + ratified in the 20191213 version of the unprivileged ISA + specification. + - const: zilsd description: The standard Zilsd extension which provides support for aligned @@ -521,12 +647,10 @@ properties: encodings, as ratified in commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of riscv-isa-manual. - - const: zclsd + - const: zimop description: - The Zclsd extension implements the compressed (16-bit) version of the - Load/Store Pair for RV32. As with Zilsd, this extension was ratified - in commit f88abf1 ("Integrating load/store pair for RV32 with the - main manual") of riscv-isa-manual. + The standard Zimop extension version 1.0, as ratified in commit + 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. - const: zk description: @@ -590,87 +714,6 @@ properties: in version 1.0 of RISC-V Cryptography Extensions Volume I specification. - - const: zicbom - description: - The standard Zicbom extension for base cache management operations as - ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. - - - const: zicbop - description: - The standard Zicbop extension for cache-block prefetch instructions - as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of - riscv-CMOs. - - - const: zicboz - description: - The standard Zicboz extension for cache-block zeroing as ratified - in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. - - - const: zicfilp - description: | - The standard Zicfilp extension for enforcing forward edge - control-flow integrity as ratified in commit 3f8e450 ("merge - pull request #227 from ved-rivos/0709") of riscv-cfi - github repo. - - - const: zicfiss - description: | - The standard Zicfiss extension for enforcing backward edge - control-flow integrity as ratified in commit 3f8e450 ("merge - pull request #227 from ved-rivos/0709") of riscv-cfi - github repo. - - - const: zicntr - description: - The standard Zicntr extension for base counters and timers, as - ratified in the 20191213 version of the unprivileged ISA - specification. - - - const: zicond - description: - The standard Zicond extension for conditional arithmetic and - conditional-select/move operations as ratified in commit 95cf1f9 - ("Add changes requested by Ved during signoff") of riscv-zicond. - - - const: zicsr - description: | - The standard Zicsr extension for control and status register - instructions, as ratified in the 20191213 version of the - unprivileged ISA specification. - - This does not include Chapter 10, "Counters", which documents - special case read-only CSRs, that were moved into the Zicntr and - Zihpm extensions after the ratification of the 20191213 version of - the unprivileged specification. - - - const: zifencei - description: - The standard Zifencei extension for instruction-fetch fence, as - ratified in the 20191213 version of the unprivileged ISA - specification. - - - const: zihintpause - description: - The standard Zihintpause extension for pause hints, as ratified in - commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. - - - const: zihintntl - description: - The standard Zihintntl extension for non-temporal locality hints, as - ratified in commit 0dc91f5 ("Zihintntl is ratified") of the - riscv-isa-manual. - - - const: zihpm - description: - The standard Zihpm extension for hardware performance counters, as - ratified in the 20191213 version of the unprivileged ISA - specification. - - - const: zimop - description: - The standard Zimop extension version 1.0, as ratified in commit - 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. - - const: ztso description: The standard Ztso extension for total store ordering, as ratified @@ -809,18 +852,18 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. - - const: zvksh - description: | - The standard Zvksh extension for ShangMi suite: SM3 secure hash - instructions, as ratified in commit 56ed795 ("Update - riscv-crypto-spec-vector.adoc") of riscv-crypto. - - const: zvksg description: The standard Zvksg extension for ShangMi algorithm suite with GCM instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zvksh + description: | + The standard Zvksh extension for ShangMi suite: SM3 secure hash + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zvkt description: The standard Zvkt extension for vector data-independent execution @@ -1113,6 +1156,32 @@ properties: allOf: - const: zilsd - const: zca + # Smcdeleg depends on Sscsrind, Zihpm, Zicntr + - if: + contains: + const: smcdeleg + then: + allOf: + - contains: + const: sscsrind + - contains: + const: zihpm + - contains: + const: zicntr + # Ssccfg depends on Smcdeleg, Sscsrind, Zihpm, Zicntr + - if: + contains: + const: ssccfg + then: + allOf: + - contains: + const: smcdeleg + - contains: + const: sscsrind + - contains: + const: zihpm + - contains: + const: zicntr allOf: # Zcf extension does not exist on rv64 diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index b958b94a924d..4ee9c88984b4 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -21,6 +21,11 @@ properties: oneOf: - items: - enum: + - bananapi,bpi-cm6-io + - const: bananapi,bpi-cm6 + - const: spacemit,k1 + - items: + - enum: - bananapi,bpi-f3 - milkv,jupiter - spacemit,musepi-pro @@ -29,8 +34,14 @@ properties: - const: spacemit,k1 - items: - enum: + - deepcomputing,fml13v05 - spacemit,k3-pico-itx - const: spacemit,k3 + - items: + - enum: + - spacemit,k3-com260-ifx + - const: spacemit,k3-com260 + - const: spacemit,k3 additionalProperties: true diff --git a/Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml b/Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml index f501fc7691c6..92d906998211 100644 --- a/Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml +++ b/Documentation/devicetree/bindings/rng/inside-secure,safexcel-eip76.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/rng/inside-secure,safexcel-eip76.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Inside-Secure HWRNG Module +title: Inside-Secure SafeXcel EIP-76 HWRNG Module maintainers: - Jayesh Choudhary <j-choudhary@ti.com> diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml index 7e8dc62e5d3a..38e67861b88f 100644 --- a/Documentation/devicetree/bindings/rng/mtk-rng.yaml +++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml @@ -11,12 +11,13 @@ maintainers: properties: $nodename: - pattern: "^rng@[0-9a-f]+$" + pattern: "^rng(@[0-9a-f]+)?$" compatible: oneOf: - enum: - mediatek,mt7623-rng + - mediatek,mt7981-rng - items: - enum: - mediatek,mt7622-rng @@ -25,6 +26,11 @@ properties: - mediatek,mt8365-rng - mediatek,mt8516-rng - const: mediatek,mt7623-rng + - items: + - enum: + - mediatek,mt7987-rng + - mediatek,mt7988-rng + - const: mediatek,mt7981-rng reg: maxItems: 1 @@ -38,18 +44,37 @@ properties: required: - compatible - - reg - - clocks - - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7981-rng + then: + properties: + reg: false + clocks: false + clock-names: false + else: + required: + - reg + - clocks + - clock-names additionalProperties: false examples: - | #include <dt-bindings/clock/mt2701-clk.h> - rng: rng@1020f000 { - compatible = "mediatek,mt7623-rng"; - reg = <0x1020f000 0x1000>; - clocks = <&infracfg CLK_INFRA_TRNG>; - clock-names = "rng"; + + rng@1020f000 { + compatible = "mediatek,mt7623-rng"; + reg = <0x1020f000 0x1000>; + clocks = <&infracfg CLK_INFRA_TRNG>; + clock-names = "rng"; + }; + - | + rng { + compatible = "mediatek,mt7981-rng"; }; diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index 9df5cdb6f63f..f2b91186ed37 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -33,6 +33,7 @@ properties: - enum: - allwinner,sun20i-d1-rtc - allwinner,sun55i-a523-rtc + - allwinner,sun60i-a733-rtc - const: allwinner,sun50i-r329-rtc reg: @@ -175,6 +176,18 @@ allOf: interrupts: minItems: 2 + - if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-h616-rtc + - allwinner,sun50i-r329-rtc + + then: + properties: + clock-output-names: false + required: - "#clock-cells" - compatible diff --git a/Documentation/devicetree/bindings/rtc/epson,rx6110.txt b/Documentation/devicetree/bindings/rtc/epson,rx6110.txt deleted file mode 100644 index 3dc313e01f77..000000000000 --- a/Documentation/devicetree/bindings/rtc/epson,rx6110.txt +++ /dev/null @@ -1,39 +0,0 @@ -Epson RX6110 Real Time Clock -============================ - -The Epson RX6110 can be used with SPI or I2C busses. The kind of -bus depends on the SPISEL pin and can not be configured via software. - -I2C mode --------- - -Required properties: - - compatible: should be: "epson,rx6110" - - reg : the I2C address of the device for I2C - -Example: - - rtc: rtc@32 { - compatible = "epson,rx6110" - reg = <0x32>; - }; - -SPI mode --------- - -Required properties: - - compatible: should be: "epson,rx6110" - - reg: chip select number - - spi-cs-high: RX6110 needs chipselect high - - spi-cpha: RX6110 works with SPI shifted clock phase - - spi-cpol: RX6110 works with SPI inverse clock polarity - -Example: - - rtc: rtc@3 { - compatible = "epson,rx6110" - reg = <3> - spi-cs-high; - spi-cpha; - spi-cpol; - }; diff --git a/Documentation/devicetree/bindings/rtc/epson,rx6110.yaml b/Documentation/devicetree/bindings/rtc/epson,rx6110.yaml new file mode 100644 index 000000000000..55086ac7d1e2 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/epson,rx6110.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/epson,rx6110.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Epson RX6110 Real Time Clock + +description: + The Epson RX6110 can be used with SPI or I2C busses. The kind of bus depends + on the SPISEL pin and cannot be configured via software. + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +allOf: + - $ref: rtc.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: epson,rx6110 + + reg: + maxItems: 1 + + spi-cs-high: true + spi-cpha: true + spi-cpol: true + +required: + - compatible + - reg + +dependencies: + spi-cs-high: [ spi-cpha, spi-cpol ] + spi-cpha: [ spi-cs-high, spi-cpol ] + spi-cpol: [ spi-cs-high, spi-cpha ] + +unevaluatedProperties: false + +examples: + # I2C mode + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@32 { + compatible = "epson,rx6110"; + reg = <0x32>; + }; + }; + + # SPI mode + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + rtc@3 { + compatible = "epson,rx6110"; + reg = <3>; + spi-cs-high; + spi-cpha; + spi-cpol; + }; + }; diff --git a/Documentation/devicetree/bindings/rtc/microchip,pic32-rtc.txt b/Documentation/devicetree/bindings/rtc/microchip,pic32-rtc.txt deleted file mode 100644 index 180b7144bfcc..000000000000 --- a/Documentation/devicetree/bindings/rtc/microchip,pic32-rtc.txt +++ /dev/null @@ -1,21 +0,0 @@ -* Microchip PIC32 Real Time Clock and Calendar - -The RTCC keeps time in hours, minutes, and seconds, and one half second. It -provides a calendar in weekday, date, month, and year. It also provides a -configurable alarm. - -Required properties: -- compatible: should be: "microchip,pic32mzda-rtc" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: RTC alarm/event interrupt -- clocks: clock phandle - -Example: - - rtc: rtc@1f8c0000 { - compatible = "microchip,pic32mzda-rtc"; - reg = <0x1f8c0000 0x60>; - interrupts = <166 IRQ_TYPE_EDGE_RISING>; - clocks = <&PBCLK6>; - }; diff --git a/Documentation/devicetree/bindings/rtc/microchip,pic32mzda-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,pic32mzda-rtc.yaml new file mode 100644 index 000000000000..481ee28c06e3 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microchip,pic32mzda-rtc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microchip,pic32mzda-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32 Real Time Clock and Calendar + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +description: | + The Microchip PIC32 Real Time Clock and Calendar (RTCC) keeps time in hours, + minutes, seconds, and one half second. It also provides a calendar with + weekday, date, month, and year, along with a configurable alarm. + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + const: microchip,pic32mzda-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + rtc@1f8c0000 { + compatible = "microchip,pic32mzda-rtc"; + reg = <0x1f8c0000 0x60>; + interrupts = <166 IRQ_TYPE_EDGE_RISING>; + clocks = <&PBCLK6>; + }; diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml index 1860f0e4c31a..ea7b039a91e7 100644 --- a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml @@ -9,15 +9,19 @@ title: Renesas RZ/N1 SoCs Real-Time Clock maintainers: - Miquel Raynal <miquel.raynal@bootlin.com> -allOf: - - $ref: rtc.yaml# - properties: compatible: - items: - - enum: - - renesas,r9a06g032-rtc - - const: renesas,rzn1-rtc + oneOf: + - items: + - enum: + - renesas,r9a06g032-rtc + - const: renesas,rzn1-rtc + + - const: renesas,r9a09g077-rtc + + - items: + - const: renesas,r9a09g087-rtc + - const: renesas,r9a09g077-rtc reg: maxItems: 1 @@ -54,6 +58,23 @@ required: - clock-names - power-domains +allOf: + - $ref: rtc.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g077-rtc + - renesas,r9a09g087-rtc + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/rtc/rtc-cmos.txt b/Documentation/devicetree/bindings/rtc/rtc-cmos.txt deleted file mode 100644 index 7d7b5f6bda65..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-cmos.txt +++ /dev/null @@ -1,27 +0,0 @@ - Motorola mc146818 compatible RTC -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Required properties: - - compatible : "motorola,mc146818" - - reg : should contain registers location and length. - -Optional properties: - - interrupts : should contain interrupt. - - ctrl-reg : Contains the initial value of the control register also - called "Register B". - - freq-reg : Contains the initial value of the frequency register also - called "Register A". - -"Register A" and "B" are usually initialized by the firmware (BIOS for -instance). If this is not done, it can be performed by the driver. - -ISA Example: - - rtc@70 { - compatible = "motorola,mc146818"; - interrupts = <8 3>; - interrupt-parent = <&ioapic1>; - ctrl-reg = <2>; - freq-reg = <0x26>; - reg = <1 0x70 2>; - }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-cmos.yaml b/Documentation/devicetree/bindings/rtc/rtc-cmos.yaml new file mode 100644 index 000000000000..e37927e9916c --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rtc-cmos.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/rtc-cmos.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Motorola mc146818 compatible RTC + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + +properties: + compatible: + oneOf: + - const: motorola,mc146818 + + - items: + - const: intel,ce4100-rtc + - const: motorola,mc146818 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ctrl-reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Initial value of the control register + (also known as Register B). + + freq-reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Initial value of the frequency register + (also known as Register A). + +required: + - compatible + - reg + +allOf: + - $ref: rtc.yaml# + +unevaluatedProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <1>; + + rtc@1,70 { + compatible = "motorola,mc146818"; + reg = <0x1 0x70 0x2>; + + interrupts = <8 3>; + + ctrl-reg = <2>; + freq-reg = <0x26>; + }; + }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-ds1307.yaml b/Documentation/devicetree/bindings/rtc/rtc-ds1307.yaml index 98d10e680144..9b2796804f07 100644 --- a/Documentation/devicetree/bindings/rtc/rtc-ds1307.yaml +++ b/Documentation/devicetree/bindings/rtc/rtc-ds1307.yaml @@ -31,6 +31,7 @@ properties: - epson,rx8025 - isil,isl12057 - epson,rx8130 + - epson,rx8901 - items: - enum: diff --git a/Documentation/devicetree/bindings/rtc/rtc-omap.txt b/Documentation/devicetree/bindings/rtc/rtc-omap.txt deleted file mode 100644 index 062ebb14cecf..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-omap.txt +++ /dev/null @@ -1,53 +0,0 @@ -TI Real Time Clock - -Required properties: -- compatible: - - "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family. - - "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family. - This RTC IP has special WAKE-EN Register to enable - Wakeup generation for event Alarm. It can also be - used to control an external PMIC via the - pmic_power_en pin. - - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family. -- reg: Address range of rtc register set -- interrupts: rtc timer, alarm interrupts in order - -Optional properties: -- system-power-controller: whether the rtc is controlling the system power - through pmic_power_en -- clocks: Any internal or external clocks feeding in to rtc -- clock-names: Corresponding names of the clocks -- pinctrl-0: a phandle pointing to the pin settings for the device -- pinctrl-names: should be "default" - -Optional subnodes: -- generic pinctrl node - -Required pinctrl subnodes properties: -- pins - Names of ext_wakeup pins to configure - -Optional pinctrl subnodes properties: -- input-enable - Enables ext_wakeup -- ti,active-high - Set input active high (by default active low) - -Example: - -rtc@1c23000 { - compatible = "ti,da830-rtc"; - reg = <0x23000 0x1000>; - interrupts = <19 - 19>; - interrupt-parent = <&intc>; - system-power-controller; - clocks = <&clk_32k_rtc>, <&clk_32768_ck>; - clock-names = "ext-clk", "int-clk"; - - pinctrl-0 = <&ext_wakeup>; - pinctrl-names = "default"; - - ext_wakeup: ext-wakeup { - pins = "ext_wakeup0"; - input-enable; - ti,active-high; - }; -}; diff --git a/Documentation/devicetree/bindings/rtc/rtc-palmas.txt b/Documentation/devicetree/bindings/rtc/rtc-palmas.txt deleted file mode 100644 index c6cf37758a77..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-palmas.txt +++ /dev/null @@ -1,32 +0,0 @@ -Palmas RTC controller bindings - -Required properties: -- compatible: - - "ti,palmas-rtc" for palma series of the RTC controller -- interrupts: Interrupt number of RTC submodule on device. - -Optional properties: - -- ti,backup-battery-chargeable: The Palmas series device like TPS65913 or - TPS80036 supports the backup battery for powering the RTC when main - battery is removed or in very low power state. The backup battery - can be chargeable or non-chargeable. This flag will tells whether - battery is chargeable or not. If charging battery then driver can - enable the charging. -- ti,backup-battery-charge-high-current: Enable high current charging in - backup battery. Device supports the < 100uA and > 100uA charging. - The high current will be > 100uA. Absence of this property will - charge battery to lower current i.e. < 100uA. - -Example: - palmas: tps65913@58 { - ... - palmas_rtc: rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&palmas>; - interrupts = <8 0>; - ti,backup-battery-chargeable; - ti,backup-battery-charge-high-current; - }; - ... - }; diff --git a/Documentation/devicetree/bindings/rtc/st,m41t93.yaml b/Documentation/devicetree/bindings/rtc/st,m41t93.yaml new file mode 100644 index 000000000000..bdd995c5c1f4 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/st,m41t93.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/st,m41t93.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST M41T93 RTC and compatible + +maintainers: + - Akhilesh Patil <akhilesh@ee.iitb.ac.in> + +description: + ST M41T93 is spi based Real Time Clock (RTC) with time, date, + alarm, watchdog, square wave clock output, 8 bit timer and + 7 bytes of user SRAM. + +properties: + compatible: + enum: + - st,m41t93 + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + +required: + - compatible + - reg + +allOf: + - $ref: rtc.yaml + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + rtc@0 { + compatible = "st,m41t93"; + reg = <0>; + #clock-cells = <0>; + spi-max-frequency = <2000000>; + }; + }; + diff --git a/Documentation/devicetree/bindings/rtc/ti,omap-rtc.yaml b/Documentation/devicetree/bindings/rtc/ti,omap-rtc.yaml new file mode 100644 index 000000000000..02b3c23cf435 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/ti,omap-rtc.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/ti,omap-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments OMAP Real Time Clock + +maintainers: + - Keerthy <j-keerthy@ti.com> + - Afzal Mohammed <afzal@ti.com> + +description: + The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock with + century-range alarm matching, driven by the 32kHz clock. + +properties: + compatible: + oneOf: + - const: ti,da830-rtc + - items: + - const: ti,am3352-rtc + - const: ti,da830-rtc + - items: + - const: ti,am4372-rtc + - const: ti,am3352-rtc + - const: ti,da830-rtc + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 2 + + system-power-controller: + type: boolean + description: + Indicates that this RTC controls system power via the pmic_power_en pin. + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - enum: [ext-clk, int-clk] + - const: int-clk + + pinctrl-0: + description: + Phandle to pin configuration for the external wakeup pins. + + pinctrl-names: + minItems: 1 + + ti,hwmods: + $ref: /schemas/types.yaml#/definitions/string + description: + Name of the hwmod associated with the RTC. + const: rtc + deprecated: true + +patternProperties: + "^ext-wakeup(-[0-9]+)?$": + type: object + + description: + Child node describing external wakeup pin configuration. + + properties: + pins: + pattern: '^ext_wakeup[0-3]$' + + input-enable: + type: boolean + description: + Enables the external wakeup input on the selected pin. + + ti,active-high: + type: boolean + description: + Sets the wakeup input polarity to active high. By default the + input is active low. + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: rtc.yaml# + - if: + not: + properties: + compatible: + contains: + const: ti,am3352-rtc + then: + properties: + system-power-controller: false + patternProperties: + "^ext-wakeup(-[0-9]+)?$": false + +unevaluatedProperties: false + +examples: + - | + rtc@23000 { + compatible = "ti,da830-rtc"; + reg = <0x23000 0x1000>; + interrupts = <19>, <19>; + clocks = <&clk_32768_ck>; + clock-names = "int-clk"; + }; + + - | + rtc@0 { + compatible = "ti,am3352-rtc", "ti,da830-rtc"; + reg = <0x0 0x1000>; + interrupts = <75>, <76>; + system-power-controller; + clocks = <&clk_32k_rtc>, <&clk_32768_ck>; + clock-names = "ext-clk", "int-clk"; + + pinctrl-0 = <&ext_wakeup>; + pinctrl-names = "default"; + + ext-wakeup { + pins = "ext_wakeup0"; + input-enable; + ti,active-high; + }; + }; diff --git a/Documentation/devicetree/bindings/rtc/ti,palmas-rtc.yaml b/Documentation/devicetree/bindings/rtc/ti,palmas-rtc.yaml new file mode 100644 index 000000000000..ac64f0589c84 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/ti,palmas-rtc.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/ti,palmas-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Palmas RTC + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +allOf: + - $ref: /schemas/rtc/rtc.yaml# + +properties: + compatible: + const: ti,palmas-rtc + + interrupts: + maxItems: 1 + + wakeup-source: true + + ti,backup-battery-chargeable: + type: boolean + description: + The backup battery can be chargeable or non-chargeable. This flag + indicates whether the battery is chargeable. If present, the driver + can enable charging. + + ti,backup-battery-charge-high-current: + type: boolean + description: + Enable high current charging in the backup battery. + Device supports the < 100uA and > 100uA charging. The high current will + be > 100uA. Absence of this property will charge battery to lower + current i.e. < 100uA. + +required: + - compatible + - interrupts + +unevaluatedProperties: false + +examples: + - | + pmic { + #address-cells = <1>; + #size-cells = <0>; + + rtc { + compatible = "ti,palmas-rtc"; + interrupts = <8 0>; + ti,backup-battery-chargeable; + ti,backup-battery-charge-high-current; + }; + }; diff --git a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml index 722176c831aa..f4d0eed98a08 100644 --- a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml @@ -30,6 +30,8 @@ properties: - aspeed,ast2500-rtc # ASPEED BMC ast2600 Real-time Clock - aspeed,ast2600-rtc + # ASPEED BMC ast2700 Real-time Clock + - aspeed,ast2700-rtc # Conexant Digicolor Real Time Clock Controller - cnxt,cx92755-rtc # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index bb7b9c87a807..8c2c177faf89 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -23,7 +23,8 @@ allOf: then: properties: compatible: - const: aspeed,ast2500-vuart + contains: + const: aspeed,ast2500-vuart - if: properties: compatible: @@ -188,6 +189,11 @@ properties: - loongson,ls2k2000-uart - const: loongson,ls2k1500-uart - const: ns16550a + - items: + - enum: + - aspeed,ast2600-vuart + - aspeed,ast2700-vuart + - const: aspeed,ast2500-vuart reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/serial/maxim,max310x.yaml b/Documentation/devicetree/bindings/serial/maxim,max310x.yaml index 889eeaca64a0..e598dda4d13f 100644 --- a/Documentation/devicetree/bindings/serial/maxim,max310x.yaml +++ b/Documentation/devicetree/bindings/serial/maxim,max310x.yaml @@ -9,6 +9,13 @@ title: Maxim MAX310X Advanced Universal Asynchronous Receiver-Transmitter (UART) maintainers: - Hugo Villeneuve <hvilleneuve@dimonoff.com> +description: + The MAX310X is a family of SPI/I2C UARTs with one (max3107, max3108), + two (max3109) or four (max14830) channels. Single-channel parts are + described as a serial node with RS-485 properties on the chip node; + multi-channel parts use one "serial@N" child node per channel, each + carrying its own serial/RS-485 properties. + properties: compatible: enum: @@ -49,8 +56,55 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# - - $ref: /schemas/serial/serial.yaml# - - $ref: /schemas/serial/rs485.yaml# + + - if: + properties: + compatible: + contains: + enum: + - maxim,max3107 + - maxim,max3108 + then: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + + - if: + properties: + compatible: + contains: + enum: + - maxim,max3109 + - maxim,max14830 + then: + properties: + "#address-cells": + const: 1 + "#size-cells": + const: 0 + patternProperties: + "^serial@[0-3]$": + type: object + description: A single UART channel of the chip. + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + properties: + reg: + description: UART channel number on the chip. + maximum: 3 + required: + - reg + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + const: maxim,max3109 + then: + patternProperties: + "^serial@[23]$": false unevaluatedProperties: false @@ -70,5 +124,39 @@ examples: interrupts = <7 IRQ_TYPE_LEVEL_LOW>; gpio-controller; #gpio-cells = <2>; + rs485-rts-active-low; + linux,rs485-enabled-at-boot-time; + }; + }; + + - | + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + serial@0 { + compatible = "maxim,max14830"; + reg = <0>; + spi-max-frequency = <26000000>; + clocks = <&xtal4m>; + clock-names = "xtal"; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + #address-cells = <1>; + #size-cells = <0>; + + serial@0 { + reg = <0>; + rs485-rts-active-low; + linux,rs485-enabled-at-boot-time; + }; + + serial@2 { + reg = <2>; + rs485-rts-active-low; + }; }; }; diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml index 788ef5c1c446..bc967ead2350 100644 --- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml +++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml @@ -17,7 +17,7 @@ description: | software perspective it's mostly compatible with the MSM serial UART except that it supports reading and writing multiple characters at a time. - Note:: Aliases may be defined to ensure the correct ordering of the UARTs. + Note: Aliases may be defined to ensure the correct ordering of the UARTs. The alias serialN will result in the UART being assigned port N. If any serialN alias exists, then an alias must exist for each enabled UART. The serialN aliases should be in a .dts file instead of in a .dtsi file. diff --git a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml index c8f01923cb25..8496f822dfa5 100644 --- a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml +++ b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml @@ -14,9 +14,16 @@ allOf: properties: compatible: - enum: - - qcom,sa8255p-geni-uart - - qcom,sa8255p-geni-debug-uart + oneOf: + - enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + - items: + - const: qcom,sa8797p-geni-uart + - const: qcom,sa8255p-geni-uart + - items: + - const: qcom,sa8797p-geni-debug-uart + - const: qcom,sa8255p-geni-debug-uart reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt deleted file mode 100644 index a7fe93efc4a5..000000000000 --- a/Documentation/devicetree/bindings/serial/rs485.txt +++ /dev/null @@ -1 +0,0 @@ -See rs485.yaml diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 685c1eceb782..664305de4986 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -54,6 +54,7 @@ properties: - anlogic,dr1v90-uart - brcm,bcm11351-dw-apb-uart - brcm,bcm21664-dw-apb-uart + - google,lga-uart - rockchip,px30-uart - rockchip,rk1808-uart - rockchip,rk3036-uart @@ -72,12 +73,14 @@ properties: - rockchip,rk3576-uart - rockchip,rk3588-uart - rockchip,rv1103b-uart + - rockchip,rv1106-uart - rockchip,rv1108-uart - rockchip,rv1126-uart - sophgo,sg2044-uart - starfive,jh7100-hsuart - starfive,jh7100-uart - starfive,jh7110-uart + - ultrarisc,dp1000-uart - const: snps,dw-apb-uart - const: snps,dw-apb-uart diff --git a/Documentation/devicetree/bindings/slimbus/slimbus.yaml b/Documentation/devicetree/bindings/slimbus/slimbus.yaml index 5a941610ce4e..3910327c8ded 100644 --- a/Documentation/devicetree/bindings/slimbus/slimbus.yaml +++ b/Documentation/devicetree/bindings/slimbus/slimbus.yaml @@ -29,7 +29,7 @@ patternProperties: description: | Every SLIMbus controller node can contain zero or more child nodes representing slave devices on the bus. Every SLIMbus slave device is - uniquely determined by the enumeration address containing 4 fields:: + uniquely determined by the enumeration address containing 4 fields: Manufacturer ID, Product code, Device index, and Instance value for the device. @@ -48,7 +48,7 @@ patternProperties: reg: maxItems: 1 description: | - Pair of (device index, instande ID), where:: + Pair of (device index, instande ID), where: - Device index, which uniquely identifies multiple devices within a single component. - Instance ID, can be used for the cases where multiple devices of diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml index 39d4637c2d08..b1200e6940ac 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml @@ -24,6 +24,8 @@ properties: - amlogic,meson-sm1-clk-measure - amlogic,c3-clk-measure - amlogic,s4-clk-measure + - amlogic,a1-clk-measure + - amlogic,t7-clk-measure reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/apple/apple,t6000-pmgr-misc.yaml b/Documentation/devicetree/bindings/soc/apple/apple,t6000-pmgr-misc.yaml new file mode 100644 index 000000000000..588100222f89 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/apple/apple,t6000-pmgr-misc.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/apple/apple,t6000-pmgr-misc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC PMGR Misc Power States + +maintainers: + - Sasha Finkelstein <k@chaosmail.tech> + +description: | + Certain Apple SoCs include additional PMGR power states that are controlled + via a different "misc" control block. This includes the fabric and memory + controller states. + +properties: + compatible: + enum: + - apple,t6000-pmgr-misc + - apple,t6020-pmgr-misc + + reg: + maxItems: 2 + + reg-names: + items: + - const: fabric-ps + - const: dcs-ps + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + power-management@8e20c000 { + compatible = "apple,t6000-pmgr-misc"; + reg = <0x8e20c000 0x400>, + <0x8e20c800 0x400>; + reg-names = "fabric-ps", "dcs-ps"; + }; diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml new file mode 100644 index 000000000000..50dd0593e1d9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cix/cix,sky1-audss-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 audio subsystem clock and reset unit + +maintainers: + - Joakim Zhang <joakim.zhang@cixtech.com> + +description: | + The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups + audio-related clock muxing, gating and block-level software reset control + in a single register block. + + A single device node exposes both the clock controller and software reset + lines. The clock driver registers as a platform driver; the reset controller + is registered by an auxiliary driver bound from the clock driver. + + Four SoC-level reference clocks listed in clocks/clock-names feed the AUDSS + clock tree. Internal AUDSS clocks are exposed via #clock-cells; indices are + defined in include/dt-bindings/clock/cix,sky1-audss-cru.h. + + Block-level software reset indices are exposed via #reset-cells; indices + are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h. + + The SoC syscon NoC (or bus) reset is described via resets. The audio + subsystem power domain is described via power-domains. + +properties: + compatible: + const: cix,sky1-audss-cru + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss-cru.h. + + '#reset-cells': + const: 1 + description: + Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h. + + clocks: + items: + - description: I2S parent clock for sampling rates multiple of 8kHz. + - description: I2S parent clock for sampling rates multiple of 11.025kHz. + - description: Clock feeding most devices in AUDSS (NOC, DSP, SRAM, HDA, DMAC, I2S, and mailbox). + - description: Clock feeding HDA, timer and watchdog, which is a dedicated 48 MHz clock. + + clock-names: + items: + - const: x8k + - const: x11k + - const: sys + - const: 48m + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + audss_cru: clock-controller@7110000 { + compatible = "cix,sky1-audss-cru"; + reg = <0x7110000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk 76>, <&scmi_clk 78>, + <&scmi_clk 70>, <&scmi_clk 71>; + clock-names = "x8k", "x11k", "sys", "48m"; + power-domains = <&smc_devpd 0>; + resets = <&s5_syscon 31>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt index 09b1b05fa677..782699c14567 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt @@ -24,28 +24,4 @@ par_io@1400 { Note that "par_io" nodes are obsolete, and should not be used for the new device trees. Instead, each Par I/O bank should be represented -via its own gpio-controller node: - -Required properties: -- #gpio-cells : should be "2". -- compatible : should be "fsl,<chip>-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank". -- reg : offset to the register set and its length. -- gpio-controller : node to identify gpio controllers. - -Example: - qe_pio_a: gpio-controller@1400 { - #gpio-cells = <2>; - compatible = "fsl,mpc8360-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank"; - reg = <0x1400 0x18>; - gpio-controller; - }; - - qe_pio_e: gpio-controller@1460 { - #gpio-cells = <2>; - compatible = "fsl,mpc8360-qe-pario-bank", - "fsl,mpc8323-qe-pario-bank"; - reg = <0x1460 0x18>; - gpio-controller; - }; +via its own gpio-controller node. diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml index 3fb0534ea597..fc14fd0bf84b 100644 --- a/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,layerscape-dcfg.yaml @@ -36,7 +36,20 @@ properties: - const: simple-mfd reg: - maxItems: 1 + minItems: 1 + items: + - description: + Customer-visible DCFG register map from CCSR address space + (Configuration, Control and Status Registers) + - description: + Customer-hidden DCFG register map from DCSR address space + (Debug Control and Status Registers) + + reg-names: + minItems: 1 + items: + - const: dcfg_ccsr + - const: dcfg_dcsr little-endian: true big-endian: true diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml index d828c2e82965..124f5c206ee3 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -26,6 +26,12 @@ properties: reg: maxItems: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + '#power-domain-cells': const: 1 @@ -92,6 +98,11 @@ properties: - compatible - ports + bridge@20: + type: object + $ref: /schemas/display/bridge/fsl,ldb.yaml# + unevaluatedProperties: false + allOf: - if: properties: @@ -112,6 +123,7 @@ allOf: - const: lcdif - const: isi - const: csi + bridge@20: false - if: properties: compatible: @@ -163,6 +175,8 @@ examples: <&clk IMX93_CLK_MIPI_DSI_GATE>; clock-names = "apb", "axi", "nic", "disp", "cam", "pxp", "lcdif", "isi", "csi", "dsi"; + #address-cells = <1>; + #size-cells = <1>; #power-domain-cells = <1>; dpi-bridge { @@ -190,4 +204,29 @@ examples: }; }; }; + + bridge@20 { + compatible = "fsl,imx93-ldb"; + reg = <0x20 0x4>, <0x24 0x4>; + reg-names = "ldb", "lvds"; + clocks = <&clk IMX93_CLK_LVDS_GATE>; + clock-names = "ldb"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&lcdif_to_ldb>; + }; + }; + + port@1 { + reg = <1>; + }; + }; + }; }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 5267cfe92572..1ba086ad749d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -4,18 +4,21 @@ $id: http://devicetree.org/schemas/soc/mediatek/mediatek,mutex.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek mutex +title: MediaTek Mute-X maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> - Chun-Kuang Hu <chunkuang.hu@kernel.org> - Philipp Zabel <p.zabel@pengutronix.de> -description: | - Mediatek mutex, namely MUTEX, is used to send the triggers signals called - Start Of Frame (SOF) / End Of Frame (EOF) to each sub-modules on the display - data path or MDP data path. - In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects - the shadow register. +description: + MediaTek Mute-X, namely MUTEX, is used to "mute" or "unmute" trigger signals + like Start Of Frame (SOF), End Of Frame (EOF), Tearing Effect (TE / VSYNC) + and others to each hardware sub-modules in the Display Controller IP or in + the Media Data Path (MDP) IP. + In some SoCs like MT2701, this hardware module may feature functionality + to, for example, protect shadow registers by blocking auto write triggers + upon operation (usually frame push) completion. MUTEX device node must be siblings to the central MMSYS_CONFIG node. For a description of the MMSYS_CONFIG binding, see Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml index 51164772724f..419b32e2df93 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml @@ -26,7 +26,11 @@ description: | properties: compatible: - const: microchip,mpfs-irqmux + oneOf: + - items: + - const: microchip,pic64gx-irqmux + - const: microchip,mpfs-irqmux + - const: microchip,mpfs-irqmux reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml new file mode 100644 index 000000000000..2958ca9e330b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq7h-olb.yaml @@ -0,0 +1,192 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq7h-olb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ7H SoC system controller + +maintainers: + - Benoît Monin <benoit.monin@bootlin.com> + - Grégory Clement <gregory.clement@bootlin.com> + - Théo Lebrun <theo.lebrun@bootlin.com> + - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com> + +description: + OLB ("Other Logic Block") is a hardware system controller grouping + smaller blocks. Clocks and resets are generated by those blocks and + used by internal controllers of the SoC. The EyeQ7H SoC hosts 14 + different OLB. + +properties: + compatible: + items: + - enum: + - mobileye,eyeq7h-acc0-olb + - mobileye,eyeq7h-acc1-olb + - mobileye,eyeq7h-ddr0-olb + - mobileye,eyeq7h-ddr1-olb + - mobileye,eyeq7h-east-olb + - mobileye,eyeq7h-mips0-olb + - mobileye,eyeq7h-mips1-olb + - mobileye,eyeq7h-mips2-olb + - mobileye,eyeq7h-periph-east-olb + - mobileye,eyeq7h-periph-west-olb + - mobileye,eyeq7h-south-olb + - mobileye,eyeq7h-west-olb + - mobileye,eyeq7h-xnn0-olb + - mobileye,eyeq7h-xnn1-olb + - const: syscon + + reg: + maxItems: 1 + + '#reset-cells': + description: + First cell is domain and optional if compatible has a single reset domain. + Second cell is reset index inside that domain. + enum: [ 1, 2 ] + + '#clock-cells': + const: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - '#clock-cells' + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-ddr0-olb + - mobileye,eyeq7h-ddr1-olb + - mobileye,eyeq7h-mips0-olb + - mobileye,eyeq7h-mips1-olb + - mobileye,eyeq7h-mips2-olb + - mobileye,eyeq7h-periph-east-olb + - mobileye,eyeq7h-south-olb + then: + properties: + clocks: + items: + - description: Reference input clock. + clock-names: + items: + - const: ref + + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-east-olb + - mobileye,eyeq7h-west-olb + then: + properties: + clocks: + items: + - description: Reference input clock from the main oscillator. + - description: 100MHz reference input clock. + clock-names: + items: + - const: ref + - const: ref_100p0 + + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-acc0-olb + - mobileye,eyeq7h-acc1-olb + - mobileye,eyeq7h-periph-west-olb + - mobileye,eyeq7h-xnn0-olb + - mobileye,eyeq7h-xnn1-olb + then: + properties: + clocks: + items: + - description: 100MHz reference input clock. + - description: 106.6MHz reference input clock. + clock-names: + items: + - const: ref_100p0 + - const: ref_106p6 + + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-ddr0-olb + - mobileye,eyeq7h-ddr1-olb + - mobileye,eyeq7h-east-olb + - mobileye,eyeq7h-periph-east-olb + - mobileye,eyeq7h-periph-west-olb + - mobileye,eyeq7h-west-olb + then: + properties: + '#reset-cells': + const: 1 + required: + - '#reset-cells' + + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-acc0-olb + - mobileye,eyeq7h-acc1-olb + - mobileye,eyeq7h-south-olb + - mobileye,eyeq7h-xnn0-olb + - mobileye,eyeq7h-xnn1-olb + then: + properties: + '#reset-cells': + const: 2 + required: + - '#reset-cells' + + - if: + properties: + compatible: + contains: + enum: + - mobileye,eyeq7h-mips0-olb + - mobileye,eyeq7h-mips1-olb + - mobileye,eyeq7h-mips2-olb + then: + properties: + '#reset-cells': false + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-controller0@45000000 { + compatible = "mobileye,eyeq7h-acc0-olb", "syscon"; + reg = <0x0 0x45000000 0x0 0x1000>; + #reset-cells = <2>; + #clock-cells = <1>; + clocks = <&olb_south 7>, <&olb_east 5>; + clock-names = "ref_100p0", "ref_106p6"; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index c5c1bac2db01..d2ae2ae87a95 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -25,9 +25,13 @@ properties: compatible: items: - enum: + - qcom,eliza-aoss-qmp - qcom,glymur-aoss-qmp + - qcom,hawi-aoss-qmp - qcom,kaanapali-aoss-qmp + - qcom,maili-aoss-qmp - qcom,milos-aoss-qmp + - qcom,nord-aoss-qmp - qcom,qcs615-aoss-qmp - qcom,qcs8300-aoss-qmp - qcom,qdu1000-aoss-qmp diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml index bdf482db32aa..b663be3ea5a1 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml @@ -40,7 +40,7 @@ properties: $ref: /schemas/types.yaml#/definitions/string-array description: | Protection domain service name and path for APR service (if supported). - Possible values are:: + Possible values are: "avs/audio", "msm/adsp/audio_pd". "kernel/elf_loader", "msm/modem/wlan_pd". "tms/servreg", "msm/adsp/audio_pd". diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index ff01d2f3ee5b..16ad4f5698fc 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -34,11 +34,18 @@ properties: - const: qcom,pmic-glink - items: - enum: + - qcom,hawi-pmic-glink + - qcom,maili-pmic-glink + - const: qcom,kaanapali-pmic-glink + - const: qcom,pmic-glink + - items: + - enum: - qcom,sm7325-pmic-glink - const: qcom,qcm6490-pmic-glink - const: qcom,pmic-glink - items: - enum: + - qcom,eliza-pmic-glink - qcom,milos-pmic-glink - qcom,sm8650-pmic-glink - qcom,sm8750-pmic-glink diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index 26d9bc773ec5..1889139a3f7a 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -23,7 +23,7 @@ description: | with a few variations that are captured by the properties here. A TCS may be triggered from Linux or triggered by the F/W after all the CPUs - have powered off to facilitate idle power saving. TCS could be classified as:: + have powered off to facilitate idle power saving. TCS could be classified as: ACTIVE - Triggered by Linux SLEEP - Triggered by F/W WAKE - Triggered by F/W @@ -76,7 +76,7 @@ properties: items: items: - description: | - TCS type:: + TCS type: - ACTIVE_TCS - SLEEP_TCS - WAKE_TCS @@ -152,7 +152,7 @@ examples: - | // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of // 2, the register offsets for DRV2 start at 0D00, the register - // calculations are like this:: + // calculations are like this: // DRV0: 0x179C0000 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 @@ -182,7 +182,7 @@ examples: - | // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the // register offsets for DRV0 start at 01C00, the register calculations are - // like this:: + // like this: // DRV0: 0xAF20000 // TCS-OFFSET: 0x1C00 #include <dt-bindings/interrupt-controller/arm-gic.h> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml index 352af3426d34..9c38ba59662b 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml @@ -19,7 +19,11 @@ description: properties: compatible: - const: qcom,sa8255p-geni-se-qup + oneOf: + - const: qcom,sa8255p-geni-se-qup + - items: + - const: qcom,sa8797p-geni-se-qup + - const: qcom,sa8255p-geni-se-qup reg: description: QUP wrapper common register address and length. @@ -49,7 +53,11 @@ patternProperties: properties: compatible: - const: qcom,sa8255p-geni-spi + oneOf: + - const: qcom,sa8255p-geni-spi + - items: + - const: qcom,sa8797p-geni-spi + - const: qcom,sa8255p-geni-spi "i2c@[0-9a-f]+$": type: object @@ -58,7 +66,11 @@ patternProperties: properties: compatible: - const: qcom,sa8255p-geni-i2c + oneOf: + - const: qcom,sa8255p-geni-i2c + - items: + - const: qcom,sa8797p-geni-i2c + - const: qcom,sa8255p-geni-i2c "serial@[0-9a-f]+$": type: object @@ -67,9 +79,16 @@ patternProperties: properties: compatible: - enum: - - qcom,sa8255p-geni-uart - - qcom,sa8255p-geni-debug-uart + oneOf: + - enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + - items: + - const: qcom,sa8797p-geni-uart + - const: qcom,sa8255p-geni-uart + - items: + - const: qcom,sa8797p-geni-debug-uart + - const: qcom,sa8255p-geni-debug-uart required: - compatible diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 270bcd079f88..bd1d32898461 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -57,6 +57,7 @@ properties: - qcom,rpm-qcm2290 - qcom,rpm-qcs404 - qcom,rpm-sdm660 + - qcom,rpm-shikra - qcom,rpm-sm6115 - qcom,rpm-sm6125 - qcom,rpm-sm6375 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml index 4fcae6bedfff..cfaa15d86ece 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml @@ -19,8 +19,8 @@ properties: const: qcom,wcnss firmware-name: - $ref: /schemas/types.yaml#/definitions/string - default: wlan/prima/WCNSS_qcom_wlan_nv.bin + maxItems: 1 + default: [ wlan/prima/WCNSS_qcom_wlan_nv.bin ] description: Relative firmware image path for the WLAN NV blob. @@ -28,7 +28,7 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: | Reference to a node specifying the wcnss "ccu" and "dxe" register blocks. - The node must be compatible with one of the following:: + The node must be compatible with one of the following: - qcom,riva" - qcom,pronto" diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml new file mode 100644 index 000000000000..72b9fa67d1f7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas MFIS (Multifunctional Interface) controller + +maintainers: + - Wolfram Sang <wsa+renesas@sang-engineering.com> + +description: + The Renesas Multifunctional Interface (MFIS) provides various functionality + like mailboxes, hardware spinlocks, product identification, error injection, + error detection and such. Parts of it can be used for communication between + different CPU cores. Those cores can be in various domains like AP, RT, or + SCP. Often multiple domain-specific MFIS instances exist in one SoC. + +properties: + compatible: + enum: + - renesas,r8a779g0-mfis # R-Car V4H + - renesas,r8a779h0-mfis # R-Car V4M + - renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR) + - renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR) + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: common + - const: mboxes + + interrupts: + minItems: 12 + maxItems: 128 + description: + The interrupts raised by the remote doorbells. + + interrupt-names: + minItems: 12 + maxItems: 128 + description: + An interrupt name is constructed with the prefix 'ch'. Then, the + channel number as specified in the documentation of the SoC. Finally, + the letter 'i' if the interrupt is raised by the IICR register. Or 'e' + if it is raised by the EICR register. + + "#hwlock-cells": + const: 1 + + "#mbox-cells": + const: 2 + description: + The first cell is the channel number as specified in the documentation + of the SoC. The second cell may specify flags as described in the file + <dt-bindings/soc/renesas,r8a78000-mfis.h>. + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,r8a779g0-mfis + - renesas,r8a779h0-mfis + then: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + interrupts: + maxItems: 12 + interrupt-names: + maxItems: 12 + items: + pattern: "^ch[0-9]+e$" + + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + interrupts: + minItems: 128 + interrupt-names: + minItems: 128 + items: + pattern: "^ch[0-9]+[ie]$" + + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis-scp + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + interrupts: + minItems: 32 + maxItems: 32 + interrupt-names: + minItems: 32 + maxItems: 32 + items: + pattern: "^ch[0-9]+i$" + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#hwlock-cells" + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + system-controller@189e0000 { + compatible = "renesas,r8a78000-mfis"; + reg = <0x189e0000 0x1000>, <0x18800000 0x40000>; + reg-names = "common", "mboxes"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; + #hwlock-cells = <1>; + #mbox-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas-soc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas-soc.yaml index 5ddd31f30f26..57c9d3c57021 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas-soc.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas-soc.yaml @@ -12,10 +12,10 @@ maintainers: description: | Guidelines for new compatibles for SoC blocks/components. - When adding new compatibles in new bindings, use the format:: + When adding new compatibles in new bindings, use the format: renesas,SoC-IP - For example:: + For example: renesas,r8a77965-csi2 When adding new compatibles to existing bindings, use the format in the diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 5c22c51b1533..eeef34e3d7d0 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -473,6 +473,12 @@ properties: - const: renesas,r8a779mb - const: renesas,r8a7795 + - description: R-Car M3Le (R8A779MD) + items: + - const: renesas,geist # M3Le Geist (RTP8A779MDASKB0F10S) + - const: renesas,r8a779md + - const: renesas,r8a77965 + - description: R-Car X5H (R8A78000) items: - enum: diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 2cc43742b8e3..7bcb4e2f47ec 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -239,11 +239,14 @@ allOf: properties: reboot-mode: type: object - $ref: /schemas/power/reset/syscon-reboot-mode.yaml# - unevaluatedProperties: false + patternProperties: + # Negative look-ahead to disallow unsupported modes. The '$' has to be + # part of lookahead group to work, instead of trailing outside of (). + "^mode-(?!(bootloader$|fastboot$|loader$|normal$|recovery$))": false + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 76ce7e98c10f..5bd39876e3b3 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -94,19 +94,19 @@ properties: reboot-mode: $ref: /schemas/power/reset/syscon-reboot-mode.yaml - type: object + unevaluatedProperties: false description: Reboot mode to alter bootloader behavior for the next boot syscon-poweroff: $ref: /schemas/power/reset/syscon-poweroff.yaml# - type: object + unevaluatedProperties: false description: Node for power off method syscon-reboot: $ref: /schemas/power/reset/syscon-reboot.yaml# - type: object + unevaluatedProperties: false description: Node for reboot method @@ -181,8 +181,29 @@ allOf: compatible: contains: enum: + - samsung,exynos7-pmu + then: + properties: + reboot-mode: + patternProperties: + # Negative look-ahead to disallow unsupported modes. The '$' has to be + # part of lookahead group to work, instead of trailing outside of (). + "^mode-(?!(bootloader$|download$|fastboot$|recovery$))": false + + - if: + properties: + compatible: + contains: + enum: - google,gs101-pmu then: + properties: + reboot-mode: + patternProperties: + # Negative look-ahead to disallow unsupported modes. The '$' has to be + # part of lookahead group to work, instead of trailing outside of (). + "^mode-(?!(bootloader$|charge$|dm-verity-device-corrupted$|fastboot$|reboot-ab-update$|recovery$)|rescue$|shutdown-thermal$|shutdown-thermal-battery$)": false + required: - google,pmu-intr-gen-syscon else: diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml index 9c63dbcd4d77..fcdb9ffd2644 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -37,6 +37,7 @@ properties: - samsung,exynos8895-peric1-sysreg - samsung,exynos990-peric0-sysreg - samsung,exynos990-peric1-sysreg + - samsung,exynosautov920-hsi0-sysreg - samsung,exynosautov920-hsi2-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml index 1c502618de51..99194d8721ef 100644 --- a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml @@ -33,6 +33,14 @@ properties: - const: sophgo,sg2000 - items: - enum: + - milkv,duo-s + - const: sophgo,sg2000 + - items: + - enum: + - milkv,duo256m + - const: sophgo,sg2002 + - items: + - enum: - sipeed,licheerv-nano-b - const: sipeed,licheerv-nano - const: sophgo,sg2002 diff --git a/Documentation/devicetree/bindings/soc/ti/ti,omap-dmm.yaml b/Documentation/devicetree/bindings/soc/ti/ti,omap-dmm.yaml new file mode 100644 index 000000000000..1a2b627cd206 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,omap-dmm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/ti/ti,omap-dmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP Dynamic Memory Manager (DMM) + +maintainers: + - Bhargav Joshi <j.bhargav.u@gmail.com> + +description: + The dynamic memory manager (DMM) is a module located immediately in front of + the SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of + memory accesses such as priority generation amongst initiators, configuration + of SDRAM interleaving, optimizing transfer of 2D block objects, and provide + MMU-like page translation for initiators which need contiguous dma bus + addresses. + +properties: + compatible: + enum: + - ti,omap4-dmm + - ti,omap5-dmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ti,hwmods: + $ref: /schemas/types.yaml#/definitions/string + description: Name of the hwmod associated to DMM, which is typically "dmm" + deprecated: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + dmm@4e000000 { + compatible = "ti,omap4-dmm"; + reg = <0x4e000000 0x800>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "dmm"; + }; diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.yaml b/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.yaml index 4f13e8ab50b2..177db900d4a0 100644 --- a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.yaml +++ b/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.yaml @@ -30,7 +30,7 @@ properties: minItems: 1 maxItems: 3 description: - Base PLL clocks of audio susbsytem, used to configure base clock + Base PLL clocks of audio subsystem, used to configure base clock frequencies for different audio use-cases. patternProperties: diff --git a/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml b/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml index 413b47778181..6fdf605ad59c 100644 --- a/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml +++ b/Documentation/devicetree/bindings/sound/amlogic,gx-sound-card.yaml @@ -31,7 +31,7 @@ properties: minItems: 1 maxItems: 3 description: - Base PLL clocks of audio susbsytem, used to configure base clock + Base PLL clocks of audio subsystem, used to configure base clock frequencies for different audio use-cases. patternProperties: diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt deleted file mode 100644 index 860fc0da39c0..000000000000 --- a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.txt +++ /dev/null @@ -1,18 +0,0 @@ -Bindings for I2S controller built into xtfpga Xtensa bitstreams. - -Required properties: -- compatible: shall be "cdns,xtfpga-i2s". -- reg: memory region (address and length) with device registers. -- interrupts: interrupt for the device. -- clocks: phandle to the clk used as master clock. I2S bus clock - is derived from it. - -Examples: - - i2s0: xtfpga-i2s@d080000 { - #sound-dai-cells = <0>; - compatible = "cdns,xtfpga-i2s"; - reg = <0x0d080000 0x40>; - interrupts = <2 1>; - clocks = <&cdce706 4>; - }; diff --git a/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml new file mode 100644 index 000000000000..9617acef3f0c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cdns,xtfpga-i2s.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cdns,xtfpga-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2S controller built into xtfpga Xtensa bitstreams + +maintainers: + - Max Filippov <jcmvbkbc@gmail.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: cdns,xtfpga-i2s + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: phandle to the clk used as master clock. I2S bus clock is derived from it. + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2s@d080000 { + compatible = "cdns,xtfpga-i2s"; + reg = <0x0d080000 0x40>; + interrupts = <2 1>; + clocks = <&cdce706 4>; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs35l36.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs35l36.yaml new file mode 100644 index 000000000000..2a142b32acf5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cirrus,cs35l36.yaml @@ -0,0 +1,240 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,cs35l36.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS35L36 Speaker Amplifier + +maintainers: + - David Rhodes <drhodes@opensource.cirrus.com> + - patches@opensource.cirrus.com + +description: + CS35L36 is a boosted mono Class D amplifier + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - cirrus,cs35l36 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + VA-supply: + description: Voltage regulator of analog internal section + + VP-supply: + description: Voltage regulator of boost converter + + reset-gpios: + maxItems: 1 + + cirrus,boost-ctl-millivolt: + description: Boost converter output voltage (step 50) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2550 + maximum: 12000 + + cirrus,boost-peak-milliamp: + description: Boost-converter peak current limit (step 50) + $ref: /schemas/types.yaml#/definitions/uint32 + default: 4500 + minimum: 1600 + maximum: 4500 + + cirrus,boost-ind-nanohenry: + description: Initial inductor estimation reference value (1000=1μH, 1200=1.2μH) + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1000 + + cirrus,multi-amp-mode: + description: Hi-Z ASP port when more than one amplifier in system + type: boolean + + cirrus,boost-ctl-select: + description: Boost converter control source selection + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + enum: + - 0 # Control Port + - 1 # Class + - 2 # Sync + + cirrus,amp-pcm-inv: + description: Invert incoming PCM data when true + type: boolean + + cirrus,imon-pol-inv: + description: Invert polarity of outbound IMON feedback when true + type: boolean + + cirrus,vmon-pol-inv: + description: Invert polarity of outbound VMON feedback when true + type: boolean + + cirrus,dcm-mode-enable: + description: Enable boost converter automatic Discontinuous Conduction Mode + type: boolean + + cirrus,weak-fet-disable: + description: Reduce output driver strength in Weak-FET Drive Mode when true + type: boolean + + cirrus,classh-wk-fet-delay-ms: + description: Weak-FET entry delay + default: 100 + enum: [0, 5, 10, 50, 100, 200, 500, 1000] + + cirrus,classh-weak-fet-thld-millivolt: + description: Weak-FET drive threshold + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700] + + cirrus,temp-warn-threshold: + description: Overtemperature warning threshold + $ref: /schemas/types.yaml#/definitions/uint32 + default: 2 + enum: + - 0 # 105°C + - 1 # 115°C + - 2 # 125°C + - 3 # 135°C + + cirrus,irq-drive-select: + description: Interrupt output driver type + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + enum: + - 0 # open-drain + - 1 # push-pull + + cirrus,irq-gpio-select: + description: Programmable IRQ pin selection + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # PDM_DATA/SWIRE_SD/INT + - 1 # GPIO + + cirrus,vpbr-config: + $ref: "#/$defs/vpbr-config" + +$defs: + vpbr-config: + description: Brownout prevention configuration sub-node + type: object + additionalProperties: false + + properties: + cirrus,vpbr-en: + description: VBST brownout prevention enable + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: + - 0 # disabled + - 1 # enabled + + cirrus,vpbr-thld: + description: Initial VPBR threshold voltage + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2 + maximum: 31 + + cirrus,vpbr-atk-rate: + description: Attenuation attack step rate + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + cirrus,vpbr-atk-vol: + description: VP brownout prevention step size + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + cirrus,vpbr-max-attn: + description: Maximum attenuation during VP brownout prevention (dB) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + cirrus,vpbr-wait: + description: Delay between brownout clearance and attenuation release (ms) + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + enum: + - 0 # 10 + - 1 # 100 + - 2 # 250 + - 3 # 500 + + cirrus,vpbr-rel-rate: + description: Attenuation release step rate + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + cirrus,vpbr-mute-en: + description: Mute audio if maximum attenuation reached + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1 + +required: + - compatible + - reg + - interrupts + - VA-supply + - cirrus,boost-ctl-millivolt + - cirrus,boost-peak-milliamp + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + codec@40 { + compatible = "cirrus,cs35l36"; + reg = <0x40>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + reset-gpios = <&gpio0 54 GPIO_ACTIVE_HIGH>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-ctl-millivolt = <10000>; + cirrus,boost-peak-milliamp = <4500>; + cirrus,boost-ctl-select = <0>; + cirrus,classh-wk-fet-delay-ms = <100>; + cirrus,classh-weak-fet-thld-millivolt = <100>; + cirrus,temp-warn-threshold = <1>; + cirrus,multi-amp-mode; + cirrus,irq-drive-select = <1>; + cirrus,irq-gpio-select = <1>; + + cirrus,vpbr-config { + cirrus,vpbr-en = <0>; + cirrus,vpbr-thld = <5>; + cirrus,vpbr-atk-rate = <2>; + cirrus,vpbr-atk-vol = <1>; + cirrus,vpbr-max-attn = <9>; + cirrus,vpbr-wait = <1>; + cirrus,vpbr-rel-rate = <5>; + cirrus,vpbr-mute-en = <0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml index 376928d1f64b..c1ef9f308396 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml @@ -27,6 +27,7 @@ properties: enum: - cirrus,cs42l43 - cirrus,cs42l43b + - cirrus,cs42l44 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs42xx8.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs42xx8.yaml index 7ae72bd901f4..a1ae548c4b7b 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs42xx8.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs42xx8.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: dai-common.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: compatible: @@ -21,6 +22,9 @@ properties: reg: maxItems: 1 + spi-max-frequency: + maximum: 6000000 + clocks: minItems: 1 maxItems: 2 @@ -86,3 +90,22 @@ examples: reset-gpios = <&gpio 1>; }; }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio 8 0>; + + codec@0 { + compatible = "cirrus,cs42888"; + reg = <0>; + spi-max-frequency = <6000000>; + clocks = <&codec_mclk 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpios = <&gpio 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/cs35l36.txt b/Documentation/devicetree/bindings/sound/cs35l36.txt deleted file mode 100644 index d34117b8558e..000000000000 --- a/Documentation/devicetree/bindings/sound/cs35l36.txt +++ /dev/null @@ -1,168 +0,0 @@ -CS35L36 Speaker Amplifier - -Required properties: - - - compatible : "cirrus,cs35l36" - - - reg : the I2C address of the device for I2C - - - VA-supply, VP-supply : power supplies for the device, - as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - - - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost - converter's output voltage in mV. The range is from 2550mV to 12000mV with - increments of 50mV. - (Default) VP - - - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. - Configures the peak current by monitoring the current through the boost FET. - Range starts at 1600mA and goes to a maximum of 4500mA with increments of - 50mA. - (Default) 4.50 Amps - - - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value. - Seeds the digital boost converter's inductor estimation block with the initial - inductance value to reference. - - 1000 = 1uH (Default) - 1200 = 1.2uH - -Optional properties: - - cirrus,multi-amp-mode : Boolean to determine if there are more than - one amplifier in the system. If more than one it is best to Hi-Z the ASP - port to prevent bus contention on the output signal - - - cirrus,boost-ctl-select : Boost converter control source selection. - Selects the source of the BST_CTL target VBST voltage for the boost - converter to generate. - 0x00 - Control Port Value - 0x01 - Class H Tracking (Default) - 0x10 - MultiDevice Sync Value - - - cirrus,amp-pcm-inv : Boolean to determine Amplifier will invert incoming - PCM data - - - cirrus,imon-pol-inv : Boolean to determine Amplifier will invert the - polarity of outbound IMON feedback data - - - cirrus,vmon-pol-inv : Boolean to determine Amplifier will invert the - polarity of outbound VMON feedback data - - - cirrus,dcm-mode-enable : Boost converter automatic DCM Mode enable. - This enables the digital boost converter to operate in a low power - (Discontinuous Conduction) mode during low loading conditions. - - - cirrus,weak-fet-disable : Boolean : The strength of the output drivers is - reduced when operating in a Weak-FET Drive Mode and must not be used to drive - a large load. - - - cirrus,classh-wk-fet-delay : Weak-FET entry delay. Controls the delay - (in ms) before the Class H algorithm switches to the weak-FET voltage - (after the audio falls and remains below the value specified in WKFET_AMP_THLD). - - 0 = 0ms - 1 = 5ms - 2 = 10ms - 3 = 50ms - 4 = 100ms (Default) - 5 = 200ms - 6 = 500ms - 7 = 1000ms - - - cirrus,classh-weak-fet-thld-millivolt : Weak-FET amplifier drive threshold. - Configures the signal threshold at which the PWM output stage enters - weak-FET operation. The range is 50mV to 700mV in 50mV increments. - - - cirrus,temp-warn-threshold : Amplifier overtemperature warning threshold. - Configures the threshold at which the overtemperature warning condition occurs. - When the threshold is met, the overtemperature warning attenuation is applied - and the TEMP_WARN_EINT interrupt status bit is set. - If TEMP_WARN_MASK = 0, INTb is asserted. - - 0 = 105C - 1 = 115C - 2 = 125C (Default) - 3 = 135C - - - cirrus,irq-drive-select : Selects the driver type of the selected interrupt - output. - - 0 = Open-drain - 1 = Push-pull (Default) - - - cirrus,irq-gpio-select : Selects the pin to serve as the programmable - interrupt output. - - 0 = PDM_DATA / SWIRE_SD / INT (Default) - 1 = GPIO - -Optional properties for the "cirrus,vpbr-config" Sub-node - - - cirrus,vpbr-en : VBST brownout prevention enable. Configures whether the - VBST brownout prevention algorithm is enabled or disabled. - - 0 = VBST brownout prevention disabled (default) - 1 = VBST brownout prevention enabled - - See Section 7.31.1 VPBR Config for configuration options & further details - - - cirrus,vpbr-thld : Initial VPBR threshold. Configures the VP brownout - threshold voltage - - - cirrus,cirrus,vpbr-atk-rate : Attenuation attack step rate. Configures the - amount delay between consecutive volume attenuation steps when a brownout - condition is present and the VP brownout condition is in an attacking state. - - - cirrus,vpbr-atk-vol : VP brownout prevention step size. Configures the VP - brownout prevention attacking attenuation step size when operating in either - digital volume or analog gain modes. - - - cirrus,vpbr-max-attn : Maximum attenuation that the VP brownout prevention - can apply to the audio signal. - - - cirrus,vpbr-wait : Configures the delay time between a brownout condition - no longer being present and the VP brownout prevention entering an attenuation - release state. - - - cirrus,vpbr-rel-rate : Attenuation release step rate. Configures the delay - between consecutive volume attenuation release steps when a brownout condition - is not longer present and the VP brownout is in an attenuation release state. - - - cirrus,vpbr-mute-en : During the attack state, if the vpbr-max-attn value - is reached, the error condition still remains, and this bit is set, the audio - is muted. - -Example: - -cs35l36: cs35l36@40 { - compatible = "cirrus,cs35l36"; - reg = <0x40>; - VA-supply = <&dummy_vreg>; - VP-supply = <&dummy_vreg>; - reset-gpios = <&gpio0 54 0>; - interrupt-parent = <&gpio8>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - cirrus,boost-ind-nanohenry = <1000>; - cirrus,boost-ctl-millivolt = <10000>; - cirrus,boost-peak-milliamp = <4500>; - cirrus,boost-ctl-select = <0x00>; - cirrus,weak-fet-delay = <0x04>; - cirrus,weak-fet-thld = <0x01>; - cirrus,temp-warn-threshold = <0x01>; - cirrus,multi-amp-mode; - cirrus,irq-drive-select = <0x01>; - cirrus,irq-gpio-select = <0x01>; - - cirrus,vpbr-config { - cirrus,vpbr-en = <0x00>; - cirrus,vpbr-thld = <0x05>; - cirrus,vpbr-atk-rate = <0x02>; - cirrus,vpbr-atk-vol = <0x01>; - cirrus,vpbr-max-attn = <0x09>; - cirrus,vpbr-wait = <0x01>; - cirrus,vpbr-rel-rate = <0x05>; - cirrus,vpbr-mute-en = <0x00>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml index 87559d0d079a..f8a602cee37b 100644 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml +++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml @@ -248,13 +248,13 @@ examples: reg-names = "mpu"; interrupts = <82>, <83>; interrupt-names = "tx", "rx"; - op-mode = <0>; /* MCASP_IIS_MODE */ + op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; ti,async-mode; dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; dma-names = "tx", "rx"; serial-dir = < - 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 0 0 0 0 0 1 2 0 0 0 >; diff --git a/Documentation/devicetree/bindings/sound/dmic-codec.yaml b/Documentation/devicetree/bindings/sound/dmic-codec.yaml index cc3c84dd4c26..83c23e029ea4 100644 --- a/Documentation/devicetree/bindings/sound/dmic-codec.yaml +++ b/Documentation/devicetree/bindings/sound/dmic-codec.yaml @@ -39,6 +39,10 @@ properties: wakeup-delay-ms: description: Delay (in ms) after enabling the DMIC + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible diff --git a/Documentation/devicetree/bindings/sound/eukrea,asoc-tlv320.yaml b/Documentation/devicetree/bindings/sound/eukrea,asoc-tlv320.yaml new file mode 100644 index 000000000000..24b793feb02d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/eukrea,asoc-tlv320.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/eukrea,asoc-tlv320.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio complex for Eukrea boards with tlv320aic23 codec. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: eukrea,asoc-tlv320 + + eukrea,model: + $ref: /schemas/types.yaml#/definitions/string + description: + The user-visible name of this sound complex. + + ssi-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the SSI controller. + + fsl,mux-int-port: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The internal port of the i.MX audio muxer (AUDMUX). + Note: The AUDMUX port numbering should start at 1, which is consistent with + hardware manual. + minimum: 1 + maximum: 8 + + fsl,mux-ext-port: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The external port of the i.MX audio muxer. + Note: The AUDMUX port numbering should start at 1, which is consistent with + hardware manual. + minimum: 1 + maximum: 8 + +required: + - compatible + - eukrea,model + - ssi-controller + - fsl,mux-int-port + - fsl,mux-ext-port + +additionalProperties: false + +examples: + - | + sound { + compatible = "eukrea,asoc-tlv320"; + eukrea,model = "imx51-eukrea-tlv320aic23"; + ssi-controller = <&ssi2>; + fsl,mux-int-port = <2>; + fsl,mux-ext-port = <3>; + }; diff --git a/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt b/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt deleted file mode 100644 index 6dfa88c4dc1e..000000000000 --- a/Documentation/devicetree/bindings/sound/eukrea-tlv320.txt +++ /dev/null @@ -1,26 +0,0 @@ -Audio complex for Eukrea boards with tlv320aic23 codec. - -Required properties: - - - compatible : "eukrea,asoc-tlv320" - - - eukrea,model : The user-visible name of this sound complex. - - - ssi-controller : The phandle of the SSI controller. - - - fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX). - - - fsl,mux-ext-port : The external port of the i.MX audio muxer. - -Note: The AUDMUX port numbering should start at 1, which is consistent with -hardware manual. - -Example: - - sound { - compatible = "eukrea,asoc-tlv320"; - eukrea,model = "imx51-eukrea-tlv320aic23"; - ssi-controller = <&ssi2>; - fsl,mux-int-port = <2>; - fsl,mux-ext-port = <3>; - }; diff --git a/Documentation/devicetree/bindings/sound/everest,es8316.yaml b/Documentation/devicetree/bindings/sound/everest,es8316.yaml index fe5d938ca310..f4ff23120c5b 100644 --- a/Documentation/devicetree/bindings/sound/everest,es8316.yaml +++ b/Documentation/devicetree/bindings/sound/everest,es8316.yaml @@ -30,6 +30,18 @@ description: | allOf: - $ref: dai-common.yaml# + - if: + properties: + compatible: + not: + contains: + const: everest,es8316 + then: + properties: + avdd-supply: false + cpvdd-supply: false + dvdd-supply: false + pvdd-supply: false properties: compatible: @@ -49,6 +61,18 @@ properties: items: - const: mclk + avdd-supply: + description: Regulator providing the analog supply, from 2.0 V to 3.6 V + + cpvdd-supply: + description: Regulator providing the charge pump supply, from 1.6 V to 2.0 V + + dvdd-supply: + description: Regulator providing the digital core supply, from 1.6 V to 3.6 V + + pvdd-supply: + description: Regulator providing the digital I/O supply, from 1.6 V to 3.6 V + interrupts: maxItems: 1 description: Headphone detect interrupt @@ -77,6 +101,10 @@ examples: reg = <0x11>; clocks = <&clks 10>; clock-names = "mclk"; + avdd-supply = <®_3p3v>; + cpvdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; #sound-dai-cells = <0>; }; }; diff --git a/Documentation/devicetree/bindings/sound/everest,es8389.yaml b/Documentation/devicetree/bindings/sound/everest,es8389.yaml index 75ce0bc48904..7db84cf11386 100644 --- a/Documentation/devicetree/bindings/sound/everest,es8389.yaml +++ b/Documentation/devicetree/bindings/sound/everest,es8389.yaml @@ -27,6 +27,10 @@ properties: items: - const: mclk + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + "#sound-dai-cells": const: 0 diff --git a/Documentation/devicetree/bindings/sound/fsl,micfil.yaml b/Documentation/devicetree/bindings/sound/fsl,micfil.yaml index c47b7a097490..4c7dadb310de 100644 --- a/Documentation/devicetree/bindings/sound/fsl,micfil.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,micfil.yaml @@ -66,6 +66,10 @@ properties: "#sound-dai-cells": const: 0 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml b/Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml index 3a32f7517d0c..e3cadb93c183 100644 --- a/Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,rpmsg.yaml @@ -98,6 +98,10 @@ properties: - rpmsg-audio-channel - rpmsg-micfil-channel + hp-det-gpios: + maxItems: 1 + description: The GPIO that detect headphones are plugged in + required: - compatible diff --git a/Documentation/devicetree/bindings/sound/fsl,sai.yaml b/Documentation/devicetree/bindings/sound/fsl,sai.yaml index 83b5ea5f3d70..ba65b3f3d066 100644 --- a/Documentation/devicetree/bindings/sound/fsl,sai.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,sai.yaml @@ -162,6 +162,13 @@ properties: of transmitter. type: boolean + fsl,sai-bit-clock-swap: + description: + Enable Bit Clock Swap, which swaps the bit clock used by the transmitter + or receiver in asynchronous mode, i.e. makes transmitter use RX_BCLK and + TX_SYNC, and vice versa, makes receiver use TX_BCLK and RX_SYNC. + type: boolean + fsl,shared-interrupt: description: Interrupt is shared with other modules. type: boolean diff --git a/Documentation/devicetree/bindings/sound/gpio-audio-amp.yaml b/Documentation/devicetree/bindings/sound/gpio-audio-amp.yaml new file mode 100644 index 000000000000..3690f3d1628c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/gpio-audio-amp.yaml @@ -0,0 +1,270 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/gpio-audio-amp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Audio amplifier driven by GPIOs + +maintainers: + - Herve Codina <herve.codina@bootlin.com> + +description: | + Audio GPIO amplifiers are driven by GPIO in order to control the gain value + of the amplifier, its mute function and/or its bypass function. + + Those amplifiers are based on discrete components (analog switches, op-amps + and more) where some of them, mostly analog switches, are controlled by GPIOs + to adjust the gain value of the whole amplifier and/or to control + the mute and/or bypass function. + + For instance, the following piece of hardware is a GPIO amplifier + + +5VA + ^ + |\ | + | \ + Vin >---------------------------|+ \ + | +-------+-----> Vout + .--\/\/\/--+------------|- / | + | | | / | + v | |/ | | + GND o v | + \ GND | + gpio >-----------> \ | + o o | + | | | + | '--\/\/\/--. | + | +--\/\/\/--' + '---------------' + +properties: + compatible: + oneOf: + - const: gpio-audio-amp-mono + description: + A single channel amplifier. All features apply to this sole channel. + + - const: gpio-audio-amp-stereo + description: + A dual channel amplifier (left and right). All features apply to both + channels producing the same effect on both channels at the same time. + + vdd-supply: + description: Main power supply of the amplifier + + vddio-supply: + description: Power supply related to the control path + + vdda1-supply: + description: Analog power supply + + vdda2-supply: + description: Additional analog power supply + + mute-gpios: + description: GPIO to control the mute function + maxItems: 1 + + bypass-gpios: + description: GPIO to control the bypass function + maxItems: 1 + + gain-gpios: + description: | + GPIOs to control the amplifier gain + + The gain value is computed from GPIOs value from 0 to 2^N-1 with N the + number of GPIO described. The first GPIO described is the lsb of the gain + value. + + For instance assuming 2 gpios + gain-gpios = <&gpio1 GPIO_ACTIVE_HIGH> <&gpio2 GPIO_ACTIVE_HIGH>; + The gain value will be the following: + + gpio1 | gpio2 | gain + ------+-------+----- + 0 | 0 | 0b00 -> 0 + 1 | 0 | 0b01 -> 1 + 0 | 1 | 0b10 -> 2 + 1 | 1 | 0b11 -> 3 + ------+-------+----- + + Note: The gain value, bits set to 1 or 0, indicate the state active (bit + set) or the state inactive (bit unset) of the related GPIO. The + physical voltage corresponding to this active/inactive state is + given by the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags. + + minItems: 1 + maxItems: 16 + + gain-ranges: + $ref: /schemas/types.yaml#/definitions/int32-matrix + description: | + A list of one or more ranges of possible values. Each range is defined by + the first and last point in the range. Each point is defined by the pair + (GPIOs value, Gain in 0.01 dB unit). + + Ranges can be contiguous or holes can be present between ranges if some + gpios value should not be used. Also in a range the first point and the + last point can be identical. In that case, the range contains only one + item, the given point. + + items: + items: + - description: GPIOs value of the first point in the range + - description: Gain in 0.01 dB unit of the first point in the range + - description: GPIOs value of the last point in the range + - description: Gain in 0.01 dB unit of the last point in the range + description: | + A range defines a linear function (linear in dB) from the first point + to the last point, both included. The number of items in the range is + N = abs(first_point.gpio_value - last_point.gpio_value) + 1 + + It allows to define the gain range from the first_point.gain to + the last_point.gain, both points included. + + Gain (0.01 dB unit) + ^ + | last + +- - - - - - - - - - + point + | + . + | + . + | + . + +- - - - + . + | first . . + | point . . + | . . + +--------+-----------+---> gpios + value + + Note: Even if first_point.gpio_value is lower than last_point.gpio_value + and first_point.gain is lower than last_point.gain in the above + graphic, all combination of values are supported leading to an + increasing or a decreasing linear segment. + + minItems: 1 + maxItems: 65536 + + gain-labels: + $ref: /schemas/types.yaml#/definitions/string-array + minItems: 2 + maxItems: 65536 + description: | + List of the gain labels attached to the combination of GPIOs controlling + the gain. The first label is related to the gain value 0, the second label + is related to the gain value 1 and so on. + + With 2 GPIOs controlling the gain, GPIOs value can be 0, 1, 2 and 3. + Assuming that gain value set the hardware according to the following + table: + + GPIOs | Hardware + value | amplification + ------+-------------- + 0 | Low + 1 | Middle + 2 | High + 3 | Max + ------+-------------- + + The description using gain labels can be: + gain-labels = "Low", "Middle", "High", "Max"; + +dependencies: + gain-ranges: [ gain-gpios ] + gain-labels: [ gain-gpios ] + +required: + - compatible + - vdd-supply + +anyOf: + - required: + - gain-gpios + - required: + - mute-gpios + - required: + - bypass-gpios + +allOf: + - $ref: component-common.yaml# + - if: + required: + - gain-ranges + then: + properties: + gain-labels: false + - if: + required: + - gain-labels + then: + properties: + gain-ranges: false + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + /* Gain controlled by gpios */ + amplifier-0 { + compatible = "gpio-audio-amp-mono"; + vdd-supply = <®ulator>; + gain-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>, <&gpio 1 GPIO_ACTIVE_HIGH>; + }; + + /* Gain controlled by gpio using a simple range on a stereo amplifier */ + amplifier-1 { + compatible = "gpio-audio-amp-stereo"; + vdd-supply = <®ulator>; + gain-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>, <&gpio 1 GPIO_ACTIVE_HIGH>; + gain-ranges = <0 (-300) 3 600>; + }; + + /* Gain controlled by gpio with labels */ + amplifier-3 { + compatible = "gpio-audio-amp-mono"; + vdd-supply = <®ulator>; + gain-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + gain-labels = "Low", "High"; + }; + + /* A mutable stereo amplifier without any gain control */ + amplifier-4 { + compatible = "gpio-audio-amp-stereo"; + vdd-supply = <®ulator>; + mute-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + }; + + /* + * Several supplies, gain controlled using more complex ranges, mute and + * bypass. + * + * Assuming 3 gpios for controlling the gain with the following table + * gpios value Gain + * 0b000 Do not use (gpios value not allowed) + * 0b001 - 3dB + * 0b010 + 3dB + * 0b011 + 10dB + * 0b100 Do not use (gpios value not allowed) + * 0b101 + 6dB + * 0b110 + 7dB + * 0b111 + 8dB + */ + amplifier-5 { + compatible = "gpio-audio-amp-mono"; + vdd-supply = <®ulator>; + vddio-supply = <®ulator1>; + vdda1-supply = <®ulator2>; + gain-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>, + <&gpio 1 GPIO_ACTIVE_HIGH>, + <&gpio 2 GPIO_ACTIVE_HIGH>; + gain-ranges = <1 (-300) 2 300>, + <3 1000 3 1000>, + <5 600 7 800>; + mute-gpios = <&gpio 3 GPIO_ACTIVE_HIGH>; + bypass-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; + }; +... diff --git a/Documentation/devicetree/bindings/sound/imx-audio-card.yaml b/Documentation/devicetree/bindings/sound/imx-audio-card.yaml index 5424d4f16f52..950e3eab2942 100644 --- a/Documentation/devicetree/bindings/sound/imx-audio-card.yaml +++ b/Documentation/devicetree/bindings/sound/imx-audio-card.yaml @@ -37,7 +37,13 @@ patternProperties: items: enum: - i2s + - left_j + - right_j + - dsp_a - dsp_b + - pdm + - msb + - lsb dai-tdm-slot-num: true diff --git a/Documentation/devicetree/bindings/sound/loongson,ls-audio-card.yaml b/Documentation/devicetree/bindings/sound/loongson,ls-audio-card.yaml index 61e8babed402..dc7f4afbb777 100644 --- a/Documentation/devicetree/bindings/sound/loongson,ls-audio-card.yaml +++ b/Documentation/devicetree/bindings/sound/loongson,ls-audio-card.yaml @@ -8,19 +8,22 @@ title: Loongson 7axxx/2kxxx ASoC audio sound card driver maintainers: - Yingkun Meng <mengyingkun@loongson.cn> + - Binbin Zhou <zhoubinbin@loongson.cn> description: The binding describes the sound card present in loongson 7axxx/2kxxx platform. The sound card is an ASoC component which uses Loongson I2S controller to transfer the audio data. +allOf: + - $ref: sound-card-common.yaml# + properties: compatible: - const: loongson,ls-audio-card - - model: - $ref: /schemas/types.yaml#/definitions/string - description: User specified audio sound card name + enum: + - loongson,ls-audio-card # Loongson-2K1000/Loongson-2K2000/LS7A + - loongson,ls2k0300-forever-pi-audio-card # CTCISZ Forever Pi + - loongson,ls2k0300-dl2k0300b-audio-card # ATK-DL2K0300B mclk-fs: $ref: simple-card.yaml#/definitions/mclk-fs @@ -45,14 +48,25 @@ properties: required: - sound-dai + spkr-en-gpios: + maxItems: 1 + description: The GPIO that enables the speakers + + hp-ctl-gpios: + maxItems: 1 + description: The GPIO that control the headphones + + hp-det-gpios: + maxItems: 1 + description: The GPIO that detect headphones are plugged in + required: - compatible - - model - mclk-fs - cpu - codec -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -68,3 +82,28 @@ examples: sound-dai = <&es8323>; }; }; + + - | + #include <dt-bindings/gpio/gpio.h> + + sound { + compatible = "loongson,ls2k0300-dl2k0300b-audio-card"; + model = "loongson-audio"; + mclk-fs = <512>; + hp-det-gpios = <&gpio 81 GPIO_ACTIVE_HIGH>; + spkr-en-gpios = <&gpio 86 GPIO_ACTIVE_HIGH>; + hp-ctl-gpios = <&gpio 87 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2"; + + cpu { + sound-dai = <&i2s>; + }; + + codec { + sound-dai = <&es8388>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/loongson,ls2k1000-i2s.yaml b/Documentation/devicetree/bindings/sound/loongson,ls2k1000-i2s.yaml index da79510bb2d9..51e23c189f7a 100644 --- a/Documentation/devicetree/bindings/sound/loongson,ls2k1000-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/loongson,ls2k1000-i2s.yaml @@ -14,9 +14,12 @@ allOf: properties: compatible: - const: loongson,ls2k1000-i2s + enum: + - loongson,ls2k0300-i2s + - loongson,ls2k1000-i2s reg: + minItems: 1 items: - description: Loongson I2S controller Registers. - description: APB DMA config register for Loongson I2S controller. @@ -49,6 +52,23 @@ required: unevaluatedProperties: false +if: + properties: + compatible: + contains: + enum: + - loongson,ls2k1000-i2s + +then: + properties: + reg: + minItems: 2 + +else: + properties: + reg: + maxItems: 1 + examples: - | #include <dt-bindings/clock/loongson,ls2k-clk.h> diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml index 45382c4d86aa..30f331366566 100644 --- a/Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml +++ b/Documentation/devicetree/bindings/sound/mediatek,mt2701-audio.yaml @@ -32,6 +32,7 @@ properties: maxItems: 1 clocks: + minItems: 34 items: - description: audio infra sys clock - description: top audio mux 1 @@ -67,8 +68,13 @@ properties: - description: top audio a1 sys pd - description: top audio a2 sys pd - description: audio merge interface pd + - description: HADDS2 PLL 294 MHz (HDMI audio path root) + - description: HDMI audio interface pd + - description: S/PDIF interface pd + - description: audio APLL root pd clock-names: + minItems: 34 items: - const: infra_sys_audio_clk - const: top_audio_mux1_sel @@ -104,6 +110,10 @@ properties: - const: audio_a1sys_pd - const: audio_a2sys_pd - const: audio_mrgif_pd + - const: hadds2pll_294m + - const: audio_hdmi_pd + - const: audio_spdf_pd + - const: audio_apll_pd required: - compatible @@ -113,4 +123,17 @@ required: - clocks - clock-names +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7622-audio + then: + properties: + clocks: + maxItems: 34 + clock-names: + maxItems: 34 + additionalProperties: false diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt2701-hdmi-audio.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt2701-hdmi-audio.yaml new file mode 100644 index 000000000000..9d5a8166e51f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt2701-hdmi-audio.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt2701-hdmi-audio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT2701/MT7623N HDMI audio output + +maintainers: + - Daniel Golle <daniel@makrotopia.org> + +description: + Sound card routing the MT2701/MT7623N Audio Front End HDMI + playback path to the on-chip HDMI transmitter. The AFE + provides the DMA memif and internal I2S engine; the HDMI + transmitter acts as the audio codec on the serialised link. + +properties: + compatible: + oneOf: + - const: mediatek,mt2701-hdmi-audio + - items: + - const: mediatek,mt7623n-hdmi-audio + - const: mediatek,mt2701-hdmi-audio + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle of the MT2701/MT7623N AFE platform node. + + mediatek,audio-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle of the HDMI transmitter acting as audio codec. + +required: + - compatible + - mediatek,platform + - mediatek,audio-codec + +additionalProperties: false + +examples: + - | + sound-hdmi { + compatible = "mediatek,mt7623n-hdmi-audio", + "mediatek,mt2701-hdmi-audio"; + mediatek,platform = <&afe>; + mediatek,audio-codec = <&hdmi0>; + }; diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt6351-sound.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt6351-sound.yaml new file mode 100644 index 000000000000..b422e238b512 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt6351-sound.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt6351-sound.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6351 Audio CODEC + +maintainers: + - KaiChieh Chuang <kaichieh.chuang@mediatek.com> + +description: + MT6351 Audio CODEC is a part of the MediaTek MT6351 PMIC. + It communicates with the SoC through the MediaTek PMIC wrapper(pwrap). + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: mediatek,mt6351-sound + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - "#sound-dai-cells" + +unevaluatedProperties: false + +examples: + - | + sound { + compatible = "mediatek,mt6351-sound"; + #sound-dai-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650-rt5514.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650-rt5514.yaml index ed698c9ff42b..becc7a11f8dc 100644 --- a/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650-rt5514.yaml +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650-rt5514.yaml @@ -18,7 +18,9 @@ properties: description: Phandles of rt5650 and rt5514 codecs items: - description: phandle of rt5650 codec + maxItems: 1 - description: phandle of rt5514 codec + maxItems: 1 mediatek,platform: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml new file mode 100644 index 000000000000..949f8622baf9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Audio Front End PCM controller for MT8196 + +maintainers: + - Darren Ye <darren.ye@mediatek.com> + +properties: + compatible: + const: mediatek,mt8196-afe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: mux for audio intbus + - description: mux for audio engen1 + - description: mux for audio engen2 + - description: mux for audio h + - description: audio apll1 clock + - description: audio apll2 clock + - description: audio apll12 divide for i2sin0 + - description: audio apll12 divide for i2sin1 + - description: audio apll12 divide for fmi2s + - description: audio apll12 divide for tdmout mck + - description: audio apll12 divide for tdmout bck + - description: mux for adsp clock + + clock-names: + items: + - const: top_aud_intbus + - const: top_aud_eng1 + - const: top_aud_eng2 + - const: top_aud_h + - const: apll1 + - const: apll2 + - const: apll12_div_i2sin0 + - const: apll12_div_i2sin1 + - const: apll12_div_fmi2s + - const: apll12_div_tdmout_m + - const: apll12_div_tdmout_b + - const: top_adsp + +required: + - compatible + - reg + - interrupts + - memory-region + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + afe@1a110000 { + compatible = "mediatek,mt8196-afe"; + reg = <0 0x1a110000 0 0x9000>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>; + memory-region = <&afe_dma_mem_reserved>; + power-domains = <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO + pinctrl-names = "default"; + pinctrl-0 = <&aud_pins_default>; + clocks = <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL + <&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL + <&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL + <&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL + <&vlp_cksys_clk 0>, //CLK_VLP_CK_VLP_APLL1 + <&vlp_cksys_clk 1>, //CLK_VLP_CK_VLP_APLL2 + <&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0 + <&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1 + <&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S + <&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M + <&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B + <&cksys_clk 45>; //CLK_CK_ADSP_SEL + clock-names = "top_aud_intbus", + "top_aud_eng1", + "top_aud_eng2", + "top_aud_h", + "apll1", + "apll2", + "apll12_div_i2sin0", + "apll12_div_i2sin1", + "apll12_div_fmi2s", + "apll12_div_tdmout_m", + "apll12_div_tdmout_b", + "top_adsp"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-nau8825.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-nau8825.yaml new file mode 100644 index 000000000000..83350faa1e29 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-nau8825.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8196-nau8825.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8196 ASoC sound card + +maintainers: + - Darren Ye <darren.ye@mediatek.com> + +allOf: + - $ref: sound-card-common.yaml# + +properties: + compatible: + enum: + - mediatek,mt8196-nau8825-sound + - mediatek,mt8196-rt5682s-sound + - mediatek,mt8196-rt5650-sound + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of MT8188 ASoC platform. + +patternProperties: + "^dai-link-[0-9]+$": + type: object + description: + Container for dai-link level properties and CODEC sub-nodes. + + properties: + link-name: + description: + This property corresponds to the name of the BE dai-link to which + we are going to update parameters in this node. + items: + enum: + - TDM_DPTX_BE + - I2SOUT6_BE + - I2SIN6_BE + - I2SOUT4_BE + - I2SOUT3_BE + + codec: + description: Holds subnode which indicates codec dai. + type: object + additionalProperties: false + properties: + sound-dai: + minItems: 1 + maxItems: 2 + required: + - sound-dai + + dai-format: + description: audio format. + items: + enum: + - i2s + - right_j + - left_j + - dsp_a + - dsp_b + + mediatek,clk-provider: + $ref: /schemas/types.yaml#/definitions/string + description: Indicates dai-link clock master. + enum: + - cpu + - codec + + additionalProperties: false + + required: + - link-name + +required: + - compatible + - mediatek,platform + +unevaluatedProperties: false + +examples: + - | + sound { + compatible = "mediatek,mt8196-nau8825-sound"; + model = "mt8196-nau8825"; + mediatek,platform = <&afe>; + dai-link-0 { + link-name = "I2SOUT6_BE"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&nau8825>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mediatek,mtk-btcvsd-snd.yaml b/Documentation/devicetree/bindings/sound/mediatek,mtk-btcvsd-snd.yaml new file mode 100644 index 000000000000..1b7451655476 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mtk-btcvsd-snd.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mtk-btcvsd-snd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek ALSA BT SCO CVSD/MSBC + +maintainers: + - Luca Leonardo Scorcia <l.scorcia@gmail.com> + +properties: + compatible: + const: mediatek,mtk-btcvsd-snd + + reg: + items: + - description: PKV region + - description: SRAM_BANK2 region + + interrupts: + items: + - description: BT-SCO interrupt + + mediatek,infracfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the infracfg controller + + mediatek,offset: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Array of register offsets and masks + items: + - description: infra_misc_offset + - description: infra_conn_bt_cvsd_mask + - description: cvsd_mcu_read_offset + - description: cvsd_mcu_write_offset + - description: cvsd_packet_indicator_offset + +required: + - compatible + - reg + - interrupts + - mediatek,infracfg + - mediatek,offset + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mtk-btcvsd-snd@18000000 { + compatible = "mediatek,mtk-btcvsd-snd"; + reg = <0x18000000 0x1000>, + <0x18080000 0x8000>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; + mediatek,infracfg = <&infrasys>; + mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; + }; diff --git a/Documentation/devicetree/bindings/sound/mt6351.txt b/Documentation/devicetree/bindings/sound/mt6351.txt deleted file mode 100644 index 7fb2cb99245e..000000000000 --- a/Documentation/devicetree/bindings/sound/mt6351.txt +++ /dev/null @@ -1,16 +0,0 @@ -Mediatek MT6351 Audio Codec - -The communication between MT6351 and SoC is through Mediatek PMIC wrapper. -For more detail, please visit Mediatek PMIC wrapper documentation. - -Must be a child node of PMIC wrapper. - -Required properties: - -- compatible : "mediatek,mt6351-sound". - -Example: - -mt6351_snd { - compatible = "mediatek,mt6351-sound"; -}; diff --git a/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt b/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt deleted file mode 100644 index 679e44839b48..000000000000 --- a/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt +++ /dev/null @@ -1,24 +0,0 @@ -Mediatek ALSA BT SCO CVSD/MSBC Driver - -Required properties: -- compatible = "mediatek,mtk-btcvsd-snd"; -- reg: register location and size of PKV and SRAM_BANK2 -- interrupts: should contain BTSCO interrupt -- mediatek,infracfg: the phandles of INFRASYS -- mediatek,offset: Array contains of register offset and mask - infra_misc_offset, - infra_conn_bt_cvsd_mask, - cvsd_mcu_read_offset, - cvsd_mcu_write_offset, - cvsd_packet_indicator_offset - -Example: - - mtk-btcvsd-snd@18000000 { - compatible = "mediatek,mtk-btcvsd-snd"; - reg=<0 0x18000000 0 0x1000>, - <0 0x18080000 0 0x8000>; - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; - mediatek,infracfg = <&infrasys>; - mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; - }; diff --git a/Documentation/devicetree/bindings/sound/neofidelity,ntp8918.yaml b/Documentation/devicetree/bindings/sound/neofidelity,ntp8918.yaml index 6946177e391a..99b739595ebf 100644 --- a/Documentation/devicetree/bindings/sound/neofidelity,ntp8918.yaml +++ b/Documentation/devicetree/bindings/sound/neofidelity,ntp8918.yaml @@ -66,7 +66,7 @@ examples: #sound-dai-cells = <0>; reg = <0x2a>; clocks = <&clkc 150>, <&clkc 151>, <&clkc 152>; - clock-names = "wck", "scl", "bck"; + clock-names = "wck", "scl", "bck"; reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; }; }; diff --git a/Documentation/devicetree/bindings/sound/nuvoton,nau8822.yaml b/Documentation/devicetree/bindings/sound/nuvoton,nau8822.yaml index cb8182bbc491..cf4c13038241 100644 --- a/Documentation/devicetree/bindings/sound/nuvoton,nau8822.yaml +++ b/Documentation/devicetree/bindings/sound/nuvoton,nau8822.yaml @@ -30,6 +30,20 @@ properties: clock-names: const: mclk + vdda-supply: + description: Analog power supply + + vddb-supply: + description: Digital buffer (input/output) supply + + vddc-supply: + description: Digital core supply + + vddspk-supply: + description: + Speaker supply (power supply pin for RSPKOUT, LSPKOUT, AUXOUT2 and + AUXTOUT1 output drivers) + nuvoton,spk-btl: description: If set, configure the two loudspeaker outputs as a Bridge Tied Load output @@ -54,5 +68,9 @@ examples: codec@1a { compatible = "nuvoton,nau8822"; reg = <0x1a>; + vdda-supply = <&vcca_3v3_s0>; + vddb-supply = <&vcca_3v3_s0>; + vddc-supply = <&vcca_3v3_s0>; + vddspk-supply = <&vcca_3v3_s0>; }; }; diff --git a/Documentation/devicetree/bindings/sound/omap-dmic.txt b/Documentation/devicetree/bindings/sound/omap-dmic.txt deleted file mode 100644 index 418e30e72e89..000000000000 --- a/Documentation/devicetree/bindings/sound/omap-dmic.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Texas Instruments OMAP4+ Digital Microphone Module - -Required properties: -- compatible: "ti,omap4-dmic" -- reg: Register location and size as an array: - <MPU access base address, size>, - <L3 interconnect address, size>; -- interrupts: Interrupt number for DMIC -- ti,hwmods: Name of the hwmod associated with OMAP dmic IP - -Example: - -dmic: dmic@4012e000 { - compatible = "ti,omap4-dmic"; - reg = <0x4012e000 0x7f>, /* MPU private access */ - <0x4902e000 0x7f>; /* L3 Interconnect */ - interrupts = <0 114 0x4>; - interrupt-parent = <&gic>; - ti,hwmods = "dmic"; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml index 2eed2277511f..4988e7ed6e34 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc8280xp-lpass-rx-macro - items: - enum: + - qcom,eliza-lpass-rx-macro - qcom,kaanapali-lpass-rx-macro - qcom,sm8650-lpass-rx-macro - qcom,sm8750-lpass-rx-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml index e5e65e226a02..d8682ff2e82c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc8280xp-lpass-tx-macro - items: - enum: + - qcom,eliza-lpass-tx-macro - qcom,kaanapali-lpass-tx-macro - qcom,sm8650-lpass-tx-macro - qcom,sm8750-lpass-tx-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index 5c42b2b323ee..aea31fbdad37 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc8280xp-lpass-va-macro - items: - enum: + - qcom,eliza-lpass-va-macro - qcom,glymur-lpass-va-macro - qcom,kaanapali-lpass-va-macro - qcom,sm8650-lpass-va-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml index d5f22b5cf021..9fedd80532e2 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc8280xp-lpass-wsa-macro - items: - enum: + - qcom,eliza-lpass-wsa-macro - qcom,glymur-lpass-wsa-macro - qcom,kaanapali-lpass-wsa-macro - qcom,sm8650-lpass-wsa-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital-codec.yaml b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital-codec.yaml index a899c4e7c1c9..33bc23b6176a 100644 --- a/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital-codec.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,msm8916-wcd-digital-codec.yaml @@ -14,7 +14,13 @@ description: properties: compatible: - const: qcom,msm8916-wcd-digital-codec + oneOf: + - items: + - enum: + - qcom,sdm660-wcd-digital-codec + - const: qcom,msm8916-wcd-digital-codec + + - const: qcom,msm8916-wcd-digital-codec reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/qcom,pm8916-wcd-analog-codec.yaml b/Documentation/devicetree/bindings/sound/qcom,pm8916-wcd-analog-codec.yaml index 94e7a1860977..be47dbdb2e92 100644 --- a/Documentation/devicetree/bindings/sound/qcom,pm8916-wcd-analog-codec.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,pm8916-wcd-analog-codec.yaml @@ -14,7 +14,16 @@ description: properties: compatible: - const: qcom,pm8916-wcd-analog-codec + oneOf: + - items: + - enum: + - qcom,pm660l-wcd-analog-codec + - const: qcom,pm8953-wcd-analog-codec + + - enum: + - qcom,pm8916-wcd-analog-codec + - qcom,pm8950-wcd-analog-codec + - qcom,pm8953-wcd-analog-codec reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml b/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml index 2fb95544db8b..4878c424ef03 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6apm-lpass-dais.yaml @@ -21,6 +21,43 @@ properties: '#sound-dai-cells': const: 1 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +# Digital Audio Interfaces +patternProperties: + '^dai@[0-9a-f]+$': + type: object + description: + Q6DSP Digital Audio Interfaces. + + properties: + reg: + maxItems: 1 + description: + Digital Audio Interface ID + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - enum: [bclk, mclk] + - const: mclk + + dependencies: + clocks: [clock-names] + + required: + - reg + + additionalProperties: false + required: - compatible - '#sound-dai-cells' @@ -29,7 +66,20 @@ unevaluatedProperties: false examples: - | + #include <dt-bindings/sound/qcom,q6afe.h> + dais { compatible = "qcom,q6apm-lpass-dais"; #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dai@10 { + reg = <PRIMARY_MI2S_RX>; + clocks = <&q6prmcc LPASS_CLK_ID_PRI_MI2S_IBIT + LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_MCLK_1 + LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "bclk", "mclk"; + }; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6asm-dais.yaml b/Documentation/devicetree/bindings/sound/qcom,q6asm-dais.yaml index 47a105a97ecf..bc8c8ba24f9c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6asm-dais.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6asm-dais.yaml @@ -45,7 +45,7 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2] description: | - The direction of the dai stream:: + The direction of the dai stream: - Q6ASM_DAI_TX_RX (0) for both tx and rx - Q6ASM_DAI_TX (1) for only tx (Capture/Encode) - Q6ASM_DAI_RX (2) for only rx (Playback/Decode) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml index 2b27d6c8f58f..3b03e2acd67e 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -127,7 +127,7 @@ patternProperties: contains: # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and # QUINARY_MI2S_RX - QUINARY_MI2S_TX and - # LPI_MI2S_RX_0 - SENARY_MI2S_TX + # LPI_MI2S_RX_0 - LPI_MI2S_TX_6 items: oneOf: - minimum: 16 @@ -135,7 +135,7 @@ patternProperties: - minimum: 127 maximum: 128 - minimum: 137 - maximum: 148 + maximum: 152 then: required: - qcom,sd-lines diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index 15f38622b98b..1536fcd96d68 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -23,12 +23,17 @@ properties: - const: qcom,sdm845-sndcard - items: - enum: + - qcom,eliza-sndcard + - qcom,hawi-sndcard - qcom,kaanapali-sndcard + - qcom,maili-sndcard + - qcom,sm8475-sndcard - qcom,sm8550-sndcard - qcom,sm8650-sndcard - qcom,sm8750-sndcard - const: qcom,sm8450-sndcard - enum: + - ayaneo,pocket-s2-sndcard - fairphone,fp4-sndcard - fairphone,fp5-sndcard - qcom,apq8096-sndcard @@ -44,6 +49,7 @@ properties: - qcom,qrb5165-rb5-sndcard - qcom,sc7180-qdsp6-sndcard - qcom,sc8280xp-sndcard + - qcom,sdm660-sndcard - qcom,sdm845-sndcard - qcom,sm8250-sndcard - qcom,sm8450-sndcard @@ -90,6 +96,19 @@ patternProperties: sound-dai: maxItems: 1 + dai-tdm-slot-num: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of slots in use + + dai-tdm-slot-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Width, in bits, of each slot + + patternProperties: + '^dai-tdm-slot-[rt]x-mask$': + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Slot mask for active TDM slots + platform: description: Holds subnode which indicates platform dai. type: object @@ -109,6 +128,19 @@ patternProperties: minItems: 1 maxItems: 8 + dai-tdm-slot-num: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of slots in use + + dai-tdm-slot-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Width, in bits, of each slot + + patternProperties: + '^dai-tdm-slot-[rt]x-mask$': + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Slot mask for active TDM slots + required: - link-name - cpu diff --git a/Documentation/devicetree/bindings/sound/qcom,wsa8855.yaml b/Documentation/devicetree/bindings/sound/qcom,wsa8855.yaml new file mode 100644 index 000000000000..00a6a05e9443 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,wsa8855.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,wsa8855.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm WSA8855 stereo smart speaker amplifier + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com> + - Prasad Kumpatla <prasad.kumpatla@oss.qualcomm.com> + +description: + WSA885X is a Qualcomm Aqstic stereo smart speaker amplifier. It uses a PCM + audio interface, an I2C control interface, and a Class-H amplifier path for + high efficiency, low output noise, and low idle power consumption. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: qcom,wsa8855 + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + powerdown-gpios: + description: GPIO controlling the SD_N powerdown pin. + maxItems: 1 + + reset-gpios: + description: GPIO controlling the SD_N powerdown pin. + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-1p8-supply: true + + vdd-io-supply: true + + qcom,battery-config: + description: + Battery topology connected to the speaker amplifier. 1S indicates one + battery cell in series, while 2S indicates two battery cells in series. + $ref: /schemas/types.yaml#/definitions/string + default: 1s + enum: + - 1s + - 2s + +required: + - compatible + - reg + - '#sound-dai-cells' + - interrupts + - vdd-1p8-supply + - vdd-io-supply + +oneOf: + - required: + - powerdown-gpios + - required: + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + speaker@c { + compatible = "qcom,wsa8855"; + reg = <0x0c>; + #sound-dai-cells = <0>; + powerdown-gpios = <&tlmm 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&tlmm>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING>; + vdd-1p8-supply = <&vreg_l2g_1p8>; + vdd-io-supply = <&vreg_l1g_1p2>; + qcom,battery-config = "1s"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/sound/realtek,rt1015.yaml b/Documentation/devicetree/bindings/sound/realtek,rt1015.yaml index 880196081a60..3c44ebf93a44 100644 --- a/Documentation/devicetree/bindings/sound/realtek,rt1015.yaml +++ b/Documentation/devicetree/bindings/sound/realtek,rt1015.yaml @@ -19,7 +19,7 @@ properties: realtek,power-up-delay-ms: description: Set a delay time for flush work to be completed, - this vlaue is adjustable depending on platform. + this value is adjustable depending on platform. maxItems: 1 required: diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5640.yaml b/Documentation/devicetree/bindings/sound/realtek,rt5640.yaml index 2eb631950963..922fe161f4d7 100644 --- a/Documentation/devicetree/bindings/sound/realtek,rt5640.yaml +++ b/Documentation/devicetree/bindings/sound/realtek,rt5640.yaml @@ -135,7 +135,6 @@ properties: required: - compatible - reg - - interrupts unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5677.yaml b/Documentation/devicetree/bindings/sound/realtek,rt5677.yaml index 9ce23e58e5ea..ae27ae78b1b2 100644 --- a/Documentation/devicetree/bindings/sound/realtek,rt5677.yaml +++ b/Documentation/devicetree/bindings/sound/realtek,rt5677.yaml @@ -58,7 +58,7 @@ properties: 0 - floating (reset value) 1 - pull down 2 - pull up - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint8-array minItems: 6 maxItems: 6 items: @@ -130,6 +130,6 @@ examples: realtek,pow-ldo2-gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; realtek,reset-gpio = <&gpio 3 GPIO_ACTIVE_LOW>; realtek,in1-differential; - realtek,gpio-config = <0 0 0 0 0 2>; + realtek,gpio-config = /bits/ 8 <0 0 0 0 0 2>; }; }; diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml index df91991699a7..803945b7f82f 100644 --- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml +++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml @@ -9,9 +9,6 @@ title: Renesas FIFO-buffered Serial Interface (FSI) maintainers: - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> -allOf: - - $ref: dai-common.yaml# - properties: $nodename: pattern: "^sound@.*" @@ -38,7 +35,32 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + items: + - description: Main FSI module clock + - description: | + SPU bus/bridge clock. On R8A7740, this clock must be enabled to allow + register access as the FSI block is connected behind the SPU bus. + - description: CPG DIV6 functional clocks for FSI port A + - description: CPG DIV6 functional clocks for FSI port B + - description: FSI dividers for port A used for audio clock generation + - description: FSI dividers for port B used for audio clock generation + - description: External clock inputs for FSI port A provided by the board + - description: External clock inputs for FSI port B provided by the board + + clock-names: + minItems: 1 + maxItems: 8 + items: + enum: + - fck # Main FSI module clock + - spu # optional SPU bus/bridge clock + - icka # optional CPG DIV6 functional clocks for FSI port A + - ickb # optional CPG DIV6 functional clocks for FSI port B + - diva # optional FSI dividers for port A used for audio clock generation + - divb # optional FSI dividers for port B used for audio clock generation + - xcka # optional External clock inputs for FSI port A provided by the board + - xckb # optional External clock inputs for FSI port B provided by the board power-domains: maxItems: 1 @@ -69,6 +91,30 @@ required: unevaluatedProperties: false +allOf: + - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + const: renesas,fsi2-r8a7740 + then: + required: + - clock-names + + properties: + clock-names: + minItems: 2 + items: + - const: fck + - const: spu + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + - enum: [icka, ickb, diva, divb, xcka, xckb] + examples: - | #include <dt-bindings/clock/r8a7740-clock.h> @@ -77,7 +123,11 @@ examples: compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupts = <GIC_SPI 9 0x4>; - clocks = <&mstp3_clks R8A7740_CLK_FSI>; + clocks = <&mstp3_clks R8A7740_CLK_FSI>, <&spu_clk>, + <&fsia_clk>, <&fsiack_clk>, <&fsidiva_clk>, + <&fsib_clk>, <&fsibck_clk>, <&fsidivb_clk>; + clock-names = "fck", "spu", "icka", "xcka", "diva", + "ickb", "xckb", "divb"; power-domains = <&pd_a4mp>; #sound-dai-cells = <1>; diff --git a/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml b/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml new file mode 100644 index 000000000000..213c1c40b6f0 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/renesas,r9a09g047-sound.yaml @@ -0,0 +1,800 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/renesas,r9a09g047-sound.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E Sound Controller + +maintainers: + - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + - John Madieu <john.madieu.xa@bp.renesas.com> + +description: + The RZ/G3E (R9A09G047) sound controller is based on R-Car Sound IP + with extended DMA channel support (up to 5 DMACs per direction), + additional clock domains (47 clocks including per-SSI ADG clocks), + and additional reset lines (14 including SCU, ADG and Audio DMAC + peri-peri resets). SSI operates exclusively in BUSIF mode with + 2-4 BUSIF channels per SSI. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: renesas,r9a09g047-sound + + reg: + maxItems: 5 + + reg-names: + items: + - const: scu + - const: adg + - const: ssiu + - const: ssi + - const: audmapp + + "#sound-dai-cells": + const: 1 + + "#clock-cells": + const: 0 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + maxItems: 47 + + clock-names: + items: + - const: ssi-all + - const: ssi-0 + - const: ssi-1 + - const: ssi-2 + - const: ssi-3 + - const: ssi-4 + - const: ssi-5 + - const: ssi-6 + - const: ssi-7 + - const: ssi-8 + - const: ssi-9 + - const: src-0 + - const: src-1 + - const: src-2 + - const: src-3 + - const: src-4 + - const: src-5 + - const: src-6 + - const: src-7 + - const: src-8 + - const: src-9 + - const: mix-0 + - const: mix-1 + - const: ctu-0 + - const: ctu-1 + - const: dvc-0 + - const: dvc-1 + - const: audio-clka + - const: audio-clkb + - const: audio-clkc + - const: audio-clki + - const: ssif_supply + - const: scu + - const: scu_x2 + - const: scu_supply + - const: adg-ssi-0 + - const: adg-ssi-1 + - const: adg-ssi-2 + - const: adg-ssi-3 + - const: adg-ssi-4 + - const: adg-ssi-5 + - const: adg-ssi-6 + - const: adg-ssi-7 + - const: adg-ssi-8 + - const: adg-ssi-9 + - const: audmapp + - const: adg + + power-domains: + maxItems: 1 + + resets: + maxItems: 14 + + reset-names: + items: + - const: ssi-all + - const: ssi-0 + - const: ssi-1 + - const: ssi-2 + - const: ssi-3 + - const: ssi-4 + - const: ssi-5 + - const: ssi-6 + - const: ssi-7 + - const: ssi-8 + - const: ssi-9 + - const: scu + - const: adg + - const: audmapp + + dvc: + type: object + additionalProperties: false + + patternProperties: + "^dvc-[0-1]$": + type: object + additionalProperties: false + + properties: + dmas: + maxItems: 5 + description: + List of references to DMA specifiers, one per DMA + controller, all for the transmission direction + (DVC is playback-only). The dma-engine core falls + through the list to find a free channel. + + dma-names: + maxItems: 5 + allOf: + - items: + enum: + - tx + + required: + - dmas + - dma-names + + mix: + type: object + additionalProperties: false + description: + Per-channel Mixer (MIX) sub-nodes. Each mix-N node has no + properties of its own. It exists so the driver can enumerate + the MIX instances and so that DT labels can be attached to it + for the dai/playback/capture phandle routing arrays. + + patternProperties: + "^mix-[0-1]$": + type: object + additionalProperties: false + + ctu: + type: object + additionalProperties: false + description: + Per-channel Channel Transfer Unit (CTU) sub-nodes. Each ctu-N + node has no properties of its own. It exists so the driver + can enumerate the CTU instances and so that DT labels can be + attached to it for the dai/playback/capture phandle routing arrays. + + patternProperties: + "^ctu-[0-7]$": + type: object + additionalProperties: false + + src: + type: object + additionalProperties: false + + patternProperties: + "^src-[0-9]$": + type: object + additionalProperties: false + + properties: + interrupts: + maxItems: 1 + + dmas: + maxItems: 10 + description: + Must contain a list of pairs of references to DMA + specifiers, one for transmission and one for reception, + repeated for each DMA controller. The dma-engine core + falls through the list to find a free channel. + + dma-names: + maxItems: 10 + allOf: + - items: + enum: + - tx + - rx + + ssiu: + type: object + additionalProperties: false + + patternProperties: + "^ssiu-[0-9]+$": + type: object + additionalProperties: false + + properties: + dmas: + maxItems: 10 + description: + Must contain a list of pairs of references to DMA + specifiers, one for transmission and one for reception, + repeated for each DMA controller. The dma-engine core + falls through the list to find a free channel. + + dma-names: + maxItems: 10 + allOf: + - items: + enum: + - tx + - rx + + required: + - dmas + - dma-names + + ssi: + type: object + additionalProperties: false + + patternProperties: + "^ssi-[0-9]$": + type: object + additionalProperties: false + + properties: + interrupts: + maxItems: 1 + + shared-pin: + description: Shared clock pin. + $ref: /schemas/types.yaml#/definitions/flag + + required: + - interrupts + + ports: + $ref: audio-graph-port.yaml#/definitions/port-base + unevaluatedProperties: false + patternProperties: + '^port@[0-9a-f]+$': + $ref: audio-graph-port.yaml#/definitions/port-base + unevaluatedProperties: false + properties: + reg: + maxItems: 1 + endpoint: + $ref: audio-graph-port.yaml#/definitions/endpoint-base + unevaluatedProperties: false + properties: + playback: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Ordered list of phandles to the in-SoC modules used + by this DAI in the playback direction. Each phandle + must reference one of the ssi-N, src-N, ctu-N, + mix-N or dvc-N sub-nodes of the parent sound + controller. The list order is the pipeline order + from CPU to off-SoC endpoint. + capture: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Ordered list of phandles to the in-SoC modules used + by this DAI in the capture direction. Each phandle + must reference one of the ssi-N, src-N, ctu-N, + mix-N or dvc-N sub-nodes of the parent sound + controller. The list order is the pipeline order + from off-SoC endpoint to CPU. + +required: + - compatible + - reg + - reg-names + - "#sound-dai-cells" + - "#clock-cells" + - clocks + - clock-names + - resets + - reset-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + sound@13c00000 { + #sound-dai-cells = <1>; + #clock-cells = <0>; + compatible = "renesas,r9a09g047-sound"; + reg = <0x13c00000 0x10000>, + <0x13c20000 0x10000>, + <0x13c30000 0x1000>, + <0x13c31000 0x1f000>, + <0x13c50000 0x10000>; + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + clocks = <&cpg 245>, + <&cpg 385>, <&cpg 386>, + <&cpg 387>, <&cpg 388>, + <&cpg 389>, <&cpg 390>, + <&cpg 391>, <&cpg 392>, + <&cpg 393>, <&cpg 394>, + <&cpg 372>, <&cpg 373>, + <&cpg 374>, <&cpg 375>, + <&cpg 376>, <&cpg 377>, + <&cpg 378>, <&cpg 379>, + <&cpg 380>, <&cpg 381>, + <&cpg 370>, <&cpg 371>, + <&cpg 370>, <&cpg 371>, + <&cpg 368>, <&cpg 369>, + <&cpg 251>, <&cpg 252>, + <&cpg 253>, <&cpg 250>, + <&cpg 384>, + <&cpg 246>, <&cpg 247>, + <&cpg 382>, + <&cpg 352>, <&cpg 353>, + <&cpg 354>, <&cpg 355>, + <&cpg 356>, <&cpg 357>, + <&cpg 358>, <&cpg 359>, + <&cpg 360>, <&cpg 361>, + <&cpg 248>, <&cpg 249>; + clock-names = "ssi-all", + "ssi-0", "ssi-1", + "ssi-2", "ssi-3", + "ssi-4", "ssi-5", + "ssi-6", "ssi-7", + "ssi-8", "ssi-9", + "src-0", "src-1", + "src-2", "src-3", + "src-4", "src-5", + "src-6", "src-7", + "src-8", "src-9", + "mix-0", "mix-1", + "ctu-0", "ctu-1", + "dvc-0", "dvc-1", + "audio-clka", "audio-clkb", + "audio-clkc", "audio-clki", + "ssif_supply", + "scu", "scu_x2", + "scu_supply", + "adg-ssi-0", "adg-ssi-1", + "adg-ssi-2", "adg-ssi-3", + "adg-ssi-4", "adg-ssi-5", + "adg-ssi-6", "adg-ssi-7", + "adg-ssi-8", "adg-ssi-9", + "audmapp", "adg"; + power-domains = <&cpg>; + resets = <&cpg 225>, + <&cpg 226>, <&cpg 227>, + <&cpg 228>, <&cpg 229>, + <&cpg 230>, <&cpg 231>, + <&cpg 232>, <&cpg 233>, + <&cpg 234>, <&cpg 235>, + <&cpg 236>, <&cpg 238>, <&cpg 237>; + reset-names = "ssi-all", + "ssi-0", "ssi-1", + "ssi-2", "ssi-3", + "ssi-4", "ssi-5", + "ssi-6", "ssi-7", + "ssi-8", "ssi-9", + "scu", "adg", + "audmapp"; + + ctu { + ctu-0 { }; + ctu-1 { }; + ctu-2 { }; + ctu-3 { }; + ctu-4 { }; + ctu-5 { }; + ctu-6 { }; + ctu-7 { }; + }; + + dvc { + dvc0: dvc-0 { + dmas = <&dmac0 0x1db3>, <&dmac1 0x1db3>, + <&dmac2 0x1db3>, <&dmac3 0x1db3>, + <&dmac4 0x1db3>; + dma-names = "tx", "tx", "tx", "tx", "tx"; + }; + dvc1: dvc-1 { + dmas = <&dmac0 0x1db4>, <&dmac1 0x1db4>, + <&dmac2 0x1db4>, <&dmac3 0x1db4>, + <&dmac4 0x1db4>; + dma-names = "tx", "tx", "tx", "tx", "tx"; + }; + }; + + mix { + mix-0 { }; + mix-1 { }; + }; + + src { + src0: src-0 { + interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1d9f>, <&dmac0 0x1da9>, + <&dmac1 0x1d9f>, <&dmac1 0x1da9>, + <&dmac2 0x1d9f>, <&dmac2 0x1da9>, + <&dmac3 0x1d9f>, <&dmac3 0x1da9>, + <&dmac4 0x1d9f>, <&dmac4 0x1da9>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da0>, <&dmac0 0x1daa>, + <&dmac1 0x1da0>, <&dmac1 0x1daa>, + <&dmac2 0x1da0>, <&dmac2 0x1daa>, + <&dmac3 0x1da0>, <&dmac3 0x1daa>, + <&dmac4 0x1da0>, <&dmac4 0x1daa>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-2 { + interrupts = <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da1>, <&dmac0 0x1dab>, + <&dmac1 0x1da1>, <&dmac1 0x1dab>, + <&dmac2 0x1da1>, <&dmac2 0x1dab>, + <&dmac3 0x1da1>, <&dmac3 0x1dab>, + <&dmac4 0x1da1>, <&dmac4 0x1dab>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-3 { + interrupts = <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da2>, <&dmac0 0x1dac>, + <&dmac1 0x1da2>, <&dmac1 0x1dac>, + <&dmac2 0x1da2>, <&dmac2 0x1dac>, + <&dmac3 0x1da2>, <&dmac3 0x1dac>, + <&dmac4 0x1da2>, <&dmac4 0x1dac>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-4 { + interrupts = <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da3>, <&dmac0 0x1dad>, + <&dmac1 0x1da3>, <&dmac1 0x1dad>, + <&dmac2 0x1da3>, <&dmac2 0x1dad>, + <&dmac3 0x1da3>, <&dmac3 0x1dad>, + <&dmac4 0x1da3>, <&dmac4 0x1dad>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-5 { + interrupts = <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da4>, <&dmac0 0x1dae>, + <&dmac1 0x1da4>, <&dmac1 0x1dae>, + <&dmac2 0x1da4>, <&dmac2 0x1dae>, + <&dmac3 0x1da4>, <&dmac3 0x1dae>, + <&dmac4 0x1da4>, <&dmac4 0x1dae>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-6 { + interrupts = <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da5>, <&dmac0 0x1daf>, + <&dmac1 0x1da5>, <&dmac1 0x1daf>, + <&dmac2 0x1da5>, <&dmac2 0x1daf>, + <&dmac3 0x1da5>, <&dmac3 0x1daf>, + <&dmac4 0x1da5>, <&dmac4 0x1daf>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-7 { + interrupts = <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da6>, <&dmac0 0x1db0>, + <&dmac1 0x1da6>, <&dmac1 0x1db0>, + <&dmac2 0x1da6>, <&dmac2 0x1db0>, + <&dmac3 0x1da6>, <&dmac3 0x1db0>, + <&dmac4 0x1da6>, <&dmac4 0x1db0>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-8 { + interrupts = <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da7>, <&dmac0 0x1db1>, + <&dmac1 0x1da7>, <&dmac1 0x1db1>, + <&dmac2 0x1da7>, <&dmac2 0x1db1>, + <&dmac3 0x1da7>, <&dmac3 0x1db1>, + <&dmac4 0x1da7>, <&dmac4 0x1db1>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + src-9 { + interrupts = <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0x1da8>, <&dmac0 0x1db2>, + <&dmac1 0x1da8>, <&dmac1 0x1db2>, + <&dmac2 0x1da8>, <&dmac2 0x1db2>, + <&dmac3 0x1da8>, <&dmac3 0x1db2>, + <&dmac4 0x1da8>, <&dmac4 0x1db2>; + dma-names = "rx", "tx", "rx", "tx", "rx", "tx", + "rx", "tx", "rx", "tx"; + }; + }; + + ssi { + ssi-0 { + interrupts = <GIC_SPI 889 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi-1 { + interrupts = <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi-2 { + interrupts = <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>; + shared-pin; + }; + ssi-5 { + interrupts = <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi-6 { + interrupts = <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi-7 { + interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi-8 { + interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; + }; + ssi-9 { + interrupts = <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + ssiu { + ssiu-0 { + dmas = <&dmac0 0x1d61>, <&dmac0 0x1d62>, + <&dmac1 0x1d61>, <&dmac1 0x1d62>, + <&dmac2 0x1d61>, <&dmac2 0x1d62>, + <&dmac3 0x1d61>, <&dmac3 0x1d62>, + <&dmac4 0x1d61>, <&dmac4 0x1d62>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-1 { + dmas = <&dmac0 0x1d63>, <&dmac0 0x1d64>, + <&dmac1 0x1d63>, <&dmac1 0x1d64>, + <&dmac2 0x1d63>, <&dmac2 0x1d64>, + <&dmac3 0x1d63>, <&dmac3 0x1d64>, + <&dmac4 0x1d63>, <&dmac4 0x1d64>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-2 { + dmas = <&dmac0 0x1d65>, <&dmac0 0x1d66>, + <&dmac1 0x1d65>, <&dmac1 0x1d66>, + <&dmac2 0x1d65>, <&dmac2 0x1d66>, + <&dmac3 0x1d65>, <&dmac3 0x1d66>, + <&dmac4 0x1d65>, <&dmac4 0x1d66>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-3 { + dmas = <&dmac0 0x1d67>, <&dmac0 0x1d68>, + <&dmac1 0x1d67>, <&dmac1 0x1d68>, + <&dmac2 0x1d67>, <&dmac2 0x1d68>, + <&dmac3 0x1d67>, <&dmac3 0x1d68>, + <&dmac4 0x1d67>, <&dmac4 0x1d68>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-4 { + dmas = <&dmac0 0x1d69>, <&dmac0 0x1d6a>, + <&dmac1 0x1d69>, <&dmac1 0x1d6a>, + <&dmac2 0x1d69>, <&dmac2 0x1d6a>, + <&dmac3 0x1d69>, <&dmac3 0x1d6a>, + <&dmac4 0x1d69>, <&dmac4 0x1d6a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-5 { + dmas = <&dmac0 0x1d6b>, <&dmac0 0x1d6c>, + <&dmac1 0x1d6b>, <&dmac1 0x1d6c>, + <&dmac2 0x1d6b>, <&dmac2 0x1d6c>, + <&dmac3 0x1d6b>, <&dmac3 0x1d6c>, + <&dmac4 0x1d6b>, <&dmac4 0x1d6c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-6 { + dmas = <&dmac0 0x1d6d>, <&dmac0 0x1d6e>, + <&dmac1 0x1d6d>, <&dmac1 0x1d6e>, + <&dmac2 0x1d6d>, <&dmac2 0x1d6e>, + <&dmac3 0x1d6d>, <&dmac3 0x1d6e>, + <&dmac4 0x1d6d>, <&dmac4 0x1d6e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-7 { + dmas = <&dmac0 0x1d6f>, <&dmac0 0x1d70>, + <&dmac1 0x1d6f>, <&dmac1 0x1d70>, + <&dmac2 0x1d6f>, <&dmac2 0x1d70>, + <&dmac3 0x1d6f>, <&dmac3 0x1d70>, + <&dmac4 0x1d6f>, <&dmac4 0x1d70>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-8 { + dmas = <&dmac0 0x1d71>, <&dmac0 0x1d72>, + <&dmac1 0x1d71>, <&dmac1 0x1d72>, + <&dmac2 0x1d71>, <&dmac2 0x1d72>, + <&dmac3 0x1d71>, <&dmac3 0x1d72>, + <&dmac4 0x1d71>, <&dmac4 0x1d72>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-9 { + dmas = <&dmac0 0x1d73>, <&dmac0 0x1d74>, + <&dmac1 0x1d73>, <&dmac1 0x1d74>, + <&dmac2 0x1d73>, <&dmac2 0x1d74>, + <&dmac3 0x1d73>, <&dmac3 0x1d74>, + <&dmac4 0x1d73>, <&dmac4 0x1d74>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-10 { + dmas = <&dmac0 0x1d75>, <&dmac0 0x1d76>, + <&dmac1 0x1d75>, <&dmac1 0x1d76>, + <&dmac2 0x1d75>, <&dmac2 0x1d76>, + <&dmac3 0x1d75>, <&dmac3 0x1d76>, + <&dmac4 0x1d75>, <&dmac4 0x1d76>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-11 { + dmas = <&dmac0 0x1d77>, <&dmac0 0x1d78>, + <&dmac1 0x1d77>, <&dmac1 0x1d78>, + <&dmac2 0x1d77>, <&dmac2 0x1d78>, + <&dmac3 0x1d77>, <&dmac3 0x1d78>, + <&dmac4 0x1d77>, <&dmac4 0x1d78>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-12 { + dmas = <&dmac0 0x1d79>, <&dmac0 0x1d7a>, + <&dmac1 0x1d79>, <&dmac1 0x1d7a>, + <&dmac2 0x1d79>, <&dmac2 0x1d7a>, + <&dmac3 0x1d79>, <&dmac3 0x1d7a>, + <&dmac4 0x1d79>, <&dmac4 0x1d7a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-13 { + dmas = <&dmac0 0x1d7b>, <&dmac0 0x1d7c>, + <&dmac1 0x1d7b>, <&dmac1 0x1d7c>, + <&dmac2 0x1d7b>, <&dmac2 0x1d7c>, + <&dmac3 0x1d7b>, <&dmac3 0x1d7c>, + <&dmac4 0x1d7b>, <&dmac4 0x1d7c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-14 { + dmas = <&dmac0 0x1d7d>, <&dmac0 0x1d7e>, + <&dmac1 0x1d7d>, <&dmac1 0x1d7e>, + <&dmac2 0x1d7d>, <&dmac2 0x1d7e>, + <&dmac3 0x1d7d>, <&dmac3 0x1d7e>, + <&dmac4 0x1d7d>, <&dmac4 0x1d7e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-15 { + dmas = <&dmac0 0x1d7f>, <&dmac0 0x1d80>, + <&dmac1 0x1d7f>, <&dmac1 0x1d80>, + <&dmac2 0x1d7f>, <&dmac2 0x1d80>, + <&dmac3 0x1d7f>, <&dmac3 0x1d80>, + <&dmac4 0x1d7f>, <&dmac4 0x1d80>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-16 { + dmas = <&dmac0 0x1d81>, <&dmac0 0x1d82>, + <&dmac1 0x1d81>, <&dmac1 0x1d82>, + <&dmac2 0x1d81>, <&dmac2 0x1d82>, + <&dmac3 0x1d81>, <&dmac3 0x1d82>, + <&dmac4 0x1d81>, <&dmac4 0x1d82>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-17 { + dmas = <&dmac0 0x1d83>, <&dmac0 0x1d84>, + <&dmac1 0x1d83>, <&dmac1 0x1d84>, + <&dmac2 0x1d83>, <&dmac2 0x1d84>, + <&dmac3 0x1d83>, <&dmac3 0x1d84>, + <&dmac4 0x1d83>, <&dmac4 0x1d84>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-18 { + dmas = <&dmac0 0x1d85>, <&dmac0 0x1d86>, + <&dmac1 0x1d85>, <&dmac1 0x1d86>, + <&dmac2 0x1d85>, <&dmac2 0x1d86>, + <&dmac3 0x1d85>, <&dmac3 0x1d86>, + <&dmac4 0x1d85>, <&dmac4 0x1d86>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-19 { + dmas = <&dmac0 0x1d87>, <&dmac0 0x1d88>, + <&dmac1 0x1d87>, <&dmac1 0x1d88>, + <&dmac2 0x1d87>, <&dmac2 0x1d88>, + <&dmac3 0x1d87>, <&dmac3 0x1d88>, + <&dmac4 0x1d87>, <&dmac4 0x1d88>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-20 { + dmas = <&dmac0 0x1d89>, <&dmac0 0x1d8a>, + <&dmac1 0x1d89>, <&dmac1 0x1d8a>, + <&dmac2 0x1d89>, <&dmac2 0x1d8a>, + <&dmac3 0x1d89>, <&dmac3 0x1d8a>, + <&dmac4 0x1d89>, <&dmac4 0x1d8a>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-21 { + dmas = <&dmac0 0x1d8b>, <&dmac0 0x1d8c>, + <&dmac1 0x1d8b>, <&dmac1 0x1d8c>, + <&dmac2 0x1d8b>, <&dmac2 0x1d8c>, + <&dmac3 0x1d8b>, <&dmac3 0x1d8c>, + <&dmac4 0x1d8b>, <&dmac4 0x1d8c>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-22 { + dmas = <&dmac0 0x1d8d>, <&dmac0 0x1d8e>, + <&dmac1 0x1d8d>, <&dmac1 0x1d8e>, + <&dmac2 0x1d8d>, <&dmac2 0x1d8e>, + <&dmac3 0x1d8d>, <&dmac3 0x1d8e>, + <&dmac4 0x1d8d>, <&dmac4 0x1d8e>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-23 { + dmas = <&dmac0 0x1d8f>, <&dmac0 0x1d90>, + <&dmac1 0x1d8f>, <&dmac1 0x1d90>, + <&dmac2 0x1d8f>, <&dmac2 0x1d90>, + <&dmac3 0x1d8f>, <&dmac3 0x1d90>, + <&dmac4 0x1d8f>, <&dmac4 0x1d90>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-24 { + dmas = <&dmac0 0x1d91>, <&dmac0 0x1d92>, + <&dmac1 0x1d91>, <&dmac1 0x1d92>, + <&dmac2 0x1d91>, <&dmac2 0x1d92>, + <&dmac3 0x1d91>, <&dmac3 0x1d92>, + <&dmac4 0x1d91>, <&dmac4 0x1d92>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-25 { + dmas = <&dmac0 0x1d93>, <&dmac0 0x1d94>, + <&dmac1 0x1d93>, <&dmac1 0x1d94>, + <&dmac2 0x1d93>, <&dmac2 0x1d94>, + <&dmac3 0x1d93>, <&dmac3 0x1d94>, + <&dmac4 0x1d93>, <&dmac4 0x1d94>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-26 { + dmas = <&dmac0 0x1d95>, <&dmac0 0x1d96>, + <&dmac1 0x1d95>, <&dmac1 0x1d96>, + <&dmac2 0x1d95>, <&dmac2 0x1d96>, + <&dmac3 0x1d95>, <&dmac3 0x1d96>, + <&dmac4 0x1d95>, <&dmac4 0x1d96>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + ssiu-27 { + dmas = <&dmac0 0x1d97>, <&dmac0 0x1d98>, + <&dmac1 0x1d97>, <&dmac1 0x1d98>, + <&dmac2 0x1d97>, <&dmac2 0x1d98>, + <&dmac3 0x1d97>, <&dmac3 0x1d98>, + <&dmac4 0x1d97>, <&dmac4 0x1d98>; + dma-names = "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx", "tx", "rx"; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + rsnd_endpoint0: endpoint { + remote-endpoint = <&codec_endpoint>; + dai-format = "i2s"; + bitclock-master = <&rsnd_endpoint0>; + frame-master = <&rsnd_endpoint0>; + playback = <&ssi3>, <&src1>, <&dvc1>; + capture = <&ssi4>, <&src0>, <&dvc0>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml index 502907dd28b3..b174d7498029 100644 --- a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml +++ b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml @@ -45,8 +45,8 @@ properties: clocks: items: - - description: clock for SPDIF bus - description: clock for SPDIF controller + - description: clock for SPDIF bus clock-names: items: diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2.yaml b/Documentation/devicetree/bindings/sound/samsung,tm2.yaml index 67586ba3e0a0..985b7d29cd33 100644 --- a/Documentation/devicetree/bindings/sound/samsung,tm2.yaml +++ b/Documentation/devicetree/bindings/sound/samsung,tm2.yaml @@ -45,8 +45,12 @@ properties: description: Phandles to the I2S controllers. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: Phandle to I2S0. - - description: Phandle to I2S1. + - items: + - description: Phandle to I2S0 + - description: Unused + - items: + - description: Phandle to I2S1 + - description: Unused mic-bias-gpios: description: GPIO pin that enables the Main Mic bias regulator. diff --git a/Documentation/devicetree/bindings/sound/simple-card.yaml b/Documentation/devicetree/bindings/sound/simple-card.yaml index a14716b2732f..23310f303be3 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.yaml +++ b/Documentation/devicetree/bindings/sound/simple-card.yaml @@ -315,7 +315,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - simple-audio-card,dai-link@0 { /* I2S - HDMI */ + simple-audio-card,dai-link@0 { /* I2S - HDMI */ reg = <0>; format = "i2s"; cpu { @@ -326,7 +326,7 @@ examples: }; }; - simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */ + simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */ reg = <1>; cpu { sound-dai = <&audio1>; @@ -336,7 +336,7 @@ examples: }; }; - simple-audio-card,dai-link@2 { /* S/PDIF - S/PDIF */ + simple-audio-card,dai-link@2 { /* S/PDIF - S/PDIF */ reg = <2>; cpu { sound-dai = <&audio2>; diff --git a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml index 55bd0b307d22..72723f067b2a 100644 --- a/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/sound/spacemit,k1-i2s.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: K1 I2S controller +title: SpacemiT K1/K3 I2S controller description: The I2S bus (Inter-IC sound bus) is a serial link for digital @@ -15,27 +15,78 @@ maintainers: allOf: - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + const: spacemit,k3-i2s + then: + properties: + clocks: + minItems: 6 + clock-names: + minItems: 6 + else: + properties: + clocks: + maxItems: 4 + clock-names: + maxItems: 4 properties: compatible: - const: spacemit,k1-i2s + enum: + - spacemit,k1-i2s + - spacemit,k3-i2s reg: maxItems: 1 clocks: - items: - - description: clock for I2S sysclk - - description: clock for I2S bclk - - description: clock for I2S bus - - description: clock for I2S controller + oneOf: + - items: + - description: clock for I2S sysclk + - description: clock for I2S bclk + - description: clock for I2S bus + - description: clock for I2S controller + - items: + - description: clock for I2S sysclk + - description: clock for I2S bclk + - description: clock for I2S bus + - description: clock for I2S controller + - description: clock for I2S common sysclk + - description: clock for I2S common bclk + - items: + - description: clock for I2S sysclk + - description: clock for I2S bclk + - description: clock for I2S bus + - description: clock for I2S controller + - description: clock for I2S sysclk divider + - description: clock for I2S common sysclk + - description: clock for I2S common bclk clock-names: - items: - - const: sysclk - - const: bclk - - const: bus - - const: func + oneOf: + - items: + - const: sysclk + - const: bclk + - const: bus + - const: func + - items: + - const: sysclk + - const: bclk + - const: bus + - const: func + - const: c_sysclk + - const: c_bclk + - items: + - const: sysclk + - const: bclk + - const: bus + - const: func + - const: sysclk_div + - const: c_sysclk + - const: c_bclk dmas: minItems: 1 diff --git a/Documentation/devicetree/bindings/sound/st,sta32x.txt b/Documentation/devicetree/bindings/sound/st,sta32x.txt index 52265fb757c5..266b6fc9f009 100644 --- a/Documentation/devicetree/bindings/sound/st,sta32x.txt +++ b/Documentation/devicetree/bindings/sound/st,sta32x.txt @@ -73,7 +73,7 @@ Optional properties: - st,odd-pwm-speed-mode: If present, PWM speed mode run on odd speed mode (341.3 kHz) on all - channels. If not present, normal PWM spped mode (384 kHz) will be used. + channels. If not present, normal PWM speed mode (384 kHz) will be used. - st,invalid-input-detect-mute: If present, automatic invalid input detect mute is enabled. diff --git a/Documentation/devicetree/bindings/sound/ti,omap4-dmic.yaml b/Documentation/devicetree/bindings/sound/ti,omap4-dmic.yaml new file mode 100644 index 000000000000..773b9bf2f1c2 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,omap4-dmic.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,omap4-dmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments OMAP4+ Digital Microphone Module + +maintainers: + - Peter Ujfalusi <peter.ujfalusi@ti.com> + +properties: + compatible: + const: ti,omap4-dmic + + reg: + items: + - description: MPU access base address + - description: L3 interconnect address + + reg-names: + items: + - const: mpu + - const: dma + + interrupts: + maxItems: 1 + + dmas: + maxItems: 1 + + dma-names: + items: + - const: up_link + +required: + - compatible + - reg + - reg-names + - interrupts + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + dmic@0 { + compatible = "ti,omap4-dmic"; + reg = <0x0 0x7f>, /* MPU private access */ + <0x4902e000 0x7f>; /* L3 Interconnect */ + reg-names = "mpu", "dma"; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 67>; + dma-names = "up_link"; + }; diff --git a/Documentation/devicetree/bindings/sound/ti,tas2781.yaml b/Documentation/devicetree/bindings/sound/ti,tas2781.yaml index b21466bb0730..aa5a317b5a36 100644 --- a/Documentation/devicetree/bindings/sound/ti,tas2781.yaml +++ b/Documentation/devicetree/bindings/sound/ti,tas2781.yaml @@ -71,6 +71,9 @@ properties: ti,tas2572: 6.6-W Digital Input smart amp with I/V sense and integrated 13-V Class-H Boost + ti,tas2573: Boosted Class-D Audio Amplifier with Integrated DSP and IV + Sense + ti,tas2574: 8.5-W Digital Input smart amp with I/V sense and integrated 15-V Class-H Boost @@ -121,6 +124,7 @@ properties: - ti,tas2568 - ti,tas2570 - ti,tas2572 + - ti,tas2573 - ti,tas2574 - ti,tas5802 - ti,tas5806m @@ -183,6 +187,7 @@ allOf: contains: enum: - ti,tas2563 + - ti,tas2573 - ti,tas5825 then: properties: diff --git a/Documentation/devicetree/bindings/sound/ti,tas67524.yaml b/Documentation/devicetree/bindings/sound/ti,tas67524.yaml new file mode 100644 index 000000000000..812a4d39e2a5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,tas67524.yaml @@ -0,0 +1,280 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,tas67524.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TAS67524 Audio Amplifier + +maintainers: + - Sen Wang <sen@ti.com> + +description: + The TAS67524 is a four-channel, digital-input, automotive + Class-D audio amplifier with load diagnostics and an integrated + DSP for audio processing. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,tas6754 + - const: ti,tas67524 + - const: ti,tas67524 + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + description: | + The device exposes three DAIs, selected by index. + 0 - Standard Audio Path (Playback) + 1 - Low-Latency Playback Path (Playback) + 2 - Sensory Feedback (Capture - Vpredict and Isense) + By default, all four channels of each DAI are active. + + interrupts: + maxItems: 1 + description: + Active-low falling-edge interrupt from the FAULT pin. When provided, + the driver uses IRQ-driven fault reporting instead of polling. + + powerdown-gpios: + maxItems: 1 + description: + GPIO connected to the PD pin, active low. Controls the internal + digital circuitry power state. When asserted the device enters + full power-down mode and all register state is lost. Can be omitted if + PD pin is hardwired or externally controlled. + + standby-gpios: + maxItems: 1 + description: + GPIO connected to the STBY pin, active low. Controls the analog + power stage. When asserted the device enters Deep Sleep mode but + remains I2C-accessible with registers retained. Can be omitted if + STBY pin is tied to PD or hardwired. + + dvdd-supply: + description: + Digital logic supply (1.62 V to 3.6 V). All three supply rails must + be within their recommended operating ranges before the PD pin is + released. + + pvdd-supply: + description: + Output FET power supply (4.5 V to 19 V). All three supply rails must + be within their recommended operating ranges before the PD pin is + released. + + vbat-supply: + description: + Battery supply for the Class-D output stage (4.5 V to 19 V). Optional + when PVDD and VBAT are connected to the same supply rail. When absent, + VBAT is assumed hardwired to PVDD. + + ti,fast-boot: + type: boolean + description: + Skip DC load diagnostic sweep at power-on to reduce boot latency. + Automatic diagnostics after fault conditions remain enabled. Hardware + overcurrent protection is always active. + + ti,audio-slot-no: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + TDM slot offset for the standard audio playback path via SDIN1. A value + of 4 maps to slot 4. If omitted, slot assignment is derived from the + tx_mask provided via set_tdm_slot(). Without either property, no slot + mapping is configured. + + ti,llp-slot-no: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + TDM slot offset for the low-latency playback path via SDIN1. If omitted, + slot assignment is derived from the tx_mask provided via set_tdm_slot(). + Without either property, no slot mapping is configured. Disabled outside + of LLP mode, and only relevant for TDM formats. + + ti,vpredict-slot-no: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + In TDM mode, enables Vpredict output and assigns its starting slot; + four consecutive slots carry Vpredict Ch1-4 on SDOUT1. May coexist + with ti,isense-slot-no using separate non-overlapping slots. + + In I2S mode, enables Vpredict output on SDOUT1 (Ch1/Ch2) and SDOUT2 + (Ch3/Ch4). The slot value is unused. Requires a GPIO configured as + sdout2 for Ch3/Ch4; without it only Ch1/Ch2 are output. Mutually + exclusive with ti,isense-slot-no; if both are set, Vpredict takes + priority. + + Irrelevant in Left-J and Right-J modes. + + ti,isense-slot-no: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + In TDM mode, enables Isense output and assigns its starting slot; + four consecutive slots carry Isense Ch1-4 on SDOUT1. May coexist + with ti,vpredict-slot-no using separate non-overlapping slots. + + In I2S mode, enables Isense output on SDOUT1 (Ch1/Ch2) and SDOUT2 + (Ch3/Ch4). The slot value is unused. Requires a GPIO configured as + SDOUT2 for Ch3/Ch4; without it only Ch1/Ch2 are output. Mutually + exclusive with ti,vpredict-slot-no; Vpredict takes priority if both + are set. + + Irrelevant in Left-J and Right-J modes. + + ti,gpio1-function: + $ref: /schemas/types.yaml#/definitions/string + description: + Function for the GPIO_1 pin. When omitted, GPIO_1 remains in its + power-on default state. + enum: + - low # Output: driven low + - auto-mute # Output: high when all channels are auto-muted + - auto-mute-ch4 # Output: high when channel 4 is auto-muted + - auto-mute-ch3 # Output: high when channel 3 is auto-muted + - auto-mute-ch2 # Output: high when channel 2 is auto-muted + - auto-mute-ch1 # Output: high when channel 1 is auto-muted + - sdout2 # Output: Routes secondary serial data output 2 + - sdout1 # Output: Re-routes secondary serial data output 1 + - warn # Output: warning signal (OTW, CBC) + - fault # Output: fault signal (OTSD, OC, DC) + - clock-sync # Output: clock synchronisation + - invalid-clock # Output: high when clock is invalid + - high # Output: driven high + - mute # Input: external mute control + - phase-sync # Input: phase synchronisation + - sdin2 # Input: secondary SDIN2 for I2S/LJ/RJ ch3/ch4 + - deep-sleep # Input: asserted transitions device to Deep Sleep + - hiz # Input: asserted transitions device to Hi-Z + - play # Input: asserted transitions device to Play + - sleep # Input: asserted transitions device to Sleep + + ti,gpio2-function: + $ref: /schemas/types.yaml#/definitions/string + description: + Function for the GPIO_2 pin. When omitted, GPIO_2 remains in its + power-on default state. + enum: + - low # Output: driven low + - auto-mute # Output: high when all channels are auto-muted + - auto-mute-ch4 # Output: high when channel 4 is auto-muted + - auto-mute-ch3 # Output: high when channel 3 is auto-muted + - auto-mute-ch2 # Output: high when channel 2 is auto-muted + - auto-mute-ch1 # Output: high when channel 1 is auto-muted + - sdout2 # Output: Routes secondary serial data output 2 + - sdout1 # Output: Re-routes secondary serial data output 1 + - warn # Output: warning signal (OTW, CBC) + - fault # Output: fault signal (OTSD, OC, DC) + - clock-sync # Output: clock synchronisation + - invalid-clock # Output: high when clock is invalid + - high # Output: driven high + - mute # Input: external mute control + - phase-sync # Input: phase synchronisation + - sdin2 # Input: secondary SDIN2 for I2S/LJ/RJ ch3/ch4 + - deep-sleep # Input: asserted transitions device to Deep Sleep + - hiz # Input: asserted transitions device to Hi-Z + - play # Input: asserted transitions device to Play + - sleep # Input: asserted transitions device to Sleep + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Standard audio playback port (DAI 0). + + port@1: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Low-latency playback port (LLP) (DAI 1). + + port@2: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Sensory feedback capture port (DAI 2). + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - '#sound-dai-cells' + - dvdd-supply + - pvdd-supply + +anyOf: + - required: [powerdown-gpios] + - required: [standby-gpios] + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + amplifier@70 { + compatible = "ti,tas67524"; + reg = <0x70>; + #sound-dai-cells = <1>; + sound-name-prefix = "TAS0"; + + standby-gpios = <&main_gpio0 33 GPIO_ACTIVE_LOW>; + + dvdd-supply = <&dvdd_1v8>; + pvdd-supply = <&pvdd_12v>; + vbat-supply = <&vbat_12v>; + + ti,audio-slot-no = <0>; + ti,llp-slot-no = <4>; + ti,vpredict-slot-no = <0>; + ti,isense-slot-no = <4>; + + ti,gpio2-function = "warn"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tas0_audio_ep: endpoint { + dai-format = "dsp_b"; + remote-endpoint = <&be_tas0_audio_ep>; + }; + }; + + port@1 { + reg = <1>; + + tas0_anc_ep: endpoint { + remote-endpoint = <&be_tas0_anc_ep>; + }; + }; + + port@2 { + reg = <2>; + + tas0_fb_ep: endpoint { + remote-endpoint = <&be_tas0_fb_ep>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml b/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml index 4d951ece394e..dffc41d5f7de 100644 --- a/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml +++ b/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml @@ -24,6 +24,10 @@ properties: description: a GPIO spec for the MUTE pin. + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - wlf,mute-gpios diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index 9447a2f371b5..8e6973fa229c 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -90,7 +90,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -101,7 +101,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-sinterval: $ref: /schemas/types.yaml#/definitions/uint16-array @@ -112,7 +112,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-offset1: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -123,7 +123,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-offset2: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -134,7 +134,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-lane-control: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -145,7 +145,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-block-pack-mode: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -158,7 +158,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 items: oneOf: - minimum: 0 @@ -175,7 +175,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 items: oneOf: - minimum: 0 @@ -192,7 +192,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 items: oneOf: - minimum: 0 @@ -208,7 +208,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 items: oneOf: - minimum: 0 diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 6af4ff233158..14c2f318dd04 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -34,6 +34,12 @@ properties: - const: allwinner,sun50i-r329-spi-dbi - const: allwinner,sun50i-r329-spi - items: + - enum: + - allwinner,sun55i-a523-spi-dbi + - allwinner,sun60i-a733-spi + - const: allwinner,sun55i-a523-spi + - items: + - const: allwinner,sun60i-a733-spi-dbi - const: allwinner,sun55i-a523-spi-dbi - const: allwinner,sun55i-a523-spi diff --git a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml index 8e441742cee6..381042e07fd0 100644 --- a/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml +++ b/Documentation/devicetree/bindings/spi/andestech,ae350-spi.yaml @@ -24,10 +24,6 @@ properties: clocks: maxItems: 1 - num-cs: - description: Number of chip selects supported - maxItems: 1 - dmas: items: - description: Transmit FIFO DMA channel diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml index 30ab42c95c08..36c698ced99b 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -22,6 +22,7 @@ properties: - microchip,sama7d65-ospi - microchip,sama7g5-qspi - microchip,sama7g5-ospi + - microchip,lan9691-qspi reg: items: diff --git a/Documentation/devicetree/bindings/spi/axiado,ax3000-spi.yaml b/Documentation/devicetree/bindings/spi/axiado,ax3000-spi.yaml index cd2aac66fca2..be258c1f36b1 100644 --- a/Documentation/devicetree/bindings/spi/axiado,ax3000-spi.yaml +++ b/Documentation/devicetree/bindings/spi/axiado,ax3000-spi.yaml @@ -37,7 +37,6 @@ properties: num-cs: description: | Number of chip selects used. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 4 default: 4 diff --git a/Documentation/devicetree/bindings/spi/cavium,octeon-3010-spi.yaml b/Documentation/devicetree/bindings/spi/cavium,octeon-3010-spi.yaml new file mode 100644 index 000000000000..f0b708e1ccbb --- /dev/null +++ b/Documentation/devicetree/bindings/spi/cavium,octeon-3010-spi.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/cavium,octeon-3010-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cavium, Inc. OCTEON SoC SPI master controller + +description: + The Cavium OCTEON SPI controller is an SPI master controller found in + OCTEON SoCs. + +maintainers: + - Rob Herring <robh@kernel.org> + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: cavium,octeon-3010-spi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + spi@1070000001000 { + compatible = "cavium,octeon-3010-spi"; + reg = <0x10700 0x00001000 0x0 0x100>; + interrupts = <0 58>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + compatible = "st,m95256", "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpha; + spi-cpol; + pagesize = <64>; + size = <32768>; + address-width = <16>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml index 1d10cfbad86c..504df31a4f90 100644 --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml @@ -21,6 +21,9 @@ properties: - fsl,ls2080a-qspi - spacemit,k1-qspi - items: + - const: spacemit,k3-qspi + - const: spacemit,k1-qspi + - items: - enum: - fsl,ls1043a-qspi - const: fsl,ls1021a-qspi diff --git a/Documentation/devicetree/bindings/spi/marvell,armada-3700-spi.yaml b/Documentation/devicetree/bindings/spi/marvell,armada-3700-spi.yaml index 61caa1d86188..75437c46e65a 100644 --- a/Documentation/devicetree/bindings/spi/marvell,armada-3700-spi.yaml +++ b/Documentation/devicetree/bindings/spi/marvell,armada-3700-spi.yaml @@ -28,9 +28,6 @@ properties: clocks: maxItems: 1 - num-cs: - maxItems: 1 - required: - compatible - reg diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml new file mode 100644 index 000000000000..40965ec5163b --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Quad SPI Controller + +maintainers: + - Chi-Wen Weng <cwweng@nuvoton.com> + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: nuvoton,ma35d1-qspi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + num-cs: + minimum: 1 + maximum: 2 + default: 2 + + cs-gpios: false + +required: + - compatible + - reg + - clocks + - resets + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + #include <dt-bindings/reset/nuvoton,ma35d1-reset.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + spi@40680000 { + compatible = "nuvoton,ma35d1-qspi"; + reg = <0 0x40680000 0 0x100>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk QSPI0_GATE>; + resets = <&sys MA35D1_RESET_QSPI0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt deleted file mode 100644 index fb38e96d395f..000000000000 --- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Nuvoton FLASH Interface Unit (FIU) SPI Controller - -NPCM FIU supports single, dual and quad communication interface. - -The NPCM7XX supports three FIU modules, -FIU0 and FIUx supports two chip selects, -FIU3 support four chip select. - -The NPCM8XX supports four FIU modules, -FIU0 and FIUx supports two chip selects, -FIU1 and FIU3 supports four chip selects. - -Required properties: - - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC - "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC - - #address-cells : should be 1. - - #size-cells : should be 0. - - reg : the first contains the register location and length, - the second contains the memory mapping address and length - - reg-names: Should contain the reg names "control" and "memory" - - clocks : phandle of FIU reference clock. - -Required properties in case the pins can be muxed: - - pinctrl-names : a pinctrl state named "default" must be defined. - - pinctrl-0 : phandle referencing pin configuration of the device. - -Optional property: - - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. - -Aliases: -- All the FIU controller nodes should be represented in the aliases node using - the following format 'fiu{n}' where n is a unique number for the alias. - In the NPCM7XX BMC: - fiu0 represent fiu 0 controller - fiu1 represent fiu 3 controller - fiu2 represent fiu x controller - - In the NPCM8XX BMC: - fiu0 represent fiu 0 controller - fiu1 represent fiu 1 controller - fiu2 represent fiu 3 controller - fiu3 represent fiu x controller - -Example: -fiu3: spi@c00000000 { - compatible = "nuvoton,npcm750-fiu"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; - reg-names = "control", "memory"; - clocks = <&clk NPCM7XX_CLK_AHB>; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins>; - flash@0 { - ... - }; -}; - diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml new file mode 100644 index 000000000000..965904a98785 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,npcm750-fiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Flash Interface Unit (FIU) SPI Controller + +maintainers: + - Tomer Maimon <tmaimon77@gmail.com> + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +description: | + NPCM FIU supports single, dual and quad communication interface. + + The NPCM7XX supports three FIU modules: + FIU0 and FIUx support two chip selects + FIU3 supports four chip selects. + + The NPCM8XX supports four FIU modules: + FIU0 and FIUx support two chip selects + FIU1 and FIU3 support four chip selects. + + The FIU control register block is always required. The direct-mapped + flash window is optional because the controller can still access flash + through the UMA path when that mapping is not described. + + Alias convention: + The '/aliases' node should define: + For NPCM7xx: fiu0=&fiu0; fiu1=&fiu3; fiu2=&fiux; + For NPCM8xx: fiu0=&fiu0; fiu1=&fiu3; fiu2=&fiux; fiu3=&fiu1; + +properties: + compatible: + enum: + - nuvoton,npcm750-fiu # Poleg NPCM7XX + - nuvoton,npcm845-fiu # Arbel NPCM8XX + + reg: + description: + The first resource is the FIU control register block. An optional second + resource describes the direct-mapped flash window used for direct + read/write accesses. + minItems: 1 + items: + - description: FIU control registers + - description: Memory-mapped flash contents + + reg-names: + description: + Resource names for the control registers and optional direct-mapped + flash window. + minItems: 1 + items: + - const: control + - const: memory + + clocks: + maxItems: 1 + description: FIU reference clock. + + nuvoton,spix-mode: + type: boolean + description: Enable SPIX mode for an expansion bus to an ASIC or CPLD. + +required: + - compatible + - reg + - reg-names + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + spi@fb000000 { + compatible = "nuvoton,npcm750-fiu"; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_SPI0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml b/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml index 16a0598c6d03..ccf841f194c0 100644 --- a/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml +++ b/Documentation/devicetree/bindings/spi/nxp,imx94-xspi.yaml @@ -30,6 +30,16 @@ properties: - const: base - const: mmap + dmas: + items: + - description: Transmit DMA + - description: Receive DMA + + dma-names: + items: + - const: tx + - const: rx + interrupts: items: - description: interrupt for EENV0 diff --git a/Documentation/devicetree/bindings/spi/qcom,sa8255p-geni-spi.yaml b/Documentation/devicetree/bindings/spi/qcom,sa8255p-geni-spi.yaml new file mode 100644 index 000000000000..6552303a4f52 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,sa8255p-geni-spi.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,sa8255p-geni-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Praveen Talari <praveen.talari@oss.qualcomm.com> + +properties: + compatible: + oneOf: + - const: qcom,sa8255p-geni-spi + - items: + - const: qcom,sa8797p-geni-spi + - const: qcom,sa8255p-geni-spi + + reg: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 2 + + power-domain-names: + items: + - const: power + - const: perf + +required: + - compatible + - reg + - interrupts + - power-domains + - power-domain-names + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/dma/qcom-gpi.h> + + spi@888000 { + compatible = "qcom,sa8255p-geni-spi"; + reg = <0x888000 0x4000>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + power-domains = <&scmi0_pd 0>, <&scmi0_dvfs 0>; + power-domain-names = "power", "perf"; + }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml index 1696ac46a660..ee2199027e89 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml @@ -13,13 +13,11 @@ description: The QSPI controller allows SPI protocol communication in single, dual, or quad wire transmission modes for read/write access to slaves such as NOR flash. -allOf: - - $ref: /schemas/spi/spi-controller.yaml# - properties: compatible: items: - enum: + - qcom,qcs615-qspi - qcom,sc7180-qspi - qcom,sc7280-qspi - qcom,sdm845-qspi @@ -67,6 +65,23 @@ required: - clock-names - clocks +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: qcom,qcs615-qspi + then: + properties: + interconnects: + minItems: 2 + interconnect-names: + minItems: 2 + required: + - interconnects + - interconnect-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml index 7d0571feb46d..829da22537d4 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - qcom,ipq5018-snand + - qcom,ipq5210-snand - qcom,ipq5332-snand - qcom,ipq5424-snand - const: qcom,ipq9574-snand diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 8ebebcebca16..e8d6d5d858b6 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -33,6 +33,32 @@ allOf: else: properties: amd,pensando-elba-syscon: false + - if: + properties: + compatible: + contains: + const: starfive,jhb100-sfc + then: + required: + - starfive,sfc-filter-syscon + else: + properties: + starfive,sfc-filter-syscon: false + - if: + properties: + compatible: + contains: + const: ultrarisc,dp1000-spi + then: + properties: + reg: + maxItems: 1 + clocks: + minItems: 2 + clock-names: + minItems: 2 + required: + - clock-names properties: compatible: @@ -50,10 +76,21 @@ properties: - enum: - mscc,ocelot-spi - mscc,jaguar2-spi - - renesas,rzn1-spi - sophgo,sg2042-spi - thead,th1520-spi + - ultrarisc,dp1000-spi - const: snps,dw-apb-ssi + - description: Vendor controllers compatible with v1.01a + items: + - enum: + - axiado,ax3005-spi + - const: snps,dwc-ssi-1.01a + - description: Vendor controllers which use snps,dwc-ssi-2.00a as fallback + items: + - enum: + - starfive,jhb100-spi + - const: snps,dwc-ssi-2.00a + - const: snps,dwc-ssi-1.01a - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi - description: Intel Mount Evans Integrated Management Complex SPI Controller @@ -62,6 +99,8 @@ properties: const: amd,pensando-elba-spi - description: Canaan Kendryte K210 SoS SPI Controller const: canaan,k210-spi + - description: StarFive JHB100 SoC SPI Flash Controller + const: starfive,jhb100-sfc - description: Renesas RZ/N1 SPI Controller items: - const: renesas,r9a06g032-spi # RZ/N1D @@ -88,6 +127,9 @@ properties: - const: ssi_clk - const: pclk + power-domains: + maxItems: 1 + resets: maxItems: 1 @@ -133,6 +175,15 @@ properties: Block address to control SPI chip-selects. The Elba SoC system controller provides an interface to override the native DWC SSI CS control. + starfive,sfc-filter-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Phandle to the system controller register that controls the SPI NOR flash + address mode filter. This system controller interface provides additional + configuration to switch between 3-byte and 4-byte addressing modes, which + is required when accessing SPI NOR flash devices with different address + width requirements. + patternProperties: "@[0-9a-f]$": type: object diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml new file mode 100644 index 000000000000..5d86cc87e4fb --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) + +maintainers: + - Alex Elder <elder@kernel.org> + +description: + The SpacemiT K1 SoC implements a SPI controller that has two 32-entry + FIFOs, for transmit and receive. Details are currently available in + section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone + K1 Documentation[1]. The controller transfers words using PIO. DMA + transfers are supported as well, if both TX and RX DMA channels are + specified, + + [1] https://developer.spacemit.com/documentation + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + oneOf: + - const: spacemit,k1-spi + - items: + - const: spacemit,k3-spi + - const: spacemit,k1-spi + + reg: + maxItems: 1 + + clocks: + items: + - description: Core clock + - description: Bus clock + + clock-names: + items: + - const: core + - const: bus + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + items: + - description: RX DMA channel + - description: TX DMA channel + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - interrupts + +unevaluatedProperties: false + +examples: + - | + + #include <dt-bindings/clock/spacemit,k1-syscon.h> + spi@d401c000 { + compatible = "spacemit,k1-spi"; + reg = <0xd401c000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_SSP3>, + <&syscon_apbc CLK_SSP3_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_SSP3>; + interrupts = <55>; + dmas = <&pdma 20>, <&pdma 19>; + dma-names = "rx", "tx"; + }; diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml index 347bed0c4956..429cd824156c 100644 --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml @@ -43,7 +43,6 @@ properties: Number of chip selects used. If a decoder is used, this will be the number of chip selects after the decoder. - $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 4 default: 4 diff --git a/Documentation/devicetree/bindings/spi/spi-octeon.txt b/Documentation/devicetree/bindings/spi/spi-octeon.txt deleted file mode 100644 index 431add192342..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-octeon.txt +++ /dev/null @@ -1,33 +0,0 @@ -Cavium, Inc. OCTEON SOC SPI master controller. - -Required properties: -- compatible : "cavium,octeon-3010-spi" -- reg : The register base for the controller. -- interrupts : One interrupt, used by the controller. -- #address-cells : <1>, as required by generic SPI binding. -- #size-cells : <0>, also as required by generic SPI binding. - -Child nodes as per the generic SPI binding. - -Example: - - spi@1070000001000 { - compatible = "cavium,octeon-3010-spi"; - reg = <0x10700 0x00001000 0x0 0x100>; - interrupts = <0 58>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - compatible = "st,m95256", "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; - - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; - }; - diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 3f1a27efff80..ee57739b73b8 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -50,6 +50,9 @@ properties: minItems: 1 maxItems: 2 + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 472e92974714..6d7d595e4ab3 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -89,12 +89,10 @@ properties: - const: rxm2m sram: - $ref: /schemas/types.yaml#/definitions/phandle - description: | - Phandles to a reserved SRAM region which is used as temporary - storage memory between DMA and MDMA engines. - The region should be defined as child node of the AHB SRAM node - as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml + maxItems: 1 + description: + SRAM region which is used as temporary storage memory between DMA and + MDMA engines. power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml index 272bc308726b..b6be47f67fcb 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml @@ -49,8 +49,9 @@ properties: description: configure OCTOSPI delay block. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: phandle to syscfg - - description: register offset within syscfg + - items: + - description: phandle to syscfg + - description: register offset within syscfg access-controllers: description: phandle to the rifsc device to check access right diff --git a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml index 3b5005b96c6d..1593a1183a36 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml +++ b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml @@ -25,6 +25,7 @@ properties: oneOf: - items: - enum: + - qcom,hawi-spmi-pmic-arb - qcom,kaanapali-spmi-pmic-arb - const: qcom,glymur-spmi-pmic-arb - enum: diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index e7f7cf72719e..6e6ab2168a2a 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -80,6 +80,7 @@ patternProperties: - const: allwinner,sun4i-a10-sram-c1 - const: allwinner,sun4i-a10-sram-d - const: allwinner,sun50i-a64-sram-c + - const: allwinner,sun50i-h616-ve-sram - items: - enum: - allwinner,sun5i-a13-sram-a3-a4 @@ -103,7 +104,9 @@ patternProperties: - allwinner,sun7i-a20-sram-d - const: allwinner,sun4i-a10-sram-d - items: - - const: allwinner,sun50i-h6-sram-c + - enum: + - allwinner,sun50i-h6-sram-c + - allwinner,sun50i-h616-sram-c - const: allwinner,sun50i-a64-sram-c required: diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index c63026904061..b4f082f2af3a 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -67,6 +67,22 @@ properties: $ref: /schemas/power/reset/syscon-reboot-mode.yaml# patternProperties: + "^minidump-sram@[0-9a-f]+$": + type: object + description: + A word in always-on SRAM shared between the kernel and boot firmware. + Before DDR is initialised on the warm reset following a crash, firmware + reads this word to decide where to deliver the minidump (USB or storage). + + properties: + reg: + maxItems: 1 + + required: + - reg + + additionalProperties: false + "^modem-tables@[0-9a-f]+$": type: object description: @@ -89,6 +105,26 @@ required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,apq8064-imem + - qcom,msm8226-imem + - qcom,msm8974-imem + then: + properties: + reboot-mode: + patternProperties: + # Negative look-ahead to disallow unsupported modes. The '$' has to be + # part of lookahead group to work, instead of trailing outside of (). + "^mode-(?!(bootloader$|normal$|recovery$))": false + else: + properties: + reboot-mode: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/sram/sram-consumer.yaml b/Documentation/devicetree/bindings/sram/sram-consumer.yaml new file mode 100644 index 000000000000..f00087bd2879 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/sram-consumer.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sram/sram-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SRAM Consumers + +maintainers: + - Rob Herring <robh@kernel.org> + +select: true + +properties: + sram: + description: + Phandles to one or more reserved on-chip SRAM regions. The regions + should be defined as child nodes of the respective SRAM node, and + should be defined as per the generic bindings in, + Documentation/devicetree/bindings/sram/sram.yaml + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 8985f89170be..b83fc6831947 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -34,10 +34,14 @@ properties: - nvidia,tegra186-sysram - nvidia,tegra194-sysram - nvidia,tegra234-sysram + - qcom,eliza-imem + - qcom,glymur-imem - qcom,hawi-imem - qcom,kaanapali-imem + - qcom,maili-imem - qcom,milos-imem - qcom,rpm-msg-ram + - qcom,shikra-imem - rockchip,rk3288-pmu-sram reg: @@ -83,6 +87,7 @@ patternProperties: - allwinner,sun4i-a10-sram-d - allwinner,sun9i-a80-smp-sram - allwinner,sun50i-a64-sram-c + - allwinner,sun50i-h616-ve-sram - amlogic,meson8-ao-arc-sram - amlogic,meson8b-ao-arc-sram - amlogic,meson8-smp-sram diff --git a/Documentation/devicetree/bindings/submitting-patches.rst b/Documentation/devicetree/bindings/submitting-patches.rst index 81e27e50f905..6b1c064d4966 100644 --- a/Documentation/devicetree/bindings/submitting-patches.rst +++ b/Documentation/devicetree/bindings/submitting-patches.rst @@ -41,6 +41,9 @@ I. For patch submitters See Documentation/devicetree/bindings/writing-schema.rst for more details about schema and tools setup. + The example DTS in new bindings should pass scripts/dtc/dt-check-style in + 'strict' mode without warnings. + 3) DT binding files should be dual licensed. The preferred license tag is (GPL-2.0-only OR BSD-2-Clause). @@ -64,9 +67,10 @@ I. For patch submitters 7) DTS is treated in general as driver-independent hardware description, thus any DTS patches, regardless whether using existing or new bindings, should - be placed at the end of patchset to indicate no dependency of drivers on - the DTS. DTS will be anyway applied through separate tree or branch, so - different order would indicate the series is non-bisectable. + be a separate posting or, when combined with driver patches, placed at the + end of the patchset to indicate no dependency of drivers on the DTS. DTS + will be anyway applied through separate tree or branch, so different order + would indicate the series is non-bisectable. If a driver subsystem maintainer prefers to apply entire set, instead of their relevant portion of patchset, please split the DTS patches into diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml index 70b273271754..8cfa44dcda58 100644 --- a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml @@ -21,7 +21,9 @@ properties: - amlogic,g12a-cpu-thermal - amlogic,g12a-ddr-thermal - const: amlogic,g12a-thermal - - const: amlogic,a1-cpu-thermal + - enum: + - amlogic,a1-cpu-thermal + - amlogic,t7-thermal reg: maxItems: 1 @@ -42,12 +44,34 @@ properties: '#thermal-sensor-cells': const: 0 + amlogic,secure-monitor: + description: phandle to the secure monitor + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the secure monitor + - description: sensor index to get specific calibration data + required: - compatible - reg - interrupts - clocks - - amlogic,ao-secure + +allOf: + - if: + properties: + compatible: + contains: + enum: + - amlogic,a1-cpu-thermal + - amlogic,g12a-thermal + then: + required: + - amlogic,ao-secure + else: + required: + - amlogic,secure-monitor unevaluatedProperties: false @@ -62,4 +86,16 @@ examples: #thermal-sensor-cells = <0>; amlogic,ao-secure = <&sec_AO>; }; + - | + #include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + temperature-sensor@20000 { + compatible = "amlogic,t7-thermal"; + reg = <0x20000 0x50>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc_periphs CLKID_TS>; + #thermal-sensor-cells = <0>; + amlogic,secure-monitor = <&sm 1>; + }; ... diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml index 975235130670..29f431fcdcd5 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -94,12 +94,23 @@ allOf: nvmem-cell-names: minItems: 2 + - if: + properties: + compatible: + not: + contains: + enum: + - mediatek,mt8196-lvts-ap + - mediatek,mt8196-lvts-mcu + then: + required: + - resets + required: - compatible - reg - interrupts - clocks - - resets - nvmem-cells - nvmem-cell-names diff --git a/Documentation/devicetree/bindings/thermal/qcom,pm8775-mbg-tm.yaml b/Documentation/devicetree/bindings/thermal/qcom,pm8775-mbg-tm.yaml new file mode 100644 index 000000000000..2e084d040625 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/qcom,pm8775-mbg-tm.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/qcom,pm8775-mbg-tm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm's SPMI PMIC MBG Thermal Monitoring + +maintainers: + - Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> + - Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> + +description: + Qualcomm's MBG(Master Bandgap) temperature alarm monitors the die + temperature and generates an interrupt if the PMIC die temperature is + over a set of programmable temperature thresholds. It allows monitoring + for both hot and cold, LVL1 and LVL2 thresholds, which makes it different + from the existing temp alarm peripheral. The interrupt comes over SPMI + and the MBG's fault status register gives details to understand whether + it is a hot/cold and LVL1/LVL2 violation. + +properties: + compatible: + const: qcom,pm8775-mbg-tm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + io-channels: + items: + - description: ADC channel, which reports chip die temperature. + + io-channel-names: + items: + - const: thermal + + '#thermal-sensor-cells': + const: 0 + +required: + - compatible + - reg + - interrupts + - io-channels + - io-channel-names + +allOf: + - $ref: thermal-sensor.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@d700 { + compatible = "qcom,pm8775-mbg-tm"; + reg = <0xd700>; + interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>; + io-channels = <&pm8775_adc 0x3>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 7d34ba00e684..5a8f7673e730 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -56,8 +56,11 @@ properties: - enum: - qcom,eliza-tsens - qcom,glymur-tsens + - qcom,hawi-tsens - qcom,kaanapali-tsens + - qcom,maili-tsens - qcom,milos-tsens + - qcom,nord-tsens - qcom,msm8953-tsens - qcom,msm8996-tsens - qcom,msm8998-tsens @@ -74,6 +77,7 @@ properties: - qcom,sdm630-tsens - qcom,sdm670-tsens - qcom,sdm845-tsens + - qcom,shikra-tsens - qcom,sm6115-tsens - qcom,sm6350-tsens - qcom,sm6375-tsens diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml index aa756dae512a..f3b136f5e1cb 100644 --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml @@ -25,6 +25,7 @@ properties: enum: - fsl,qoriq-tmu - fsl,imx8mq-tmu + - fsl,imx93-tmu reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml b/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml index 29a08b0729ee..3f333db72a71 100644 --- a/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml @@ -40,7 +40,7 @@ properties: description: | The Exynos TMU supports generating interrupts when reaching given temperature thresholds. Number of supported thermal trip points depends - on the SoC (only first trip points defined in DT will be configured):: + on the SoC (only first trip points defined in DT will be configured): - most of SoC: 4 - samsung,exynos5433-tmu: 8 - samsung,exynos7-tmu: 8 @@ -52,7 +52,7 @@ properties: - description: | Shared TMU registers. - Note:: On Exynos5420, the TRIMINFO register is misplaced for TMU + Note: On Exynos5420, the TRIMINFO register is misplaced for TMU channels 2, 3 and 4 Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced register, also provide clock to access that base. diff --git a/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml new file mode 100644 index 000000000000..6dad76a7dd36 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/spacemit,k1-tsensor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 Thermal Sensor + +description: + The SpacemiT K1 Thermal Sensor monitors the temperature of the SoC + using multiple internal sensors (e.g., soc, package, gpu, clusters). + +maintainers: + - Shuwei Wu <shuwei.wu@mailbox.org> + +$ref: thermal-sensor.yaml# + +properties: + compatible: + const: spacemit,k1-tsensor + + reg: + maxItems: 1 + + clocks: + items: + - description: Core clock for thermal sensor + - description: Bus clock for thermal sensor + + clock-names: + items: + - const: core + - const: bus + + interrupts: + maxItems: 1 + + resets: + items: + - description: Reset for the thermal sensor + + "#thermal-sensor-cells": + const: 1 + description: + The first cell indicates the sensor ID. + 0 = soc + 1 = package + 2 = gpu + 3 = cluster0 + 4 = cluster1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - resets + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/spacemit,k1-syscon.h> + + thermal@d4018000 { + compatible = "spacemit,k1-tsensor"; + reg = <0xd4018000 0x100>; + clocks = <&syscon_apbc CLK_TSEN>, + <&syscon_apbc CLK_TSEN_BUS>; + clock-names = "core", "bus"; + interrupts = <61>; + resets = <&syscon_apbc RESET_TSEN>; + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml b/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml index b9022f1613d8..28f5818f1e60 100644 --- a/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml +++ b/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml @@ -44,10 +44,14 @@ select: true properties: "#cooling-cells": description: - Must be 2, in order to specify minimum and maximum cooling state used in + Must be 2 or 3. If 2, specifies minimum and maximum cooling state used in the cooling-maps reference. The first cell is the minimum cooling state and the second cell is the maximum cooling state requested. - const: 2 + If 3, the first cell specifies the thermal mitigation device specifier + index for devices that support multiple thermal mitigation mechanisms. + The two other cells are respectively the minimum cooling state and the + maximum cooling state. + enum: [2, 3] additionalProperties: true diff --git a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml index 07d9f576ffe7..999ad40a20d5 100644 --- a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml +++ b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml @@ -211,7 +211,8 @@ patternProperties: device. Using the THERMAL_NO_LIMIT (-1UL) constant in the cooling-device phandle limit specifier lets the framework use the minimum and maximum cooling state for that cooling - device automatically. + device automatically. If three arguments are specified, + the first argument is the cooling device specifier. contribution: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml index f1853daec2f9..3e2725c56995 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -15,9 +15,13 @@ properties: oneOf: - const: allwinner,sun5i-a13-hstimer - const: allwinner,sun7i-a20-hstimer + - const: allwinner,sun20i-d1-hstimer - items: - const: allwinner,sun6i-a31-hstimer - const: allwinner,sun7i-a20-hstimer + - items: + - const: allwinner,sun50i-h616-hstimer + - const: allwinner,sun20i-d1-hstimer reg: maxItems: 1 @@ -45,7 +49,10 @@ required: if: properties: compatible: - const: allwinner,sun5i-a13-hstimer + anyOf: + - const: allwinner,sun5i-a13-hstimer + - contains: + const: allwinner,sun20i-d1-hstimer then: properties: diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml index c5fc3b6c8bd0..c65e48a155ab 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -10,13 +10,8 @@ maintainers: - Marc Zyngier <marc.zyngier@arm.com> - Mark Rutland <mark.rutland@arm.com> description: |+ - ARM cores may have a per-core architected timer, which provides per-cpu timers, - or a memory mapped architected timer, which provides up to 8 frames with a - physical and optional virtual timer per frame. - - The per-core architected timer is attached to a GIC to deliver its - per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC - to deliver its interrupts via SPIs. + The per-core architected timer is expected to deliver per-CPU interrupts + (commonly to a GIC to deliver its per-processor interrupts as PPIs). properties: compatible: @@ -33,13 +28,13 @@ properties: - const: arm,armv7-timer interrupts: - minItems: 1 + minItems: 2 items: - - description: secure timer irq - - description: non-secure timer irq - - description: virtual timer irq - - description: hypervisor timer irq - - description: hypervisor virtual timer irq + - description: EL1 secure physical timer irq, if EL3 is implemented + - description: EL1 non-secure physical timer irq + - description: EL1 virtual timer irq + - description: EL2 physical timer irq, if EL2 is implemented + - description: EL2 virtual timer irq, if FEAT_VHE is implemented interrupt-names: oneOf: diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml index 9898dc7ea97b..6d41fb120379 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml @@ -14,6 +14,7 @@ properties: oneOf: - const: fsl,imx1-gpt - const: fsl,imx21-gpt + - const: fsl,imx25-epit - items: - const: fsl,imx27-gpt - const: fsl,imx21-gpt diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml index 3ad10c5b66ba..ecff2912d812 100644 --- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml @@ -112,6 +112,8 @@ properties: - renesas,r9a07g043-mtu3 # RZ/{G2UL,Five} - renesas,r9a07g044-mtu3 # RZ/G2{L,LC} - renesas,r9a07g054-mtu3 # RZ/V2L + - renesas,r9a09g077-mtu3 # RZ/T2H + - renesas,r9a09g087-mtu3 # RZ/N2H - const: renesas,rz-mtu3 reg: @@ -162,7 +164,6 @@ properties: - description: MTU8.TGRC input capture/compare match - description: MTU8.TGRD input capture/compare match - description: MTU8.TCNT overflow - - description: MTU8.TCNT underflow interrupt-names: items: @@ -209,7 +210,6 @@ properties: - const: tgic8 - const: tgid8 - const: tciv8 - - const: tciu8 clocks: maxItems: 1 @@ -233,7 +233,22 @@ required: - interrupt-names - clocks - power-domains - - resets + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-mtu3 + - renesas,r9a07g044-mtu3 + - renesas,r9a07g054-mtu3 + then: + required: + - resets + else: + properties: + resets: false additionalProperties: false @@ -287,8 +302,7 @@ examples: <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, - <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>; interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0", "tgif0", "tgia1", "tgib1", "tciv1", "tciu1", @@ -298,7 +312,7 @@ examples: "tgiu5", "tgiv5", "tgiw5", "tgia6", "tgib6", "tgic6", "tgid6", "tciv6", "tgia7", "tgib7", "tgic7", "tgid7", "tciv7", - "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8"; + "tgia8", "tgib8", "tgic8", "tgid8", "tciv8"; clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3c16b260db04..3673836e14de 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -38,6 +38,7 @@ properties: - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 + - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole - const: sifive,clint0 # SiFive CLINT v0 IP block - items: @@ -49,8 +50,10 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - canaan,k230-clint - sophgo,cv1800b-clint - sophgo,cv1812h-clint + - sophgo,sg2000-clint - sophgo,sg2002-clint - thead,th1520-clint - const: thead,c900-clint @@ -72,22 +75,6 @@ properties: minItems: 1 maxItems: 4095 - sifive,fine-ctr-bits: - maximum: 15 - description: The width in bits of the fine counter. - -if: - properties: - compatible: - contains: - const: sifive,clint2 -then: - required: - - sifive,fine-ctr-bits -else: - properties: - sifive,fine-ctr-bits: false - additionalProperties: false required: diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 23fd4513933a..2de8eb09cb7d 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -67,8 +67,10 @@ properties: - arduino,unoq-mcu # Temperature monitoring of Astera Labs PT5161L PCIe retimer - asteralabs,pt5161l - # i2c h/w elliptic curve crypto module + # ATECC508A - i2c h/w elliptic curve crypto module - atmel,atecc508a + # ATECC608B - i2c h/w elliptic curve crypto module + - atmel,atecc608b # ATSHA204 - i2c h/w symmetric crypto module - atmel,atsha204 # ATSHA204A - i2c h/w symmetric crypto module @@ -99,6 +101,8 @@ properties: - delta,dps800 # Delta Electronics DPS920AB 920W 54V Power Supply - delta,dps920ab + # 600W Non-isolated 1/8th Brick DC/DC Power Modules + - delta,e50sn12051 # 1/4 Brick DC/DC Regulated Power Module - delta,q54sj108a2 # 1300W 1/4 Brick DC/DC Regulated Power Module @@ -127,6 +131,8 @@ properties: - domintech,dmard09 # DMARD10: 3-axis Accelerometer - domintech,dmard10 + # Freescale 2.4 GHz IEEE® 802.15.4/ZigBee + - fsl,mc1323 # MMA7660FC: 3-Axis Orientation/Motion Detection Sensor - fsl,mma7660 # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer @@ -190,8 +196,12 @@ properties: - isil,isl76682 # JEDEC JESD300 (SPD5118) Hub and Serial Presence Detect - jedec,spd5118 + # Kandou KB9002 PCIe 5.0 retimer + - kandou,kb9002 # Linear Technology LTC2488 - lineartechnology,ltc2488 + # Regulated 12V, 860W, Digital DC/DC Power Module + - luxshare,lx1308 # 5 Bit Programmable, Pulse-Width Modulator - maxim,ds1050 # 10 kOhm digital potentiometer with I2C interface @@ -336,6 +346,8 @@ properties: - mps,mp29612 # Monolithic Power Systems Inc. multi-phase controller mp29816 - mps,mp29816 + # Monolithic Power Systems Inc. multi-phase controller mp2985 + - mps,mp2985 # Monolithic Power Systems Inc. multi-phase controller mp2993 - mps,mp2993 # Monolithic Power Systems Inc. hot-swap protection device @@ -352,6 +364,10 @@ properties: - mps,mp9941 # Monolithic Power Systems Inc. digital step-down converter mp9945 - mps,mp9945 + # Monolithic Power Systems Inc. digital step-down converter mpq82d00 + - mps,mpq82d00 + # Murata D1U74T-W power supply unit + - murata,d1u74t # Temperature sensor with integrated fan control - national,lm63 # Temperature sensor with integrated fan control diff --git a/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml index 75fae9f1eba7..66d73e9025d6 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml @@ -11,10 +11,21 @@ maintainers: properties: compatible: - const: qcom,sa8255p-ufshc + oneOf: + - const: qcom,sa8255p-ufshc + - items: + - const: qcom,sa8797p-ufshc + - const: qcom,sa8255p-ufshc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: std + - const: mcq interrupts: maxItems: 1 diff --git a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml index f28641c6e68f..d03295806657 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml @@ -16,7 +16,10 @@ select: contains: enum: - qcom,eliza-ufshc + - qcom,hawi-ufshc - qcom,kaanapali-ufshc + - qcom,maili-ufshc + - qcom,nord-ufshc - qcom,sm8650-ufshc - qcom,sm8750-ufshc required: @@ -27,7 +30,10 @@ properties: items: - enum: - qcom,eliza-ufshc + - qcom,hawi-ufshc - qcom,kaanapali-ufshc + - qcom,maili-ufshc + - qcom,nord-ufshc - qcom,sm8650-ufshc - qcom,sm8750-ufshc - const: qcom,ufshc @@ -74,6 +80,8 @@ allOf: contains: enum: - qcom,eliza-ufshc + - qcom,maili-ufshc + - qcom,nord-ufshc then: properties: reg: diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml index a7eb7ad85a94..710ce493f3b6 100644 --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml @@ -19,6 +19,7 @@ properties: - samsung,exynos7-ufs - samsung,exynosautov9-ufs - samsung,exynosautov9-ufs-vh + - samsung,exynosautov920-ufs - tesla,fsd-ufs reg: diff --git a/Documentation/devicetree/bindings/ufs/ufs-common.yaml b/Documentation/devicetree/bindings/ufs/ufs-common.yaml index ed97f5682509..cc32e1189d50 100644 --- a/Documentation/devicetree/bindings/ufs/ufs-common.yaml +++ b/Documentation/devicetree/bindings/ufs/ufs-common.yaml @@ -105,6 +105,64 @@ properties: Restricts the UFS controller to rate-a or rate-b for both TX and RX directions. + tx-precode-enable-g6: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + items: + - items: + - description: Host_Lane0 precode + enum: [0, 1] + - description: Device_Lane0 precode + enum: [0, 1] + - items: + - description: Host_Lane1 precode + enum: [0, 1] + - description: Device_Lane1 precode + enum: [0, 1] + description: + Static TX Precode enable values for HS-G6 only. + +patternProperties: + "^txeq-preshoot-g[1-6]$": + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + items: + - items: + - description: Host_Lane0 Preshoot value + enum: [0, 1, 2, 3, 4, 5, 6, 7] + - description: Device_Lane0 Preshoot value + enum: [0, 1, 2, 3, 4, 5, 6, 7] + - items: + - description: Host_Lane1 Preshoot value + enum: [0, 1, 2, 3, 4, 5, 6, 7] + - description: Device_Lane1 Preshoot value + enum: [0, 1, 2, 3, 4, 5, 6, 7] + description: | + Static TX Equalization PreShoot settings for High Speed Gears. These + values are programmed to the corresponding UniPro PA layer attribute + PA_TxEQG[1-6]Setting. Each value selects a Pre-Shoot level as defined + by the MIPI M-PHY specification (TX_HS_PreShoot_Setting). + + "^txeq-deemphasis-g[1-6]$": + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + items: + - items: + - description: Host_Lane0 DeEmphasis value + enum: [0, 1, 2, 3, 4, 5, 6, 7] + - description: Device_Lane0 DeEmphasis value + enum: [0, 1, 2, 3, 4, 5, 6, 7] + - items: + - description: Host_Lane1 DeEmphasis value + enum: [0, 1, 2, 3, 4, 5, 6, 7] + - description: Device_Lane1 DeEmphasis value + enum: [0, 1, 2, 3, 4, 5, 6, 7] + description: | + Static TX Equalization DeEmphasis settings for High Speed Gears. These + values are programmed to the corresponding UniPro PA layer attribute + PA_TxEQG[1-6]Setting. Each value selects a De-Emphasis level as defined + by the MIPI M-PHY specification (TX_HS_DeEmphasis_Setting). + dependencies: freq-table-hz: [ clocks ] operating-points-v2: [ clocks, clock-names ] diff --git a/Documentation/devicetree/bindings/usb/aspeed,dwc3.yaml b/Documentation/devicetree/bindings/usb/aspeed,dwc3.yaml new file mode 100644 index 000000000000..fff5a200f8c7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/aspeed,dwc3.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/aspeed,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed SuperSpeed DWC3 USB SoC controller + +maintainers: + - Ryan Chen <ryan_chen@aspeedtech.com> + +description: + The common content of the node is defined in snps,dwc3.yaml. + +select: + properties: + compatible: + contains: + const: aspeed,ast2700-xhci + required: + - compatible + +properties: + compatible: + items: + - const: aspeed,ast2700-xhci + - const: snps,dwc3 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Controller bus early clock + - description: PHY reference clock + - description: Controller suspend clock + + clock-names: + items: + - const: bus_early + - const: ref + - const: suspend + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: usb3-phy + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - phys + - phy-names + +allOf: + - $ref: snps,dwc3.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/aspeed,ast2700-scu.h> + #include <dt-bindings/reset/aspeed,ast2700-scu.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + usb@12030000 { + compatible = "aspeed,ast2700-xhci", "snps,dwc3"; + reg = <0x0 0x12030000 0x0 0x10000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>, + <&syscon0 SCU0_CLK_U2PHY_REFCLK>, + <&syscon0 SCU0_CLK_U2PHY_CLK12M>; + clock-names = "bus_early", "ref", "suspend"; + resets = <&syscon0 SCU0_RESET_PORTA_XHCI>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3axh_default &pinctrl_usb2axh_default>; + phys = <&uphy3a>; + phy-names = "usb3-phy"; + dr_mode = "host"; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml index a199e5ba6416..c14a88aad31e 100644 --- a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml +++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml @@ -4,29 +4,37 @@ $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence USBSS-DRD controller +title: Cadence USBSS and USBSSP DRD controller maintainers: - Pawel Laszczak <pawell@cadence.com> +description: + Cadence USB dual-role controller. Covers USBSS (SuperSpeed, USB 3.0) and + USBSSP (SuperSpeed Plus, USB 3.1 gen2x1). Both variants share the same + DRD/OTG register interface, so the driver auto-detects the controller + version at runtime. + properties: compatible: - const: cdns,usb3 + oneOf: + - const: cdns,usb3 + - items: + - {} + - const: cdns,cdnsp reg: - items: - - description: OTG controller registers - - description: XHCI Host controller registers - - description: DEVICE controller registers + minItems: 2 + maxItems: 3 reg-names: + minItems: 2 + maxItems: 3 items: - - const: otg - - const: xhci - - const: dev + enum: [ otg, xhci, dev ] interrupts: - minItems: 3 + minItems: 2 items: - description: XHCI host controller interrupt - description: Device controller interrupt @@ -35,13 +43,16 @@ properties: cleared by xhci core, this interrupt is optional interrupt-names: - minItems: 3 + minItems: 2 items: - const: host - const: peripheral - const: otg - const: wakeup + iommus: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port description: @@ -49,7 +60,7 @@ properties: cdns3 to type C connector. maximum-speed: - enum: [super-speed, high-speed, full-speed] + enum: [super-speed-plus, super-speed, high-speed, full-speed] phys: minItems: 1 @@ -87,6 +98,47 @@ allOf: - $ref: usb-drd.yaml# - $ref: usb-xhci.yaml# + - if: + properties: + compatible: + contains: + const: cdns,cdnsp + then: + properties: + reg: + items: + - description: XHCI Host controller registers + - description: DEVICE controller registers + reg-names: + items: + - const: xhci + - const: dev + interrupts: + maxItems: 2 + interrupt-names: + items: + - const: host + - const: peripheral + dr_mode: + enum: [host, peripheral] + else: + properties: + reg: + items: + - description: OTG controller registers + - description: XHCI Host controller registers + - description: DEVICE controller registers + reg-names: + items: + - const: otg + - const: xhci + - const: dev + interrupts: + minItems: 3 + maxItems: 4 + interrupt-names: + minItems: 3 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml b/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml index 10020af15afc..e6a5e79df348 100644 --- a/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml +++ b/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml @@ -97,7 +97,9 @@ properties: minItems: 1 items: - description: vbus extcon + maxItems: 1 - description: id extcon + maxItems: 1 phy-clkgate-delay-us: description: diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml index 691d6cf02c27..620b564914d4 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml @@ -45,11 +45,11 @@ properties: clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 operating-points-v2: description: A phandle to the OPP table containing the performance states. @@ -61,9 +61,10 @@ properties: offset, and phy index $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: phandle to TCSR node - - description: register offset - - description: phy index + - items: + - description: phandle to TCSR node + - description: register offset + - description: phy index nvidia,phy: description: phandle of usb phy that connects to the port. Use "phys" instead. @@ -91,6 +92,27 @@ allOf: - $ref: chipidea,usb2-common.yaml# - $ref: usb-hcd.yaml# - $ref: usb-drd.yaml# + - if: + properties: + compatible: + contains: + const: qcom,ci-hdrc + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + items: + - const: iface + - const: core + - const: fs + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml index 41c3b1b98991..658260619423 100644 --- a/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml +++ b/Documentation/devicetree/bindings/usb/eswin,eic7700-usb.yaml @@ -41,12 +41,13 @@ properties: - const: usb_en resets: - maxItems: 2 + maxItems: 3 reset-names: items: - const: vaux - const: usb_rst + - const: usb_phy eswin,hsp-sp-csr: description: @@ -85,8 +86,8 @@ examples: interrupt-parent = <&plic>; interrupts = <85>; interrupt-names = "peripheral"; - resets = <&reset 84>, <&hspcrg 2>; - reset-names = "vaux", "usb_rst"; + resets = <&reset 84>, <&hspcrg 2>, <&hspcrg 4>; + reset-names = "vaux", "usb_rst", "usb_phy"; dr_mode = "peripheral"; maximum-speed = "high-speed"; phy_type = "utmi"; diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml index 55a5aa7d7a54..ae9fb70d0212 100644 --- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml @@ -98,6 +98,10 @@ properties: - if a USB DRD channel: first clock should be host and second one should be peripheral + clock-names: + minItems: 1 + maxItems: 4 + power-domains: maxItems: 1 @@ -186,6 +190,9 @@ allOf: required: - clocks - clock-names + else: + properties: + clock-names: false unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml index d42f448fa204..322808aaa283 100644 --- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml +++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml @@ -83,6 +83,10 @@ properties: - if a USB DRD channel: first clock should be host and second one should be peripheral + clock-names: + minItems: 1 + maxItems: 4 + power-domains: maxItems: 1 @@ -182,6 +186,7 @@ allOf: else: properties: + clock-names: false atmel,vbus-gpio: false atmel,oc-gpio: false diff --git a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml index 9a94b2a74a1e..e8b8c03f87a0 100644 --- a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml +++ b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml @@ -15,6 +15,7 @@ properties: - usb5e3,608 - usb5e3,610 - usb5e3,620 + - usb5e3,625 - usb5e3,626 reg: true @@ -26,6 +27,10 @@ properties: description: The regulator that provides 3.3V or 5.0V core power to the hub. + vdd12-supply: + description: + The regulator that provides 1.2V power to the hub. + peer-hub: true ports: @@ -56,6 +61,7 @@ allOf: properties: peer-hub: false vdd-supply: false + vdd12-supply: false - if: properties: @@ -68,6 +74,18 @@ allOf: properties: peer-hub: true vdd-supply: true + vdd12-supply: false + + - if: + properties: + compatible: + contains: + enum: + - usb5e3,625 + then: + properties: + peer-hub: true + vdd-supply: true unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 21fc6bbe954f..d148e938d647 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -28,6 +28,7 @@ properties: - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 + - mediatek,mt8196-mtu3 - mediatek,mt8365-mtu3 - const: mediatek,mtu3 @@ -200,7 +201,10 @@ properties: 103 - used by mt8195, IP0, specific 1.03; 105 - used by mt8195, IP2, specific 1.05; 106 - used by mt8195, IP3, specific 1.06; - enum: [1, 2, 101, 102, 103, 105, 106] + 107 - used by mt8196, IP0, specific 1.07; + 108 - used by mt8196, IP1, specific 1.08; + 109 - used by mt8196, IP2, specific 1.09; + enum: [1, 2, 101, 102, 103, 105, 106, 107, 108, 109] mediatek,u3p-dis-msk: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index a7f58114c02e..90daee616880 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -92,14 +92,14 @@ properties: clocks: description: | - Several clocks are used, depending on the variant. Typical ones are:: - - cfg_noc:: System Config NOC clock. - - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= + Several clocks are used, depending on the variant. Typical ones are: + - cfg_noc: System Config NOC clock. + - core: Master/Core clock, has to be >= 125 MHz for SS operation and >= 60MHz for HS operation. - - iface:: System bus AXI clock. - - sleep:: Sleep clock, used for wakeup when USB3 core goes into low + - iface: System bus AXI clock. + - sleep: Sleep clock, used for wakeup when USB3 core goes into low power mode (U3). - - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host + - mock_utmi: Mock utmi clock needed for ITP/SOF generation in host mode. Its frequency should be 19.2MHz. minItems: 1 maxItems: 9 diff --git a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml index 6d3fa2bc9cee..ba790c4488b7 100644 --- a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml @@ -79,22 +79,17 @@ properties: - const: fr-swap vdd-vbus-supply: - description: VBUS power supply. + deprecated: true + description: use connector/vbus-supply instead. vdd-pdphy-supply: description: VDD regulator supply to the PDPHY. - port: - $ref: /schemas/graph.yaml#/properties/port - description: - Contains a port which produces data-role switching messages. - required: - compatible - reg - interrupts - interrupt-names - - vdd-vbus-supply allOf: - if: diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml index 8201656b41ed..ea60f7220afe 100644 --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml @@ -29,6 +29,7 @@ properties: - qcom,glymur-dwc3-mp - qcom,ipq4019-dwc3 - qcom,ipq5018-dwc3 + - qcom,ipq5210-dwc3 - qcom,ipq5332-dwc3 - qcom,ipq5424-dwc3 - qcom,ipq6018-dwc3 @@ -36,6 +37,7 @@ properties: - qcom,ipq8074-dwc3 - qcom,ipq9574-dwc3 - qcom,kaanapali-dwc3 + - qcom,maili-dwc3 - qcom,milos-dwc3 - qcom,msm8953-dwc3 - qcom,msm8994-dwc3 @@ -60,6 +62,7 @@ properties: - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 + - qcom,shikra-dwc3 - qcom,sm4250-dwc3 - qcom,sm6115-dwc3 - qcom,sm6125-dwc3 @@ -87,14 +90,14 @@ properties: clocks: description: | - Several clocks are used, depending on the variant. Typical ones are:: - - cfg_noc:: System Config NOC clock. - - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= + Several clocks are used, depending on the variant. Typical ones are: + - cfg_noc: System Config NOC clock. + - core: Master/Core clock, has to be >= 125 MHz for SS operation and >= 60MHz for HS operation. - - iface:: System bus AXI clock. - - sleep:: Sleep clock, used for wakeup when USB3 core goes into low + - iface: System bus AXI clock. + - sleep: Sleep clock, used for wakeup when USB3 core goes into low power mode (U3). - - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host + - mock_utmi: Mock utmi clock needed for ITP/SOF generation in host mode. Its frequency should be 19.2MHz. minItems: 1 maxItems: 9 @@ -203,9 +206,11 @@ allOf: compatible: contains: enum: + - qcom,ipq5210-dwc3 - qcom,ipq5424-dwc3 - qcom,ipq9574-dwc3 - qcom,kaanapali-dwc3 + - qcom,maili-dwc3 - qcom,msm8953-dwc3 - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 @@ -218,6 +223,7 @@ allOf: - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 + - qcom,shikra-dwc3 - qcom,sm6350-dwc3 - qcom,sm8750-dwc3 then: @@ -497,6 +503,7 @@ allOf: compatible: contains: enum: + - qcom,ipq5210-dwc3 - qcom,ipq5424-dwc3 - qcom,ipq9574-dwc3 then: @@ -543,6 +550,7 @@ allOf: - qcom,ipq4019-dwc3 - qcom,ipq8064-dwc3 - qcom,kaanapali-dwc3 + - qcom,maili-dwc3 - qcom,qcs615-dwc3 - qcom,qcs8300-dwc3 - qcom,qdu1000-dwc3 @@ -556,6 +564,7 @@ allOf: - qcom,sdx55-dwc3 - qcom,sdx65-dwc3 - qcom,sdx75-dwc3 + - qcom,shikra-dwc3 - qcom,sm6350-dwc3 - qcom,sm6375-dwc3 - qcom,sm8150-dwc3 diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index dc74e70f1b92..13715b7c94c8 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -27,6 +27,7 @@ properties: - renesas,usbhs-r9a07g044 # RZ/G2{L,LC} - renesas,usbhs-r9a07g054 # RZ/V2L - renesas,usbhs-r9a08g045 # RZ/G3S + - renesas,usbhs-r9a08g046 # RZ/G3L - renesas,usbhs-r9a09g047 # RZ/G3E - renesas,usbhs-r9a09g056 # RZ/V2N - renesas,usbhs-r9a09g057 # RZ/V2H(P) diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt b/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt deleted file mode 100644 index 6f8115db2ea9..000000000000 --- a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt +++ /dev/null @@ -1,44 +0,0 @@ -Richtek RT1711H TypeC PD Controller. - -Required properties: - - compatible : Must be "richtek,rt1711h". - - reg : Must be 0x4e, it's slave address of RT1711H. - - interrupts : <a b> where a is the interrupt number and b represents an - encoding of the sense and level information for the interrupt. - -Required sub-node: -- connector: The "usb-c-connector" attached to the tcpci chip, the bindings - of connector node are specified in - Documentation/devicetree/bindings/connector/usb-connector.yaml - -Example : -rt1711h@4e { - compatible = "richtek,rt1711h"; - reg = <0x4e>; - interrupt-parent = <&gpio26>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; - sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM) - PDO_VAR(5000, 12000, 2000)>; - op-sink-microwatt = <10000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - usb_con_ss: endpoint { - remote-endpoint = <&usb3_data_ss>; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml b/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml index 7ded36384518..e3357f5abe2b 100644 --- a/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml +++ b/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml @@ -43,8 +43,7 @@ properties: vbus-supply: description: VBUS power supply - wakeup-source: - type: boolean + wakeup-source: true connector: type: object diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml index fd1b13c0ed6b..0554dbc4b854 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -26,6 +26,7 @@ select: contains: enum: - rockchip,rk3328-dwc3 + - rockchip,rk3528-dwc3 - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 @@ -38,6 +39,7 @@ properties: items: - enum: - rockchip,rk3328-dwc3 + - rockchip,rk3528-dwc3 - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 @@ -135,6 +137,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3528-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 then: diff --git a/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml b/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml index 653a89586f4e..0aaaadb584e4 100644 --- a/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml +++ b/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml @@ -88,7 +88,7 @@ examples: power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ + assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ #address-cells = <2>; #size-cells = <2>; @@ -99,9 +99,9 @@ examples: <0x00 0x6010000 0x00 0x10000>, <0x00 0x6020000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ interrupt-names = "host", "peripheral", "otg"; diff --git a/Documentation/devicetree/bindings/usb/ti,omap4-musb.yaml b/Documentation/devicetree/bindings/usb/ti,omap4-musb.yaml index a3d15f217658..e1887e490e02 100644 --- a/Documentation/devicetree/bindings/usb/ti,omap4-musb.yaml +++ b/Documentation/devicetree/bindings/usb/ti,omap4-musb.yaml @@ -81,9 +81,7 @@ properties: const: usb2-phy usb-phy: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: Phandle for the PHY device. - deprecated: true + maxItems: 1 ctrl-module: $ref: /schemas/types.yaml#/definitions/phandle @@ -96,6 +94,9 @@ required: - interrupts - interrupt-names +allOf: + - $ref: usb-hcd.yaml# + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml b/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml index 1745e28b3110..2c589e9e712e 100644 --- a/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml +++ b/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml @@ -4,13 +4,14 @@ $id: http://devicetree.org/schemas/usb/ti,tps6598x.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Texas Instruments 6598x Type-C Port Switch and Power Delivery controller +title: Texas Instruments Type-C port switch and USB Power Delivery controllers maintainers: - Bryan O'Donoghue <bryan.odonoghue@linaro.org> description: | - Texas Instruments 6598x Type-C Port Switch and Power Delivery controller + Texas Instruments 6598x and 66993 Type-C Port Switch and Power Delivery + controller. A variant of this controller known as Apple CD321x or Apple ACE is also present on hardware with Apple SoCs such as the M1. @@ -19,6 +20,7 @@ properties: compatible: enum: - ti,tps6598x + - ti,tps66993 - apple,cd321x - ti,tps25750 diff --git a/Documentation/devicetree/bindings/usb/ti,twl4030-usb.yaml b/Documentation/devicetree/bindings/usb/ti,twl4030-usb.yaml index 6ef337507425..c338ad0368de 100644 --- a/Documentation/devicetree/bindings/usb/ti,twl4030-usb.yaml +++ b/Documentation/devicetree/bindings/usb/ti,twl4030-usb.yaml @@ -67,7 +67,7 @@ examples: usb1v5-supply = <®_vusb1v5>; usb1v8-supply = <®_vusb1v8>; - usb3v1-supply = <®_vusb3v1>; + usb3v1-supply = <®_vusb3v1>; usb_mode = <1>; #phy-cells = <0>; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7b..ba2002969373 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -88,6 +88,8 @@ patternProperties: description: ALFA Network Inc. "^algoltek,.*": description: AlgolTek, Inc. + "^alientek,.*": + description: Guangzhou Xingyi Intelligent Technology Co., Ltd. "^allegro,.*": description: Allegro DVT "^allegromicro,.*": @@ -225,10 +227,14 @@ patternProperties: description: Axis Communications AB "^ayaneo,.*": description: Anyun Intelligent Technology (Hong Kong) Co., Ltd + "^ayntec,.*": + description: AYN Technologies Co., Ltd. "^azoteq,.*": description: Azoteq (Pty) Ltd "^azw,.*": description: Shenzhen AZW Technology Co., Ltd. + "^baijie,.*": + description: Shenzhen Baijie Technology Co., Ltd. "^baikal,.*": description: BAIKAL ELECTRONICS, JSC "^bananapi,.*": @@ -407,6 +413,8 @@ patternProperties: description: DataImage, Inc. "^davicom,.*": description: DAVICOM Semiconductor, Inc. + "^dcltek,.*": + description: DCL Technologies Inc. "^deepcomputing,.*": description: DeepComputing (HK) Limited "^dell,.*": @@ -437,6 +445,8 @@ patternProperties: description: Diodes, Inc. "^dioo,.*": description: Dioo Microcircuit Co., Ltd + "^displaytech,.*": + description: Displaytech Ltd. "^djn,.*": description: Shenzhen DJN Optronics Technology Co., Ltd "^dlc,.*": @@ -455,6 +465,8 @@ patternProperties: description: Dongwoon Anatech "^dptechnics,.*": description: DPTechnics + "^dptel,.*": + description: Guangdong Dapu Telecom Co., Ltd. "^dragino,.*": description: Dragino Technology Co., Limited "^dream,.*": @@ -489,6 +501,8 @@ patternProperties: description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc + "^efinix,.*": + description: Efinix, Inc. "^egnite,.*": description: egnite GmbH "^einfochips,.*": @@ -600,6 +614,8 @@ patternProperties: description: Flipkart Inc. "^focaltech,.*": description: FocalTech Systems Co.,Ltd + "^focuslcds,.*": + description: Focus Display Solutions, Inc. "^forlinx,.*": description: Baoding Forlinx Embedded Technology Co., Ltd. "^foursemi,.*": @@ -656,6 +672,8 @@ patternProperties: description: Giantec Semiconductor, Inc. "^giantplus,.*": description: Giantplus Technology Co., Ltd. + "^gira,.*": + description: Gira Giersiepen GmbH & Co. KG "^glinet,.*": description: GL Intelligence, Inc. "^globalscale,.*": @@ -676,6 +694,8 @@ patternProperties: description: Goramo Gorecki "^gplus,.*": description: GPLUS + "^graperain,.*": + description: Shenzhen Graperain Technology Co., Ltd. "^grinn,.*": description: Grinn "^grmn,.*": @@ -686,6 +706,8 @@ patternProperties: description: Gateworks Corporation use "gateworks" vendor prefix deprecated: true + "^gxcas,.*": + description: Beijing Galaxy-CAS Technology Co., Ltd. "^hannstar,.*": description: HannStar Display Corporation "^haochuangyi,.*": @@ -729,6 +751,8 @@ patternProperties: description: Honestar Technologies Co., Ltd. "^honeywell,.*": description: Honeywell + "^honor,.*": + description: Honor Device Co., Ltd. "^hoperf,.*": description: Shenzhen Hope Microelectronics Co., Ltd. "^hoperun,.*": @@ -783,6 +807,8 @@ patternProperties: description: ILI Technology Corporation (ILITEK) "^imagis,.*": description: Imagis Technologies Co., Ltd. + "^imdt,.*": + description: IMD Technologies Ltd. "^img,.*": description: Imagination Technologies Ltd. "^imi,.*": @@ -873,6 +899,8 @@ patternProperties: description: JuTouch Technology Co., Ltd. "^kam,.*": description: Kamstrup A/S + "^kandou,.*": + description: Kandou AI "^karo,.*": description: Ka-Ro electronics GmbH "^keithkoep,.*": @@ -981,6 +1009,8 @@ patternProperties: description: Shenzhen Luckfox Technology Co., Ltd. "^lunzn,.*": description: Shenzhen Lunzn Technology Co., Ltd. + "^luxshare,.*": + description: Luxshare-ICT Co., Ltd. "^luxul,.*": description: Lagrand | AV "^lwn,.*": @@ -1241,6 +1271,8 @@ patternProperties: description: OpenWrt "^option,.*": description: Option NV + "^optologic,.*": + description: Opto Logic S.A. "^oranth,.*": description: Shenzhen Oranth Technology Co., Ltd. "^ORCL,.*": @@ -1355,6 +1387,8 @@ patternProperties: description: Shenzhen QiShenglong Industrialist Co., Ltd. "^qnap,.*": description: QNAP Systems, Inc. + "^qstcorp,.*": + description: QST Corporation Limited "^quanta,.*": description: Quanta Computer Inc. "^radxa,.*": @@ -1403,6 +1437,8 @@ patternProperties: description: Embest RIoT "^riscv,.*": description: RISC-V Foundation + "^riverdi,.*": + description: Riverdi Sp. z o.o "^rockchip,.*": description: Rockchip Electronics Co., Ltd. "^rocktech,.*": @@ -1654,6 +1690,8 @@ patternProperties: description: Technologic Systems "^techstar,.*": description: Shenzhen Techstar Electronics Co., Ltd. + "^techvision,.*": + description: Techvision Intelligent Technology Co., Ltd "^techwell,.*": description: Techwell, Inc. "^teejet,.*": @@ -1783,6 +1821,8 @@ patternProperties: description: Variscite Ltd. "^vdl,.*": description: Van der Laan b.v. + "^verbatim,.*": + description: Verbatim Corporation "^verisilicon,.*": description: VeriSilicon Microelectronics (Shanghai) Co., Ltd. "^vertexcom,.*": @@ -1791,6 +1831,8 @@ patternProperties: description: VIA Technologies, Inc. "^vialab,.*": description: VIA Labs, Inc. + "^vicharak,.*": + description: Vicharak Computers Pvt. Ltd. "^vicor,.*": description: Vicor Corporation "^videostrong,.*": @@ -1915,6 +1957,8 @@ patternProperties: description: YSH & ATIL "^yones-toptech,.*": description: Yones Toptech Co., Ltd. + "^youyeetoo,.*": + description: Hong Kong Cybodev Tech Limited (youyeetoo) "^ys,.*": description: Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. "^ysoft,.*": diff --git a/Documentation/devicetree/bindings/w1/omap-hdq.txt b/Documentation/devicetree/bindings/w1/omap-hdq.txt deleted file mode 100644 index 913c5f91a0f9..000000000000 --- a/Documentation/devicetree/bindings/w1/omap-hdq.txt +++ /dev/null @@ -1,22 +0,0 @@ -* OMAP HDQ One wire bus master controller - -Required properties: -- compatible : should be "ti,omap3-1w" or "ti,am4372-hdq" -- reg : Address and length of the register set for the device -- interrupts : interrupt line. -- ti,hwmods : "hdq1w" - -Optional properties: -- ti,mode: should be "hdq": HDQ mode "1w": one-wire mode. - If not specified HDQ mode is implied. - -Example: - -- From omap3.dtsi - hdqw1w: 1w@480b2000 { - compatible = "ti,omap3-1w"; - reg = <0x480b2000 0x1000>; - interrupts = <58>; - ti,hwmods = "hdq1w"; - ti,mode = "hdq"; - }; diff --git a/Documentation/devicetree/bindings/w1/ti,hdq.yaml b/Documentation/devicetree/bindings/w1/ti,hdq.yaml new file mode 100644 index 000000000000..fd402c0510db --- /dev/null +++ b/Documentation/devicetree/bindings/w1/ti,hdq.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/w1/ti,hdq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments OMAP HDQ One Wire Bus Master Controller + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +properties: + compatible: + enum: + - ti,omap3-1w + - ti,am4372-hdq + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: fck + + ti,hwmods: + description: Name of the hwmod associated to the hdq + $ref: /schemas/types.yaml#/definitions/string + const: hdq1w + + ti,mode: + description: | + Operation mode. "hdq" for HDQ mode, "1w" for One-Wire mode. + If not specified, HDQ mode is implied. + $ref: /schemas/types.yaml#/definitions/string + enum: + - hdq + - 1w + default: hdq + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + onewire@0 { + compatible = "ti,am4372-hdq"; + reg = <0x0 0x1000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&func_12m_clk>; + clock-names = "fck"; + }; + - | + onewire@480b2000 { + compatible = "ti,omap3-1w"; + reg = <0x480b2000 0x1000>; + interrupts = <58>; + ti,hwmods = "hdq1w"; + ti,mode = "hdq"; + }; diff --git a/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml new file mode 100644 index 000000000000..f1107c552788 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/andestech,ae350-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes ATCWDT200 Watchdog Timer + +maintainers: + - CL Wang <cl634@andestech.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-wdt + - const: andestech,ae350-wdt + - const: andestech,ae350-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + andestech,clock-source: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Select the clock source for the watchdog timer. + 0 - External clock + 1 - P clock + +required: + - compatible + - reg + - clocks + - andestech,clock-source + +unevaluatedProperties: false + +examples: + - | + watchdog@f0500000 { + compatible = "andestech,ae350-wdt"; + reg = <0xf0500000 0x20>; + clocks = <&clk_wdt>; + andestech,clock-source = <0>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml index 05602678c070..ca4cf01db59f 100644 --- a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -16,7 +16,12 @@ properties: compatible: oneOf: - items: - - const: apple,t6020-wdt + - enum: + - apple,t6020-wdt + - apple,t6030-wdt + - apple,t6031-wdt + - apple,t8122-wdt + - apple,t8132-wdt - const: apple,t8103-wdt - items: - enum: diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml index 0821ba0e84a3..872a8471ef65 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -18,12 +18,7 @@ allOf: properties: compatible: - oneOf: - - items: - - enum: - - kontron,sa67mcu-wdt - - const: kontron,sl28cpld-wdt - - const: kontron,sl28cpld-wdt + const: kontron,sl28cpld-wdt reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt b/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt deleted file mode 100644 index 49485f831373..000000000000 --- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Microchip PIC32 Deadman Timer - -The deadman timer is used to reset the processor in the event of a software -malfunction. It is a free-running instruction fetch timer, which is clocked -whenever an instruction fetch occurs until a count match occurs. - -Required properties: -- compatible: must be "microchip,pic32mzda-dmt". -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: phandle of source clk. Should be <&rootclk PB7CLK>. - -Example: - - watchdog@1f800a00 { - compatible = "microchip,pic32mzda-dmt"; - reg = <0x1f800a00 0x80>; - clocks = <&rootclk PB7CLK>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt b/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt deleted file mode 100644 index f03a29a1b323..000000000000 --- a/Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt +++ /dev/null @@ -1,18 +0,0 @@ -* Microchip PIC32 Watchdog Timer - -When enabled, the watchdog peripheral can be used to reset the device if the -WDT is not cleared periodically in software. - -Required properties: -- compatible: must be "microchip,pic32mzda-wdt". -- reg: physical base address of the controller and length of memory mapped - region. -- clocks: phandle of source clk. Should be <&rootclk LPRCCLK>. - -Example: - - watchdog@1f800800 { - compatible = "microchip,pic32mzda-wdt"; - reg = <0x1f800800 0x200>; - clocks = <&rootclk LPRCCLK>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-dmt.yaml b/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-dmt.yaml new file mode 100644 index 000000000000..01638624e334 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-dmt.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/microchip,pic32mzda-dmt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32MZDA Deadman Timer + +maintainers: + - Thomas Bogendoerfer <tsbogend@alpha.franken.de> + +description: | + The deadman timer is used to reset the processor in the event of a software + malfunction. It is a free-running instruction fetch timer, which is clocked + whenever an instruction fetch occurs until a count match occurs. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: microchip,pic32mzda-dmt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/microchip,pic32-clock.h> + + watchdog@1f800a00 { + compatible = "microchip,pic32mzda-dmt"; + reg = <0x1f800a00 0x80>; + clocks = <&rootclk PB7CLK>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-wdt.yaml b/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-wdt.yaml new file mode 100644 index 000000000000..a5dd633c3e78 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/microchip,pic32mzda-wdt.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/microchip,pic32mzda-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC32MZDA Watchdog Timer + +maintainers: + - Thomas Bogendoerfer <tsbogend@alpha.franken.de> + +description: + The PIC32 watchdog timer can be used to reset the device if software fails + to periodically service the watchdog. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + const: microchip,pic32mzda-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/microchip,pic32-clock.h> + + watchdog@1f800800 { + compatible = "microchip,pic32mzda-wdt"; + reg = <0x1f800800 0x200>; + clocks = <&rootclk LPRCCLK>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,ma35d1-wdt.yaml b/Documentation/devicetree/bindings/watchdog/nuvoton,ma35d1-wdt.yaml new file mode 100644 index 000000000000..aced7d77a7d3 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,ma35d1-wdt.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/nuvoton,ma35d1-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 Watchdog Timer + +maintainers: + - Zi-Yu Chen <zychennvt@gmail.com> + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - nuvoton,ma35d1-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + wakeup-source: true + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + wdt1: watchdog@40440000 { + compatible = "nuvoton,ma35d1-wdt"; + reg = <0x0 0x40440000 0x0 0x100>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk WDT1_GATE>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml index 7aa30f5b5c49..81269fdc81a5 100644 --- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml @@ -16,6 +16,14 @@ description: allOf: - $ref: watchdog.yaml# + - if: + properties: + compatible: + contains: + const: nuvoton,wpcm450-wdt + then: + properties: + nuvoton,sysgcr: false properties: compatible: @@ -40,6 +48,12 @@ properties: clock-frequency: description: Frequency in Hz of the clock that drives the NPCM timer. + nuvoton,sysgcr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + a phandle to access the GCR reset-status registers that latch + watchdog reset indications on NPCM750 and NPCM845. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 9f861045b71e..4ff61102e407 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -18,15 +18,20 @@ properties: - items: - enum: - qcom,apss-wdt-glymur + - qcom,apss-wdt-hawi - qcom,kpss-wdt-ipq4019 - qcom,apss-wdt-ipq5018 + - qcom,apss-wdt-ipq5210 - qcom,apss-wdt-ipq5332 - qcom,apss-wdt-ipq5424 - qcom,apss-wdt-ipq9574 + - qcom,apss-wdt-ipq9650 - qcom,apss-wdt-kaanapali + - qcom,apss-wdt-maili - qcom,apss-wdt-msm8226 - qcom,apss-wdt-msm8974 - qcom,apss-wdt-msm8994 + - qcom,apss-wdt-nord - qcom,apss-wdt-qcm2290 - qcom,apss-wdt-qcs404 - qcom,apss-wdt-qcs615 @@ -40,6 +45,7 @@ properties: - qcom,apss-wdt-sdm845 - qcom,apss-wdt-sdx55 - qcom,apss-wdt-sdx65 + - qcom,apss-wdt-shikra - qcom,apss-wdt-sm6115 - qcom,apss-wdt-sm6350 - qcom,apss-wdt-sm8150 @@ -84,6 +90,12 @@ properties: minItems: 1 maxItems: 5 + sram: + maxItems: 1 + description: + A reference to an region residing in IMEM(on-chip SRAM), which contains + the system restart reason value populated by the bootloader. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml index 099200c4f136..975c5aa4d747 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml @@ -89,11 +89,11 @@ examples: - | #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> - watchdog@11c00400 { + watchdog@14400000 { compatible = "renesas,r9a09g057-wdt"; - reg = <0x11c00400 0x400>; - clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; + reg = <0x14400000 0x400>; + clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; clock-names = "pclk", "oscclk"; - resets = <&cpg 0x75>; + resets = <&cpg 0x76>; power-domains = <&cpg>; }; diff --git a/Documentation/devicetree/bindings/watchdog/renesas,rzg2l-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,rzg2l-wdt.yaml index a4d06c9c8b86..40b4fb26d9c5 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,rzg2l-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,rzg2l-wdt.yaml @@ -18,6 +18,7 @@ properties: - renesas,r9a07g044-wdt # RZ/G2{L,LC} - renesas,r9a07g054-wdt # RZ/V2L - renesas,r9a08g045-wdt # RZ/G3S + - renesas,r9a08g046-wdt # RZ/G3L - const: renesas,rzg2l-wdt - items: diff --git a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml index 7e3ee533cd56..0e4b5b529e9c 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml @@ -29,7 +29,6 @@ properties: required: - compatible - reg - - interrupts - clocks allOf: diff --git a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml index 609e98cdaaff..2b16b7c2787b 100644 --- a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml @@ -29,10 +29,13 @@ properties: - rockchip,rk3368-wdt - rockchip,rk3399-wdt - rockchip,rk3506-wdt + - rockchip,rk3528-wdt - rockchip,rk3562-wdt - rockchip,rk3568-wdt - rockchip,rk3576-wdt - rockchip,rk3588-wdt + - rockchip,rv1103b-wdt + - rockchip,rv1106-wdt - rockchip,rv1108-wdt - rockchip,rv1126-wdt - const: snps,dw-wdt diff --git a/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml b/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml new file mode 100644 index 000000000000..5c2541ac60cf --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/technologic,ts4800-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems TS-4800 Watchdog + +maintainers: + - Eduard Bostina <egbostina@gmail.com> + +properties: + compatible: + const: technologic,ts4800-wdt + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the FPGA's syscon + - description: Offset to the watchdog register + description: Phandle / integers array that points to the syscon node which + describes the FPGA's syscon registers. + +required: + - compatible + - syscon + +allOf: + - $ref: watchdog.yaml# + +unevaluatedProperties: false + +examples: + - | + watchdog { + compatible = "technologic,ts4800-wdt"; + syscon = <&syscon 0xe>; + timeout-sec = <10>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml index 62ddc284a524..2966e5bfb6c0 100644 --- a/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml @@ -23,6 +23,7 @@ allOf: properties: compatible: enum: + - ti,am62l-rti-wdt - ti,j7-rti-wdt reg: diff --git a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt b/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt deleted file mode 100644 index 8f6caad4258d..000000000000 --- a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt +++ /dev/null @@ -1,25 +0,0 @@ -Technologic Systems Watchdog - -Required properties: -- compatible: must be "technologic,ts4800-wdt" -- syscon: phandle / integer array that points to the syscon node which - describes the FPGA's syscon registers. - - phandle to FPGA's syscon - - offset to the watchdog register - -Optional property: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -syscon: syscon@b0010000 { - compatible = "syscon", "simple-mfd"; - reg = <0xb0010000 0x3d>; - reg-io-width = <2>; - - wdt@e { - compatible = "technologic,ts4800-wdt"; - syscon = <&syscon 0xe>; - timeout-sec = <10>; - }; -} diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index 667816dd7d50..1a51764833a1 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -53,7 +53,17 @@ Properties - DON'T use wildcards or device-family names in compatible strings. - DO use fallback compatibles when devices are the same as or a superset of - prior implementations. + prior implementations. Fallback compatibles are applicable especially + when sharing a programming interface or when able to discover the + variants. + + - DON'T add fake fallback compatibles when software cannot use such to match + and bind to a device, and still operate correctly. + + - DO use the commit message to explain why devices that may appear + compatible in a diff (e.g. no differences in property use, same handling + by the software) but are not made compatible in the binding, are not + compatible. - DO add new compatibles in case there are new features or bugs. diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index 2ff5b0565a31..d31b94300f46 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -127,12 +127,19 @@ additionalProperties / unevaluatedProperties two above cases ('false'). examples - Optional. A list of one or more DTS hunks implementing this binding only. - Example should not contain unrelated device nodes, e.g. consumer nodes in a - provider binding, other nodes referenced by phandle. + Optional, although expected outside of bindings describing common properties + or sub-blocks of more complex devices. A list of one or more DTS hunks + implementing this binding only. Example should not contain unrelated device + nodes, e.g. consumer nodes in a provider binding, other nodes referenced by + phandles or node labels which are not directly referenced in the example + itself. Phandles in the example do not have to be resolvable. The example + must be complete as much as possible - have most of the properties - and look + readable to developers, thus for example use known defines for interrupt or + GPIO flags. Example should not contain 'status' property in typical cases. + Note: YAML doesn't allow leading tabs, so spaces must be used instead. -Unless noted otherwise, all properties are required. +Unless noted otherwise, all above schema properties are required. Property Schema --------------- diff --git a/Documentation/devicetree/bindings/xilinx.txt b/Documentation/devicetree/bindings/xilinx.txt index 0ee9de99b3ae..a1a2cde7b7d8 100644 --- a/Documentation/devicetree/bindings/xilinx.txt +++ b/Documentation/devicetree/bindings/xilinx.txt @@ -1,93 +1,4 @@ - d) Xilinx IP cores - - The Xilinx EDK toolchain ships with a set of IP cores (devices) for use - in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range - of standard device types (network, serial, etc.) and miscellaneous - devices (gpio, LCD, spi, etc). Also, since these devices are - implemented within the fpga fabric every instance of the device can be - synthesised with different options that change the behaviour. - - Each IP-core has a set of parameters which the FPGA designer can use to - control how the core is synthesized. Historically, the EDK tool would - extract the device parameters relevant to device drivers and copy them - into an 'xparameters.h' in the form of #define symbols. This tells the - device drivers how the IP cores are configured, but it requires the kernel - to be recompiled every time the FPGA bitstream is resynthesized. - - The new approach is to export the parameters into the device tree and - generate a new device tree each time the FPGA bitstream changes. The - parameters which used to be exported as #defines will now become - properties of the device node. In general, device nodes for IP-cores - will take the following form: - - (name): (generic-name)@(base-address) { - compatible = "xlnx,(ip-core-name)-(HW_VER)" - [, (list of compatible devices), ...]; - reg = <(baseaddr) (size)>; - interrupt-parent = <&interrupt-controller-phandle>; - interrupts = < ... >; - xlnx,(parameter1) = "(string-value)"; - xlnx,(parameter2) = <(int-value)>; - }; - - (generic-name): an open firmware-style name that describes the - generic class of device. Preferably, this is one word, such - as 'serial' or 'ethernet'. - (ip-core-name): the name of the ip block (given after the BEGIN - directive in system.mhs). Should be in lowercase - and all underscores '_' converted to dashes '-'. - (name): is derived from the "PARAMETER INSTANCE" value. - (parameter#): C_* parameters from system.mhs. The C_ prefix is - dropped from the parameter name, the name is converted - to lowercase and all underscore '_' characters are - converted to dashes '-'. - (baseaddr): the baseaddr parameter value (often named C_BASEADDR). - (HW_VER): from the HW_VER parameter. - (size): the address range size (often C_HIGHADDR - C_BASEADDR + 1). - - Typically, the compatible list will include the exact IP core version - followed by an older IP core version which implements the same - interface or any other device with the same interface. - - 'reg' and 'interrupts' are all optional properties. - - For example, the following block from system.mhs: - - BEGIN opb_uartlite - PARAMETER INSTANCE = opb_uartlite_0 - PARAMETER HW_VER = 1.00.b - PARAMETER C_BAUDRATE = 115200 - PARAMETER C_DATA_BITS = 8 - PARAMETER C_ODD_PARITY = 0 - PARAMETER C_USE_PARITY = 0 - PARAMETER C_CLK_FREQ = 50000000 - PARAMETER C_BASEADDR = 0xEC100000 - PARAMETER C_HIGHADDR = 0xEC10FFFF - BUS_INTERFACE SOPB = opb_7 - PORT OPB_Clk = CLK_50MHz - PORT Interrupt = opb_uartlite_0_Interrupt - PORT RX = opb_uartlite_0_RX - PORT TX = opb_uartlite_0_TX - PORT OPB_Rst = sys_bus_reset_0 - END - - becomes the following device tree node: - - opb_uartlite_0: serial@ec100000 { - device_type = "serial"; - compatible = "xlnx,opb-uartlite-1.00.b"; - reg = <ec100000 10000>; - interrupt-parent = <&opb_intc_0>; - interrupts = <1 0>; // got this from the opb_intc parameters - current-speed = <d#115200>; // standard serial device prop - clock-frequency = <d#50000000>; // standard serial device prop - xlnx,data-bits = <8>; - xlnx,odd-parity = <0>; - xlnx,use-parity = <0>; - }; - - That covers the general approach to binding xilinx IP cores into the - device tree. The following are bindings for specific devices: + Bindings for specific devices: i) Xilinx ML300 Framebuffer @@ -102,13 +13,6 @@ Default is <d#1024 d#480>. - rotate-display (empty) : rotate display 180 degrees. - iii) Xilinx EMAC and Xilinx TEMAC - - Xilinx Ethernet devices. In addition to general xilinx properties - listed above, nodes for these devices should include a phy-handle - property, and may include other common network device properties - like local-mac-address. - v) Xilinx hwicap Xilinx hwicap devices provide access to the configuration logic |