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path: root/drivers/gpu/drm/amd/include/asic_reg
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2026-10-07drm/amdgpu/gfx12: read xccs-per-xcp from RLC_IMU_AID_CONFIG for VFIYuBiao Wang
gfx_v12_1_get_xccs_per_xcp() supplies the compute partition layout that gfx_v12_1_cp_resume() needs on a VF. Once VFI is enabled the VF reaches registers through RLCG, which cannot access the GFX_IMU registers, so the GFX_IMU_PARTITION_SWITCH read stops working. Take the same field from RLC_IMU_AID_CONFIG instead, and read it with a direct MMIO access rather than RREG32_SOC15, which would route back into the RLCG path. Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mmhub v5_0_1 ip headers v3Alex Deucher
Add header files for mmhub v5_0_1 register offsets and shift masks v2: Update mmhub ip headers to BTO version v3: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add vpe v3_0_0 ip headers v4Hawking Zhang
Add header files for vpe v3_0_0 register offsets and shift masks v2: Update vpe ip headers to LSC version v3: Update vpe ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mp v15_0_3 ip headers v4Hawking Zhang
Add header files for mp v15_0_3 register offsets and shift masks v2: Update mp ip headers to LSC version v3: Update mp ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add lsdma v8_0_1 ip headersHawking Zhang
Add header files for lsdma v8_0_1 register offsets and shift masks v2: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add hdp v8_0_1 ip headers v3Hawking Zhang
Add header files for hdp v8_0_1 register offsets and shift masks v2: Update hdp ip headers to BTO version v3: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add smuio v15_0_3 ip headers v4Hawking Zhang
Add header files for smuio v15_0_3 register offsets and shift masks v2: Update smuio ip headers to LSC version v3: Update smuio ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add pcie v6_1_3 ip headers v4Hawking Zhang
Add header files for pcie v6_1_3 register offsets and shift masks v2: Update pcie ip headers to LSC version v3: Update pcie ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add nbif v7_10_0 ip headers v4Hawking Zhang
Add header files for nbif v7_10_0 register headers and shift masks v2: Update nbif ip headers to LSC version v3: Update nbif ip headers to BTO version v4: Update registers (Alex) v5: Squash in SR-IOV updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add osssys v8_0_1 ip headers v3Hawking Zhang
Add header files for osssys v8_0_1 register offsets and shift masks v2: Update osssys ip headers to BTO version v3: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Use partition switch shadow registerLijo Lazar
Control register is access restricted. Use the read-only copy to read the partition settings. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Add NBIO 7.11.5 header filesShubhankar Milind Sardeshpande
Add the NBIO 7.11.5 register offset and shift-mask headers required by the new driver. v2: update register headers (Alex) Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amdgpu/gfx6: Add IP block soft reset implementationTimur Kristóf
Update the register definition for GRBM_SOFT_RESET to match what was in the old radeon driver and use these bits in the soft reset implementation. For the soft reset, use basically the same implementation as GFX7-8, the main difference being the GRBM_SOFT_RESET bit fields and the fact that GFX6 doesn't have MQD/HQD. Reset every block using the GRBM, then proceed to reset the GRBM and SEM blocks using the SRBM. The soft reset also calls the clock and powergating functions of the IP block. This is necessary for correct operation, otherwise the GPU might fall off the PCIe bus. Add a gfx_v6_0_late_init() function for consistency with other GPU generations. This function will later serve the same purpose as it does on GFX7+ when we get around to enable more IRQs on GFX6. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd: Add DCN6 register headersAurabindo Pillai
Add new headers for: - dcn 6.0.0 - dpcs 6.0.0 - mmhub 5.0.1 Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdkfd: add sdma queue counter for gfxv9.4.3Eric Huang
since gfx 9.4.3 HW is calculating accumulated activity counter per-queue in register sdmax_rlcx_utilization_hi/lo, CPFW adds it in sdma MQD for save/restore, KFD will read it from there. gfx 9.4.2 will still keep the way to read from memory at rptr+8. v2: read dynamic counter directly from utilization register v3: add CPFW supported version check (Harish) Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd: Add register header files for DCN42BMatthew Stewart
[Why & How] Add register headers for: - clk 15.0.5 - dcn 4.2.1 - dpcs 4.0.1 - nbio 7.15.5 v2: add in missing license (Alex) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amdgpu/vpe: add new vpe v2.0.0 register offset and sh/maskCaden Chien
New offset and sh/mask are added for vpe v2.0.0 Acked-by: Roy Chan <Roy.Chan@amd.com> Signed-off-by: Caden Chien <chih-wei.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add FRL registers for DCN316Rodrigo Siqueira
Add the required FRL registers for DCN316. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add FRL registers for DCN315Rodrigo Siqueira
Add the required FRL registers for DCN315. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add FRL register for DCN303Rodrigo Siqueira
Add all the required registers to support FRL on DCN303. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add FRL register for DCN302Rodrigo Siqueira
Add the required FRL registers for DCN302. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add the necessary FRL registers for DCN314Rodrigo Siqueira
Add all the required registers to support FRL on DCN314. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Introduce FRL registers for DCN32Rodrigo Siqueira
This commit add the basic set of FRL registers associated with DCN32. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add FRL registers for DCN321Rodrigo Siqueira
Add the required DCN3.2.1 registers to enable FRL in this ASIC. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add required FRL registers for DCN31Rodrigo Siqueira
This commit introduces multiple hardware registers necessary to enable FRL on AMD devices. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-05-11drm/amd/display: Add FRL registers for DCN30Rodrigo Siqueira
Introduce the stream creation function, which requires the FRL registers for DCN30. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-24drm/amdgpu: Add nbio v6_3_2 ip headers v4Hawking Zhang
Add header files for nbio v6_3_2 register offsets and shift masks v2: Update nbio v6_3_2 ip headers up to CL7337280 v3: Update nbio v6_3_2 ip headers up to CL7749557 v4: Clean up registers (Alex) v5: squash in updates (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Add gc v12_1_0 ip headers v6Bing Ma
Add header files for gc v12_1_0 register offsets and shift masks v2: Update gc v12_1_0 ip headers v3: Update gc v12_1_0 ip headers v4, v5: Clean up registers (Alex) v6: Update gc v12_1_0 ip headers Signed-off-by: Bing Ma <Bing.Ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amdgpu: Add gc v12_1_1 ip headers v3Bing Ma
Add header files for gc v12_1_1 register offsets and shift masks v2: Update gc v12_1_1 ip headers v3: Update gc v12_1_1 ip headers Signed-off-by: Bing Ma <Bing.Ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-23drm/amd/display: Update underflow detection for DCN42Roman Li
[Why] The DCN42 underflow detection functions in dcn42_optc.c use OPTC_RSMU_UNDERFLOW register but the register offset definitions were missing from dcn_4_2_0_offset.h and dcn42_resource.h. [How] Add missing register definitions. Fixes: e56e3cff2a1b ("drm/amd/display: Sync dcn42 with DC 3.2.373") Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amdgpu: Add lsdma v7_1_0 ip headersLikun Gao
Add header files for lsdma v7_1_0 register offsets and shift masks Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amd/display: Sync dcn42 with DC 3.2.373Roman Li
This patch provides a bulk merge to align driver support for DCN42 with Display Core version 3.2.373. It includes upgrade for: - clk_mgr - dml2/dml21 - optc - hubp - mpc - optc - hwseq Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amd/display: Enable dcn42 DC clk_mgrRoman Li
Add support for DCN 4.2 clock manager. Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-04drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailboxsguttula
The reason the RAP is not granting access to 0x58200 is that a dedicated RSMU slot would have to be spent for this address range, and MPASP is close to running out of RSMU slots. This will help to fix PSP TOC load failure during secureboot. GFX Driver Need to use indirect access for SMN address regs. Signed-off-by: sguttula <suresh.guttula@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Add dcn42 register headersRoman Li
Register headers for the following IPs: - DCN 4.2.0 - DPCS 4.0.0 Signed-off-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-08drm/amdgpu: Add THM 15.0.0 headersAlex Deucher
Add headers for THM 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-08drm/amdgpu: add SMUIO 15.0.0 headersAlex Deucher
Add headers for SMUIO 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amd/amdgpu: Port over some missing registers and bits from GC 10.1 to ↵Tom St Denis
10.3 (v2) v2: Added SPI bits to sh_mask header Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: RLC-G VF Register Access InterfaceBokun Zhang
- Implement Gfx v12.1 VFi interface under SRIOV - Redirect all RLCG interface access to new function after Gfx v12.1 v2: squash in register updates Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add MP 15.0.0 headersAlex Deucher
Add headers for MP 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05drm/amdgpu: add VCN 5.3.0 headersAlex Deucher
Add headers for VCN 5.3.0. v2: Squash in updates (Alex) Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Add gc v12_1_0 ip headers v4Hawking Zhang
Add header files for gc v12_1_0 register offsets and shift masks v2: Update gc v12_1_0 ip headers v3: Update gc v12_1_0 ip headers v4, v5: Clean up registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Add osssys v7_1_0 ip headers v3Hawking Zhang
Add header files for osssys v7_1_0 register offsets and shift masks v2: Update osssys v7_1_0 ip headers to the latest version v3: Clean up registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Add mmhub v4_2_0 ip headers v5Hawking Zhang
Add header files for mmhub v4_2_0 register offsets and shift masks v2: Update mmhub v4_2_0 ip headers v3: Update mmhub v4_2_0 ip headers v4: Clean up registers (Alex) v5: Clean up registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Add mp v15_0_8 ip headers v4Hawking Zhang
Add header files for mp v15_0_8 register offsets and shift masks v2: Update mp v15_0_8 ip headers v3: Update mp v15_0_8 ip headers v4: Clean up registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Add smuio v15_0_8 ip headers v4Hawking Zhang
Add header files for smuio v15_0_8 register offsets and shift masks v2: Update smuio v15_0_8 ip headers v3: Update smuio v15_0_8 ip headers v4: Clean up registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11drm/amdgpu/vce1: Clean up register definitionsTimur Kristóf
The sid.h header contained some VCE1 register definitions, but they were using byte offsets (probably copied from the old radeon driver). Move all of these to the proper VCE1 headers and ensure they are in dword offsets. Also add the register definitions that we need for the firmware validation mechanism in VCE1. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Co-developed-by: Alexandre Demers <alexandre.f.demers@gmail.com> Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-10-07drm/amdgpu: Add additional DCE6 SCL registersAlex Deucher
Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)") Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-28drm/amd/display: Add some missing register headers for DCN401Aurabindo Pillai
Add some HDCP related register headers for future use. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-05-22drm/amdgpu: Add jpeg poison status regMangesh Gadre
added registers to enable jpeg ras Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.0.4) at 2026-10-25 17:45:11 +0000