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-rw-r--r--arch/arm/mach-snapdragon/board.c13
-rw-r--r--arch/riscv/Kconfig4
-rw-r--r--arch/riscv/cpu/cpu.c14
-rw-r--r--arch/riscv/dts/Makefile2
-rw-r--r--arch/riscv/dts/qilai-voyager.dts227
-rw-r--r--arch/riscv/dts/voyager-u-boot.dtsi52
-rw-r--r--arch/riscv/dts/xilinx-binman.dts12
-rw-r--r--arch/riscv/dts/xilinx-mbv32.dts8
-rw-r--r--arch/riscv/dts/xilinx-mbv64.dts8
-rw-r--r--arch/riscv/lib/memcpy.S12
-rw-r--r--arch/riscv/lib/memmove.S12
11 files changed, 340 insertions, 24 deletions
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index fc921a4be26..5fb3240acc5 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -534,8 +534,7 @@ int board_late_init(void)
env_set_hex("ramdisk_addr_r", addr) : 1;
status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ?
env_set_hex("kernel_comp_addr_r", addr) : 1;
- status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ?
- env_set_hex("kernel_comp_size", addr) : 1;
+ status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
status |= !lmb_alloc(SZ_4M, &addr) ?
env_set_hex("scriptaddr", addr) : 1;
status |= !lmb_alloc(SZ_4M, &addr) ?
@@ -544,9 +543,13 @@ int board_late_init(void)
if (IS_ENABLED(CONFIG_FASTBOOT)) {
status |= !lmb_alloc(FASTBOOT_BUF_SIZE, &addr) ?
env_set_hex("fastboot_addr_r", addr) : 1;
- /* override loadaddr for memory rich soc */
- status |= !lmb_alloc(SZ_128M, &addr) ?
- env_set_hex("loadaddr", addr) : 1;
+ /*
+ * Override loadaddr for memory rich soc since ${loadaddr} and
+ * ${kernel_addr_r} need to be different for the Android boot image
+ * flow. It's typically safe for ${loadaddr} to be the same address
+ * as the fastboot buffer.
+ */
+ status |= env_set_hex("loadaddr", addr);
}
fdt_status |= !lmb_alloc(SZ_2M, &addr) ?
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8c6feae5735..04eb0e6f23c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,9 @@ choice
config TARGET_ANDES_AE350
bool "Support Andes ae350"
+config TARGET_ANDES_VOYAGER
+ bool "Support Andes Voyager Board"
+
config TARGET_BANANAPI_F3
bool "Support BananaPi F3 Board"
@@ -101,6 +104,7 @@ config SPL_ZERO_MEM_BEFORE_USE
# board-specific options below
source "board/andestech/ae350/Kconfig"
+source "board/andestech/voyager/Kconfig"
source "board/aspeed/ibex_ast2700/Kconfig"
source "board/canaan/k230_canmv/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 15c4e14599d..d5123e4b7d9 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -608,14 +608,14 @@ static inline bool supports_extension(char ext)
static int riscv_cpu_probe(void)
{
-#ifdef CONFIG_CPU
- int ret;
+ if (CONFIG_IS_ENABLED(CPU)) {
+ int ret;
- /* probe cpus so that RISC-V timer can be bound */
- ret = cpu_probe_all();
- if (ret)
- return log_msg_ret("RISC-V cpus probe failed\n", ret);
-#endif
+ /* probe cpus so that RISC-V timer can be bound */
+ ret = cpu_probe_all();
+ if (ret)
+ return log_msg_ret("RISC-V cpus probe failed\n", ret);
+ }
return 0;
}
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 2b10c2d6c01..a637727b76b 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb
dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb
dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
@@ -14,6 +15,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
+dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb
dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
include $(srctree)/scripts/Makefile.dts
diff --git a/arch/riscv/dts/qilai-voyager.dts b/arch/riscv/dts/qilai-voyager.dts
new file mode 100644
index 00000000000..44933529f89
--- /dev/null
+++ b/arch/riscv/dts/qilai-voyager.dts
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+
+#include "binman.dtsi"
+#include "voyager-u-boot.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ compatible = "andestech,voyager", "andestech,qilai";
+ model = "Voyager";
+
+ aliases {
+ uart0 = &serial0;
+ spi0 = &spi;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlycon=sbi debug loglevel=7";
+ stdout-path = "uart0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ timebase-frequency = <0x3938700>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ riscv,priv-major = <0x1>;
+ riscv,priv-minor = <0xa>;
+ mmu-type = "riscv,sv39";
+ clock-frequency = <0x3938700>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x20>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x20>;
+ next-level-cache = <&L2>;
+
+ CPU0_intc: interrupt-controller {
+ #interrupt-cells = <0x1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ riscv,priv-major = <0x1>;
+ riscv,priv-minor = <0xa>;
+ mmu-type = "riscv,sv39";
+ clock-frequency = <0x3938700>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x20>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x20>;
+ next-level-cache = <&L2>;
+
+ CPU1_intc: interrupt-controller {
+ #interrupt-cells = <0x1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ reg = <0x2>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ riscv,priv-major = <0x1>;
+ riscv,priv-minor = <0xa>;
+ mmu-type = "riscv,sv39";
+ clock-frequency = <0x3938700>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x20>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x20>;
+ next-level-cache = <&L2>;
+
+ CPU2_intc: interrupt-controller {
+ #interrupt-cells = <0x1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ reg = <0x3>;
+ status = "okay";
+ compatible = "riscv";
+ riscv,isa = "rv64imafdc";
+ riscv,priv-major = <0x1>;
+ riscv,priv-minor = <0xa>;
+ mmu-type = "riscv,sv39";
+ clock-frequency = <0x3938700>;
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <0x20>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <0x20>;
+ next-level-cache = <&L2>;
+
+ CPU3_intc: interrupt-controller {
+ #interrupt-cells = <0x1>;
+ interrupt-controller;
+ compatible = "riscv,cpu-intc";
+ };
+ };
+ };
+
+ L2: l2-cache@200000 {
+ compatible = "cache";
+ cache-level = <0x2>;
+ cache-size = <0x40000>;
+ reg = <0x0 0x00200000 0x0 0x100000>;
+ andes,inst-prefetch = <0x3>;
+ andes,data-prefetch = <0x3>;
+ andes,tag-ram-ctl = <0x0 0x0>;
+ andes,data-ram-ctl = <0x0 0x0>;
+ };
+
+ memory@400000000 {
+ device_type = "memory";
+ reg = <0x04 0x00000000 0x0 0x40000000>;
+ };
+
+ soc {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ compatible = "simple-bus";
+ ranges;
+
+ plic0: interrupt-controller@2000000 {
+ compatible = "riscv,plic0";
+ #address-cells = <0x2>;
+ #interrupt-cells = <0x2>;
+ interrupt-controller;
+ reg = <0x0 0x02000000 0x0 0x2000000>;
+ riscv,ndev = <0x47>;
+ interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
+ &CPU1_intc 11 &CPU1_intc 9
+ &CPU2_intc 11 &CPU2_intc 9
+ &CPU3_intc 11 &CPU3_intc 9>;
+ };
+
+ plic1: interrupt-controller@400000 {
+ compatible = "andestech,plicsw";
+ #address-cells = <0x2>;
+ #interrupt-cells = <0x2>;
+ interrupt-controller;
+ reg = <0x0 0x00400000 0x0 0x400000>;
+ riscv,ndev = <0x1>;
+ interrupts-extended = <&CPU0_intc 3
+ &CPU1_intc 3
+ &CPU2_intc 3
+ &CPU3_intc 3>;
+ };
+
+ plmt0@100000 {
+ compatible = "andestech,plmt0";
+ reg = <0x0 0x00100000 0x0 0x100000>;
+ interrupts-extended = <&CPU0_intc 7
+ &CPU1_intc 7
+ &CPU2_intc 7
+ &CPU3_intc 7>;
+ };
+ };
+
+ spiclk: virt_100mhz {
+ #clock-cells = <0x0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0x5f5e100>;
+ };
+
+ serial0: serial@30300000 {
+ compatible = "andestech,uart16550", "ns16550a";
+ reg = <0x0 0x30300000 0x0 0x1000>;
+ interrupts = <0x9 0x4>;
+ clock-frequency = <0x12c0000>;
+ reg-shift = <0x2>;
+ reg-offset = <0x20>;
+ no-loopback-test = <0x1>;
+ interrupt-parent = <&plic0>;
+ };
+
+ mmc0: mmc@30c00000 {
+ compatible = "andestech,atfsdc010";
+ max-frequency = <0x5f5e100>;
+ clock-freq-min-max = <0x61a80 0x5f5e100>;
+ fifo-depth = <0x10>;
+ reg = <0x0 0x30c00000 0x0 0x1000>;
+ interrupts = <0x12 0x4>;
+ cap-sd-highspeed;
+ interrupt-parent = <&plic0>;
+ dma-coherent;
+ };
+
+ spi: spi@30900000 {
+ compatible = "andestech,atcspi200";
+ reg = <0x0 0x30900000 0x0 0x100000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ num-cs = <0x1>;
+ clocks = <&spiclk>;
+ interrupts = <0x4 0x4>;
+ interrupt-parent = <&plic0>;
+
+ flash@0 {
+ compatible = "mx25u1635e", "jedec,spi-nor";
+ spi-max-frequency = <0x2faf080>;
+ reg = <0x0>;
+ spi-cpol;
+ spi-cpha;
+ };
+ };
+};
diff --git a/arch/riscv/dts/voyager-u-boot.dtsi b/arch/riscv/dts/voyager-u-boot.dtsi
new file mode 100644
index 00000000000..cef0aa08b37
--- /dev/null
+++ b/arch/riscv/dts/voyager-u-boot.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/ {
+ cpus {
+ bootph-pre-ram;
+ CPU0: cpu@0 {
+ bootph-pre-ram;
+ CPU0_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+ CPU1: cpu@1 {
+ bootph-pre-ram;
+ CPU1_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+ CPU2: cpu@2 {
+ bootph-pre-ram;
+ CPU2_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+ CPU3: cpu@3 {
+ bootph-pre-ram;
+ CPU3_intc: interrupt-controller {
+ bootph-pre-ram;
+ };
+ };
+ };
+
+ memory@0 {
+ bootph-pre-ram;
+ };
+
+ soc {
+ bootph-pre-ram;
+
+ plic1: interrupt-controller@400000 {
+ bootph-pre-ram;
+ };
+
+ plmt0@100000 {
+ bootph-pre-ram;
+ };
+ };
+
+ serial0: serial@30300000 {
+ bootph-pre-ram;
+ };
+
+};
diff --git a/arch/riscv/dts/xilinx-binman.dts b/arch/riscv/dts/xilinx-binman.dts
new file mode 100644
index 00000000000..715080ed763
--- /dev/null
+++ b/arch/riscv/dts/xilinx-binman.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * binman file for AMD MicroBlaze V
+ *
+ * (C) Copyright 2025, Advanced Micro Devices, Inc.
+ *
+ * Michal Simek <michal.simek@amd.com>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 4050ce2f051..f7a3e076fd5 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -2,15 +2,13 @@
/*
* dts file for AMD MicroBlaze V
*
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
-#include "binman.dtsi"
-
/ {
#address-cells = <1>;
#size-cells = <1>;
@@ -26,6 +24,7 @@
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imafdc";
+ mmu-type = "riscv,sv39";
i-cache-size = <32768>;
d-cache-size = <32768>;
clock-frequency = <100000000>;
@@ -70,7 +69,8 @@
interrupt-controller;
interrupt-parent = <&cpu0_intc>;
#interrupt-cells = <2>;
- kind-of-intr = <0>;
+ xlnx,num-intr-inputs = <2>;
+ xlnx,kind-of-intr = <0>;
};
xlnx_timer0: timer@41c00000 {
diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts
index 4d65d338ecb..e6235ed2f52 100644
--- a/arch/riscv/dts/xilinx-mbv64.dts
+++ b/arch/riscv/dts/xilinx-mbv64.dts
@@ -2,15 +2,13 @@
/*
* dts file for AMD MicroBlaze V
*
- * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
-#include "binman.dtsi"
-
/ {
#address-cells = <2>;
#size-cells = <2>;
@@ -26,6 +24,7 @@
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imafdc";
+ mmu-type = "riscv,sv39";
i-cache-size = <32768>;
d-cache-size = <32768>;
clock-frequency = <100000000>;
@@ -70,7 +69,8 @@
interrupt-controller;
interrupt-parent = <&cpu0_intc>;
#interrupt-cells = <2>;
- kind-of-intr = <0>;
+ xlnx,num-intr-inputs = <2>;
+ xlnx,kind-of-intr = <0>;
};
xlnx_timer0: timer@41c00000 {
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
index 9884077c933..e5479bbe84e 100644
--- a/arch/riscv/lib/memcpy.S
+++ b/arch/riscv/lib/memcpy.S
@@ -125,6 +125,14 @@ WEAK(memcpy)
.copy_end:
ret
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define M_SLL sll
+#define M_SRL srl
+#else
+#define M_SLL srl
+#define M_SRL sll
+#endif
+
.Lmisaligned_word_copy:
/*
* Misaligned word-wise copy.
@@ -144,10 +152,10 @@ WEAK(memcpy)
addi t0, t0, -(SZREG-1)
/* At least one iteration will be executed here, no check */
1:
- srl a4, a5, t3
+ M_SRL a4, a5, t3
REG_L a5, SZREG(a1)
addi a1, a1, SZREG
- sll a2, a5, t4
+ M_SLL a2, a5, t4
or a2, a2, a4
REG_S a2, 0(a0)
addi a0, a0, SZREG
diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S
index fbe6701dbe4..b2c1c736713 100644
--- a/arch/riscv/lib/memmove.S
+++ b/arch/riscv/lib/memmove.S
@@ -91,6 +91,14 @@ WEAK(memmove)
mv a0, t0
ret
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+#define M_SLL sll
+#define M_SRL srl
+#else
+#define M_SLL srl
+#define M_SRL sll
+#endif
+
.Lmisaligned_word_copy:
/*
* Misaligned word-wise copy.
@@ -110,10 +118,10 @@ WEAK(memmove)
addi t0, t0, SZREG-1
/* At least one iteration will be executed here, no check */
1:
- sll a4, a5, t4
+ M_SLL a4, a5, t4
addi a1, a1, -SZREG
REG_L a5, 0(a1)
- srl a2, a5, t3
+ M_SRL a2, a5, t3
or a2, a2, a4
addi a0, a0, -SZREG
REG_S a2, 0(a0)
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-15 04:24:43 +0000