diff options
Diffstat (limited to 'arch')
484 files changed, 17865 insertions, 16400 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 7e05e0c2263..3133f892f94 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -202,7 +202,6 @@ config SANDBOX select DM_SPI select DM_SPI_FLASH select GZIP_COMPRESSED - select IO_TRACE select LZO select MMC select MTD diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4e7593616d8..3db5474a05b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -30,7 +30,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 + default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -68,10 +68,10 @@ config INIT_SP_RELATIVE SYS_INIT_SP_BSS_OFFSET. config SYS_INIT_SP_BSS_OFFSET - int "Early stack offset from the .bss base address" + hex "Early stack offset from the .bss base address" depends on ARM64 depends on INIT_SP_RELATIVE - default 524288 + default 0x80000 help This option's value is the offset added to &_bss_start in order to calculate the stack pointer. This offset should be large enough so @@ -445,7 +445,7 @@ config ARCH_CPU_INIT config SYS_ARCH_TIMER bool "ARM Generic Timer support" - depends on CPU_V7A || ARM64 + depends on CPU_V7A || CPU_V7M || ARM64 default y if ARM64 help The ARM Generic Timer (aka arch-timer) provides an architected @@ -833,6 +833,7 @@ config ARCH_K3 select FIT select REGEX select FIT_SIGNATURE if ARM64 + select DMA_ADDR_T_64BIT select LTO imply TI_SECURE_DEVICE imply DM_RNG if ARM64 @@ -882,6 +883,7 @@ config ARCH_MMP select OF_CONTROL select SAVE_PREV_BL_FDT_ADDR select SAVE_PREV_BL_INITRAMFS_START_ADDR + imply OF_UPSTREAM config ARCH_LPC32XX bool "NXP LPC32xx platform" @@ -896,6 +898,7 @@ config ARCH_LPC32XX config ARCH_IMX8 bool "NXP i.MX8 platform" + select ARCH_MISC_INIT if FSL_CAAM select ARM64 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 @@ -1173,8 +1176,9 @@ config ARCH_SOCFPGA select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ - TARGET_SOCFPGA_SOC64 + TARGET_SOCFPGA_SOC64 select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5 + select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY @@ -1416,6 +1420,8 @@ config ARCH_VEXPRESS64 select MTD_NOR_FLASH if MTD select FLASH_CFI_DRIVER if MTD select ENV_IS_IN_FLASH if MTD + select SYSRESET + select SYSRESET_PSCI if ARM_PSCI_FW imply DISTRO_DEFAULTS config TARGET_CORSTONE1000 @@ -2002,7 +2008,6 @@ config ARCH_SYNQUACER bool "Socionext SynQuacer SoCs" select ARM64 select DM - select GIC_V3 select PSCI_RESET select SYSRESET select SYSRESET_PSCI @@ -2068,30 +2073,30 @@ config ARCH_ROCKCHIP bool "Support Rockchip SoCs" select BINMAN if SPL_OPTEE || SPL select DM - select DM_GPIO - select DM_I2C - select DM_PWM - select DM_REGULATOR - select DM_SERIAL - select DM_SPI - select DM_SPI_FLASH select DM_USB_GADGET if USB_DWC3_GADGET select ENABLE_ARM_SOC_BOOT0_HOOK select OF_CONTROL - select MMC - select MTD - select SPI select SPL_DM if SPL - select SPL_DM_SPI if SPL - select SPL_DM_SPI_FLASH if SPL select SYS_MALLOC_F select SYS_THUMB_BUILD if !ARM64 imply ADC + imply BOOTSTD_DEFAULTS imply CMD_DM imply DEBUG_UART_BOARD_INIT - imply BOOTSTD_DEFAULTS + imply DM_GPIO + imply DM_I2C + imply DM_PWM + imply DM_REGULATOR + imply DM_SERIAL + imply DM_SPI + imply DM_SPI_FLASH imply FAT_WRITE + imply MMC + imply MTD imply SARADC_ROCKCHIP + imply SPI + imply SPL_DM_SPI if SPL + imply SPL_DM_SPI_FLASH if SPL imply SPL_SYSRESET imply SPL_SYS_MALLOC_SIMPLE imply SYS_NS16550 diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 6e725ba1081..ba7dd99672a 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -23,9 +23,12 @@ endif PLATFORM_RELFLAGS += -fno-common $(FIXED_REG) PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ - $(call cc-option,-mgeneral-regs-only) \ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +ifeq ($(CONFIG_ARM64),y) +PLATFORM_RELFLAGS += $(call cc-option,-mgeneral-regs-only) +endif + # LLVM support LLVM_RELFLAGS := $(call cc-option,-mllvm,) \ $(call cc-option,-mno-movt,) diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 318a71f24b1..e3415cfd1d1 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -32,7 +32,6 @@ ifneq (,$(filter s5pc1xx exynos,$(SOC))) obj-y += s5p-common/ endif -obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ diff --git a/arch/arm/cpu/armv7/bcm235xx/Makefile b/arch/arm/cpu/armv7/bcm235xx/Makefile deleted file mode 100644 index 3d09126cabe..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Broadcom Corporation. - -obj-y += clk-core.o -obj-y += clk-bcm235xx.o -obj-y += clk-sdio.o -obj-y += clk-bsc.o -obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o -obj-y += clk-usb-otg.o diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c b/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c deleted file mode 100644 index 7f73f893458..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c +++ /dev/null @@ -1,567 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -/* - * - * bcm235xx-specific clock tables - * - */ - -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include "clk-core.h" - -#define CLOCK_1K 1000 -#define CLOCK_1M (CLOCK_1K * 1000) - -/* declare a reference clock */ -#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \ -static struct refclk clk_name = { \ - .clk = { \ - .name = #clk_name, \ - .parent = clk_parent, \ - .rate = clk_rate, \ - .div = clk_div, \ - .ops = &ref_clk_ops, \ - }, \ -} - -/* - * Reference clocks - */ - -/* Declare a list of reference clocks */ -DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1); -DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1); -DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1); -DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0); -DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3); -DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2); -DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4); -DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0); -DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3); -DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2); -DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4); - -struct refclk_lkup { - struct refclk *procclk; - const char *name; -}; - -/* Lookup table for string to clk tranlation */ -#define MKSTR(x) {&x, #x} -static struct refclk_lkup refclk_str_tbl[] = { - MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m), - MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m), - MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m), - MKSTR(var_52m), MKSTR(var_13m), -}; - -int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]); - -/* convert ref clock string to clock structure pointer */ -struct refclk *refclk_str_to_clk(const char *name) -{ - int i; - struct refclk_lkup *tblp = refclk_str_tbl; - for (i = 0; i < refclk_entries; i++, tblp++) { - if (!(strcmp(name, tblp->name))) - return tblp->procclk; - } - return NULL; -} - -/* frequency tables indexed by freq_id */ -unsigned long master_axi_freq_tbl[8] = { - 26 * CLOCK_1M, - 52 * CLOCK_1M, - 104 * CLOCK_1M, - 156 * CLOCK_1M, - 156 * CLOCK_1M, - 208 * CLOCK_1M, - 312 * CLOCK_1M, - 312 * CLOCK_1M -}; - -unsigned long master_ahb_freq_tbl[8] = { - 26 * CLOCK_1M, - 52 * CLOCK_1M, - 52 * CLOCK_1M, - 52 * CLOCK_1M, - 78 * CLOCK_1M, - 104 * CLOCK_1M, - 104 * CLOCK_1M, - 156 * CLOCK_1M -}; - -unsigned long slave_axi_freq_tbl[8] = { - 26 * CLOCK_1M, - 52 * CLOCK_1M, - 78 * CLOCK_1M, - 104 * CLOCK_1M, - 156 * CLOCK_1M, - 156 * CLOCK_1M -}; - -unsigned long slave_apb_freq_tbl[8] = { - 26 * CLOCK_1M, - 26 * CLOCK_1M, - 39 * CLOCK_1M, - 52 * CLOCK_1M, - 52 * CLOCK_1M, - 78 * CLOCK_1M -}; - -unsigned long esub_freq_tbl[8] = { - 78 * CLOCK_1M, - 156 * CLOCK_1M, - 156 * CLOCK_1M, - 156 * CLOCK_1M, - 208 * CLOCK_1M, - 208 * CLOCK_1M, - 208 * CLOCK_1M -}; - -static struct bus_clk_data bsc1_apb_data = { - .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1), -}; - -static struct bus_clk_data bsc2_apb_data = { - .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1), -}; - -static struct bus_clk_data bsc3_apb_data = { - .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1), -}; - -/* * Master CCU clocks */ -static struct peri_clk_data sdio1_data = { - .gate = HW_SW_GATE(0x0358, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_52m", - "ref_52m", - "var_96m", - "ref_96m"), - .sel = SELECTOR(0x0a28, 0, 3), - .div = DIVIDER(0x0a28, 4, 14), - .trig = TRIGGER(0x0afc, 9), -}; - -static struct peri_clk_data sdio2_data = { - .gate = HW_SW_GATE(0x035c, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_52m", - "ref_52m", - "var_96m", - "ref_96m"), - .sel = SELECTOR(0x0a2c, 0, 3), - .div = DIVIDER(0x0a2c, 4, 14), - .trig = TRIGGER(0x0afc, 10), -}; - -static struct peri_clk_data sdio3_data = { - .gate = HW_SW_GATE(0x0364, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_52m", - "ref_52m", - "var_96m", - "ref_96m"), - .sel = SELECTOR(0x0a34, 0, 3), - .div = DIVIDER(0x0a34, 4, 14), - .trig = TRIGGER(0x0afc, 12), -}; - -static struct peri_clk_data sdio4_data = { - .gate = HW_SW_GATE(0x0360, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_52m", - "ref_52m", - "var_96m", - "ref_96m"), - .sel = SELECTOR(0x0a30, 0, 3), - .div = DIVIDER(0x0a30, 4, 14), - .trig = TRIGGER(0x0afc, 11), -}; - -static struct peri_clk_data sdio1_sleep_data = { - .clocks = CLOCKS("ref_32k"), - .gate = SW_ONLY_GATE(0x0358, 20, 4), -}; - -static struct peri_clk_data sdio2_sleep_data = { - .clocks = CLOCKS("ref_32k"), - .gate = SW_ONLY_GATE(0x035c, 20, 4), -}; - -static struct peri_clk_data sdio3_sleep_data = { - .clocks = CLOCKS("ref_32k"), - .gate = SW_ONLY_GATE(0x0364, 20, 4), -}; - -static struct peri_clk_data sdio4_sleep_data = { - .clocks = CLOCKS("ref_32k"), - .gate = SW_ONLY_GATE(0x0360, 20, 4), -}; - -static struct bus_clk_data usb_otg_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1), -}; - -static struct bus_clk_data sdio1_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1), -}; - -static struct bus_clk_data sdio2_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1), -}; - -static struct bus_clk_data sdio3_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1), -}; - -static struct bus_clk_data sdio4_ahb_data = { - .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1), -}; - -/* * Slave CCU clocks */ -static struct peri_clk_data bsc1_data = { - .gate = HW_SW_GATE(0x0458, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_104m", - "ref_104m", - "var_13m", - "ref_13m"), - .sel = SELECTOR(0x0a64, 0, 3), - .trig = TRIGGER(0x0afc, 23), -}; - -static struct peri_clk_data bsc2_data = { - .gate = HW_SW_GATE(0x045c, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_104m", - "ref_104m", - "var_13m", - "ref_13m"), - .sel = SELECTOR(0x0a68, 0, 3), - .trig = TRIGGER(0x0afc, 24), -}; - -static struct peri_clk_data bsc3_data = { - .gate = HW_SW_GATE(0x0484, 18, 2, 3), - .clocks = CLOCKS("ref_crystal", - "var_104m", - "ref_104m", - "var_13m", - "ref_13m"), - .sel = SELECTOR(0x0a84, 0, 3), - .trig = TRIGGER(0x0b00, 2), -}; - -/* - * CCU clocks - */ - -static struct ccu_clock kpm_ccu_clk = { - .clk = { - .name = "kpm_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = master_axi_freq_tbl, -}; - -static struct ccu_clock kps_ccu_clk = { - .clk = { - .name = "kps_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = slave_axi_freq_tbl, -}; - -#ifdef CONFIG_BCM_SF2_ETH -static struct ccu_clock esub_ccu_clk = { - .clk = { - .name = "esub_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = esub_freq_tbl, -}; -#endif - -/* - * Bus clocks - */ - -/* KPM bus clocks */ -static struct bus_clock usb_otg_ahb_clk = { - .clk = { - .name = "usb_otg_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &usb_otg_ahb_data, -}; - -static struct bus_clock sdio1_ahb_clk = { - .clk = { - .name = "sdio1_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &sdio1_ahb_data, -}; - -static struct bus_clock sdio2_ahb_clk = { - .clk = { - .name = "sdio2_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &sdio2_ahb_data, -}; - -static struct bus_clock sdio3_ahb_clk = { - .clk = { - .name = "sdio3_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &sdio3_ahb_data, -}; - -static struct bus_clock sdio4_ahb_clk = { - .clk = { - .name = "sdio4_ahb_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .freq_tbl = master_ahb_freq_tbl, - .data = &sdio4_ahb_data, -}; - -static struct bus_clock bsc1_apb_clk = { - .clk = { - .name = "bsc1_apb_clk", - .parent = &kps_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .freq_tbl = slave_apb_freq_tbl, - .data = &bsc1_apb_data, -}; - -static struct bus_clock bsc2_apb_clk = { - .clk = { - .name = "bsc2_apb_clk", - .parent = &kps_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .freq_tbl = slave_apb_freq_tbl, - .data = &bsc2_apb_data, -}; - -static struct bus_clock bsc3_apb_clk = { - .clk = { - .name = "bsc3_apb_clk", - .parent = &kps_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .freq_tbl = slave_apb_freq_tbl, - .data = &bsc3_apb_data, -}; - -/* KPM peripheral */ -static struct peri_clock sdio1_clk = { - .clk = { - .name = "sdio1_clk", - .parent = &ref_52m.clk, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio1_data, -}; - -static struct peri_clock sdio2_clk = { - .clk = { - .name = "sdio2_clk", - .parent = &ref_52m.clk, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio2_data, -}; - -static struct peri_clock sdio3_clk = { - .clk = { - .name = "sdio3_clk", - .parent = &ref_52m.clk, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio3_data, -}; - -static struct peri_clock sdio4_clk = { - .clk = { - .name = "sdio4_clk", - .parent = &ref_52m.clk, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio4_data, -}; - -static struct peri_clock sdio1_sleep_clk = { - .clk = { - .name = "sdio1_sleep_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio1_sleep_data, -}; - -static struct peri_clock sdio2_sleep_clk = { - .clk = { - .name = "sdio2_sleep_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio2_sleep_data, -}; - -static struct peri_clock sdio3_sleep_clk = { - .clk = { - .name = "sdio3_sleep_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio3_sleep_data, -}; - -static struct peri_clock sdio4_sleep_clk = { - .clk = { - .name = "sdio4_sleep_clk", - .parent = &kpm_ccu_clk.clk, - .ops = &bus_clk_ops, - .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR, - }, - .data = &sdio4_sleep_data, -}; - -/* KPS peripheral clock */ -static struct peri_clock bsc1_clk = { - .clk = { - .name = "bsc1_clk", - .parent = &ref_13m.clk, - .rate = 13 * CLOCK_1M, - .div = 1, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .data = &bsc1_data, -}; - -static struct peri_clock bsc2_clk = { - .clk = { - .name = "bsc2_clk", - .parent = &ref_13m.clk, - .rate = 13 * CLOCK_1M, - .div = 1, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .data = &bsc2_data, -}; - -static struct peri_clock bsc3_clk = { - .clk = { - .name = "bsc3_clk", - .parent = &ref_13m.clk, - .rate = 13 * CLOCK_1M, - .div = 1, - .ops = &peri_clk_ops, - .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR, - }, - .data = &bsc3_data, -}; - -/* public table for registering clocks */ -struct clk_lookup arch_clk_tbl[] = { - /* Peripheral clocks */ - CLK_LK(sdio1), - CLK_LK(sdio2), - CLK_LK(sdio3), - CLK_LK(sdio4), - CLK_LK(sdio1_sleep), - CLK_LK(sdio2_sleep), - CLK_LK(sdio3_sleep), - CLK_LK(sdio4_sleep), - CLK_LK(bsc1), - CLK_LK(bsc2), - CLK_LK(bsc3), - /* Bus clocks */ - CLK_LK(usb_otg_ahb), - CLK_LK(sdio1_ahb), - CLK_LK(sdio2_ahb), - CLK_LK(sdio3_ahb), - CLK_LK(sdio4_ahb), - CLK_LK(bsc1_apb), - CLK_LK(bsc2_apb), - CLK_LK(bsc3_apb), -#ifdef CONFIG_BCM_SF2_ETH - CLK_LK(esub_ccu), -#endif -}; - -/* public array size */ -unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl); diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c b/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c deleted file mode 100644 index 55dcc2fd78c..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-bsc.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include "clk-core.h" - -/* Enable appropriate clocks for a BSC/I2C port */ -int clk_bsc_enable(void *base) -{ - int ret; - char *bscstr, *apbstr; - - switch ((u32) base) { - case PMU_BSC_BASE_ADDR: - /* PMU clock is always enabled */ - return 0; - case BSC1_BASE_ADDR: - bscstr = "bsc1_clk"; - apbstr = "bsc1_apb_clk"; - break; - case BSC2_BASE_ADDR: - bscstr = "bsc2_clk"; - apbstr = "bsc2_apb_clk"; - break; - case BSC3_BASE_ADDR: - bscstr = "bsc3_clk"; - apbstr = "bsc3_apb_clk"; - break; - default: - printf("%s: base 0x%p not found\n", __func__, base); - return -EINVAL; - } - - /* Note that the bus clock must be enabled first */ - - ret = clk_get_and_enable(apbstr); - if (ret) - return ret; - - ret = clk_get_and_enable(bscstr); - if (ret) - return ret; - - return 0; -} diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c deleted file mode 100644 index fa8af1b6941..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ /dev/null @@ -1,512 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -/* - * - * bcm235xx architecture clock framework - * - */ - -#include <log.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <bitfield.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include "clk-core.h" - -#define CLK_WR_ACCESS_PASSWORD 0x00a5a501 -#define WR_ACCESS_OFFSET 0 /* common to all clock blocks */ -#define POLICY_CTL_GO 1 /* Load and refresh policy masks */ -#define POLICY_CTL_GO_ATL 4 /* Active Load */ - -/* Helper function */ -int clk_get_and_enable(char *clkstr) -{ - int ret = 0; - struct clk *c; - - debug("%s: %s\n", __func__, clkstr); - - c = clk_get(clkstr); - if (c) { - ret = clk_enable(c); - if (ret) - return ret; - } else { - printf("%s: Couldn't find %s\n", __func__, clkstr); - return -EINVAL; - } - return ret; -} - -/* - * Poll a register in a CCU's address space, returning when the - * specified bit in that register's value is set (or clear). Delay - * a microsecond after each read of the register. Returns true if - * successful, or false if we gave up trying. - * - * Caller must ensure the CCU lock is held. - */ -#define CLK_GATE_DELAY_USEC 2000 -static inline int wait_bit(void *base, u32 offset, u32 bit, bool want) -{ - unsigned int tries; - u32 bit_mask = 1 << bit; - - for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) { - u32 val; - bool bit_val; - - val = readl(base + offset); - bit_val = (val & bit_mask) ? 1 : 0; - if (bit_val == want) - return 0; /* success */ - udelay(1); - } - - debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n", - __func__, base + offset, bit, want); - - return -ETIMEDOUT; -} - -/* Enable a peripheral clock */ -static int peri_clk_enable(struct clk *c, int enable) -{ - int ret = 0; - u32 reg; - struct peri_clock *peri_clk = to_peri_clk(c); - struct peri_clk_data *cd = peri_clk->data; - struct bcm_clk_gate *gate = &cd->gate; - void *base = (void *)c->ccu_clk_mgr_base; - - debug("%s: %s\n", __func__, c->name); - - clk_get_rate(c); /* Make sure rate and sel are filled in */ - - /* enable access */ - writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); - - if (enable) { - debug("%s %s set rate %lu div %lu sel %d parent %lu\n", - __func__, c->name, c->rate, c->div, c->sel, - c->parent->rate); - - /* - * clkgate - only software controllable gates are - * supported by u-boot which includes all clocks - * that matter. This avoids bringing in a lot of extra - * complexity as done in the kernel framework. - */ - if (gate_exists(gate)) { - reg = readl(base + cd->gate.offset); - reg |= (1 << cd->gate.en_bit); - writel(reg, base + cd->gate.offset); - } - - /* div and pll select */ - if (divider_exists(&cd->div)) { - reg = readl(base + cd->div.offset); - bitfield_replace(reg, cd->div.shift, cd->div.width, - c->div - 1); - writel(reg, base + cd->div.offset); - } - - /* frequency selector */ - if (selector_exists(&cd->sel)) { - reg = readl(base + cd->sel.offset); - bitfield_replace(reg, cd->sel.shift, cd->sel.width, - c->sel); - writel(reg, base + cd->sel.offset); - } - - /* trigger */ - if (trigger_exists(&cd->trig)) { - writel((1 << cd->trig.bit), base + cd->trig.offset); - - /* wait for trigger status bit to go to 0 */ - ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0); - if (ret) - return ret; - } - - /* wait for running (status_bit = 1) */ - ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1); - if (ret) - return ret; - } else { - debug("%s disable clock %s\n", __func__, c->name); - - /* clkgate */ - reg = readl(base + cd->gate.offset); - reg &= ~(1 << cd->gate.en_bit); - writel(reg, base + cd->gate.offset); - - /* wait for stop (status_bit = 0) */ - ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0); - } - - /* disable access */ - writel(0, base + WR_ACCESS_OFFSET); - - return ret; -} - -/* Set the rate of a peripheral clock */ -static int peri_clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret = 0; - int i; - unsigned long diff; - unsigned long new_rate = 0, div = 1; - struct peri_clock *peri_clk = to_peri_clk(c); - struct peri_clk_data *cd = peri_clk->data; - const char **clock; - - debug("%s: %s\n", __func__, c->name); - diff = rate; - - i = 0; - for (clock = cd->clocks; *clock; clock++, i++) { - struct refclk *ref = refclk_str_to_clk(*clock); - if (!ref) { - printf("%s: Lookup of %s failed\n", __func__, *clock); - return -EINVAL; - } - - /* round to the new rate */ - div = ref->clk.rate / rate; - if (div == 0) - div = 1; - - new_rate = ref->clk.rate / div; - - /* get the min diff */ - if (abs(new_rate - rate) < diff) { - diff = abs(new_rate - rate); - c->sel = i; - c->parent = &ref->clk; - c->rate = new_rate; - c->div = div; - } - } - - debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__, - c->name, c->rate, c->div, c->sel, c->parent->rate); - return ret; -} - -/* Get the rate of a peripheral clock */ -static unsigned long peri_clk_get_rate(struct clk *c) -{ - struct peri_clock *peri_clk = to_peri_clk(c); - struct peri_clk_data *cd = peri_clk->data; - void *base = (void *)c->ccu_clk_mgr_base; - int div = 1; - const char **clock; - struct refclk *ref; - u32 reg; - - debug("%s: %s\n", __func__, c->name); - if (selector_exists(&cd->sel)) { - reg = readl(base + cd->sel.offset); - c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width); - } else { - /* - * For peri clocks that don't have a selector, the single - * reference clock will always exist at index 0. - */ - c->sel = 0; - } - - if (divider_exists(&cd->div)) { - reg = readl(base + cd->div.offset); - div = bitfield_extract(reg, cd->div.shift, cd->div.width); - div += 1; - } - - clock = cd->clocks; - ref = refclk_str_to_clk(clock[c->sel]); - if (!ref) { - printf("%s: Can't lookup %s\n", __func__, clock[c->sel]); - return 0; - } - - c->parent = &ref->clk; - c->div = div; - c->rate = c->parent->rate / c->div; - debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__, - c->parent->rate, div, c->sel, c->rate); - - return c->rate; -} - -/* Peripheral clock operations */ -struct clk_ops peri_clk_ops = { - .enable = peri_clk_enable, - .set_rate = peri_clk_set_rate, - .get_rate = peri_clk_get_rate, -}; - -/* Enable a CCU clock */ -static int ccu_clk_enable(struct clk *c, int enable) -{ - struct ccu_clock *ccu_clk = to_ccu_clk(c); - void *base = (void *)c->ccu_clk_mgr_base; - int ret = 0; - u32 reg; - - debug("%s: %s\n", __func__, c->name); - if (!enable) - return -EINVAL; /* CCU clock cannot shutdown */ - - /* enable access */ - writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); - - /* config enable for policy engine */ - writel(1, base + ccu_clk->lvm_en_offset); - - /* wait for bit to go to 0 */ - ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0); - if (ret) - return ret; - - /* freq ID */ - if (!ccu_clk->freq_bit_shift) - ccu_clk->freq_bit_shift = 8; - - /* Set frequency id for each of the 4 policies */ - reg = ccu_clk->freq_id | - (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) | - (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) | - (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3)); - writel(reg, base + ccu_clk->policy_freq_offset); - - /* enable all clock mask */ - writel(0x7fffffff, base + ccu_clk->policy0_mask_offset); - writel(0x7fffffff, base + ccu_clk->policy1_mask_offset); - writel(0x7fffffff, base + ccu_clk->policy2_mask_offset); - writel(0x7fffffff, base + ccu_clk->policy3_mask_offset); - - if (ccu_clk->num_policy_masks == 2) { - writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset); - writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset); - writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset); - writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset); - } - - /* start policy engine */ - reg = readl(base + ccu_clk->policy_ctl_offset); - reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL); - writel(reg, base + ccu_clk->policy_ctl_offset); - - /* wait till started */ - ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0); - if (ret) - return ret; - - /* disable access */ - writel(0, base + WR_ACCESS_OFFSET); - - return ret; -} - -/* Get the CCU clock rate */ -static unsigned long ccu_clk_get_rate(struct clk *c) -{ - struct ccu_clock *ccu_clk = to_ccu_clk(c); - debug("%s: %s\n", __func__, c->name); - c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id]; - return c->rate; -} - -/* CCU clock operations */ -struct clk_ops ccu_clk_ops = { - .enable = ccu_clk_enable, - .get_rate = ccu_clk_get_rate, -}; - -/* Enable a bus clock */ -static int bus_clk_enable(struct clk *c, int enable) -{ - struct bus_clock *bus_clk = to_bus_clk(c); - struct bus_clk_data *cd = bus_clk->data; - void *base = (void *)c->ccu_clk_mgr_base; - int ret = 0; - u32 reg; - - debug("%s: %s\n", __func__, c->name); - /* enable access */ - writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); - - /* enable gating */ - reg = readl(base + cd->gate.offset); - if (!!(reg & (1 << cd->gate.status_bit)) == !!enable) - debug("%s already %s\n", c->name, - enable ? "enabled" : "disabled"); - else { - int want = (enable) ? 1 : 0; - reg |= (1 << cd->gate.hw_sw_sel_bit); - - if (enable) - reg |= (1 << cd->gate.en_bit); - else - reg &= ~(1 << cd->gate.en_bit); - - writel(reg, base + cd->gate.offset); - ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, - want); - if (ret) - return ret; - } - - /* disable access */ - writel(0, base + WR_ACCESS_OFFSET); - - return ret; -} - -/* Get the rate of a bus clock */ -static unsigned long bus_clk_get_rate(struct clk *c) -{ - struct bus_clock *bus_clk = to_bus_clk(c); - struct ccu_clock *ccu_clk; - - debug("%s: %s\n", __func__, c->name); - ccu_clk = to_ccu_clk(c->parent); - - c->rate = bus_clk->freq_tbl[ccu_clk->freq_id]; - c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate; - return c->rate; -} - -/* Bus clock operations */ -struct clk_ops bus_clk_ops = { - .enable = bus_clk_enable, - .get_rate = bus_clk_get_rate, -}; - -/* Enable a reference clock */ -static int ref_clk_enable(struct clk *c, int enable) -{ - debug("%s: %s\n", __func__, c->name); - return 0; -} - -/* Reference clock operations */ -struct clk_ops ref_clk_ops = { - .enable = ref_clk_enable, -}; - -/* - * clk.h implementation follows - */ - -/* Initialize the clock framework */ -int clk_init(void) -{ - debug("%s:\n", __func__); - return 0; -} - -/* Get a clock handle, give a name string */ -struct clk *clk_get(const char *con_id) -{ - int i; - struct clk_lookup *clk_tblp; - - debug("%s: %s\n", __func__, con_id); - - clk_tblp = arch_clk_tbl; - for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) { - if (clk_tblp->con_id) { - if (!con_id || strcmp(clk_tblp->con_id, con_id)) - continue; - return clk_tblp->clk; - } - } - return NULL; -} - -/* Enable a clock */ -int clk_enable(struct clk *c) -{ - int ret = 0; - - debug("%s: %s\n", __func__, c->name); - if (!c->ops || !c->ops->enable) - return -1; - - /* enable parent clock first */ - if (c->parent) - ret = clk_enable(c->parent); - - if (ret) - return ret; - - if (!c->use_cnt) - ret = c->ops->enable(c, 1); - c->use_cnt++; - - return ret; -} - -/* Disable a clock */ -void clk_disable(struct clk *c) -{ - debug("%s: %s\n", __func__, c->name); - if (!c->ops || !c->ops->enable) - return; - - if (c->use_cnt > 0) { - c->use_cnt--; - if (c->use_cnt == 0) - c->ops->enable(c, 0); - } - - /* disable parent */ - if (c->parent) - clk_disable(c->parent); -} - -/* Get the clock rate */ -unsigned long clk_get_rate(struct clk *c) -{ - unsigned long rate; - - if (!c || !c->ops || !c->ops->get_rate) - return 0; - debug("%s: %s\n", __func__, c->name); - - rate = c->ops->get_rate(c); - debug("%s: rate = %ld\n", __func__, rate); - return rate; -} - -/* Set the clock rate */ -int clk_set_rate(struct clk *c, unsigned long rate) -{ - int ret; - - if (!c || !c->ops || !c->ops->set_rate) - return -EINVAL; - debug("%s: %s rate=%ld\n", __func__, c->name, rate); - - if (c->use_cnt) - return -EINVAL; - - ret = c->ops->set_rate(c, rate); - - return ret; -} - -/* Not required for this arch */ -/* -long clk_round_rate(struct clk *clk, unsigned long rate); -int clk_set_parent(struct clk *clk, struct clk *parent); -struct clk *clk_get_parent(struct clk *clk); -*/ diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.h b/arch/arm/cpu/armv7/bcm235xx/clk-core.h deleted file mode 100644 index ace384dea78..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.h +++ /dev/null @@ -1,491 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <linux/stddef.h> -#include <linux/stringify.h> - -#ifdef CONFIG_CLK_DEBUG -#undef writel -#undef readl -static inline void writel(u32 val, void *addr) -{ - printf("Write [0x%p] = 0x%08x\n", addr, val); - *(u32 *)addr = val; -} - -static inline u32 readl(void *addr) -{ - u32 val = *(u32 *)addr; - printf("Read [0x%p] = 0x%08x\n", addr, val); - return val; -} -#endif - -struct clk; - -struct clk_lookup { - const char *dev_id; - const char *con_id; - struct clk *clk; -}; - -extern struct clk_lookup arch_clk_tbl[]; -extern unsigned int arch_clk_tbl_array_size; - -/** - * struct clk_ops - standard clock operations - * @enable: enable/disable clock, see clk_enable() and clk_disable() - * @set_rate: set the clock rate, see clk_set_rate(). - * @get_rate: get the clock rate, see clk_get_rate(). - * @round_rate: round a given clock rate, see clk_round_rate(). - * @set_parent: set the clock's parent, see clk_set_parent(). - * - * Group the common clock implementations together so that we - * don't have to keep setting the same fiels again. We leave - * enable in struct clk. - * - */ -struct clk_ops { - int (*enable)(struct clk *c, int enable); - int (*set_rate)(struct clk *c, unsigned long rate); - unsigned long (*get_rate)(struct clk *c); - unsigned long (*round_rate)(struct clk *c, unsigned long rate); - int (*set_parent)(struct clk *c, struct clk *parent); -}; - -struct clk { - struct clk *parent; - const char *name; - int use_cnt; - unsigned long rate; /* in HZ */ - - /* programmable divider. 0 means fixed ratio to parent clock */ - unsigned long div; - - struct clk_src *src; - struct clk_ops *ops; - - unsigned long ccu_clk_mgr_base; - int sel; -}; - -struct refclk *refclk_str_to_clk(const char *name); - -/* The common clock framework uses u8 to represent a parent index */ -#define PARENT_COUNT_MAX ((u32)U8_MAX) - -#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ -#define BAD_CLK_NAME ((const char *)-1) - -#define BAD_SCALED_DIV_VALUE U64_MAX - -/* - * Utility macros for object flag management. If possible, flags - * should be defined such that 0 is the desired default value. - */ -#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag -#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) -#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) -#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) -#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) - -/* Clock field state tests */ - -#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) -#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) -#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) -#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) -#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) -#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) - -#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) - -#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) -#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) -#define divider_has_fraction(div) (!divider_is_fixed(div) && \ - (div)->frac_width > 0) - -#define selector_exists(sel) ((sel)->width != 0) -#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) - -/* Clock type, used to tell common block what it's part of */ -enum bcm_clk_type { - bcm_clk_none, /* undefined clock type */ - bcm_clk_bus, - bcm_clk_core, - bcm_clk_peri -}; - -/* - * Gating control and status is managed by a 32-bit gate register. - * - * There are several types of gating available: - * - (no gate) - * A clock with no gate is assumed to be always enabled. - * - hardware-only gating (auto-gating) - * Enabling or disabling clocks with this type of gate is - * managed automatically by the hardware. Such clocks can be - * considered by the software to be enabled. The current status - * of auto-gated clocks can be read from the gate status bit. - * - software-only gating - * Auto-gating is not available for this type of clock. - * Instead, software manages whether it's enabled by setting or - * clearing the enable bit. The current gate status of a gate - * under software control can be read from the gate status bit. - * To ensure a change to the gating status is complete, the - * status bit can be polled to verify that the gate has entered - * the desired state. - * - selectable hardware or software gating - * Gating for this type of clock can be configured to be either - * under software or hardware control. Which type is in use is - * determined by the hw_sw_sel bit of the gate register. - */ -struct bcm_clk_gate { - u32 offset; /* gate register offset */ - u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ - u32 en_bit; /* 0: disable; 1: enable */ - u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ - u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ -}; - -/* - * Gate flags: - * HW means this gate can be auto-gated - * SW means the state of this gate can be software controlled - * NO_DISABLE means this gate is (only) enabled if under software control - * SW_MANAGED means the status of this gate is under software control - * ENABLED means this software-managed gate is *supposed* to be enabled - */ -#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ -#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ -#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ -#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ -#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ -#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ - -/* - * Gate initialization macros. - * - * Any gate initially under software control will be enabled. - */ - -/* A hardware/software gate initially under software control */ -#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .en_bit = (_en_bit), \ - .hw_sw_sel_bit = (_hw_sw_sel_bit), \ - .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ - FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ - FLAG(GATE, EXISTS), \ - } - -/* A hardware/software gate initially under hardware control */ -#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .en_bit = (_en_bit), \ - .hw_sw_sel_bit = (_hw_sw_sel_bit), \ - .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ - FLAG(GATE, EXISTS), \ - } - -/* A hardware-or-enabled gate (enabled if not under hardware control) */ -#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .en_bit = (_en_bit), \ - .hw_sw_sel_bit = (_hw_sw_sel_bit), \ - .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ - FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ - } - -/* A software-only gate */ -#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .en_bit = (_en_bit), \ - .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ - FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ - } - -/* A hardware-only gate */ -#define HW_ONLY_GATE(_offset, _status_bit) \ - { \ - .offset = (_offset), \ - .status_bit = (_status_bit), \ - .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ - } - -/* - * Each clock can have zero, one, or two dividers which change the - * output rate of the clock. Each divider can be either fixed or - * variable. If there are two dividers, they are the "pre-divider" - * and the "regular" or "downstream" divider. If there is only one, - * there is no pre-divider. - * - * A fixed divider is any non-zero (positive) value, and it - * indicates how the input rate is affected by the divider. - * - * The value of a variable divider is maintained in a sub-field of a - * 32-bit divider register. The position of the field in the - * register is defined by its offset and width. The value recorded - * in this field is always 1 less than the value it represents. - * - * In addition, a variable divider can indicate that some subset - * of its bits represent a "fractional" part of the divider. Such - * bits comprise the low-order portion of the divider field, and can - * be viewed as representing the portion of the divider that lies to - * the right of the decimal point. Most variable dividers have zero - * fractional bits. Variable dividers with non-zero fraction width - * still record a value 1 less than the value they represent; the - * added 1 does *not* affect the low-order bit in this case, it - * affects the bits above the fractional part only. (Often in this - * code a divider field value is distinguished from the value it - * represents by referring to the latter as a "divisor".) - * - * In order to avoid dealing with fractions, divider arithmetic is - * performed using "scaled" values. A scaled value is one that's - * been left-shifted by the fractional width of a divider. Dividing - * a scaled value by a scaled divisor produces the desired quotient - * without loss of precision and without any other special handling - * for fractions. - * - * The recorded value of a variable divider can be modified. To - * modify either divider (or both), a clock must be enabled (i.e., - * using its gate). In addition, a trigger register (described - * below) must be used to commit the change, and polled to verify - * the change is complete. - */ -struct bcm_clk_div { - union { - struct { /* variable divider */ - u32 offset; /* divider register offset */ - u32 shift; /* field shift */ - u32 width; /* field width */ - u32 frac_width; /* field fraction width */ - - u64 scaled_div; /* scaled divider value */ - }; - u32 fixed; /* non-zero fixed divider value */ - }; - u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ -}; - -/* - * Divider flags: - * EXISTS means this divider exists - * FIXED means it is a fixed-rate divider - */ -#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ -#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ - -/* Divider initialization macros */ - -/* A fixed (non-zero) divider */ -#define FIXED_DIVIDER(_value) \ - { \ - .fixed = (_value), \ - .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ - } - -/* A divider with an integral divisor */ -#define DIVIDER(_offset, _shift, _width) \ - { \ - .offset = (_offset), \ - .shift = (_shift), \ - .width = (_width), \ - .scaled_div = BAD_SCALED_DIV_VALUE, \ - .flags = FLAG(DIV, EXISTS), \ - } - -/* A divider whose divisor has an integer and fractional part */ -#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ - { \ - .offset = (_offset), \ - .shift = (_shift), \ - .width = (_width), \ - .frac_width = (_frac_width), \ - .scaled_div = BAD_SCALED_DIV_VALUE, \ - .flags = FLAG(DIV, EXISTS), \ - } - -/* - * Clocks may have multiple "parent" clocks. If there is more than - * one, a selector must be specified to define which of the parent - * clocks is currently in use. The selected clock is indicated in a - * sub-field of a 32-bit selector register. The range of - * representable selector values typically exceeds the number of - * available parent clocks. Occasionally the reset value of a - * selector field is explicitly set to a (specific) value that does - * not correspond to a defined input clock. - * - * We register all known parent clocks with the common clock code - * using a packed array (i.e., no empty slots) of (parent) clock - * names, and refer to them later using indexes into that array. - * We maintain an array of selector values indexed by common clock - * index values in order to map between these common clock indexes - * and the selector values used by the hardware. - * - * Like dividers, a selector can be modified, but to do so a clock - * must be enabled, and a trigger must be used to commit the change. - */ -struct bcm_clk_sel { - u32 offset; /* selector register offset */ - u32 shift; /* field shift */ - u32 width; /* field width */ - - u32 parent_count; /* number of entries in parent_sel[] */ - u32 *parent_sel; /* array of parent selector values */ - u8 clk_index; /* current selected index in parent_sel[] */ -}; - -/* Selector initialization macro */ -#define SELECTOR(_offset, _shift, _width) \ - { \ - .offset = (_offset), \ - .shift = (_shift), \ - .width = (_width), \ - .clk_index = BAD_CLK_INDEX, \ - } - -/* - * Making changes to a variable divider or a selector for a clock - * requires the use of a trigger. A trigger is defined by a single - * bit within a register. To signal a change, a 1 is written into - * that bit. To determine when the change has been completed, that - * trigger bit is polled; the read value will be 1 while the change - * is in progress, and 0 when it is complete. - * - * Occasionally a clock will have more than one trigger. In this - * case, the "pre-trigger" will be used when changing a clock's - * selector and/or its pre-divider. - */ -struct bcm_clk_trig { - u32 offset; /* trigger register offset */ - u32 bit; /* trigger bit */ - u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ -}; - -/* - * Trigger flags: - * EXISTS means this trigger exists - */ -#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ - -/* Trigger initialization macro */ -#define TRIGGER(_offset, _bit) \ - { \ - .offset = (_offset), \ - .bit = (_bit), \ - .flags = FLAG(TRIG, EXISTS), \ - } - -struct bus_clk_data { - struct bcm_clk_gate gate; -}; - -struct core_clk_data { - struct bcm_clk_gate gate; -}; - -struct peri_clk_data { - struct bcm_clk_gate gate; - struct bcm_clk_trig pre_trig; - struct bcm_clk_div pre_div; - struct bcm_clk_trig trig; - struct bcm_clk_div div; - struct bcm_clk_sel sel; - const char *clocks[]; /* must be last; use CLOCKS() to declare */ -}; -#define CLOCKS(...) { __VA_ARGS__, NULL, } -#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ - -struct refclk { - struct clk clk; -}; - -struct peri_clock { - struct clk clk; - struct peri_clk_data *data; -}; - -struct ccu_clock { - struct clk clk; - - int num_policy_masks; - unsigned long policy_freq_offset; - int freq_bit_shift; /* 8 for most CCUs */ - unsigned long policy_ctl_offset; - unsigned long policy0_mask_offset; - unsigned long policy1_mask_offset; - unsigned long policy2_mask_offset; - unsigned long policy3_mask_offset; - unsigned long policy0_mask2_offset; - unsigned long policy1_mask2_offset; - unsigned long policy2_mask2_offset; - unsigned long policy3_mask2_offset; - unsigned long lvm_en_offset; - - int freq_id; - unsigned long *freq_tbl; -}; - -struct bus_clock { - struct clk clk; - struct bus_clk_data *data; - unsigned long *freq_tbl; -}; - -struct ref_clock { - struct clk clk; -}; - -static inline int is_same_clock(struct clk *a, struct clk *b) -{ - return a == b; -} - -#define to_clk(p) (&((p)->clk)) -#define name_to_clk(name) (&((name##_clk).clk)) -/* declare a struct clk_lookup */ -#define CLK_LK(name) \ -{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),} - -static inline struct refclk *to_refclk(struct clk *clock) -{ - return container_of(clock, struct refclk, clk); -} - -static inline struct peri_clock *to_peri_clk(struct clk *clock) -{ - return container_of(clock, struct peri_clock, clk); -} - -static inline struct ccu_clock *to_ccu_clk(struct clk *clock) -{ - return container_of(clock, struct ccu_clock, clk); -} - -static inline struct bus_clock *to_bus_clk(struct clk *clock) -{ - return container_of(clock, struct bus_clock, clk); -} - -static inline struct ref_clock *to_ref_clk(struct clk *clock) -{ - return container_of(clock, struct ref_clock, clk); -} - -extern struct clk_ops peri_clk_ops; -extern struct clk_ops ccu_clk_ops; -extern struct clk_ops bus_clk_ops; -extern struct clk_ops ref_clk_ops; - -int clk_get_and_enable(char *clkstr); diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c b/arch/arm/cpu/armv7/bcm235xx/clk-eth.c deleted file mode 100644 index 5f7cc4a102d..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-eth.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include "clk-core.h" - -#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR -#define WR_ACCESS_PASSWORD 0xA5A500 - -#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00) - -#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58) -#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000 -#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001 - -#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38) -#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001 - -#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04) -#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300 -#define ESW_SYS_DIV_DIV_MASK 0x0000001C -#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100 -#define ESW_SYS_DIV_DIV_SELECT 0x4 -#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001 - -#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04) -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040 -#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0 -#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001 - -#define PLL_MAX_RETRY 100 - -/* Enable appropriate clocks for Ethernet */ -int clk_eth_enable(void) -{ - int rc = -1; - int retry_count = 0; - rc = clk_get_and_enable("esub_ccu_clk"); - - /* Enable Access to CCU registers */ - writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR); - - writel(readl(PLLE_POST_RESETB_ADDR) & - ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Take PLL out of reset and put into normal mode */ - writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, - PLLE_RESETB_ADDR); - - /* Wait for PLL lock */ - rc = -1; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - writel(readl(PLLE_POST_RESETB_ADDR) | - PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ - writel((readl(ESW_SYS_DIV_ADDR) & - ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) | - ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT, - ESW_SYS_DIV_ADDR); - - writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, - ESW_SYS_DIV_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* switch Esub AXI clock to 208MHz */ - writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) | - ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* Disable Access to CCU registers */ - writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR); - - return rc; -} diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c b/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c deleted file mode 100644 index f3ff29bebe8..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-sdio.c +++ /dev/null @@ -1,71 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include "clk-core.h" - -/* Enable appropriate clocks for an SDIO port */ -int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) -{ - int ret; - struct clk *c; - - char *clkstr; - char *slpstr; - char *ahbstr; - - switch ((u32) base) { - case CONFIG_SYS_SDIO_BASE0: - clkstr = CONFIG_SYS_SDIO0 "_clk"; - ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk"; - slpstr = CONFIG_SYS_SDIO0 "_sleep_clk"; - break; - case CONFIG_SYS_SDIO_BASE1: - clkstr = CONFIG_SYS_SDIO1 "_clk"; - ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk"; - slpstr = CONFIG_SYS_SDIO1 "_sleep_clk"; - break; - case CONFIG_SYS_SDIO_BASE2: - clkstr = CONFIG_SYS_SDIO2 "_clk"; - ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk"; - slpstr = CONFIG_SYS_SDIO2 "_sleep_clk"; - break; - case CONFIG_SYS_SDIO_BASE3: - clkstr = CONFIG_SYS_SDIO3 "_clk"; - ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk"; - slpstr = CONFIG_SYS_SDIO3 "_sleep_clk"; - break; - default: - printf("%s: base 0x%p not found\n", __func__, base); - return -EINVAL; - } - - ret = clk_get_and_enable(ahbstr); - if (ret) - return ret; - - ret = clk_get_and_enable(slpstr); - if (ret) - return ret; - - c = clk_get(clkstr); - if (c) { - ret = clk_set_rate(c, rate); - if (ret) - return ret; - - ret = clk_enable(c); - if (ret) - return ret; - } else { - printf("%s: Couldn't find %s\n", __func__, clkstr); - return -EINVAL; - } - *actual_ratep = rate; - return 0; -} diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c b/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c deleted file mode 100644 index 87918059408..00000000000 --- a/arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include "clk-core.h" - -/* Enable appropriate clocks for the USB OTG port */ -int clk_usb_otg_enable(void *base) -{ - char *ahbstr; - - switch ((u32) base) { - case HSOTG_BASE_ADDR: - ahbstr = "usb_otg_ahb_clk"; - break; - default: - printf("%s: base 0x%p not found\n", __func__, base); - return -EINVAL; - } - - return clk_get_and_enable(ahbstr); -} diff --git a/arch/arm/cpu/armv7/bcm281xx/Makefile b/arch/arm/cpu/armv7/bcm281xx/Makefile index e5099975cba..f6323af1d06 100644 --- a/arch/arm/cpu/armv7/bcm281xx/Makefile +++ b/arch/arm/cpu/armv7/bcm281xx/Makefile @@ -7,5 +7,4 @@ obj-y += clk-core.o obj-y += clk-bcm281xx.o obj-y += clk-sdio.o obj-y += clk-bsc.o -obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o obj-y += clk-usb-otg.o diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c index b258fea45c8..39eb2ca01dc 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c @@ -307,27 +307,6 @@ static struct ccu_clock kps_ccu_clk = { .freq_tbl = slave_axi_freq_tbl, }; -#ifdef CONFIG_BCM_SF2_ETH -static struct ccu_clock esub_ccu_clk = { - .clk = { - .name = "esub_ccu_clk", - .ops = &ccu_clk_ops, - .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR, - }, - .num_policy_masks = 1, - .policy_freq_offset = 0x00000008, - .freq_bit_shift = 8, - .policy_ctl_offset = 0x0000000c, - .policy0_mask_offset = 0x00000010, - .policy1_mask_offset = 0x00000014, - .policy2_mask_offset = 0x00000018, - .policy3_mask_offset = 0x0000001c, - .lvm_en_offset = 0x00000034, - .freq_id = 2, - .freq_tbl = esub_freq_tbl, -}; -#endif - /* * Bus clocks */ @@ -562,9 +541,6 @@ struct clk_lookup arch_clk_tbl[] = { CLK_LK(bsc1_apb), CLK_LK(bsc2_apb), CLK_LK(bsc3_apb), -#ifdef CONFIG_BCM_SF2_ETH - CLK_LK(esub_ccu), -#endif }; /* public array size */ diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c b/arch/arm/cpu/armv7/bcm281xx/clk-eth.c deleted file mode 100644 index 5f7cc4a102d..00000000000 --- a/arch/arm/cpu/armv7/bcm281xx/clk-eth.c +++ /dev/null @@ -1,142 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include "clk-core.h" - -#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR -#define WR_ACCESS_PASSWORD 0xA5A500 - -#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00) - -#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58) -#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000 -#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001 - -#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38) -#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001 - -#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04) -#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300 -#define ESW_SYS_DIV_DIV_MASK 0x0000001C -#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100 -#define ESW_SYS_DIV_DIV_SELECT 0x4 -#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001 - -#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04) -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C -#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040 -#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0 -#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001 - -#define PLL_MAX_RETRY 100 - -/* Enable appropriate clocks for Ethernet */ -int clk_eth_enable(void) -{ - int rc = -1; - int retry_count = 0; - rc = clk_get_and_enable("esub_ccu_clk"); - - /* Enable Access to CCU registers */ - writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR); - - writel(readl(PLLE_POST_RESETB_ADDR) & - ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Take PLL out of reset and put into normal mode */ - writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK, - PLLE_RESETB_ADDR); - - /* Wait for PLL lock */ - rc = -1; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - writel(readl(PLLE_POST_RESETB_ADDR) | - PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK, - PLLE_POST_RESETB_ADDR); - - /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */ - writel((readl(ESW_SYS_DIV_ADDR) & - ~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) | - ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT, - ESW_SYS_DIV_ADDR); - - writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK, - ESW_SYS_DIV_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* switch Esub AXI clock to 208MHz */ - writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) | - ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT | - ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) | - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK, - ESUB_AXI_DIV_DEBUG_ADDR); - - /* Wait for trigger complete */ - rc = -1; - retry_count = 0; - while (retry_count < PLL_MAX_RETRY) { - udelay(100); - if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) & - ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) { - rc = 0; - break; - } - retry_count++; - } - - if (rc == -1) { - printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n", - __func__); - return -1; - } - - /* Disable Access to CCU registers */ - writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR); - - return rc; -} diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c index b4440d3f3f8..bea0e1d3263 100644 --- a/arch/arm/cpu/armv7m/cpu.c +++ b/arch/arm/cpu/armv7m/cpu.c @@ -57,7 +57,7 @@ void reset_cpu(void) | V7M_AIRCR_SYSRESET, &V7M_SCB->aircr); } -void spl_perform_fixups(struct spl_image_info *spl_image) +void spl_perform_arch_fixups(struct spl_image_info *spl_image) { spl_image->entry_point |= 0x1; } diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 199335cd604..dfc4ce851c3 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -4,6 +4,14 @@ config CMO_BY_VA_ONLY bool "Force cache maintenance to be exclusively by VA" depends on !SYS_DISABLE_DCACHE_OPS +config ARMV8_CNTFRQ_BROKEN + bool "Fix broken ARMv8 generic timer" + depends on SYS_ARCH_TIMER + help + Say Y here if U-Boot depends on a prior stage bootloader, which + does not set the CNTFRQ_EL0 frequency, and its not possible to + set it from U-Boot either. + config ARMV8_SPL_EXCEPTION_VECTORS bool "Install crash dump exception vectors" depends on SPL diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 1c1e33bec24..0309da6d397 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -58,6 +58,54 @@ static int get_effective_el(void) return el; } +int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs) +{ + unsigned int i; + + if (index + CONFIG_NR_DRAM_BANKS >= len) { + log_err("%s: Provided mem_map array has insufficient size for DRAM entries\n", + __func__); + return -ENOMEM; + } + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + mem_map[index].virt = gd->bd->bi_dram[i].start; + mem_map[index].phys = gd->bd->bi_dram[i].start; + mem_map[index].size = gd->bd->bi_dram[i].size; + mem_map[index].attrs = attrs; + index++; + } + + memset(&mem_map[index], 0, sizeof(mem_map[index])); + + return 0; +} + +int mmu_unmap_reserved_mem(const char *name, bool check_nomap) +{ + void *fdt = (void *)gd->fdt_blob; + char node_path[128]; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + snprintf(node_path, sizeof(node_path), "/reserved-memory/%s", name); + ret = fdt_path_offset(fdt, node_path); + if (ret < 0) + return ret; + + if (check_nomap && !fdtdec_get_bool(fdt, ret, "no-map")) + return -EINVAL; + + addr = fdtdec_get_addr_size(fdt, ret, "reg", &size); + if (addr == FDT_ADDR_T_NONE) + return -1; + + mmu_change_region_attr_nobreak(addr, size, PTE_TYPE_FAULT); + + return 0; +} + u64 get_tcr(u64 *pips, u64 *pva_bits) { int el = get_effective_el(); @@ -830,16 +878,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop) void dcache_enable(void) { /* The data cache is not active unless the mmu is enabled */ - if (!(get_sctlr() & CR_M)) { - invalidate_dcache_all(); - __asm_invalidate_tlb_all(); + if (!mmu_status()) mmu_setup(); - } /* Set up page tables only once (it is done also by mmu_setup()) */ if (!gd->arch.tlb_fillptr) setup_all_pgtables(); + invalidate_dcache_all(); + __asm_invalidate_tlb_all(); set_sctlr(get_sctlr() | CR_C); } @@ -1134,11 +1181,6 @@ int icache_status(void) return (get_sctlr() & CR_I) != 0; } -int mmu_status(void) -{ - return (get_sctlr() & CR_M) != 0; -} - void invalidate_icache_all(void) { __asm_invalidate_icache_all(); @@ -1160,17 +1202,17 @@ int icache_status(void) return 0; } -int mmu_status(void) -{ - return 0; -} - void invalidate_icache_all(void) { } #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */ +int mmu_status(void) +{ + return (get_sctlr() & CR_M) != 0; +} + /* * Enable dCache & iCache, whether cache is actually enabled * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c index 1de7ec596fc..744ab3b91e5 100644 --- a/arch/arm/cpu/armv8/generic_timer.c +++ b/arch/arm/cpu/armv8/generic_timer.c @@ -19,6 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; unsigned long notrace get_tbclk(void) { unsigned long cntfrq; + + if (IS_ENABLED(CONFIG_ARMV8_CNTFRQ_BROKEN) && gd->arch.timer_rate_hz) + return gd->arch.timer_rate_hz; + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); return cntfrq; } diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c index 492353c93df..f4009e89a98 100644 --- a/arch/arm/cpu/armv8/spl_data.c +++ b/arch/arm/cpu/armv8/spl_data.c @@ -11,15 +11,15 @@ char __data_save_end[0] __section(".__data_save_end"); u32 cold_reboot_flag = 1; -u32 __weak reset_flag(void) +u32 __weak reset_flag(u32 flag) { - return 1; + return flag; } void spl_save_restore_data(void) { u32 data_size = __data_save_end - __data_save_start; - cold_reboot_flag = reset_flag(); + cold_reboot_flag = reset_flag(cold_reboot_flag); if (cold_reboot_flag == 1) { /* Save data section to data_save section */ diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 829a620faeb..40c342e97e9 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -387,23 +387,18 @@ ENDPROC(c_runtime_cpu_setup) WEAK(save_boot_params) #if (IS_ENABLED(CONFIG_BLOBLIST)) /* Calculate the PC-relative address of saved_args */ - adr x9, saved_args_offset - ldr w10, saved_args_offset - add x9, x9, w10, sxtw - - stp x0, x1, [x9] - stp x2, x3, [x9, #16] + adrp x9, saved_args + add x9, x9, :lo12:saved_args + stp x0, x1, [x9] + stp x2, x3, [x9, #16] #endif b save_boot_params_ret /* back to my caller */ ENDPROC(save_boot_params) #if (IS_ENABLED(CONFIG_BLOBLIST)) -saved_args_offset: - .long saved_args - . /* offset from current code to save_args */ - - .section .data - .align 2 - .global saved_args +.section .data +.align 2 +.global saved_args saved_args: .rept 4 .dword 0 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0dc7e190eb9..865ceb65f9a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -92,6 +92,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra20-motorola-olympus.dtb \ tegra20-paz00.dtb \ tegra20-plutux.dtb \ + tegra20-samsung-bose.dtb \ + tegra20-samsung-n1.dtb \ tegra20-seaboard.dtb \ tegra20-tec.dtb \ tegra20-trimslice.dtb \ @@ -117,10 +119,13 @@ dtb-$(CONFIG_ARCH_TEGRA) += \ tegra30-lg-p895.dtb \ tegra30-microsoft-surface-rt.dtb \ tegra30-ouya.dtb \ + tegra30-pegatron-chagall.dtb \ tegra30-tec-ng.dtb \ tegra30-wexler-qc750.dtb \ tegra114-asus-tf701t.dtb \ tegra114-dalmore.dtb \ + tegra114-microsoft-surface-2-0b.dtb \ + tegra114-microsoft-surface-2-13.dtb \ tegra114-nvidia-tegratab.dtb \ tegra124-apalis.dtb \ tegra124-jetson-tk1.dtb \ @@ -445,7 +450,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ - socfpga_agilex_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_arria5_secu1.dtb \ socfpga_arria5_socdk.dtb \ @@ -646,13 +650,6 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-oka40i-c.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v40-bananapi-m2-berry.dtb -dtb-$(CONFIG_MACH_SUN8I_V3S) += \ - sun8i-s3-elimo-initium.dtb \ - sun8i-s3-pinecube.dtb \ - sun8i-v3-sl631-imx179.dtb \ - sun8i-v3s-licheepi-zero.dtb -dtb-$(CONFIG_MACH_SUN8I_R528) += \ - sun8i-t113s-mangopi-mq-r-t113.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-bananapi-m2-plus.dtb \ sun50i-h5-emlid-neutis-n5-devboard.dtb \ @@ -694,8 +691,6 @@ dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-sopine-baseboard.dtb \ sun50i-a64-teres-i.dtb dtb-$(CONFIG_MACH_SUN9I) += \ - sun9i-a80-optimus.dtb \ - sun9i-a80-cubieboard4.dtb \ sun9i-a80-cx-a99.dtb dtb-$(CONFIG_VF610) += vf610-colibri-eval-v3.dtb \ @@ -836,9 +831,7 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-liteboard.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ imx6ul-pico-hobbit.dtb \ - imx6ul-pico-pi.dtb \ - imx6ul-kontron-bl.dtb \ - imx6ull-kontron-bl.dtb + imx6ul-pico-pi.dtb dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ @@ -894,8 +887,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-data-modul-edm-sbc.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ - imx8mm-kontron-bl.dtb \ - imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-phg.dtb \ imx8mq-cm.dtb \ @@ -1112,9 +1103,10 @@ dtb-$(CONFIG_SOC_K3_AM62A7) += \ k3-am62a7-r5-sk.dtb \ k3-am62a7-r5-phycore-som-2gb.dtb +dtb-$(CONFIG_SOC_K3_AM62D2) += k3-am62d2-r5-evm.dtb + dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \ - k3-am62p5-verdin-r5.dtb \ - k3-am62p5-verdin-wifi-dev.dtb + k3-am62p5-verdin-r5.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi b/arch/arm/dts/apq8016-sbc-u-boot.dtsi index 26d4506815e..de77a31cf11 100644 --- a/arch/arm/dts/apq8016-sbc-u-boot.dtsi +++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi @@ -9,12 +9,3 @@ reg = <0 0x80000000 0 0x40000000>; }; }; - -/* - * When running as a first-stage bootloader, we need to re-configure the UART pins - * because SBL de-initialises them. Indicate that the UART pins should be configured - * during all boot stages. - */ -&blsp_uart2_console_default { - bootph-all; -}; diff --git a/arch/arm/dts/en7523-evb-u-boot.dtsi b/arch/arm/dts/en7523-evb-u-boot.dtsi new file mode 100644 index 00000000000..c109d6794fb --- /dev/null +++ b/arch/arm/dts/en7523-evb-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/ { + /* When running as a first-stage bootloader this isn't filled in automatically */ + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +#include "en7523-u-boot.dtsi" diff --git a/arch/arm/dts/en7523-u-boot.dtsi b/arch/arm/dts/en7523-u-boot.dtsi new file mode 100644 index 00000000000..90838c00a85 --- /dev/null +++ b/arch/arm/dts/en7523-u-boot.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <dt-bindings/reset/airoha,en7523-reset.h> + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + atf-reserved-memory@80000000 { + no-map; + reg = <0x80000000 0x40000>; + }; + }; + + scu: system-controller@1fa20000 { + compatible = "airoha,en7523-scu"; + reg = <0x1fa20000 0x400>, + <0x1fb00000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + eth: ethernet@1fb50000 { + compatible = "airoha,en7523-eth"; + reg = <0x1fb50000 0x2600>, + <0x1fb54000 0x2000>, + <0x1fb56000 0x2000>; + reg-names = "fe", "qdma0", "qdma1"; + + resets = <&scu EN7523_FE_RST>, + <&scu EN7523_FE_PDMA_RST>, + <&scu EN7523_FE_QDMA_RST>, + <&scu EN7523_DUAL_HSI0_MAC_RST>, + <&scu EN7523_DUAL_HSI1_MAC_RST>, + <&scu EN7523_HSI_MAC_RST>; + reset-names = "fe", "pdma", "qdma", + "hsi0-mac", "hsi1-mac", "hsi-mac"; + }; + + switch: switch@1fb58000 { + compatible = "airoha,en7523-switch"; + reg = <0x1fb58000 0x8000>; + }; + + snfi: spi@1fa10000 { + compatible = "airoha,en7523-snand", "airoha,en7581-snand"; + reg = <0x1fa10000 0x140>, + <0x1fa11000 0x600>; + + clocks = <&scu EN7523_CLK_SPI>; + clock-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; + }; +}; + +&uart1 { + bootph-all; +}; diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index 88e9c0ed2bb..38b168950df 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -102,9 +102,9 @@ status = "okay"; max8997-pmic@66 { - compatible = "maxim,max8997"; + compatible = "maxim,max8997-pmic"; reg = <0x66 0 0>; - voltage-regulators { + regulators { valive_reg: LDO2 { regulator-name = "VALIVE_1.1V_C210"; regulator-min-microvolt = <1100000>; diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index c87b92be609..cfa99b62828 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -77,7 +77,7 @@ max8998-pmic@66 { compatible = "maxim,max8998"; reg = <0x66 0 0>; - voltage-regulators { + regulators { ldo2_reg: LDO2 { regulator-name = "VALIVE_1.2V"; regulator-min-microvolt = <1200000>; diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts b/arch/arm/dts/exynos5422-odroidxu3.dts index ef25cf77447..e147fcb8643 100644 --- a/arch/arm/dts/exynos5422-odroidxu3.dts +++ b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -40,7 +40,7 @@ s2mps11_pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; - voltage-regulators { + regulators { ldo1_reg: LDO1 { regulator-name = "vdd_ldo1"; regulator-min-microvolt = <1000000>; diff --git a/arch/arm/dts/imx6ul-kontron-bl-43.dts b/arch/arm/dts/imx6ul-kontron-bl-43.dts deleted file mode 100644 index 0c643706a15..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl-43.dts +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> - */ - -#include "imx6ul-kontron-bl.dts" - -/ { - model = "Kontron BL i.MX6UL 43 (N631X S 43)"; - compatible = "kontron,bl-imx6ul-43", "kontron,bl-imx6ul", - "kontron,sl-imx6ul", "fsl,imx6ul"; - - backlight { - compatible = "pwm-backlight"; - pwms = <&pwm7 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; -}; - -&i2c4 { - touchscreen@5d { - compatible = "goodix,gt928"; - reg = <0x5d>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cap_touch>; - interrupt-parent = <&gpio5>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; - irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; - }; -}; - -&lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; - /* Leave status disabled because of missing display panel node */ -}; - -&pwm7 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm7>; - status = "okay"; -}; - -&iomuxc { - pinctrl_cap_touch: captouchgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */ - MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */ - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */ - >; - }; - - pinctrl_lcdif_ctrl: lcdifctrlgrp { - fsl,pins = < - MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 - MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 - MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 - MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 - MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 - >; - }; - - pinctrl_lcdif_dat: lcdifdatgrp { - fsl,pins = < - MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 - MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 - MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 - MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 - MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 - MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 - MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 - MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 - MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 - MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 - MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 - MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 - MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 - MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 - MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 - MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 - MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 - MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 - MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 - MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 - MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 - MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 - MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 - MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 - >; - }; - - pinctrl_pwm7: pwm7grp { - fsl,pins = < - MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi index 39cc6d05d3f..042bda7462a 100644 --- a/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-kontron-bl-common-u-boot.dtsi @@ -30,9 +30,6 @@ * in Linux we can't assign the shared reset GPIO to the PHYs, as this * would cause Linux to reset both PHYs every time one of them gets * reinitialized. - * - * Also we disable the second ethernet as it currently doesn't work with - * the devicetree setup in U-Boot. */ &fec1 { @@ -53,11 +50,16 @@ clocks = <&clks IMX6UL_CLK_ENET_REF>; clock-names = "rmii-ref"; }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + micrel,led-mode = <0>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; }; }; &fec2 { - status = "disabled"; - /delete-property/ phy-handle; /delete-node/ mdio; }; diff --git a/arch/arm/dts/imx6ul-kontron-bl-common.dtsi b/arch/arm/dts/imx6ul-kontron-bl-common.dtsi deleted file mode 100644 index a6cf0f21c66..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl-common.dtsi +++ /dev/null @@ -1,406 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> - */ - -#include <dt-bindings/gpio/gpio.h> - -/ { - gpio-leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led1 { - label = "debug-led1"; - gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; - default-state = "off"; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "debug-led2"; - gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - led3 { - label = "debug-led3"; - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - }; - - pwm-beeper { - compatible = "pwm-beeper"; - pwms = <&pwm8 0 5000>; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_vref_adc: regulator-vref-adc { - compatible = "regulator-fixed"; - regulator-name = "vref-adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&adc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc1>; - num-channels = <3>; - vref-supply = <®_vref_adc>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&ecspi1 { - cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - - eeprom@0 { - compatible = "anvo,anv32e61w", "atmel,at25"; - reg = <0>; - spi-max-frequency = <20000000>; - spi-cpha; - spi-cpol; - pagesize = <1>; - size = <8192>; - address-width = <16>; - }; -}; - -&fec1 { - pinctrl-0 = <&pinctrl_enet1>; - /delete-node/ mdio; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy2>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - - ethphy2: ethernet-phy@2 { - reg = <2>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET2_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&pwm8 { - #pwm-cells = <2>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm8>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - rs485-rx-during-tx; - rs485-rts-active-low; - uart-has-rtscts; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg1>; - dr_mode = "otg"; - srp-disable; - hnp-disable; - adp-disable; - over-current-active-low; - vbus-supply = <®_usb_otg1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - non-removable; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <®_3v3>; - voltage-ranges = <3300 3300>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>; - - pinctrl_adc1: adc1grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0 - >; - }; - - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1 - MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */ - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009 - >; - }; - - pinctrl_enet2_mdio: enet2mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp{ - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 - MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */ - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ - MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ - >; - }; - - pinctrl_gpio_leds: gpioledsgrp { - fsl,pins = < - MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */ - MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */ - MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */ - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0 - MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0 - >; - }; - - pinctrl_pwm8: pwm8grp { - fsl,pins = < - MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1 - /* - * mux unused RTS to make sure it doesn't cause - * any interrupts when it is undefined - */ - MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_uart4: uart4grp { - fsl,pins = < - MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 - MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_usbotg1: usbotg1 { - fsl,pins = < - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */ - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-bl.dts b/arch/arm/dts/imx6ul-kontron-bl.dts deleted file mode 100644 index dadf6d3d5f5..00000000000 --- a/arch/arm/dts/imx6ul-kontron-bl.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> - */ - -/dts-v1/; - -#include "imx6ul-kontron-sl.dtsi" -#include "imx6ul-kontron-bl-common.dtsi" - -/ { - model = "Kontron BL i.MX6UL (N631X S)"; - compatible = "kontron,bl-imx6ul", "kontron,sl-imx6ul", "fsl,imx6ul"; -}; diff --git a/arch/arm/dts/imx6ul-kontron-sl-common.dtsi b/arch/arm/dts/imx6ul-kontron-sl-common.dtsi deleted file mode 100644 index dcf88f61034..00000000000 --- a/arch/arm/dts/imx6ul-kontron-sl-common.dtsi +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> - */ - -#include <dt-bindings/gpio/gpio.h> - -/ { - chosen { - stdout-path = &uart4; - }; - - memory@80000000 { - reg = <0x80000000 0x10000000>; - device_type = "memory"; - }; -}; - -&ecspi2 { - cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; - - flash@0 { - compatible = "mxicy,mx25v8035f", "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - micrel,led-mode = <0>; - clocks = <&clks IMX6UL_CLK_ENET_REF>; - clock-names = "rmii-ref"; - }; - }; -}; - -&fec2 { - phy-mode = "rmii"; - status = "disabled"; -}; - -&qspi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - spi-max-frequency = <104000000>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - reg = <0>; - }; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_out>; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1 - MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1 - MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1 - MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1 - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009 - >; - }; - - pinctrl_enet1_mdio: enet1mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - >; - }; - - pinctrl_qspi: qspigrp { - fsl,pins = < - MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 - MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 - MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 - MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 - MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 - MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 - >; - }; - - pinctrl_reset_out: rstoutgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6ul-kontron-sl.dtsi b/arch/arm/dts/imx6ul-kontron-sl.dtsi deleted file mode 100644 index 0580d043e5a..00000000000 --- a/arch/arm/dts/imx6ul-kontron-sl.dtsi +++ /dev/null @@ -1,14 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org> - */ - -#include "imx6ul.dtsi" -#include "imx6ul-kontron-sl-common.dtsi" - -/ { - model = "Kontron SL i.MX6UL (N631X SOM)"; - compatible = "kontron,sl-imx6ul", "fsl,imx6ul"; -}; diff --git a/arch/arm/dts/imx6ull-kontron-bl.dts b/arch/arm/dts/imx6ull-kontron-bl.dts deleted file mode 100644 index fa016465cdb..00000000000 --- a/arch/arm/dts/imx6ull-kontron-bl.dts +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx6ull-kontron-sl.dtsi" -#include "imx6ul-kontron-bl-common.dtsi" - -/ { - model = "Kontron BL i.MX6ULL (N641X S)"; - compatible = "kontron,bl-imx6ull", "kontron,sl-imx6ull", "fsl,imx6ull"; -}; diff --git a/arch/arm/dts/imx6ull-kontron-sl.dtsi b/arch/arm/dts/imx6ull-kontron-sl.dtsi deleted file mode 100644 index 93f10eb3494..00000000000 --- a/arch/arm/dts/imx6ull-kontron-sl.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2017 exceet electronics GmbH - * Copyright (C) 2018 Kontron Electronics GmbH - */ - -#include "imx6ull.dtsi" -#include "imx6ul-kontron-sl-common.dtsi" - -/ { - model = "Kontron SL i.MX6ULL (N641X SOM)"; - compatible = "kontron,sl-imx6ull", "fsl,imx6ull"; -}; diff --git a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi index ae542fdcffa..acb26cd5af6 100644 --- a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi @@ -18,6 +18,10 @@ }; }; +&aips4 { + bootph-pre-ram; +}; + &i2c1 { bootph-pre-ram; bootph-all; @@ -108,6 +112,18 @@ bootph-all; }; +&usbmisc1 { + bootph-pre-ram; +}; + +&usbphynop1 { + bootph-pre-ram; +}; + +&usbotg1 { + bootph-pre-ram; +}; + &usdhc1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx8mm-kontron-bl-osm-s.dts b/arch/arm/dts/imx8mm-kontron-bl-osm-s.dts deleted file mode 100644 index 8b16bd68576..00000000000 --- a/arch/arm/dts/imx8mm-kontron-bl-osm-s.dts +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2022 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx8mm-kontron-osm-s.dtsi" - -/ { - model = "Kontron BL i.MX8MM OSM-S (N802X S)"; - compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm"; - - aliases { - ethernet1 = &usbnet; - }; - - /* fixed crystal dedicated to mcp2542fd */ - osc_can: clock-osc-can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - clock-output-names = "osc-can"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - led1 { - label = "led1"; - gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "led2"; - gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; - }; - - led3 { - label = "led3"; - gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - }; - }; - - pwm-beeper { - compatible = "pwm-beeper"; - pwms = <&pwm2 0 5000 0>; - }; - - reg_rst_eth2: regulator-rst-eth2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_eth2>; - gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-name = "rst-usb-eth2"; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_vbus>; - gpio = <&gpio3 25 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "usb1-vbus"; - }; - - reg_vdd_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-always-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-name = "vdd-5v"; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - can@0 { - compatible = "microchip,mcp251xfd"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can>; - clocks = <&osc_can>; - interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; - /* - * Limit the SPI clock to 15 MHz to prevent issues - * with corrupted data due to chip errata. - */ - spi-max-frequency = <15000000>; - vdd-supply = <®_vdd_3v3>; - xceiver-supply = <®_vdd_5v>; - }; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; - status = "okay"; - - eeram@0 { - compatible = "microchip,48l640"; - reg = <0>; - spi-max-frequency = <20000000>; - }; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-connection-type = "rgmii-rxid"; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - reg = <0>; - reset-assert-us = <1>; - reset-deassert-us = <15000>; - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&gpio1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>; - gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", - "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&gpio5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5>; - gpio-line-names = "", "", "dio4-in", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - disable-over-current; - vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - usb1@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - usbnet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - vmmc-supply = <®_vdd_3v3>; - vqmmc-supply = <®_nvcc_sd>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl_can: cangrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - >; - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 - >; - }; - - pinctrl_reg_usb1_vbus: regusb1vbusgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - >; - }; - - pinctrl_usb_eth2: usbeth2grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-kontron-bl.dts b/arch/arm/dts/imx8mm-kontron-bl.dts deleted file mode 100644 index dcec57c2039..00000000000 --- a/arch/arm/dts/imx8mm-kontron-bl.dts +++ /dev/null @@ -1,355 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -/dts-v1/; - -#include "imx8mm-kontron-sl.dtsi" - -/ { - model = "Kontron BL i.MX8MM (N801X S)"; - compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; - - aliases { - ethernet1 = &usbnet; - rtc0 = &rx8900; - rtc1 = &snvs_rtc; - }; - - /* fixed crystal dedicated to mcp2515 */ - osc_can: clock-osc-can { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "osc-can"; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_led>; - - led1 { - label = "led1"; - gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led2 { - label = "led2"; - gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; - }; - - led3 { - label = "led3"; - gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; - }; - - led4 { - label = "led4"; - gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; - }; - - led5 { - label = "led5"; - gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; - }; - - led6 { - label = "led6"; - gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; - }; - }; - - pwm-beeper { - compatible = "pwm-beeper"; - pwms = <&pwm2 0 5000 0>; - }; - - reg_rst_eth2: regulator-rst-eth2 { - compatible = "regulator-fixed"; - regulator-name = "rst-usb-eth2"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_eth2>; - gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_vdd_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "vdd-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; - -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; - status = "okay"; - - can0: can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can>; - clocks = <&osc_can>; - interrupt-parent = <&gpio4>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <10000000>; - vdd-supply = <®_vdd_3v3>; - xceiver-supply = <®_vdd_5v>; - }; -}; - -&ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-connection-type = "rgmii-rxid"; - phy-handle = <ðphy>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy: ethernet-phy@0 { - reg = <0>; - reset-assert-us = <1>; - reset-deassert-us = <15000>; - reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - rx8900: rtc@32 { - compatible = "epson,rx8900"; - reg = <0x32>; - }; -}; - -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - linux,rs485-enabled-at-boot-time; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - over-current-active-low; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - - usb1@1 { - compatible = "usb424,9514"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - usbnet: ethernet@1 { - compatible = "usb424,ec00"; - reg = <1>; - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - vmmc-supply = <®_vdd_3v3>; - vqmmc-supply = <®_nvcc_sd>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - pinctrl_can: cangrp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */ - MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - >; - }; - - pinctrl_usb_eth2: usbeth2grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-kontron-osm-s.dtsi b/arch/arm/dts/imx8mm-kontron-osm-s.dtsi deleted file mode 100644 index 695da2fa7c4..00000000000 --- a/arch/arm/dts/imx8mm-kontron-osm-s.dtsi +++ /dev/null @@ -1,335 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2022 Kontron Electronics GmbH - */ - -#include <dt-bindings/interrupt-controller/irq.h> -#include "imx8mm.dtsi" - -/ { - model = "Kontron OSM-S i.MX8MM (N802X SOM)"; - compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm"; - - aliases { - rtc0 = &rv3028; - rtc1 = &snvs_rtc; - }; - - memory@40000000 { - device_type = "memory"; - /* - * There are multiple SoM flavors with different DDR sizes. - * The smallest is 1GB. For larger sizes the bootloader will - * update the reg property. - */ - reg = <0x0 0x40000000 0 0x80000000>; - }; - - chosen { - stdout-path = &uart3; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; - spi-max-frequency = <80000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x1e0000>; - }; - - partition@1e0000 { - label = "env"; - reg = <0x1e0000 0x10000>; - }; - - partition@1f0000 { - label = "env_redundant"; - reg = <0x1f0000 0x10000>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pca9450: pmic@25 { - compatible = "nxp,pca9450a"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_vdd_soc: BUCK1 { - regulator-name = "+0V8_VDD_SOC (BUCK1)"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <850000>; - nxp,dvs-standby-voltage = <800000>; - }; - - reg_vdd_arm: BUCK2 { - regulator-name = "+0V9_VDD_ARM (BUCK2)"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - reg_vdd_dram: BUCK3 { - regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_3v3: BUCK4 { - regulator-name = "+3V3 (BUCK4)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_1v8: BUCK5 { - regulator-name = "+1V8 (BUCK5)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_nvcc_dram: BUCK6 { - regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_nvcc_snvs: LDO1 { - regulator-name = "+1V8_NVCC_SNVS (LDO1)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_snvs: LDO2 { - regulator-name = "+0V8_VDD_SNVS (LDO2)"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdda: LDO3 { - regulator-name = "+1V8_VDDA (LDO3)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_phy: LDO4 { - regulator-name = "+0V9_VDD_PHY (LDO4)"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_nvcc_sd: LDO5 { - regulator-name = "NVCC_SD (LDO5)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; - - rv3028: rtc@52 { - compatible = "microcrystal,rv3028"; - reg = <0x52>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; - trickle-diode-disable; - }; -}; - -&uart3 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <®_vdd_3v3>; - vqmmc-supply = <®_vdd_1v8>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 - MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 - MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 - MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 - MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 - MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 - MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 - MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 - MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 - MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 - MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 - MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 - MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 - MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 - MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 - MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-kontron-sl.dtsi b/arch/arm/dts/imx8mm-kontron-sl.dtsi deleted file mode 100644 index 0679728d248..00000000000 --- a/arch/arm/dts/imx8mm-kontron-sl.dtsi +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR MIT -/* - * Copyright (C) 2019 Kontron Electronics GmbH - */ - -#include "imx8mm.dtsi" - -/ { - model = "Kontron SL i.MX8MM (N801X SOM)"; - compatible = "kontron,imx8mm-sl", "fsl,imx8mm"; - - memory@40000000 { - device_type = "memory"; - /* - * There are multiple SoM flavors with different DDR sizes. - * The smallest is 1GB. For larger sizes the bootloader will - * update the reg property. - */ - reg = <0x0 0x40000000 0 0x80000000>; - }; - - chosen { - stdout-path = &uart3; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -&ddrc { - operating-points-v2 = <&ddrc_opp_table>; - - ddrc_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100M { - opp-hz = /bits/ 64 <100000000>; - }; - - opp-750M { - opp-hz = /bits/ 64 <750000000>; - }; - }; -}; - -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; - status = "okay"; - - flash@0 { - compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; - spi-max-frequency = <80000000>; - reg = <0>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x1e0000>; - }; - - partition@1e0000 { - label = "env"; - reg = <0x1e0000 0x10000>; - }; - - partition@1f0000 { - label = "env_redundant"; - reg = <0x1f0000 0x10000>; - }; - }; - }; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pca9450: pmic@25 { - compatible = "nxp,pca9450a"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_vdd_soc: BUCK1 { - regulator-name = "+0V8_VDD_SOC (BUCK1)"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <850000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <850000>; - nxp,dvs-standby-voltage = <800000>; - }; - - reg_vdd_arm: BUCK2 { - regulator-name = "+0V9_VDD_ARM (BUCK2)"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - reg_vdd_dram: BUCK3 { - regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_3v3: BUCK4 { - regulator-name = "+3V3 (BUCK4)"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_1v8: BUCK5 { - regulator-name = "+1V8 (BUCK5)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_nvcc_dram: BUCK6 { - regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_nvcc_snvs: LDO1 { - regulator-name = "+1V8_NVCC_SNVS (LDO1)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_snvs: LDO2 { - regulator-name = "+0V8_VDD_SNVS (LDO2)"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdda: LDO3 { - regulator-name = "+1V8_VDDA (LDO3)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_vdd_phy: LDO4 { - regulator-name = "+0V9_VDD_PHY (LDO4)"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_nvcc_sd: LDO5 { - regulator-name = "NVCC_SD (LDO5)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - }; - }; -}; - -&uart3 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - vmmc-supply = <®_vdd_3v3>; - vqmmc-supply = <®_vdd_1v8>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 - MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 - MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 - MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; - - pinctrl_pmic: pmicgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 - MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 - MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 - MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 - MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 - MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 - MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 - MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 - MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 - MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 - MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 - MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 - MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 - MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 - MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 - MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; -}; diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index 59453dc36d3..d891e8062fe 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -15,6 +15,10 @@ }; }; #endif + imx8mm-cm4 { + compatible = "fsl,imx8mm-cm4"; + syscon = <&src>; + }; }; #ifdef CONFIG_FSL_CAAM @@ -164,7 +168,6 @@ }; #endif -#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -176,9 +179,9 @@ tee-os { filename = "tee.bin"; + optional; }; }; -#endif binman_fip: fip { arch = "arm64"; @@ -208,11 +211,7 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI -#ifdef CONFIG_OPTEE loadables = "atf", "tee"; -#else - loadables = "atf"; -#endif #endif }; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 96a6df94c6c..29eecd6d70d 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -16,6 +16,10 @@ }; #endif + imx8mn-cm7 { + compatible = "fsl,imx8mn-cm7"; + }; + wdt-reboot { compatible = "wdt-reboot"; wdt = <&wdog1>; @@ -240,7 +244,6 @@ }; #endif -#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -252,9 +255,9 @@ tee-os { filename = "tee.bin"; + optional; }; }; -#endif binman_fip: fip { arch = "arm64"; @@ -284,11 +287,7 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI -#ifdef CONFIG_OPTEE loadables = "atf", "tee"; -#else - loadables = "atf"; -#endif #endif }; }; diff --git a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts index 8066f7fb649..6b40106e3bd 100644 --- a/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts +++ b/arch/arm/dts/imx8mp-data-modul-edm-sbc.dts @@ -344,7 +344,6 @@ pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; /* * i.MX 8M Plus Data Sheet for Consumer Products diff --git a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi index be2d4fb184a..b8b3abd0f03 100644 --- a/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-pdk2-u-boot.dtsi @@ -4,3 +4,23 @@ */ #include "imx8mp-dhcom-u-boot.dtsi" + +/ { + led { + led-0 { + function-enumerator = <0>; + }; + + led-1 { + function-enumerator = <1>; + }; + + led-2 { + function-enumerator = <2>; + }; + + led-3 { + function-enumerator = <3>; + }; + }; +}; diff --git a/arch/arm/dts/imx8mp-dhcom-som.dtsi b/arch/arm/dts/imx8mp-dhcom-som.dtsi index f2d99d05854..c1ca3805737 100644 --- a/arch/arm/dts/imx8mp-dhcom-som.dtsi +++ b/arch/arm/dts/imx8mp-dhcom-som.dtsi @@ -245,7 +245,6 @@ pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; /* * i.MX 8M Plus Data Sheet for Consumer Products diff --git a/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi new file mode 100644 index 00000000000..1320f1540ed --- /dev/null +++ b/arch/arm/dts/imx8mp-libra-rdk-fpsc-u-boot.dtsi @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + */ + +#include "imx8mp-u-boot.dtsi" + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + bootph-pre-ram; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc2", "mmc1", "ethernet"; + + efi { + compatible = "u-boot,distro-efi"; + }; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart4 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc3 { + bootph-pre-ram; +}; + +&pinctrl_wdog { + bootph-pre-ram; +}; + +&gpio1 { + bootph-pre-ram; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&uart4 { + bootph-pre-ram; +}; + +&i2c1 { + bootph-pre-ram; +}; + +&pmic { + bootph-pre-ram; +}; + +/* USB1 Type-C */ +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + fsl,power-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB */ +&usb3_phy1 { + vbus-supply = <®_vdd_5v0>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&usdhc3 { + bootph-pre-ram; +}; + +&wdog1 { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx8mp-toradex-smarc.dtsi b/arch/arm/dts/imx8mp-toradex-smarc.dtsi deleted file mode 100644 index 0a8b9eee5ed..00000000000 --- a/arch/arm/dts/imx8mp-toradex-smarc.dtsi +++ /dev/null @@ -1,1284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* Copyright (C) 2025 Toradex */ - -#include <dt-bindings/phy/phy-imx8-pcie.h> -#include <dt-bindings/net/ti-dp83867.h> -#include "imx8mp.dtsi" - -/ { - aliases { - can0 = &flexcan2; - can1 = &flexcan1; - ethernet0 = &eqos; - ethernet1 = &fec; - mmc0 = &usdhc3; - mmc1 = &usdhc2; - mmc2 = &usdhc1; - rtc0 = &rtc_i2c; - rtc1 = &snvs_rtc; - serial0 = &uart1; - serial1 = &uart4; - serial2 = &uart2; - serial3 = &uart3; - }; - - chosen { - stdout-path = &uart4; - }; - - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_id>; - id-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; - label = "USB0"; - self-powered; - type = "micro"; - vbus-supply = <®_usb0_vbus>; - - port { - usb_dr_connector: endpoint { - remote-endpoint = <&usb3_0_dwc>; - }; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sleep>; - - smarc_key_sleep: key-sleep { - gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; - label = "SMARC_SLEEP#"; - wakeup-source; - linux,code = <KEY_SLEEP>; - }; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_en_oc>; - gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "USB0_EN_OC#"; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1_en_oc>; - gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "USB2_EN_OC#"; - }; - - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; - gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <100000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "3V3_SD"; - startup-delay-us = <20000>; - }; - - reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_vsel>; - gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - states = <1800000 0x1>, - <3300000 0x0>; - regulator-name = "PMIC_USDHC_VSELECT"; - vin-supply = <®_sd_3v3_1v8>; - }; - - reg_wifi_en: regulator-wifi-en { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pwr_en>; - gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "CTRL_EN_WIFI"; - startup-delay-us = <2000>; - }; - - reserved-memory { - linux,cma { - size = <0 0x20000000>; - alloc-ranges = <0 0x40000000 0 0x80000000>; - }; - }; - - sound_hdmi: sound-hdmi { - compatible = "fsl,imx-audio-hdmi"; - model = "audio-hdmi"; - audio-cpu = <&aud2htx>; - hdmi-out; - status = "disabled"; - }; -}; - -&A53_0 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_1 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_2 { - cpu-supply = <®_vdd_arm>; -}; - -&A53_3 { - cpu-supply = <®_vdd_arm>; -}; - -/* SMARC SPI0 */ -&ecspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio4 28 GPIO_ACTIVE_LOW>; -}; - -/* SMARC SPI1 */ -&ecspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, - <&gpio4 3 GPIO_ACTIVE_LOW>, - <&gpio3 6 GPIO_ACTIVE_LOW>; - status = "okay"; - - tpm@2 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - reg = <2>; - spi-max-frequency = <18500000>; - }; -}; - -/* SMARC GBE0 */ -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>, - <&pinctrl_eth_mdio>, - <&pinctrl_eqos_1588_event>; - phy-handle = <&eqos_phy>; - phy-mode = "rgmii-id"; - snps,force_thresh_dma_mode; - snps,mtl-rx-config = <&mtl_rx_setup>; - snps,mtl-tx-config = <&mtl_tx_setup>; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <5>; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - snps,map-to-dma-channel = <0>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - snps,map-to-dma-channel = <1>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - snps,map-to-dma-channel = <2>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - snps,map-to-dma-channel = <3>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - snps,map-to-dma-channel = <4>; - }; - }; - - mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <5>; - - queue0 { - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue1 { - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue2 { - snps,dcb-algorithm; - snps,priority = <0x4>; - }; - - queue3 { - snps,dcb-algorithm; - snps,priority = <0x8>; - }; - - queue4 { - snps,dcb-algorithm; - snps,priority = <0xf0>; - }; - }; -}; - -/* SMARC GBE1 */ -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_1588_event>; - phy-handle = <&fec_phy>; - phy-mode = "rgmii-id"; - fsl,magic-packet; -}; - -/* SMARC CAN1 */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; -}; - -/* SMARC CAN0 */ -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -&gpio1 { - gpio-line-names = "SMARC_GPIO7", /* 0 */ - "SMARC_GPIO8", - "", - "PMIC_INT#", - "PMIC_USDHC_VSELECT", - "SMARC_GPIO9", - "SMARC_GPIO10", - "SMARC_GPIO11", - "SMARC_GPIO12", - "", - "SMARC_GPIO5", /* 10 */ - "", - "SMARC_USB0_EN_OC#", - "SMARC_GPIO13", - "SMARC_USB2_EN_OC#"; -}; - -&gpio2 { - gpio-line-names = "", /* 0 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "SMARC_SDIO_CD#", - "", - "", - "", - "", - "", - "", - "SMARC_SDIO_PWR_EN", - "SMARC_SDIO_WP"; /* 20 */ -}; - -&gpio3 { - gpio-line-names = "ETH_0_INT#", /* 0 */ - "SLEEP#", - "", - "", - "", - "", - "TPM_CS#", - "LVDS_DSI_SEL", - "MCU_INT#", - "GPIO_EX_INT#", - "", /* 10 */ - "", - "", - "", - "", - "", - "SMARC_SMB_ALERT#", - "", - "", - "", - "SMARC_I2C_PM_DAT", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "SMARC_I2C_PM_CK"; - - lvds_dsi_mux_hog: lvds-dsi-mux-hog { - gpio-hog; - gpios = <7 GPIO_ACTIVE_HIGH>; - line-name = "LVDS_DSI_SEL"; - /* LVDS_DSI_SEL as DSI */ - output-low; - }; -}; - -&gpio4 { - gpio-line-names = "SMARC_PCIE_WAKE#", /* 0 */ - "", - "", - "SMARC_SPI1_CS1#", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "", - "", - "", - "SMARC_GPIO4", - "SMARC_PCIE_A_RST#", - "", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "SMARC_SPI0_CS1#", - "SMARC_GPIO6"; -}; - -&gpio5 { - gpio-line-names = "", /* 0 */ - "", - "SMARC_USB0_OTG_ID", - "SMARC_I2C_CAM1_CK", - "SMARC_I2C_CAM1_DAT", - "", - "", - "", - "", - "SMARC_SPI0_CS0#", - "", /* 10 */ - "", - "", - "SMARC_SPI1_CS0#", - "CTRL_I2C_SCL", - "CTRL_I2C_SDA", - "SMARC_I2C_LCD_CK", - "SMARC_I2C_LCD_DAT", - "SMARC_I2C_CAM0_CK", - "SMARC_I2C_CAM0_DAT", - "SMARC_I2C_GP_CK", /* 20 */ - "SMARC_I2C_GP_DAT"; -}; - -/* SMARC HDMI */ -&hdmi_tx { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi>; -}; - -/* On-module I2C */ -&i2c1 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; - clock-frequency = <400000>; - scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - single-master; - status = "okay"; - - som_gpio_expander: gpio-expander@21 { - compatible = "nxp,pcal6408"; - reg = <0x21>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6408>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&gpio3>; - interrupts = <9 IRQ_TYPE_LEVEL_LOW>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = - "SMARC_GPIO0", - "SMARC_GPIO1", - "SMARC_GPIO2", - "SMARC_GPIO3", - "SMARC_LCD0_VDD_EN", - "SMARC_LCD0_BKLT_EN", - "SMARC_LCD1_VDD_EN", - "SMARC_LCD1_BKLT_EN"; - }; - - pca9450: pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - BUCK1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <805000>; - regulator-name = "+VDD_SOC (PMIC BUCK1)"; - regulator-ramp-delay = <3125>; - }; - - reg_vdd_arm: BUCK2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1000000>; - regulator-min-microvolt = <805000>; - regulator-name = "+VDD_ARM (PMIC BUCK2)"; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - reg_3v3: BUCK4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3 (PMIC BUCK4)"; - }; - - reg_1v8: BUCK5 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8 (PMIC BUCK5)"; - }; - - BUCK6 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1155000>; - regulator-min-microvolt = <1045000>; - regulator-name = "+VDD_DDR (PMIC BUCK6)"; - }; - - LDO1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1950000>; - regulator-min-microvolt = <1710000>; - regulator-name = "+V1.8_SNVS (PMIC LDO1)"; - }; - - LDO3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8A (PMIC LDO3)"; - }; - - LDO4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_ADC (PMIC LDO4)"; - }; - - reg_sd_3v3_1v8: LDO5 { - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V3.3_1.8_SD (PMIC LDO5)"; - }; - }; - }; - - rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - temperature-sensor@48 { - compatible = "ti,tmp1075"; - reg = <0x48>; - }; - - eeprom@50 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -/* SMARC I2C_LCD */ -&i2c2 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; - clock-frequency = <100000>; - scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - single-master; -}; - -/* SMARC I2C_CAM0 */ -&i2c3 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; - clock-frequency = <400000>; - scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - single-master; -}; - -/* SMARC I2C_GP */ -&i2c4 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; - clock-frequency = <400000>; - scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - single-master; - status = "okay"; - - eeprom@50 { - compatible = "st,24c32", "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - }; -}; - -/* SMARC I2C_CAM1 */ -&i2c5 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c5>; - pinctrl-1 = <&pinctrl_i2c5_gpio>; - clock-frequency = <400000>; - scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - single-master; -}; - -/* SMARC I2C_PM */ -&i2c6 { - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c6>; - pinctrl-1 = <&pinctrl_i2c6_gpio>; - clock-frequency = <400000>; - scl-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - single-master; -}; - -&mdio { - eqos_phy: ethernet-phy@1 { - reg = <1>; - interrupt-parent = <&gpio3>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - }; - - fec_phy: ethernet-phy@2 { - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - }; -}; - -/* SMARC PCIE_A */ -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; -}; - -&pcie_phy { - clocks = <&hsio_blk_ctrl>; - clock-names = "ref"; - fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; -}; - -/* SMARC LCD1_BKLT_PWM */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_bklt_pwm1>; -}; - -/* SMARC LCD0_BKLT_PWM */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_bklt_pwm2>; -}; - -/* SMARC GPIO5 as PWM */ -&pwm3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5_pwm>; -}; - -&snvs_pwrkey { - status = "okay"; -}; - -/* SMARC SER0 */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; -}; - -/* SMARC SER2 */ -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; -}; - -/* On-module Bluetooth, optional SMARC SER3 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_uart>; - uart-has-rtscts; - status = "okay"; - - som_bt: bluetooth { - compatible = "mrvl,88w8997"; - max-speed = <921600>; - }; -}; - -/* SMARC SER1, used as the Linux Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; -}; - -/* SMARC USB0 */ -&usb3_0 { - fsl,disable-port-power-control; -}; - -/* SMARC USB1..4 */ -&usb3_1 { - fsl,disable-port-power-control; -}; - -&usb3_phy1 { - vbus-supply = <®_usb1_vbus>; -}; - -&usb_dwc3_0 { - adp-disable; - dr_mode = "otg"; - hnp-disable; - maximum-speed = "high-speed"; - srp-disable; - usb-role-switch; - - port { - usb3_0_dwc: endpoint { - remote-endpoint = <&usb_dr_connector>; - }; - }; -}; - -&usb_dwc3_1 { - dr_mode = "host"; -}; - -/* On-module Wi-Fi */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - keep-power-in-suspend; - non-removable; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; - -/* SMARC SDIO */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, - <&pinctrl_usdhc2_cd>, - <&pinctrl_usdhc2_wp>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, - <&pinctrl_usdhc2_cd>, - <&pinctrl_usdhc2_wp>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, - <&pinctrl_usdhc2_cd>, - <&pinctrl_usdhc2_wp>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, - <&pinctrl_usdhc2_cd_sleep>, - <&pinctrl_usdhc2_wp>; - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; - cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; -}; - -/* On-module eMMC */ -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; - -&iomuxc { - /* On-module Bluetooth */ - pinctrl_bt_uart: btuartgrp { - fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x1c4>, /* WiFi_UART_TXD */ - <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x1c4>, /* WiFi_UART_RXD */ - <MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x1c4>, /* WiFi_UART_RTS */ - <MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x1c4>; /* WiFi_UART_CTS */ - }; - - /* SMARC CAM_MCK */ - pinctrl_csi_mclk: csimclkgrp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x16>; /* SMARC S6 - CAM_MCK */ - }; - - /* SMARC SPI0 */ - pinctrl_ecspi1: ecspi1grp { - fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SMARC P45 - SPI0_DIN */ - <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SMARC P46 - SPI0_DO */ - <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SMARC P44 - SPI0_CK */ - <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>, /* SMARC P43 - SPI0_CS0# */ - <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SMARC P31 - SPI0_CS1# */ - }; - - /* SMARC SPI1 */ - pinctrl_ecspi2: ecspi2grp { - fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1c4>, /* SMARC P56 - SPI1_DIN */ - <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x4>, /* SMARC P57 - SPI1_DO */ - <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x4>, /* SMARC P58 - SPI1_CK */ - <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>, /* SMARC P54 - SPI1_CS0# */ - <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c4>; /* SMARC P55 - SPI1_CS1# */ - }; - - /* ETH_0 RGMII (On-module PHY) */ - pinctrl_eqos: eqosgrp { - fsl,pins = <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, /* ETH0_RGMII_RXD0 */ - <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, /* ETH0_RGMII_RXD1 */ - <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, /* ETH0_RGMII_RXD2 */ - <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, /* ETH0_RGMII_RXD3 */ - <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, /* ETH0_RGMII_RXC */ - <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, /* ETH0_RGMII_RX_CTL */ - <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16>, /* ETH0_RGMII_TXD0 */ - <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16>, /* ETH0_RGMII_TXD1 */ - <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16>, /* ETH0_RGMII_TXD2 */ - <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16>, /* ETH0_RGMII_TXD3 */ - <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16>, /* ETH0_RGMII_TX_CTL */ - <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16>; /* ETH0_RGMII_TXC */ - }; - - /* SMARC GBE0_SDP */ - pinctrl_eqos_1588_event: eqos1588eventgrp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x4>; /* SMARC P6 - GBE0_SDP */ - }; - - /* ETH_0_MDIO and ETH_0_INT# shared between ETH_PHY0 and ETH_PHY1 */ - pinctrl_eth_mdio: ethmdiogrp { - fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2>, /* ETH_0_MDC */ - <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2>, /* ETH_0_MDIO */ - <MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x80>; /* ETH_0_INT# */ - }; - - /* ETH_1 RGMII (On-module PHY) */ - pinctrl_fec: fecgrp { - fsl,pins = <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, /* ETH1_RGMII_RXD0 */ - <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, /* ETH1_RGMII_RXD1 */ - <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, /* ETH1_RGMII_RXD2 */ - <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, /* ETH1_RGMII_RXD3 */ - <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, /* ETH1_RGMII_RXC */ - <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, /* ETH1_RGMII_RX_CTL */ - <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16>, /* ETH1_RGMII_TXD0 */ - <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16>, /* ETH1_RGMII_TXD1 */ - <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16>, /* ETH1_RGMII_TXD2 */ - <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16>, /* ETH1_RGMII_TXD3 */ - <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16>, /* ETH1_RGMII_TX_CTL */ - <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16>; /* ETH1_RGMII_TXC */ - }; - - /* SMARC GBE1_SDP */ - pinctrl_fec_1588_event: fec1588eventgrp { - fsl,pins = <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x4>; /* SMARC P5 - GBE1_SDP */ - }; - - /* SMARC CAN1 */ - pinctrl_flexcan1: flexcan1grp { - fsl,pins = <MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154>, /* SMARC P146 - CAN1_RX */ - <MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154>; /* SMARC P145 - CAN1_TX */ - }; - - /* SMARC CAN0 */ - pinctrl_flexcan2: flexcan2grp { - fsl,pins = <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SMARC P144 - CAN0_RX */ - <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SMARC P143 - CAN0_TX */ - }; - - /* SMARC GPIO4 */ - pinctrl_gpio4: gpio4grp { - fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x144>; /* SMARC P112 - GPIO4 */ - }; - - /* SMARC GPIO5 */ - pinctrl_gpio5: gpio5grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x144>; /* SMARC P113 - GPIO5 */ - }; - - /* SMARC GPIO5 as PWM */ - pinctrl_gpio5_pwm: gpio5pwmgrp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x12>; /* SMARC P113 - PWM_OUT */ - }; - - /* SMARC GPIO6 */ - pinctrl_gpio6: gpio6grp { - fsl,pins = <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x144>; /* SMARC P114 - GPIO6 */ - }; - - /* SMARC GPIO7 */ - pinctrl_gpio7: gpio7grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x144>; /* SMARC P115 - GPIO7 */ - }; - - /* SMARC GPIO8 */ - pinctrl_gpio8: gpio8grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x144>; /* SMARC P116 - GPIO8 */ - }; - - /* SMARC GPIO9 */ - pinctrl_gpio9: gpio9grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x144>; /* SMARC P117 - GPIO9 */ - }; - - /* SMARC GPIO10 */ - pinctrl_gpio10: gpio10grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x144>; /* SMARC P118 - GPIO10 */ - }; - - /* SMARC GPIO11 */ - pinctrl_gpio11: gpio11grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x144>; /* SMARC P119 - GPIO11 */ - }; - - /* SMARC GPIO12 */ - pinctrl_gpio12: gpio12grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x144>; /* SMARC S142 - GPIO12 */ - }; - - /* SMARC GPIO13 */ - pinctrl_gpio13: gpio13grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144>; /* SMARC S123 - GPIO13 */ - }; - - /* SMARC HDMI */ - pinctrl_hdmi: hdmigrp { - fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c6>, /* SMARC P105 - HDMI_CTRL_CK */ - <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c6>, /* SMARC P106 - HDMI_CTRL_DAT */ - <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SMARC P104 - HDMI_HPD */ - }; - - /* On-module I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* CTRL_I2C_SCL */ - <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* CTRL_I2C_SDA */ - }; - - /* On-module I2C as GPIOs */ - pinctrl_i2c1_gpio: i2c1gpiogrp { - fsl,pins = <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* CTRL_I2C_SCL */ - <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* CTRL_I2C_SDA */ - }; - - /* SMARC I2C_LCD */ - pinctrl_i2c2: i2c2grp { - fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */ - <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */ - }; - - /* SMARC I2C_LCD as GPIOs */ - pinctrl_i2c2_gpio: i2c2gpiogrp { - fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SMARC S139 - I2C_LCD_CK */ - <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SMARC S140 - I2C_LCD_DAT */ - }; - - /* SMARC I2C_CAM0 */ - pinctrl_i2c3: i2c3grp { - fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */ - <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */ - }; - - /* SMARC I2C_CAM0 as GPIOs */ - pinctrl_i2c3_gpio: i2c3gpiogrp { - fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SMARC S5 - I2C_CAM0_CK */ - <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SMARC S7 - I2C_CAM0_DAT */ - }; - - /* SMARC I2C_GP */ - pinctrl_i2c4: i2c4grp { - fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SMARC S48 - I2C_GP_CK */ - <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */ - }; - - /* SMARC I2C_GP as GPIOs */ - pinctrl_i2c4_gpio: i2c4gpiogrp { - fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SMARC S48 - I2C_GP_CK */ - <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SMARC S49 - I2C_GP_DAT */ - }; - - /* SMARC I2C_CAM1 */ - pinctrl_i2c5: i2c5grp { - fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */ - <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */ - }; - - /* SMARC I2C_CAM1 as GPIOs */ - pinctrl_i2c5_gpio: i2c5gpiogrp { - fsl,pins = <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001c6>, /* SMARC S2 - I2C_CAM1_DAT */ - <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001c6>; /* SMARC S1 - I2C_CAM1_CK */ - }; - - /* SMARC I2C_PM */ - pinctrl_i2c6: i2c6grp { - fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x400001c6>, /* SMARC P121 - I2C_PM_CK */ - <MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */ - }; - - /* SMARC I2C_PM as GPIOs */ - pinctrl_i2c6_gpio: i2c6gpiogrp { - fsl,pins = <MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x400001c6>, /* SMARC P121 - I2C_PM_CK */ - <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x400001c6>; /* SMARC P122 - I2C_PM_DAT */ - }; - - pinctrl_lvds_dsi_sel: lvdsdsiselgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x104>; /* LVDS_DSI_SEL */ - }; - - pinctrl_mcu_int: mcuintgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */ - }; - - /* SMARC LCD1_BKLT_PWM */ - pinctrl_lcd1_bklt_pwm1: pwm1grp { - fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x12>; /* SMARC S122 - LCD1_BKLT_PWM */ - }; - - /* SMARC LCD0_BKLT_PWM */ - pinctrl_lcd0_bklt_pwm2: pwm2grp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x12>; /* SMARC S141 - LCD0_BKLT_PWM */ - }; - - /* PCAL6408 Interrupt */ - pinctrl_pcal6408: pcal6408intgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x1c4>; /* GPIO_EX_INT# */ - }; - - /* SMARC PCIE_A */ - pinctrl_pcie: pciegrp { - fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c0>, /* SMARC S146 - PCIE_WAKE# */ - <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x04>; /* SMARC P75 - PCIE_A_RST# */ - }; - - /* PMIC Interrupt */ - pinctrl_pmic: pmicintgrp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ - }; - - /* SMARC I2S0 */ - pinctrl_sai1: sai1grp { - fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x94>, /* SMARC S42 - I2S0_CK */ - <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x94>, /* SMARC S39 - I2S0_LRCLK */ - <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x94>, /* SMARC S41 - I2S0_SDIN */ - <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x94>; /* SMARC S40 - I2S0_SDOUT */ - }; - - /* SMARC AUDIO_MCK */ - pinctrl_sai1_mclk: sai1mclkgrp { - fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>; /* SMARC S38 - AUDIO_MCK */ - }; - - /* SMARC I2S2 */ - pinctrl_sai3: sai3grp { - fsl,pins = <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x94>, /* SMARC S52 - I2S2_SDIN */ - <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x94>, /* SMARC S53 - I2S2_CK */ - <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x94>, /* SMARC S51 - I2S2_SDOUT */ - <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x94>; /* SMARC S50 - I2S2_LRCLK */ - }; - - /* SMARC SLEEP# */ - pinctrl_sleep: sleepgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */ - }; - - /* SMARC SMB_ALERT# */ - pinctrl_smb_alert: smbalertgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */ - }; - - /* TPM_CS# */ - pinctrl_tpm_cs: tpmcsgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x82>; /* TPM_CS# */ - }; - - /* WIFI_BT_WKUP_HOST/TPM_INT# */ - pinctrl_tpm_irq_wifi_bt_wkup: tpmirq-wifibtwkupgrp { - fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x16>; /* WIFI_BT_WKUP_HOST/TPM_INT# */ - }; - - /* SMARC SER0 */ - pinctrl_uart1: uart1grp { - fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SMARC P132 - SER2_CTS */ - <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SMARC P131 - SER2_RTS */ - <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SMARC P130 - SER2_RX */ - <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SMARC P139 - SER2_TX */ - }; - - /* SMARC SER2 */ - pinctrl_uart2: uart2grp { - fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SMARC P139 - SER2_CTS */ - <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SMARC P138 - SER2_RTS */ - <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SMARC P137 - SER2_RX */ - <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SMARC P136 - SER2_TX */ - }; - - /* SMARC SER3 */ - pinctrl_uart3: uart3grp { - fsl,pins = <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SMARC P141 - SER3_RX */ - <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SMARC P140 - SER3_TX */ - }; - - /* SMARC SER1 */ - pinctrl_uart4: uart4grp { - fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SMARC P135 - SER1_RX */ - <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SMARC P134 - SER1_TX */ - }; - - /* SMARC USB0_OTG_ID */ - pinctrl_usb0_id: usb0idgrp { - fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SMARC P64 - USB0_OTG_ID */ - }; - - /* SMARC USB0_EN_OC# */ - pinctrl_usb0_en_oc: usb0enocgrp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x04>; /* SMARC P62 - USB0_EN_OC# */ - }; - - /* On module USB Hub VBUS, or SMARC USB2_EN_OC# depending on assembling */ - pinctrl_usb1_en_oc: usb1enocgrp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04>; /* SMARC P71 - USB2_EN_OC# */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, /* WiFi_SDIO_CLK */ - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, /* WiFi_SDIO_CMD */ - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, /* WiFi_SDIO_DATA0 */ - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, /* WiFi_SDIO_DATA1 */ - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, /* WiFi_SDIO_DATA2 */ - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; /* WiFi_SDIO_DATA3 */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, /* WiFi_SDIO_CLK */ - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, /* WiFi_SDIO_CMD */ - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, /* WiFi_SDIO_DATA0 */ - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, /* WiFi_SDIO_DATA1 */ - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, /* WiFi_SDIO_DATA2 */ - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; /* WiFi_SDIO_DATA3 */ - }; - - /* On-module Wi-Fi */ - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, /* WiFi_SDIO_CLK */ - <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, /* WiFi_SDIO_CMD */ - <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, /* WiFi_SDIO_DATA0 */ - <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, /* WiFi_SDIO_DATA1 */ - <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, /* WiFi_SDIO_DATA2 */ - <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; /* WiFi_SDIO_DATA3 */ - }; - - /* SMARC SDIO */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SMARC P36 - SDIO_CK */ - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SMARC P34 - SDIO_CMD */ - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SMARC P39 - SDIO_DO */ - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SMARC P40 - SDIO_D1 */ - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SMARC P41 - SDIO_D2 */ - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO 100MHz */ - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, /* SMARC P36 - SDIO_CK */ - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, /* SMARC P34 - SDIO_CMD */ - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, /* SMARC P39 - SDIO_DO */ - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, /* SMARC P40 - SDIO_D1 */ - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, /* SMARC P41 - SDIO_D2 */ - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO 200MHz */ - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, /* SMARC P36 - SDIO_CK */ - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, /* SMARC P34 - SDIO_CMD */ - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, /* SMARC P39 - SDIO_DO */ - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, /* SMARC P40 - SDIO_D1 */ - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, /* SMARC P41 - SDIO_D2 */ - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; /* SMARC P42 - SDIO_D3 */ - }; - - /* SMARC SDIO_CD# */ - pinctrl_usdhc2_cd: usdhc2cdgrp { - fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SMARC P35 - SDIO_CD# */ - }; - - /* SMARC SDIO_CD# */ - pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { - fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SMARC P35 - SDIO_CD# */ - }; - - /* SMARC SDIO_PWR_EN */ - pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { - fsl,pins = <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* SMARC P37 - SDIO_PWR_EN */ - }; - - /* SMARC SDIO Sleep - Avoid backfeeding with removed card power */ - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, /* SMARC P36 - SDIO_CK */ - <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, /* SMARC P34 - SDIO_CMD */ - <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, /* SMARC P39 - SDIO_DO */ - <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, /* SMARC P39 - SDIO_D1 */ - <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, /* SMARC P39 - SDIO_D2 */ - <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; /* SMARC P39 - SDIO_D3 */ - }; - - pinctrl_usdhc2_vsel: usdhc2vselgrp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x4>; /* PMIC_USDHC_VSELECT */ - }; - - /* SMARC SDIO_WP */ - pinctrl_usdhc2_wp: usdhc2wpgrp { - fsl,pins = <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x144>; /* SMARC P33 - SDIO_WP */ - }; - - /* On-module eMMC */ - pinctrl_usdhc3: usdhc3grp { - fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, /* eMMC_STROBE */ - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, /* eMMC_DATA5 */ - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, /* eMMC_DATA6 */ - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, /* eMMC_DATA7 */ - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, /* eMMC_DATA0 */ - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, /* eMMC_DATA1 */ - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, /* eMMC_DATA2 */ - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, /* eMMC_DATA3 */ - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, /* eMMC_DATA4 */ - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, /* eMMC_CLK */ - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; /* eMMC_CMD */ - }; - - /* On-module eMMC */ - pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, /* eMMC_STROBE */ - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, /* eMMC_DATA5 */ - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, /* eMMC_DATA6 */ - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, /* eMMC_DATA7 */ - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, /* eMMC_DATA0 */ - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, /* eMMC_DATA1 */ - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, /* eMMC_DATA2 */ - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, /* eMMC_DATA3 */ - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, /* eMMC_DATA4 */ - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, /* eMMC_CLK */ - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; /* eMMC_CMD */ - }; - - /* On-module eMMC */ - pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, /* eMMC_STROBE */ - <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, /* eMMC_DATA5 */ - <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, /* eMMC_DATA6 */ - <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, /* eMMC_DATA7 */ - <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, /* eMMC_DATA0 */ - <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, /* eMMC_DATA1 */ - <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, /* eMMC_DATA2 */ - <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, /* eMMC_DATA3 */ - <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, /* eMMC_DATA4 */ - <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, /* eMMC_CLK */ - <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; /* eMMC_CMD */ - }; - - /* SoC Watchdog */ - pinctrl_wdog: wdoggrp { - fsl,pins = <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x4>; /* CTRL_SOC_WDOG */ - }; - - /* On-module Wi-Fi power enable */ - pinctrl_wifi_pwr_en: wifipwrengrp { - fsl,pins = <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x104>; /* CTRL_EN_WIFI */ - }; -}; diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi index 6de9ab5d37c..d9d220c70db 100644 --- a/arch/arm/dts/imx8mp-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-u-boot.dtsi @@ -16,6 +16,10 @@ }; }; #endif + + imx8mp-cm7 { + compatible = "fsl,imx8mp-cm7"; + }; }; #ifdef CONFIG_FSL_CAAM @@ -185,7 +189,6 @@ }; #endif -#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -197,9 +200,9 @@ tee-os { filename = "tee.bin"; + optional; }; }; -#endif @fdt-SEQ { description = "NAME"; @@ -220,11 +223,7 @@ fdt = "fdt-SEQ"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI -#ifdef CONFIG_OPTEE loadables = "atf", "tee"; -#else - loadables = "atf"; -#endif #endif }; }; diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index 8a536b16e8f..0687fcdbd68 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -7,6 +7,10 @@ binman: binman { }; + imx8mq-cm4 { + compatible = "fsl,imx8mq-cm4"; + syscon = <&src>; + }; }; &soc { @@ -144,7 +148,6 @@ }; #endif -#ifdef CONFIG_OPTEE tee: tee { description = "OP-TEE"; type = "tee"; @@ -156,9 +159,9 @@ tee-os { filename = "tee.bin"; + optional; }; }; -#endif fdt { compression = "none"; @@ -180,11 +183,7 @@ fdt = "fdt"; firmware = "uboot"; #ifndef CONFIG_ARMV8_PSCI -#ifdef CONFIG_OPTEE loadables = "atf", "tee"; -#else - loadables = "atf"; -#endif #endif }; }; diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 0c3ca2961c9..0c8d0ba9693 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -69,6 +69,16 @@ bootph-some-ram; }; +&pinctrl_lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; + bootph-some-ram; +}; + &pinctrl_reg_usdhc2_vmmc { bootph-pre-ram; }; @@ -83,6 +93,16 @@ bootph-some-ram; }; +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + &pinctrl_usdhc2_cd { bootph-pre-ram; bootph-some-ram; @@ -128,31 +148,9 @@ bootph-some-ram; }; -/* - * Remove once USB support is added to imx93-phyboard-segin.dts upstream. - */ -&usbotg1 { - disable-over-current; - dr_mode = "otg"; - status = "okay"; -}; - -&usbotg2 { - disable-over-current; - dr_mode = "host"; - status = "okay"; -}; - &usdhc1 { bootph-pre-ram; bootph-some-ram; - /* - * Remove pinctrl assignments once they are added to imx93-phycore-som.dtsi - */ - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; }; &usdhc2 { @@ -174,6 +172,21 @@ &lpi2c3 { bootph-pre-ram; bootph-some-ram; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + }; + }; + + eeprom@50 { + bootph-pre-ram; + bootph-some-ram; + }; }; &s4muap { @@ -209,165 +222,3 @@ bootph-all; bootph-pre-ram; }; - -/* - * The two nodes below won't be needed once nxp,pca9451a - * support is added to the Linux kernel. - */ -&iomuxc { - pinctrl_lpi2c3: lpi2c3grp { - bootph-pre-ram; - fsl,pins = < - MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e - MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e - >; - }; - - pinctrl_pmic: pmicgrp { - bootph-pre-ram; - fsl,pins = < - MX93_PAD_ENET2_RD3__GPIO4_IO27 0x31e - >; - }; - - /* - * Remove pinctrl_usdhc1_100mhz and pinctrl_usdhc1_200mhz once they - * are added to imx93-phycore-som.dtsi - */ - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - bootph-pre-ram; - bootph-some-ram; - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000139e - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000139e - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000139e - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000139e - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000139e - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000139e - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; - - /* need to config the SION for data and cmd pad, refer to ERR052021 */ - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - bootph-pre-ram; - bootph-some-ram; - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be - MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000139e - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000139e - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013be - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013be - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013be - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013be - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013be - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013be - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013be - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x179e - >; - }; -}; - -&lpi2c3 { - bootph-pre-ram; - bootph-some-ram; - clock-frequency = <400000>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_lpi2c3>; - pinctrl-1 = <&pinctrl_lpi2c3>; - status = "okay"; - - pmic@25 { - bootph-pre-ram; - bootph-some-ram; - compatible = "nxp,pca9451a"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio4>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - regulators { - bootph-pre-ram; - bootph-some-ram; - buck1: BUCK1 { - regulator-name = "VDD_SOC"; - regulator-min-microvolt = <610000>; - regulator-max-microvolt = <950000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "VDDQ_0V6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <600000>; - regulator-boot-on; - regulator-always-on; - }; - - buck4: BUCK4 { - regulator-name = "VDD_3V3_BUCK"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "VDD_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "VDD_1V1"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "PMIC_SNVS_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "VDD_0V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "NVCC_SD2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - eeprom@50 { - bootph-pre-ram; - bootph-some-ram; - compatible = "atmel,24c32"; - reg = <0x50>; - pagesize = <32>; - vcc-supply = <&buck4>; - }; -}; diff --git a/arch/arm/dts/imx943-evk-u-boot.dtsi b/arch/arm/dts/imx943-evk-u-boot.dtsi new file mode 100644 index 00000000000..528b3b02a3f --- /dev/null +++ b/arch/arm/dts/imx943-evk-u-boot.dtsi @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "imx943-u-boot.dtsi" + +&enetc1 { + clocks = <&scmi_clk IMX94_CLK_MAC4>; + clock-names = "enet_ref_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth3>; + phy-handle = <ðphy5>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enetc2 { + clocks = <&scmi_clk IMX94_CLK_MAC5>; + clock-names = "enet_ref_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth4>; + phy-handle = <ðphy6>; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9548_i2c3: i2c-mux@77 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x77>; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + + pcal6416_i2c3_u171: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + ethphy2-on-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + }; + + ethphy3-on-hog { + gpio-hog; + gpios = <3 GPIO_ACTIVE_HIGH>; + output-high; + }; + + ethphy4-on-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; + + lvds-en-hog { + gpio-hog; + gpios = <9 GPIO_ACTIVE_HIGH>; + output-high; + }; + }; + }; + }; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +&netc_blk_ctrl { + assigned-clocks = <&scmi_clk IMX94_CLK_MAC2>, + <&scmi_clk IMX94_CLK_MAC4>, + <&scmi_clk IMX94_CLK_MAC5>; + assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>, + <&scmi_clk IMX94_CLK_SYSPLL1_PFD0>; + assigned-clock-rates = <250000000>, <250000000>, <250000000>; + status = "okay"; +}; + +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + phy-supply = <®_gpy_en>; + status = "okay"; + + ethphy5: ethernet-phy@6 { + reg = <0x6>; + realtek,clkout-disable; + }; + + ethphy6: ethernet-phy@7 { + reg = <0x7>; + realtek,clkout-disable; + }; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&usb2 { + dr_mode = "host"; + hnp-disable; + srp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usb3 { + bootph-pre-ram; + status = "okay"; +}; + +&usb3_dwc3 { + bootph-pre-ram; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; +}; + +&usb3_phy { + bootph-pre-ram; + orientation-switch; + status = "okay"; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&wdog3 { + status = "disabled"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX94_PAD_ETH4_MDC_GPIO1__NETC_EMDC 0x57e + IMX94_PAD_ETH4_MDIO_GPIO2__NETC_EMDIO 0x97e + >; + }; + + pinctrl_eth3: eth3grp { + fsl,pins = < + IMX94_PAD_ETH3_TXD3__NETC_PINMUX_ETH3_TXD3 0x57e + IMX94_PAD_ETH3_TXD2__NETC_PINMUX_ETH3_TXD2 0x57e + IMX94_PAD_ETH3_TXD1__NETC_PINMUX_ETH3_TXD1 0x57e + IMX94_PAD_ETH3_TXD0__NETC_PINMUX_ETH3_TXD0 0x57e + IMX94_PAD_ETH3_TX_CTL__NETC_PINMUX_ETH3_TX_CTL 0x57e + IMX94_PAD_ETH3_TX_CLK__NETC_PINMUX_ETH3_TX_CLK 0x5fe + IMX94_PAD_ETH3_RX_CTL__NETC_PINMUX_ETH3_RX_CTL 0x57e + IMX94_PAD_ETH3_RX_CLK__NETC_PINMUX_ETH3_RX_CLK 0x5fe + IMX94_PAD_ETH3_RXD0__NETC_PINMUX_ETH3_RXD0 0x57e + IMX94_PAD_ETH3_RXD1__NETC_PINMUX_ETH3_RXD1 0x57e + IMX94_PAD_ETH3_RXD2__NETC_PINMUX_ETH3_RXD2 0x57e + IMX94_PAD_ETH3_RXD3__NETC_PINMUX_ETH3_RXD3 0x57e + >; + }; + + pinctrl_eth4: eth4grp { + fsl,pins = < + IMX94_PAD_ETH4_TXD3__NETC_PINMUX_ETH4_TXD3 0x57e + IMX94_PAD_ETH4_TXD2__NETC_PINMUX_ETH4_TXD2 0x57e + IMX94_PAD_ETH4_TXD1__NETC_PINMUX_ETH4_TXD1 0x57e + IMX94_PAD_ETH4_TXD0__NETC_PINMUX_ETH4_TXD0 0x57e + IMX94_PAD_ETH4_TX_CTL__NETC_PINMUX_ETH4_TX_CTL 0x57e + IMX94_PAD_ETH4_TX_CLK__NETC_PINMUX_ETH4_TX_CLK 0x5fe + IMX94_PAD_ETH4_RX_CTL__NETC_PINMUX_ETH4_RX_CTL 0x57e + IMX94_PAD_ETH4_RX_CLK__NETC_PINMUX_ETH4_RX_CLK 0x5fe + IMX94_PAD_ETH4_RXD0__NETC_PINMUX_ETH4_RXD0 0x57e + IMX94_PAD_ETH4_RXD1__NETC_PINMUX_ETH4_RXD1 0x57e + IMX94_PAD_ETH4_RXD2__NETC_PINMUX_ETH4_RXD2 0x57e + IMX94_PAD_ETH4_RXD3__NETC_PINMUX_ETH4_RXD3 0x57e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX94_PAD_GPIO_IO16__LPI2C3_SDA 0x40000b9e + IMX94_PAD_GPIO_IO17__LPI2C3_SCL 0x40000b9e + >; + }; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx943-u-boot.dtsi b/arch/arm/dts/imx943-u-boot.dtsi new file mode 100644 index 00000000000..2b93ba9a38b --- /dev/null +++ b/arch/arm/dts/imx943-u-boot.dtsi @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +/ { + binman { + multiple-images; + + m33-oei-ddrfw { + pad-byte = <0x00>; + align-size = <0x8>; + filename = "m33-oei-ddrfw.bin"; + + oei-m33-ddr { + align-size = <0x4>; + filename = "oei-m33-ddr.bin"; + type = "blob-ext"; + }; + + imx-lpddr { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem { + filename = "lpddr5_imem_v202409.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem { + filename = "lpddr5_dmem_v202409.bin"; + type = "blob-ext"; + }; + }; + + imx-lpddr-qb { + type = "nxp-header-ddrfw"; + + imx-lpddr-imem-qb { + filename = "lpddr5_imem_qb_v202409.bin"; + type = "blob-ext"; + }; + + imx-lpddr-dmem-qb { + filename = "lpddr5_dmem_qb_v202409.bin"; + type = "blob-ext"; + }; + }; + }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl { + type = "nxp-imx9image"; + cfg-path = "spl/u-boot-spl.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + append = "mx943a0-ahab-container.img"; + container; + dummy-ddr; + image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000"; + hold = <0x10000>; + image1 = "m33", "m33_image.bin", "0x1ffc0000"; + image2 = "a55", "spl/u-boot-spl.bin", "0x20480000"; + dummy-v2x = <0x8b000000>; + }; + + u-boot { + type = "nxp-imx9image"; + cfg-path = "u-boot-container.cfgout"; + args; + + cntr-version = <2>; + boot-from = "sd"; + soc-type = "IMX9"; + container; + image0 = "a55", "bl31.bin", "0x8a200000"; + image1 = "a55", "u-boot.bin", "0x90200000"; + }; + }; + }; + + reg_gpy_stby: regulator-gpy-stby { + compatible = "regulator-fixed"; + regulator-name = "gpy-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pcal6416_i2c3_u171 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_gpy_en: regulator-gpy-en { + compatible = "regulator-fixed"; + regulator-name = "gpy-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_gpy_stby>; + gpio = <&pcal6416_i2c3_u171 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usbphynop: usbphynop { + compatible = "usb-nop-xceiv"; + clocks = <&scmi_clk IMX94_CLK_HSIO>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; +}; + +&cpu0 { + clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&cpu1 { + clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&cpu2 { + clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&cpu3 { + clocks = <&scmi_clk IMX94_CLK_ARMPLL_PFD0>; + /delete-property/ power-domains; +}; + +&aips1 { + bootph-all; +}; + +&aips2 { + bootph-all; +}; + +&aips3 { + bootph-all; +}; + +&clk_ext1 { + bootph-all; +}; + +&dummy { + bootph-all; +}; + +&{/firmware} { + bootph-all; +}; + +&{/firmware/scmi} { + bootph-all; +}; + +&{/firmware/scmi/protocol@11} { + bootph-all; +}; + +&{/firmware/scmi/protocol@13} { + bootph-all; +}; + +&{/firmware/scmi/protocol@14} { + bootph-all; +}; + +&{/firmware/scmi/protocol@19} { + bootph-all; +}; + +&gpio2 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&gpio5 { + bootph-pre-ram; +}; + +&gpio6 { + bootph-pre-ram; +}; + +&gpio7 { + bootph-pre-ram; +}; + +&mu2 { + bootph-all; +}; + +&osc_24m { + bootph-all; +}; + +&scmi_buf0 { + bootph-all; +}; + +&scmi_buf1 { + bootph-all; +}; + +&{/soc} { + bootph-all; + + usb3: usb@4c010010 { + compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; + reg = <0x0 0x4c010010 0x0 0x04>, + <0x0 0x4c1f0000 0x0 0x20>; + ranges; + interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_32K>; + clock-names = "hsio", "suspend"; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + status = "disabled"; + + usb3_dwc3: usb@4c100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x4c100000 0x0 0x10000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_24M>, + <&scmi_clk IMX94_CLK_32K>; + clock-names = "bus_early", "ref", "suspend"; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; + }; + }; + + usb3_phy: phy@4c1f0040 { + compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; + reg = <0x0 0x4c1f0040 0x0 0x40>, + <0x0 0x4c1fc000 0x0 0x100>; + clocks = <&scmi_clk IMX94_CLK_HSIO>; + clock-names = "phy"; + #phy-cells = <0>; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + status = "disabled"; + }; + + usb2: usb@4c200000 { + compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x0 0x4c200000 0x0 0x200>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk IMX94_CLK_HSIO>, + <&scmi_clk IMX94_CLK_32K>; + clock-names = "usb_ctrl_root", "usb_wakeup"; + power-domains = <&scmi_devpd IMX94_PD_HSIO_TOP>; + phys = <&usbphynop>; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbmisc: usbmisc@4c200200 { + compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x4c200200 0x0 0x200>, + <0x0 0x4c010014 0x0 0x04>; + #index-cells = <1>; + }; + + netc_blk_ctrl: system-controller@4ceb0000 { + compatible = "nxp,imx94-netc-blk-ctrl"; + reg = <0x0 0x4ceb0000 0x0 0x10000>, + <0x0 0x4cec0000 0x0 0x10000>, + <0x0 0x4c810000 0x0 0x7C>; + reg-names = "ierb", "prb", "netcmix"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&scmi_devpd IMX94_PD_NETC>; + status = "disabled"; + + netc_bus0: pcie@4ca00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4ca00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x0 0x0>; + /* Switch BAR0 - non-prefetchable memory */ + ranges = <0x02000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0x80000 + /* ENETC 3 and Timer 0 BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4cd40000 0x0 0x4cd40000 0x0 0x60000 + /* Switch and Timer 0 BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce00000 0x0 0x4ce00000 0x0 0x20000 + /* ENETC 3 VF0-2 BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4ce50000 0x0 0x4ce50000 0x0 0x30000 + /* ENETC 3 VF0-2 BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce80000 0x0 0x4ce80000 0x0 0x30000>; + + enetc3: ethernet@0,0 { + compatible = "pci1131,e110"; + reg = <0x0 0 0 0 0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + netc_timer0: ethernet@0,1 { + compatible = "pci1131,ee02"; + reg = <0x100 0 0 0 0>; + status = "disabled"; + }; + + netc_switch: ethernet-switch@0,2 { + compatible = "pci1131,eef2", "nxp,imx943-netc-switch"; + reg = <0x200 0 0 0 0>; + status = "disabled"; + + netc_switch_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* External ports */ + netc_switch_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + netc_switch_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + netc_switch_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + /* Internal port, a.k.a management port */ + netc_switch_port3: port@3 { + reg = <3>; + phy-mode = "internal"; + ethernet = <&enetc3>; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; + + netc_bus1: pcie@4cb00000 { + compatible = "pci-host-ecam-generic"; + reg = <0x0 0x4cb00000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x1 0x1>; + /* ENETC 0-2 BAR0 - non-prefetchable memory */ + ranges = <0x02000000 0x0 0x4cC80000 0x0 0x4cc80000 0x0 0xc0000 + /* Timer 1-2 and EMDIO BAR0 - non-prefetchable memory */ + 0x02000000 0x0 0x4cda0000 0x0 0x4cda0000 0x0 0x60000 + /* Timer 1-2 and EMDIO BAR2 - prefetchable memory */ + 0x42000000 0x0 0x4ce20000 0x0 0x4ce20000 0x0 0x30000>; + + enetc0: ethernet@0,0 { + compatible = "pci1131,e101"; + reg = <0x10000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer1: ethernet@0,1 { + compatible = "pci1131,ee02"; + reg = <0x10100 0 0 0 0>; + status = "disabled"; + }; + + enetc1: ethernet@8,0 { + compatible = "pci1131,e101"; + reg = <0x14000 0 0 0 0>; + status = "disabled"; + }; + + enetc2: ethernet@10,0 { + compatible = "pci1131,e101"; + reg = <0x18000 0 0 0 0>; + status = "disabled"; + }; + + netc_timer2: ethernet@10,1 { + compatible = "pci1131,ee02"; + reg = <0x18100 0 0 0 0>; + status = "disabled"; + }; + + netc_emdio: mdio@18,0 { + compatible = "pci1131,ee00"; + reg = <0x1c000 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + }; + + elemu1: mailbox@47530000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x0 0x47530000 0x0 0x10000>; + bootph-all; + status = "okay"; + }; + + elemu3: mailbox@47550000 { + compatible = "fsl,imx93-mu-s4"; + reg = <0x0 0x47550000 0x0 0x10000>; + bootph-all; + status = "okay"; + }; +}; + +&sram0 { + bootph-all; +}; diff --git a/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi b/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi new file mode 100644 index 00000000000..514dd729be9 --- /dev/null +++ b/arch/arm/dts/imx95-15x15-evk-u-boot.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + */ + +#include "imx95-u-boot.dtsi" + +/ { + aliases { + pci0 = &netc_bus0; + pci1 = &netc_bus1; + }; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-imem} { + filename = "lpddr4x_imem_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr/imx-lpddr-dmem} { + filename = "lpddr4x_dmem_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-imem-qb} { + filename = "lpddr4x_imem_qb_v202409.bin"; +}; + +&{/binman/m33-oei-ddrfw/imx-lpddr-qb/imx-lpddr-dmem-qb} { + filename = "lpddr4x_dmem_qb_v202409.bin"; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&wdog3 { + status = "disabled"; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_gpio { + bootph-pre-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi index 2d1f02baa5f..8b59831b7ca 100644 --- a/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi +++ b/arch/arm/dts/imx95-19x19-evk-u-boot.dtsi @@ -5,6 +5,13 @@ #include "imx95-u-boot.dtsi" +/ { + aliases { + pci0 = &netc_bus0; + pci1 = &netc_bus1; + }; +}; + &lpuart1 { bootph-pre-ram; }; diff --git a/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi new file mode 100644 index 00000000000..97ce7402e50 --- /dev/null +++ b/arch/arm/dts/imx95-toradex-smarc-dev-u-boot.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (C) 2025 Toradex */ + +#include "imx95-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&gpio1 { + reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; + bootph-pre-ram; +}; + +&lpi2c4 { + bootph-pre-ram; +}; + +&lpuart1 { + clocks = <&scmi_clk IMX95_CLK_LPUART1>, <&scmi_clk IMX95_CLK_LPUART1>; + clock-names = "ipg", "per"; + bootph-pre-ram; +}; + +/* Conflict with JTAG interface */ +&lpuart5 { + status = "disabled"; +}; + +&pinctrl_lpi2c4 { + bootph-pre-ram; +}; + +&pinctrl_lpi2c4_gpio { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2 { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_cd { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_pwr_en { + bootph-pre-ram; +}; + +&pinctrl_usdhc2_vsel { + bootph-pre-ram; +}; + +®_usdhc2_vmmc { + bootph-pre-ram; +}; + +®_usdhc2_vqmmc { + bootph-pre-ram; +}; + +&som_gpio_expander_0 { + bootph-pre-ram; +}; + +&som_gpio_expander_1 { + bootph-pre-ram; +}; + +&usb2 { + /delete-property/power-domains; +}; + +&usb3 { + status = "disabled"; +}; + +&usb3_dwc3 { + status = "disabled"; +}; + +&usdhc1 { + bootph-pre-ram; +}; + +&usdhc2 { + bootph-pre-ram; +}; + +&wdog3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mp-toradex-smarc-dev.dts b/arch/arm/dts/imx95-toradex-smarc-dev.dts index 581f221323b..5b05f256fd5 100644 --- a/arch/arm/dts/imx8mp-toradex-smarc-dev.dts +++ b/arch/arm/dts/imx95-toradex-smarc-dev.dts @@ -1,27 +1,21 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* Copyright (C) 2025 Toradex */ +/* + * Copyright (C) 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/smarc-development-board-kit + */ /dts-v1/; -#include "imx8mp-toradex-smarc.dtsi" +#include <dt-bindings/pwm/pwm.h> +#include "imx95-toradex-smarc.dtsi" / { - model = "Toradex SMARC iMX8M Plus on Toradex SMARC Development Board"; - compatible = "toradex,smarc-imx8mp-dev", - "toradex,smarc-imx8mp", - "fsl,imx8mp"; - - hdmi-connector { - compatible = "hdmi-connector"; - label = "J64"; - type = "a"; - - port { - native_hdmi_connector_in: endpoint { - remote-endpoint = <&hdmi_tx_out>; - }; - }; - }; + model = "Toradex SMARC iMX95 on Toradex SMARC Development Board"; + compatible = "toradex,smarc-imx95-dev", + "toradex,smarc-imx95", + "fsl,imx95"; reg_carrier_1p8v: regulator-carrier-1p8v { compatible = "regulator-fixed"; @@ -50,128 +44,77 @@ "Line", "Line In Jack"; codec_dai: simple-audio-card,codec { - clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; sound-dai = <&wm8904_1a>; }; simple-audio-card,cpu { - sound-dai = <&sai1>; + sound-dai = <&sai3>; }; }; }; -&aud2htx { - status = "okay"; -}; - -/* SMARC SPI0 */ -&ecspi1 { - status = "okay"; -}; - /* SMARC GBE0 */ -&eqos { +&enetc_port0 { status = "okay"; }; /* SMARC GBE1 */ -&fec { +&enetc_port1 { status = "okay"; }; -/* SMARC CAN1 */ +/* SMARC CAN0 */ &flexcan1 { status = "okay"; }; -/* SMARC CAN0 */ +/* SMARC CAN1 */ &flexcan2 { status = "okay"; }; -&gpio1 { +&gpio2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio7>, - <&pinctrl_gpio8>, - <&pinctrl_gpio9>, - <&pinctrl_gpio10>, - <&pinctrl_gpio11>, - <&pinctrl_gpio12>, - <&pinctrl_gpio13>; -}; - -&gpio3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lvds_dsi_sel>; + pinctrl-0 = <&pinctrl_gpio12>, <&pinctrl_gpio13>; }; &gpio4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_gpio6>; + pinctrl-0 = <&pinctrl_gpio10>, <&pinctrl_gpio11>; }; -&hdmi_pvi { - status = "okay"; -}; - -/* SMARC HDMI */ -&hdmi_tx { - status = "okay"; - - ports { - port@1 { - hdmi_tx_out: endpoint { - remote-endpoint = <&native_hdmi_connector_in>; - }; - }; - }; +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>, + <&pinctrl_gpio3>, + <&pinctrl_gpio4>, + <&pinctrl_gpio6>, + <&pinctrl_gpio8>, + <&pinctrl_gpio9>; }; -&hdmi_tx_phy { +/* SMARC I2C_CAM0 */ +&i2c_cam0 { status = "okay"; }; -/* SMARC I2C_LCD */ -&i2c2 { +/* SMARC I2C_CAM1 */ +&i2c_cam1 { status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9543"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - - /* I2C on DSI Connector Pins 4/6 */ - i2c_dsi_0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - /* I2C on DSI Connector Pins 52/54 */ - i2c_dsi_1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; }; -/* SMARC I2C_CAM0 */ -&i2c3 { +/* SMARC I2C_GP */ +&lpi2c2 { status = "okay"; -}; -/* SMARC I2C_GP */ -&i2c4 { - /* Audio Codec */ wm8904_1a: audio-codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>, <&pinctrl_sai1_mclk>; + pinctrl-0 = <&pinctrl_sai3>, <&pinctrl_sai3_mclk>; #sound-dai-cells = <0>; - clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; clock-names = "mclk"; AVDD-supply = <®_carrier_1p8v>; CPVDD-supply = <®_carrier_1p8v>; @@ -180,37 +123,36 @@ MICVDD-supply = <®_carrier_1p8v>; }; - /* On-Carrier Temperature Sensor */ temperature-sensor@4f { compatible = "ti,tmp1075"; reg = <0x4f>; }; - /* On-Carrier EEPROM */ eeprom@57 { compatible = "st,24c02", "atmel,24c02"; reg = <0x57>; pagesize = <16>; }; -}; -/* SMARC I2C_CAM1 */ -&i2c5 { - status = "okay"; }; /* SMARC I2C_PM */ -&i2c6 { +&lpi2c3 { clock-frequency = <100000>; status = "okay"; - /* Fan controller */ - fan@18 { + fan_controller: fan@18 { compatible = "ti,amc6821"; reg = <0x18>; + #pwm-cells = <2>; + + fan { + cooling-levels = <255>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; }; - /* Current measurement into module VDD */ + /* Current measurement into module VCC */ hwmon@40 { compatible = "ti,ina226"; reg = <0x40>; @@ -218,76 +160,114 @@ }; }; -&lcdif3 { +/* SMARC I2C_LCD */ +&lpi2c5 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + i2c-mux-idle-disconnect; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pins 4/6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pins 52/54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* SMARC SPI0 */ +&lpspi6 { status = "okay"; }; -/* SMARC PCIE_A, M2 Key B */ -&pcie { +/* SMARC SER1, used as the Linux Console */ +&lpuart1 { status = "okay"; }; -&pcie_phy { +/* SMARC SER0, RS485 */ +&lpuart2 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; status = "okay"; }; -/* SMARC LCD1_BKLT_PWM */ -&pwm1 { +/* SMARC SER3, RS232 */ +&lpuart3 { status = "okay"; }; -/* SMARC LCD0_BKLT_PWM */ -&pwm2 { +/* SMARC MDIO, shared between all ethernet ports */ +&netc_emdio { + status = "okay"; + + ethphy3: ethernet-phy@4 { + reg = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>; + interrupt-parent = <&gpio5>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +/* SMARC PCIE_A / M2 Key B */ +&pcie0 { status = "okay"; }; -/* SMARC I2S0 */ -&sai1 { - assigned-clocks = <&clk IMX8MP_CLK_SAI1>; - assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; - assigned-clock-rates = <24576000>; - fsl,sai-mclk-direction-output; +/* SMARC PCIE_B / M2 Key E */ +&pcie1 { status = "okay"; }; -/* SMARC HDMI Audio */ -&sound_hdmi { +/* SMARC I2S0 */ +&sai3 { status = "okay"; }; -/* SMARC SER0, RS485. Optional M.2 KEY E */ -&uart1 { - linux,rs485-enabled-at-boot-time; - rs485-rts-active-low; - rs485-rx-during-tx; +/* SMARC LCD0_BKLT_PWM */ +&tpm3 { status = "okay"; }; -/* SMARC SER2 */ -&uart2 { +/* SMARC LCD1_BKLT_PWM */ +&tpm4 { status = "okay"; }; -/* SMARC SER1, used as the Linux Console */ -&uart4 { +/* SMARC GPIO5 as PWM */ +&tpm5 { status = "okay"; }; /* SMARC USB0 */ -&usb3_0 { +&usb2 { status = "okay"; }; /* SMARC USB1..4 */ -&usb3_1 { +&usb3 { status = "okay"; }; -&usb3_phy0 { +&usb3_dwc3 { status = "okay"; }; -&usb3_phy1 { +&usb3_phy { status = "okay"; }; diff --git a/arch/arm/dts/imx95-toradex-smarc.dtsi b/arch/arm/dts/imx95-toradex-smarc.dtsi new file mode 100644 index 00000000000..e99f1a57af8 --- /dev/null +++ b/arch/arm/dts/imx95-toradex-smarc.dtsi @@ -0,0 +1,1153 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/net/ti-dp83867.h> +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart2; + serial1 = &lpuart1; + serial3 = &lpuart3; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + clk_dsi2dp_bridge: clock-dsi2dp-bridge { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_serdes_eth_ref: clock-eth-ref { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + /* CTRL_ETH_REF_CLK_STBY# */ + enable-gpios = <&som_gpio_expander_1 13 GPIO_ACTIVE_HIGH>; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + /* SMARC P64 - USB0_OTG_ID */ + id-gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; + label = "USB0"; + self-powered; + type = "micro"; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb0_otg_id>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + smarc_key_sleep: key-sleep { + gpios = <&som_ec_gpio_expander 4 GPIO_ACTIVE_LOW>; + label = "SMARC_SLEEP#"; + wakeup-source; + linux,code = <KEY_SLEEP>; + }; + + smarc_switch_lid: switch-lid { + gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>; + label = "SMARC_LID#"; + linux,code = <SW_LID>; + linux,input-type = <EV_SW>; + }; + }; + + reg_module_1p8v: regulator-module-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + /* Non PMIC On-module Supplies */ + reg_module_dp_1p2v: regulator-module-dp-1p2v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DP"; + vin-supply = <®_module_1p8v>; + }; + + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + /* SMARC P62 - USB0_EN_OC# */ + gpios = <&som_gpio_expander_0 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB0_EN_OC#"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* CTRL_V_BUS_USB_HUB or SMARC P71 - USB2_EN_OC# */ + gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "CTRL_V_BUS_USB_HUB"; + }; + + reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + enable-active-high; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SDIO_PWR_EN"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vsel>; + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "PMIC_SD2_VSEL"; + }; + + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + /* CTRL_EN_WIFI */ + gpios = <&som_gpio_expander_1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "CTRL_EN_WIFI"; + startup-delay-us = <2000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + linux,cma-default; + }; + }; +}; + +/* SMARC GBE0 */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>, <&pinctrl_enetc0_1588_tmr>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* SMARC GBE1 */ +&enetc_port1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc1>, <&pinctrl_enetc1_1588_tmr>; + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; +}; + +/* SMARC CAN0 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* SMARC CAN1 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "SMARC_I2C_GP_CK", + "SMARC_I2C_GP_DAT", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "CTRL_IO_EXP_INT_B"; + status = "okay"; +}; + +&gpio2 { + gpio-line-names = "SMARC_SPI0_CS0#", /* 0 */ + "", + "", + "", + "", + "", + "SMARC_GPIO5", + "", + "I2C_CAM_DAT", + "I2C_CAM_CK", + "SMARC_GPIO12", /* 10 */ + "SMARC_GPIO13", + "", + "", + "", + "", + "", + "", + "SMARC_SPI1_CS0#", + "", + "", /* 20 */ + "", + "SMARC_I2C_LCD_DAT", + "SMARC_I2C_LCD_CK", + "SMARC_SPI0_CS1#", + "", + "", + "", + "SMARC_I2C_PM_DAT", + "SMARC_I2C_PM_CK", + "I2C_SOM_DAT", /* 30 */ + "I2C_SOM_CK"; + status = "okay"; +}; + +&gpio3 { + gpio-line-names = "SMARC_SDIO_CD#", /* 0 */ + "", + "", + "", + "", + "", + "", + "SMARC_SDIO_PWR_EN", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "PMIC_SD2_VSEL"; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "SMARC_GPIO11", + "SMARC_GPIO10", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "SMARC_SMB_ALERT#"; + status = "okay"; +}; + +&gpio5 { + gpio-line-names = "SMARC_GPIO2", /* 0 */ + "SMARC_GPIO3", + "SMARC_GPIO4", + "SMARC_GPIO6", + "", + "", + "", + "", + "SMARC_GPIO9", + "SMARC_GPIO7", + "SMARC_GPIO8", /* 10 */ + "SMARC_SPI1_CS1#", + "", + "SPI1_TPM_CS#"; + status = "okay"; +}; + +/* SMARC I2C_GP */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + eeprom@50 { + compatible = "st,24c32", "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; +}; + +/* SMARC I2C_PM */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* I2C_SOM */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>, <&pinctrl_ctrl_io_exp_int_b>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>, <&pinctrl_ctrl_io_exp_int_b>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + som_gpio_expander_0: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "SMARC_PCIE_WAKE#", /* 0 */ + "SMARC_PCIE_B_RST#", + "SMARC_PCIE_A_RST#", + "SMARC_USB0_OTG_ID", + "SMARC_USB0_EN", /* SMARC USB0_EN_OC# - Open Drain Output */ + "SMARC_USB0_OC#", /* SMARC USB0_EN_OC# - Over-Current Sense Input */ + "", + "SMARC_PCIE_C_RST#"; + }; + + som_gpio_expander_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "SMARC_GPIO0", /* 0 */ + "SMARC_GPIO1", + "SMARC_LCD0_VDD_EN", + "SMARC_LCD0_BKLT_EN", + "SMARC_LCD1_VDD_EN", + "SMARC_LCD1_BKLT_EN", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "SMARC_SDIO_WP"; + }; + + embedded-controller@28 { + compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec"; + reg = <0x28>; + }; + + som_ec_gpio_expander: gpio@29 { + compatible = "toradex,ecgpiol16", "nxp,pcal6416"; + reg = <0x29>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ec_int>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "SMARC_CHARGER_PRSNT#", + "SMARC_CHARGING#", + "SMARC_LID#", + "SMARC_BATLOW#", + "SMARC_SLEEP#"; + }; + + /* SMARC DP0 */ + som_dsi2dp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clocks = <&clk_dsi2dp_bridge>; + clock-names = "refclk"; + vcc-supply = <®_module_dp_1p2v>; + vcca-supply = <®_module_dp_1p2v>; + vccio-supply = <®_module_1p8v>; + vpll-supply = <®_module_1p8v>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + data-lanes = <3 2 1 0>; + }; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* SMARC I2C_LCD */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* I2C_CAM */ +&lpi2c7 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c7>; + pinctrl-1 = <&pinctrl_lpi2c7_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* SMARC I2C_CAM0 */ + i2c_cam0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* SMARC I2C_CAM1 */ + i2c_cam1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* SMARC SPI1 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, + <&gpio5 11 GPIO_ACTIVE_LOW>, + <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + som_tpm: tpm@2 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x2>; + spi-max-frequency = <18500000>; + }; +}; + +/* SMARC SPI0 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, + <&gpio2 24 GPIO_ACTIVE_LOW>; +}; + +/* SMARC SER1, used as the Linux Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* SMARC SER0 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; +}; + +/* SMARC SER3 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +/* SMARC MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; + + ethphy2: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_timer { + status = "okay"; +}; + +/* SMARC PCIE_A */ +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_LOW>; +}; + +/* SMARC PCIE_B */ +&pcie1 { + pinctrl-0 = <&pinctrl_pcie1>; + pinctrl-names = "default"; + reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; +}; + +/* SMARC I2S0 */ +&sai3 { + #sound-dai-cells = <0>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + fsl,sai-mclk-direction-output; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* SMARC LCD0_BKLT_PWM */ +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_bklt_pwm>; +}; + +/* SMARC LCD1_BKLT_PWM */ +&tpm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_bklt_pwm>; +}; + +/* SMARC GPIO5 as PWM */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5_pwm>; +}; + +/* SMARC USB0 */ +&usb2 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + vbus-supply = <®_usb0_vbus>; + + port { + usb0_otg_id: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usb3 { + fsl,disable-port-power-control; +}; + +/* SMARC USB1..4 */ +&usb3_dwc3 { + dr_mode = "host"; +}; + +&usb3_phy { + vbus-supply = <®_usb1_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +/* SMARC SDIO */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; + wp-gpios = <&som_gpio_expander_1 15 GPIO_ACTIVE_HIGH>; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + keep-power-in-suspend; + non-removable; + vmmc-supply = <®_wifi_en>; +}; + +&scmi_bbm { + linux,code = <KEY_POWER>; +}; + +&wdog3 { + fsl,ext-reset-output; + status = "okay"; +}; + +&scmi_iomuxc { + /* SMARC CAM_MCK */ + pinctrl_cam_mck: cammckgrp { + fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SMARC S6 - CAM_MCK */ + }; + + pinctrl_ec_int: ecintgrp { + fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x31e>; /* SAI1_TXFS - EC_MCU_INT# */ + }; + + /* SMARC MDIO, shared between all ethernet ports */ + pinctrl_emdio: emdiogrp { + fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* SMARC S45 - MDIO_CLK */ + <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* SMARC S46 - MDIO_DAT */ + }; + + /* SMARC GBE0 */ + pinctrl_enetc0: enetc0grp { + fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ + <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ + <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ + <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ + <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ + <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ + <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ + <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ + <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ + <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ + <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ + <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ + }; + + /* SMARC GBE0_SDP */ + pinctrl_enetc0_1588_tmr: enetc01588tmrgrp { + fsl,pins = <IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x51e>; /* SMARC P6 - GBE0_SDP */ + }; + + /* SMARC GBE1 */ + pinctrl_enetc1: enetc1grp { + fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */ + <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */ + <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */ + <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */ + <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */ + <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */ + <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */ + <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */ + <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */ + <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */ + <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */ + <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */ + }; + + /* SMARC GBE1_SDP */ + pinctrl_enetc1_1588_tmr: enetc11588tmrgrp { + fsl,pins = <IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x51e>; /* SMARC P5 - GBE1_SDP */ + }; + + /* SMARC CAN0 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SMARC P143 - CAN0_TX */ + <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SMARC P144 - CAN0_RX */ + }; + + /* SMARC CAN1 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SMARC P145 - CAN1_TX */ + <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SMARC P146 - CAN1_RX */ + }; + + /* SMARC GPIO2 */ + pinctrl_gpio2: gpio2grp { + fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x31e>; /* SMARC P110 - GPIO2 */ + }; + + /* SMARC GPIO3 */ + pinctrl_gpio3: gpio3grp { + fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x31e>; /* SMARC P111 - GPIO3 */ + }; + + /* SMARC GPIO4 */ + pinctrl_gpio4: gpio4grp { + fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x31e>; /* SMARC P112 - GPIO4 */ + }; + + /* SMARC GPIO5 */ + pinctrl_gpio5: gpio5grp { + fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x31e>; /* SMARC P113 - GPIO5 */ + }; + + /* SMARC GPIO5 as PWM */ + pinctrl_gpio5_pwm: gpio5pwmgrp { + fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SMARC P113 - PWM_OUT */ + }; + + /* SMARC GPIO6 */ + pinctrl_gpio6: gpio6grp { + fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e>; /* SMARC P114 - GPIO6 */ + }; + + /* SMARC GPIO7 */ + pinctrl_gpio7: gpio7grp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e>; /* SMARC P115 - GPIO7 */ + }; + + /* SMARC GPIO8 */ + pinctrl_gpio8: gpio8grp { + fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x31e>; /* SMARC P116 - GPIO8 */ + }; + + /* SMARC GPIO9 */ + pinctrl_gpio9: gpio9grp { + fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x31e>; /* SMARC P117 - GPIO9 */ + }; + + /* SMARC GPIO10 */ + pinctrl_gpio10: gpio10grp { + fsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x31e>; /* SMARC P118 - GPIO10 */ + }; + + /* SMARC GPIO11 */ + pinctrl_gpio11: gpio11grp { + fsl,pins = <IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x31e>; /* SMARC P119 - GPIO11 */ + }; + + /* SMARC GPIO12 */ + pinctrl_gpio12: gpio12grp { + fsl,pins = <IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e>; /* SMARC S142 - GPIO12 */ + }; + + /* SMARC GPIO13 */ + pinctrl_gpio13: gpio13grp { + fsl,pins = <IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e>; /* SMARC S123 - GPIO13 */ + }; + + pinctrl_ctrl_io_exp_int_b: ioexpintgrp { + fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* CTRL_IO_EXP_INT_B */ + }; + + /* SMARC LCD0_BKLT_PWM */ + pinctrl_lcd0_bklt_pwm: lcd0bkltpwmgrp { + fsl,pins = <IMX95_PAD_GPIO_IO12__TPM3_CH2 0x51e>; /* SMARC S141 - LCD0_BKLT_PWM */ + }; + + /* SMARC LCD1_BKLT_PWM */ + pinctrl_lcd1_bklt_pwm: lcd1bkltpwmgrp { + fsl,pins = <IMX95_PAD_GPIO_IO13__TPM4_CH2 0x51e>; /* SMARC S122 - LCD1_BKLT_PWM */ + }; + + /* SMARC I2C_GP */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ + }; + + /* SMARC I2C_GP as GPIOs */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ + }; + + /* SMARC I2C_PM */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ + <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ + }; + + /* SMARC I2C_PM as GPIOs */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ + <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ + }; + + /* I2C_SOM */ + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* I2C_SOM_CK */ + <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* I2C_SOM_DAT */ + }; + + /* I2C_SOM as GPIOs */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* I2C_SOM_CK */ + <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* I2C_SOM_DAT */ + }; + + /* SMARC I2C_LCD */ + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ + <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ + }; + + /* SMARC I2C_LCD as GPIOs */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ + <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ + }; + + /* I2C_CAM */ + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = <IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40001b9e>, /* I2C_CAM_DAT */ + <IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40001b9e>; /* I2C_CAM_CK */ + }; + + /* I2C_CAM as GPIOs */ + pinctrl_lpi2c7_gpio: lpi2c7gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x40001b9e>, /* I2C_CAM_DAT */ + <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x40001b9e>; /* I2C_CAM_CK */ + }; + + /* SMARC SPI1 */ + pinctrl_lpspi4: lpspi4grp { + fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x3fe>, /* SMARC P56 - SPI1_CK */ + <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x3fe>, /* SMARC P58 - SPI1_DO */ + <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* SMARC P57 - SPI1_DIN */ + <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x3fe>, /* SPI1_TPM_CS# */ + <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* SMARC P54 - SPI1_CS0# */ + <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe>; /* SMARC P55 - SPI1_CS1# */ + }; + + /* SMARC SPI0 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* SMARC P43 - SPI0_CS0# */ + <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x3fe>, /* SMARC P31 - SPI0_CS1# */ + <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SMARC P45 - SPI0_DIN */ + <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SMARC P46 - SPI0_DO */ + <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SMARC P44 - SPI0_CK */ + }; + + /* SMARC PCIE_A */ + pinctrl_pcie0: pcie0grp { + fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* SMARC P78 - PCIE_A_CKREQ# */ + }; + + /* SMARC PCIE_B */ + pinctrl_pcie1: pcie1grp { + fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* SMARC P77 - PCIE_B_CKREQ# */ + }; + + /* SMARC I2S0 */ + pinctrl_sai3: sai3grp { + fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SMARC S38 - I2S0_CK */ + <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SMARC S41 - I2S0_SDIN */ + <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SMARC S40 - I2S0_SDOUT */ + <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SMARC S39 - I2S0_LRCK */ + }; + + /* SMARC AUDIO_MCK */ + pinctrl_sai3_mclk: sai3mclkgrp { + fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SMARC S42 - AUDIO_MCK */ + }; + + /* SMARC I2S2 */ + pinctrl_sai5: sai5grp { + fsl,pins = <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SMARC S53 - I2S2_CK */ + <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SMARC S51 - I2S2_SDOUT */ + <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>, /* SMARC S52 - I2S2_SDIN */ + <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>; /* SMARC S50 - I2S2_LRCK */ + }; + + /* SMARC SMB_ALERT# */ + pinctrl_smb_alert_gpio: smbalertgrp { + fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e>; /* SMARC P1 - SMB_ALERT# */ + }; + + /* SMARC SER1, used as the Linux Console */ + pinctrl_uart1: uart1grp { + fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* SMARC P134 - SER1_TX */ + <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* SMARC P135 - SER1_RX */ + }; + + /* SMARC SER0 */ + pinctrl_uart2: uart2grp { + fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x31e>, /* SMARC P132 - SER0_CTS# */ + <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x31e>, /* SMARC P131 - SER0_RTS# */ + <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SMARC P130 - SER0_RX */ + <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SMARC P129 - SER0_TX */ + }; + + /* SMARC SER3 */ + pinctrl_uart3: uart3grp { + fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* SMARC P140 - SER3_TX */ + <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>; /* SMARC P141 - SER3_RX */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */ + }; + + /* SMARC SDIO */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SMARC P36 - SDIO_CK */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SMARC P34 - SDIO_CMD */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SMARC P39 - SDIO_D0 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SMARC P40 - SDIO_D1 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SMARC P41 - SDIO_D2 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO */ + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SMARC P36 - SDIO_CK */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SMARC P34 - SDIO_CMD */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SMARC P39 - SDIO_D0 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SMARC P40 - SDIO_D1 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SMARC P41 - SDIO_D2 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO */ + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SMARC P36 - SDIO_CK */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SMARC P34 - SDIO_CMD */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SMARC P39 - SDIO_D0 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SMARC P40 - SDIO_D1 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SMARC P41 - SDIO_D2 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SMARC P42 - SDIO_D3 */ + }; + + /* SMARC SDIO_CD# */ + pinctrl_usdhc2_cd: usdhc2-cdgrp { + fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SMARC P35 - SDIO_CD# */ + }; + + /* SMARC SDIO_PWR_EN */ + pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { + fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SMARC P37 - SDIO_PWR_EN */ + }; + + pinctrl_usdhc2_vsel: usdhc2-vselgrp { + fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */ + <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */ + <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */ + <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */ + <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */ + <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */ + <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */ + <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */ + <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */ + <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */ + <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */ + }; +}; diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi index 9bf8f9834c9..591cb317508 100644 --- a/arch/arm/dts/imx95-u-boot.dtsi +++ b/arch/arm/dts/imx95-u-boot.dtsi @@ -52,15 +52,47 @@ pad-byte = <0x00>; spl { - align = <0x400>; - align-size = <0x400>; - type = "mkimage"; - args = "-n spl/u-boot-spl.cfgout -T imx8image"; + type = "nxp-imx9image"; + cfg-path = "spl/u-boot-spl.cfgout"; + args; + +#ifndef CONFIG_IMX95_A0 + cntr-version = <2>; +#endif + boot-from = "sd"; + soc-type = "IMX9"; +#ifdef CONFIG_IMX95_A0 + append = "mx95a0-ahab-container.img"; +#else + append = "mx95b0-ahab-container.img"; +#endif + container; +#ifndef CONFIG_IMX95_A0 + dummy-ddr; +#endif + image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000"; + hold = <0x10000>; +#ifdef CONFIG_IMX95_A0 + image1 = "oei", "oei-m33-tcm.bin", "0x1ffc0000"; +#endif + image2 = "m33", "m33_image.bin", "0x1ffc0000"; + image3 = "a55", "spl/u-boot-spl.bin", "0x20480000"; + dummy-v2x = <0x8b000000>; }; u-boot { - type = "mkimage"; - args = "-n u-boot-container.cfgout -T imx8image"; + type = "nxp-imx9image"; + cfg-path = "u-boot-container.cfgout"; + args; + +#ifndef CONFIG_IMX95_A0 + cntr-version = <2>; +#endif + boot-from = "sd"; + soc-type = "IMX9"; + container; + image0 = "a55", "bl31.bin", "0x8a200000"; + image1 = "a55", "u-boot.bin", "0x90200000"; }; }; }; @@ -170,6 +202,22 @@ bootph-all; }; +&pcie0 { + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; +}; + +&pcie1 { + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_HSIOPLL>, + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; + assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; +}; + &{/soc} { bootph-all; }; diff --git a/arch/arm/dts/k3-am62-r5-lp-sk.dts b/arch/arm/dts/k3-am62-r5-lp-sk.dts index 135e8d49b91..95cd9b707c7 100644 --- a/arch/arm/dts/k3-am62-r5-lp-sk.dts +++ b/arch/arm/dts/k3-am62-r5-lp-sk.dts @@ -64,7 +64,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; diff --git a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi index ee273563e83..3a1a8b06dc6 100644 --- a/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am625-phyboard-lyra-rdk-u-boot.dtsi @@ -95,6 +95,22 @@ bootph-all; }; +&main_rti1 { + status = "disabled"; +}; + +&main_rti2 { + status = "disabled"; +}; + +&main_rti3 { + status = "disabled"; +}; + +&main_rti15 { + status = "disabled"; +}; + &main_uart0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am625-r5-beagleplay.dts b/arch/arm/dts/k3-am625-r5-beagleplay.dts index f4b2cd8904e..bba69871fd2 100644 --- a/arch/arm/dts/k3-am625-r5-beagleplay.dts +++ b/arch/arm/dts/k3-am625-r5-beagleplay.dts @@ -70,7 +70,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts index 7132fae36fa..03dc81a4afa 100644 --- a/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am625-r5-phycore-som-2gb.dts @@ -69,7 +69,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts index 34c501dd51b..67589f941ba 100644 --- a/arch/arm/dts/k3-am625-r5-sk.dts +++ b/arch/arm/dts/k3-am625-r5-sk.dts @@ -64,7 +64,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am625-sk-binman.dtsi b/arch/arm/dts/k3-am625-sk-binman.dtsi index f743c4353b4..42edb35fa7b 100644 --- a/arch/arm/dts/k3-am625-sk-binman.dtsi +++ b/arch/arm/dts/k3-am625-sk-binman.dtsi @@ -206,6 +206,70 @@ }; }; + ti-falcon { + insert-template = <&ti_falcon_template>; + + fit { + images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + tifsstub-gp { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-gp"; + load = <0x9dc00000>; + entry = <0x9dc00000>; + blob-ext { + filename = "tifsstub.bin_gp"; + }; + }; + dm { + ti-secure { + content = <&dm_falcon>; + keyfile = "custMpk.pem"; + }; + dm_falcon: ti-dm { + filename = "ti-dm/am62xx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + }; + + configurations { + default = "conf-0"; + conf-0 { + description = "k3-am625-sk-falcon"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "tifsstub-gp", "dm"; + }; + }; + }; + }; + ti-spl { insert-template = <&ti_spl_template>; diff --git a/arch/arm/dts/k3-am625-verdin-r5.dts b/arch/arm/dts/k3-am625-verdin-r5.dts index 39e8ab8158e..fb431c96337 100644 --- a/arch/arm/dts/k3-am625-verdin-r5.dts +++ b/arch/arm/dts/k3-am625-verdin-r5.dts @@ -53,7 +53,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am6254atl-r5-sk.dts b/arch/arm/dts/k3-am6254atl-r5-sk.dts new file mode 100644 index 00000000000..225ad44e722 --- /dev/null +++ b/arch/arm/dts/k3-am6254atl-r5-sk.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM6254atl SiP SK dts for R5 SPL + * Webpage: https://www.ti.com/tool/SK-AM62-SIP + * + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am6254atl-sk.dts" +#include "k3-am6254atl-sip-ddr-lp4-50-800.dtsi" +#include "k3-am62-ddr.dtsi" + +#include "k3-am6254atl-sk-u-boot.dtsi" + +/ { + aliases { + tick-timer = &main_timer0; + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + serial0 = &wkup_uart0; + serial3 = &main_uart1; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + bootph-pre-ram; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&secure_proxy_sa3 { + /* We require this for boot handshake */ + status = "okay"; +}; + +&cbass_main { + sysctrler: sysctrler { + compatible = "ti,am654-tisci-rproc-r5"; + mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; + +/* WKUP UART0 is used for DM firmware logs */ +&wkup_uart0 { + status = "okay"; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + status = "okay"; +}; + +&ospi0 { + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x00 0x60000000 0x00 0x08000000>; +}; + +&main_pktdma { + ti,sci = <&dm_tifs>; + bootph-all; +}; diff --git a/arch/arm/dts/k3-am6254atl-sip-ddr-lp4-50-800.dtsi b/arch/arm/dts/k3-am6254atl-sip-ddr-lp4-50-800.dtsi new file mode 100644 index 00000000000..61894ee3aee --- /dev/null +++ b/arch/arm/dts/k3-am6254atl-sip-ddr-lp4-50-800.dtsi @@ -0,0 +1,2191 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.10 + * Mon Oct 16 2023 09:44:16 GMT-0500 (Central Daylight Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 800MHz + * Density (per channel): 4Gb + * Write DBI: Enable + * Number of Ranks: 1 +*/ + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 + + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x00027100 +#define DDRSS_CTL_12_DATA 0x00186A00 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000640 +#define DDRSS_CTL_15_DATA 0x00027100 +#define DDRSS_CTL_16_DATA 0x00186A00 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000640 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00002020 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x0000040C +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000081C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x0000081C +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x05000804 +#define DDRSS_CTL_45_DATA 0x00000700 +#define DDRSS_CTL_46_DATA 0x09090004 +#define DDRSS_CTL_47_DATA 0x00000303 +#define DDRSS_CTL_48_DATA 0x00320007 +#define DDRSS_CTL_49_DATA 0x09090023 +#define DDRSS_CTL_50_DATA 0x0000210F +#define DDRSS_CTL_51_DATA 0x00320007 +#define DDRSS_CTL_52_DATA 0x09090023 +#define DDRSS_CTL_53_DATA 0x0900210F +#define DDRSS_CTL_54_DATA 0x000A0A09 +#define DDRSS_CTL_55_DATA 0x040006DB +#define DDRSS_CTL_56_DATA 0x09092004 +#define DDRSS_CTL_57_DATA 0x00000C0A +#define DDRSS_CTL_58_DATA 0x06006DB0 +#define DDRSS_CTL_59_DATA 0x09092006 +#define DDRSS_CTL_60_DATA 0x00000C0A +#define DDRSS_CTL_61_DATA 0x06006DB0 +#define DDRSS_CTL_62_DATA 0x03042006 +#define DDRSS_CTL_63_DATA 0x04050002 +#define DDRSS_CTL_64_DATA 0x100F100F +#define DDRSS_CTL_65_DATA 0x01010008 +#define DDRSS_CTL_66_DATA 0x041F1F07 +#define DDRSS_CTL_67_DATA 0x03111103 +#define DDRSS_CTL_68_DATA 0x00001111 +#define DDRSS_CTL_69_DATA 0x00000101 +#define DDRSS_CTL_70_DATA 0x00000000 +#define DDRSS_CTL_71_DATA 0x01000000 +#define DDRSS_CTL_72_DATA 0x00090803 +#define DDRSS_CTL_73_DATA 0x000000BB +#define DDRSS_CTL_74_DATA 0x00000090 +#define DDRSS_CTL_75_DATA 0x00000C2B +#define DDRSS_CTL_76_DATA 0x00000090 +#define DDRSS_CTL_77_DATA 0x00000C2B +#define DDRSS_CTL_78_DATA 0x00000005 +#define DDRSS_CTL_79_DATA 0x00000005 +#define DDRSS_CTL_80_DATA 0x00000010 +#define DDRSS_CTL_81_DATA 0x00000048 +#define DDRSS_CTL_82_DATA 0x0000017E +#define DDRSS_CTL_83_DATA 0x00000048 +#define DDRSS_CTL_84_DATA 0x0000017E +#define DDRSS_CTL_85_DATA 0x03004000 +#define DDRSS_CTL_86_DATA 0x00001201 +#define DDRSS_CTL_87_DATA 0x00060005 +#define DDRSS_CTL_88_DATA 0x00000006 +#define DDRSS_CTL_89_DATA 0x00000000 +#define DDRSS_CTL_90_DATA 0x05121208 +#define DDRSS_CTL_91_DATA 0x05030A05 +#define DDRSS_CTL_92_DATA 0x05030C06 +#define DDRSS_CTL_93_DATA 0x01030C06 +#define DDRSS_CTL_94_DATA 0x02010201 +#define DDRSS_CTL_95_DATA 0x00000A01 +#define DDRSS_CTL_96_DATA 0x0096000A +#define DDRSS_CTL_97_DATA 0x00960096 +#define DDRSS_CTL_98_DATA 0x00000096 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x05010303 +#define DDRSS_CTL_101_DATA 0x0C040505 +#define DDRSS_CTL_102_DATA 0x06050203 +#define DDRSS_CTL_103_DATA 0x030C0605 +#define DDRSS_CTL_104_DATA 0x05060502 +#define DDRSS_CTL_105_DATA 0x03030306 +#define DDRSS_CTL_106_DATA 0x03010000 +#define DDRSS_CTL_107_DATA 0x00010000 +#define DDRSS_CTL_108_DATA 0x00000000 +#define DDRSS_CTL_109_DATA 0x01000000 +#define DDRSS_CTL_110_DATA 0x80104002 +#define DDRSS_CTL_111_DATA 0x00040003 +#define DDRSS_CTL_112_DATA 0x00040005 +#define DDRSS_CTL_113_DATA 0x00030000 +#define DDRSS_CTL_114_DATA 0x00050004 +#define DDRSS_CTL_115_DATA 0x00000004 +#define DDRSS_CTL_116_DATA 0x00040003 +#define DDRSS_CTL_117_DATA 0x00040005 +#define DDRSS_CTL_118_DATA 0x00000000 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00030AC0 +#define DDRSS_CTL_127_DATA 0x00030AC0 +#define DDRSS_CTL_128_DATA 0x00030AC0 +#define DDRSS_CTL_129_DATA 0x00030AC0 +#define DDRSS_CTL_130_DATA 0x00030AC0 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000552D +#define DDRSS_CTL_133_DATA 0x00030AC0 +#define DDRSS_CTL_134_DATA 0x00030AC0 +#define DDRSS_CTL_135_DATA 0x00030AC0 +#define DDRSS_CTL_136_DATA 0x00030AC0 +#define DDRSS_CTL_137_DATA 0x00030AC0 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000552D +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x03050000 +#define DDRSS_CTL_157_DATA 0x03050305 +#define DDRSS_CTL_158_DATA 0x00000000 +#define DDRSS_CTL_159_DATA 0x08010000 +#define DDRSS_CTL_160_DATA 0x000E0808 +#define DDRSS_CTL_161_DATA 0x01000000 +#define DDRSS_CTL_162_DATA 0x0E080808 +#define DDRSS_CTL_163_DATA 0x00000000 +#define DDRSS_CTL_164_DATA 0x08080801 +#define DDRSS_CTL_165_DATA 0x0000080E +#define DDRSS_CTL_166_DATA 0x00040003 +#define DDRSS_CTL_167_DATA 0x00000007 +#define DDRSS_CTL_168_DATA 0x00000000 +#define DDRSS_CTL_169_DATA 0x00000000 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x01000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x00001500 +#define DDRSS_CTL_177_DATA 0x0000100E +#define DDRSS_CTL_178_DATA 0x00000002 +#define DDRSS_CTL_179_DATA 0x00000000 +#define DDRSS_CTL_180_DATA 0x00000001 +#define DDRSS_CTL_181_DATA 0x00000002 +#define DDRSS_CTL_182_DATA 0x00000C00 +#define DDRSS_CTL_183_DATA 0x00001000 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00001000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00001000 +#define DDRSS_CTL_188_DATA 0x00000000 +#define DDRSS_CTL_189_DATA 0x00000000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x0005000A +#define DDRSS_CTL_193_DATA 0x0404000D +#define DDRSS_CTL_194_DATA 0x0000000D +#define DDRSS_CTL_195_DATA 0x005000A0 +#define DDRSS_CTL_196_DATA 0x060600C8 +#define DDRSS_CTL_197_DATA 0x000000C8 +#define DDRSS_CTL_198_DATA 0x005000A0 +#define DDRSS_CTL_199_DATA 0x060600C8 +#define DDRSS_CTL_200_DATA 0x000000C8 +#define DDRSS_CTL_201_DATA 0x00000000 +#define DDRSS_CTL_202_DATA 0x00000000 +#define DDRSS_CTL_203_DATA 0x00000000 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000004 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000024 +#define DDRSS_CTL_209_DATA 0x00000012 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000024 +#define DDRSS_CTL_212_DATA 0x00000012 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000004 +#define DDRSS_CTL_215_DATA 0x00000000 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000024 +#define DDRSS_CTL_218_DATA 0x00000012 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000024 +#define DDRSS_CTL_221_DATA 0x00000012 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000000 +#define DDRSS_CTL_224_DATA 0x00000031 +#define DDRSS_CTL_225_DATA 0x000000B1 +#define DDRSS_CTL_226_DATA 0x000000B1 +#define DDRSS_CTL_227_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 +#define DDRSS_CTL_230_DATA 0x00000000 +#define DDRSS_CTL_231_DATA 0x00000000 +#define DDRSS_CTL_232_DATA 0x00000000 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x65006565 +#define DDRSS_CTL_255_DATA 0x00002765 +#define DDRSS_CTL_256_DATA 0x00000027 +#define DDRSS_CTL_257_DATA 0x00000027 +#define DDRSS_CTL_258_DATA 0x00000027 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000000 +#define DDRSS_CTL_262_DATA 0x00000000 +#define DDRSS_CTL_263_DATA 0x0000000F +#define DDRSS_CTL_264_DATA 0x0000000F +#define DDRSS_CTL_265_DATA 0x0000000F +#define DDRSS_CTL_266_DATA 0x0000000F +#define DDRSS_CTL_267_DATA 0x0000000F +#define DDRSS_CTL_268_DATA 0x0000000F +#define DDRSS_CTL_269_DATA 0x00000000 +#define DDRSS_CTL_270_DATA 0x00001000 +#define DDRSS_CTL_271_DATA 0x00000015 +#define DDRSS_CTL_272_DATA 0x00000015 +#define DDRSS_CTL_273_DATA 0x00000010 +#define DDRSS_CTL_274_DATA 0x00000015 +#define DDRSS_CTL_275_DATA 0x00000015 +#define DDRSS_CTL_276_DATA 0x00000020 +#define DDRSS_CTL_277_DATA 0x00010000 +#define DDRSS_CTL_278_DATA 0x00000100 +#define DDRSS_CTL_279_DATA 0x00000000 +#define DDRSS_CTL_280_DATA 0x00000000 +#define DDRSS_CTL_281_DATA 0x00000101 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000000 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x0C181511 +#define DDRSS_CTL_291_DATA 0x00000304 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x00000000 +#define DDRSS_CTL_297_DATA 0x00000000 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00020000 +#define DDRSS_CTL_306_DATA 0x00400100 +#define DDRSS_CTL_307_DATA 0x00080032 +#define DDRSS_CTL_308_DATA 0x01000200 +#define DDRSS_CTL_309_DATA 0x03200040 +#define DDRSS_CTL_310_DATA 0x00020018 +#define DDRSS_CTL_311_DATA 0x00400100 +#define DDRSS_CTL_312_DATA 0x00180320 +#define DDRSS_CTL_313_DATA 0x00030000 +#define DDRSS_CTL_314_DATA 0x00280028 +#define DDRSS_CTL_315_DATA 0x00000100 +#define DDRSS_CTL_316_DATA 0x01010000 +#define DDRSS_CTL_317_DATA 0x00000202 +#define DDRSS_CTL_318_DATA 0x0FFF0000 +#define DDRSS_CTL_319_DATA 0x000FFF00 +#define DDRSS_CTL_320_DATA 0xFFFFFFFF +#define DDRSS_CTL_321_DATA 0x00FFFF00 +#define DDRSS_CTL_322_DATA 0x0B000000 +#define DDRSS_CTL_323_DATA 0x0001FFFF +#define DDRSS_CTL_324_DATA 0x01010101 +#define DDRSS_CTL_325_DATA 0x01010101 +#define DDRSS_CTL_326_DATA 0x00000118 +#define DDRSS_CTL_327_DATA 0x00000C01 +#define DDRSS_CTL_328_DATA 0x01000100 +#define DDRSS_CTL_329_DATA 0x00000000 +#define DDRSS_CTL_330_DATA 0x00000000 +#define DDRSS_CTL_331_DATA 0x01030303 +#define DDRSS_CTL_332_DATA 0x00000001 +#define DDRSS_CTL_333_DATA 0x00000000 +#define DDRSS_CTL_334_DATA 0x00000000 +#define DDRSS_CTL_335_DATA 0x00000000 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x00000000 +#define DDRSS_CTL_339_DATA 0x00000000 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0x00000000 +#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00000000 +#define DDRSS_CTL_366_DATA 0x00000000 +#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x01000101 +#define DDRSS_CTL_372_DATA 0x01010001 +#define DDRSS_CTL_373_DATA 0x00010101 +#define DDRSS_CTL_374_DATA 0x01050503 +#define DDRSS_CTL_375_DATA 0x05020201 +#define DDRSS_CTL_376_DATA 0x08080C0C +#define DDRSS_CTL_377_DATA 0x00080308 +#define DDRSS_CTL_378_DATA 0x000B030E +#define DDRSS_CTL_379_DATA 0x000B0310 +#define DDRSS_CTL_380_DATA 0x0B0B0810 +#define DDRSS_CTL_381_DATA 0x01000000 +#define DDRSS_CTL_382_DATA 0x03020301 +#define DDRSS_CTL_383_DATA 0x04000102 +#define DDRSS_CTL_384_DATA 0x1B000004 +#define DDRSS_CTL_385_DATA 0x00000176 +#define DDRSS_CTL_386_DATA 0x00000200 +#define DDRSS_CTL_387_DATA 0x00000200 +#define DDRSS_CTL_388_DATA 0x00000200 +#define DDRSS_CTL_389_DATA 0x00000200 +#define DDRSS_CTL_390_DATA 0x00000693 +#define DDRSS_CTL_391_DATA 0x00000E9C +#define DDRSS_CTL_392_DATA 0x03050202 +#define DDRSS_CTL_393_DATA 0x00250201 +#define DDRSS_CTL_394_DATA 0x00001856 +#define DDRSS_CTL_395_DATA 0x00000200 +#define DDRSS_CTL_396_DATA 0x00000200 +#define DDRSS_CTL_397_DATA 0x00000200 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00006D83 +#define DDRSS_CTL_400_DATA 0x0000F35C +#define DDRSS_CTL_401_DATA 0x070D0402 +#define DDRSS_CTL_402_DATA 0x00250405 +#define DDRSS_CTL_403_DATA 0x00001856 +#define DDRSS_CTL_404_DATA 0x00000200 +#define DDRSS_CTL_405_DATA 0x00000200 +#define DDRSS_CTL_406_DATA 0x00000200 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00006D83 +#define DDRSS_CTL_409_DATA 0x0000F35C +#define DDRSS_CTL_410_DATA 0x070D0402 +#define DDRSS_CTL_411_DATA 0x00000405 +#define DDRSS_CTL_412_DATA 0x00000000 +#define DDRSS_CTL_413_DATA 0x0302000A +#define DDRSS_CTL_414_DATA 0x01000500 +#define DDRSS_CTL_415_DATA 0x01010001 +#define DDRSS_CTL_416_DATA 0x00010001 +#define DDRSS_CTL_417_DATA 0x01010001 +#define DDRSS_CTL_418_DATA 0x02010000 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x02000201 +#define DDRSS_CTL_421_DATA 0x10100600 +#define DDRSS_CTL_422_DATA 0x00202020 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x00010001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00010000 +#define DDRSS_PI_24_DATA 0x280A0001 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x00010000 +#define DDRSS_PI_27_DATA 0x00003200 +#define DDRSS_PI_28_DATA 0x00000000 +#define DDRSS_PI_29_DATA 0x00000000 +#define DDRSS_PI_30_DATA 0x01010102 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x00000000 +#define DDRSS_PI_34_DATA 0x00000001 +#define DDRSS_PI_35_DATA 0x000000AA +#define DDRSS_PI_36_DATA 0x00000055 +#define DDRSS_PI_37_DATA 0x000000B5 +#define DDRSS_PI_38_DATA 0x0000004A +#define DDRSS_PI_39_DATA 0x00000056 +#define DDRSS_PI_40_DATA 0x000000A9 +#define DDRSS_PI_41_DATA 0x000000A9 +#define DDRSS_PI_42_DATA 0x000000B5 +#define DDRSS_PI_43_DATA 0x00000000 +#define DDRSS_PI_44_DATA 0x00000000 +#define DDRSS_PI_45_DATA 0x00010100 +#define DDRSS_PI_46_DATA 0x00000015 +#define DDRSS_PI_47_DATA 0x000007D0 +#define DDRSS_PI_48_DATA 0x00000300 +#define DDRSS_PI_49_DATA 0x00000000 +#define DDRSS_PI_50_DATA 0x00000000 +#define DDRSS_PI_51_DATA 0x01000000 +#define DDRSS_PI_52_DATA 0x00010101 +#define DDRSS_PI_53_DATA 0x01000000 +#define DDRSS_PI_54_DATA 0x03000000 +#define DDRSS_PI_55_DATA 0x00000000 +#define DDRSS_PI_56_DATA 0x00001701 +#define DDRSS_PI_57_DATA 0x00000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00000000 +#define DDRSS_PI_60_DATA 0x0A0A140A +#define DDRSS_PI_61_DATA 0x10020101 +#define DDRSS_PI_62_DATA 0x01000210 +#define DDRSS_PI_63_DATA 0x05000404 +#define DDRSS_PI_64_DATA 0x00010001 +#define DDRSS_PI_65_DATA 0x0001000E +#define DDRSS_PI_66_DATA 0x01010100 +#define DDRSS_PI_67_DATA 0x00010000 +#define DDRSS_PI_68_DATA 0x00000034 +#define DDRSS_PI_69_DATA 0x00000000 +#define DDRSS_PI_70_DATA 0x00000000 +#define DDRSS_PI_71_DATA 0x0000FFFF +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x00000000 +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x01000000 +#define DDRSS_PI_77_DATA 0x08020100 +#define DDRSS_PI_78_DATA 0x00020000 +#define DDRSS_PI_79_DATA 0x00010002 +#define DDRSS_PI_80_DATA 0x00000001 +#define DDRSS_PI_81_DATA 0x00020001 +#define DDRSS_PI_82_DATA 0x00020002 +#define DDRSS_PI_83_DATA 0x00000000 +#define DDRSS_PI_84_DATA 0x00000000 +#define DDRSS_PI_85_DATA 0x00000000 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000400 +#define DDRSS_PI_92_DATA 0x0A090B0C +#define DDRSS_PI_93_DATA 0x04060708 +#define DDRSS_PI_94_DATA 0x01000005 +#define DDRSS_PI_95_DATA 0x00000800 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00010008 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x0000AA00 +#define DDRSS_PI_100_DATA 0x00000000 +#define DDRSS_PI_101_DATA 0x00010000 +#define DDRSS_PI_102_DATA 0x00000000 +#define DDRSS_PI_103_DATA 0x00000000 +#define DDRSS_PI_104_DATA 0x00000000 +#define DDRSS_PI_105_DATA 0x00000000 +#define DDRSS_PI_106_DATA 0x00000000 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x00000000 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00000000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000008 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00010000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x0000000A +#define DDRSS_PI_137_DATA 0x000186A0 +#define DDRSS_PI_138_DATA 0x00000100 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x01000000 +#define DDRSS_PI_145_DATA 0x00010003 +#define DDRSS_PI_146_DATA 0x02000101 +#define DDRSS_PI_147_DATA 0x01030001 +#define DDRSS_PI_148_DATA 0x00010400 +#define DDRSS_PI_149_DATA 0x06000105 +#define DDRSS_PI_150_DATA 0x01070001 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00010001 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x00000000 +#define DDRSS_PI_157_DATA 0x00000000 +#define DDRSS_PI_158_DATA 0x00000000 +#define DDRSS_PI_159_DATA 0x00010000 +#define DDRSS_PI_160_DATA 0x00000004 +#define DDRSS_PI_161_DATA 0x00000000 +#define DDRSS_PI_162_DATA 0x00000000 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000800 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00101001 +#define DDRSS_PI_167_DATA 0x00000034 +#define DDRSS_PI_168_DATA 0x00000042 +#define DDRSS_PI_169_DATA 0x00020042 +#define DDRSS_PI_170_DATA 0x02000200 +#define DDRSS_PI_171_DATA 0x00000004 +#define DDRSS_PI_172_DATA 0x0000080C +#define DDRSS_PI_173_DATA 0x00081C00 +#define DDRSS_PI_174_DATA 0x001C0000 +#define DDRSS_PI_175_DATA 0x00000009 +#define DDRSS_PI_176_DATA 0x000000BB +#define DDRSS_PI_177_DATA 0x00000090 +#define DDRSS_PI_178_DATA 0x00000C2B +#define DDRSS_PI_179_DATA 0x00000090 +#define DDRSS_PI_180_DATA 0x04000C2B +#define DDRSS_PI_181_DATA 0x01010404 +#define DDRSS_PI_182_DATA 0x00001501 +#define DDRSS_PI_183_DATA 0x001D001D +#define DDRSS_PI_184_DATA 0x01000100 +#define DDRSS_PI_185_DATA 0x00000100 +#define DDRSS_PI_186_DATA 0x00000000 +#define DDRSS_PI_187_DATA 0x05050503 +#define DDRSS_PI_188_DATA 0x01010C0C +#define DDRSS_PI_189_DATA 0x01010101 +#define DDRSS_PI_190_DATA 0x000C0C0A +#define DDRSS_PI_191_DATA 0x00000000 +#define DDRSS_PI_192_DATA 0x00000000 +#define DDRSS_PI_193_DATA 0x04000000 +#define DDRSS_PI_194_DATA 0x04020808 +#define DDRSS_PI_195_DATA 0x04040204 +#define DDRSS_PI_196_DATA 0x00090031 +#define DDRSS_PI_197_DATA 0x00110039 +#define DDRSS_PI_198_DATA 0x00110039 +#define DDRSS_PI_199_DATA 0x01010101 +#define DDRSS_PI_200_DATA 0x0002000D +#define DDRSS_PI_201_DATA 0x000200C8 +#define DDRSS_PI_202_DATA 0x010000C8 +#define DDRSS_PI_203_DATA 0x000E000E +#define DDRSS_PI_204_DATA 0x00C90100 +#define DDRSS_PI_205_DATA 0x010000C9 +#define DDRSS_PI_206_DATA 0x00C900C9 +#define DDRSS_PI_207_DATA 0x32103200 +#define DDRSS_PI_208_DATA 0x01013210 +#define DDRSS_PI_209_DATA 0x0A070601 +#define DDRSS_PI_210_DATA 0x0D09070D +#define DDRSS_PI_211_DATA 0x0D09070D +#define DDRSS_PI_212_DATA 0x000C000D +#define DDRSS_PI_213_DATA 0x00001000 +#define DDRSS_PI_214_DATA 0x00000C00 +#define DDRSS_PI_215_DATA 0x00001000 +#define DDRSS_PI_216_DATA 0x00000C00 +#define DDRSS_PI_217_DATA 0x02001000 +#define DDRSS_PI_218_DATA 0x0016000D +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x000000C8 +#define DDRSS_PI_221_DATA 0x00001900 +#define DDRSS_PI_222_DATA 0x32000056 +#define DDRSS_PI_223_DATA 0x06000101 +#define DDRSS_PI_224_DATA 0x001D0204 +#define DDRSS_PI_225_DATA 0x32120058 +#define DDRSS_PI_226_DATA 0x05000101 +#define DDRSS_PI_227_DATA 0x001D0408 +#define DDRSS_PI_228_DATA 0x32120058 +#define DDRSS_PI_229_DATA 0x05000101 +#define DDRSS_PI_230_DATA 0x00000408 +#define DDRSS_PI_231_DATA 0x05030900 +#define DDRSS_PI_232_DATA 0x00040900 +#define DDRSS_PI_233_DATA 0x0000062B +#define DDRSS_PI_234_DATA 0x20010004 +#define DDRSS_PI_235_DATA 0x0A0A0A03 +#define DDRSS_PI_236_DATA 0x11090000 +#define DDRSS_PI_237_DATA 0x1009000F +#define DDRSS_PI_238_DATA 0x000062B8 +#define DDRSS_PI_239_DATA 0x20030023 +#define DDRSS_PI_240_DATA 0x0C0A0C0C +#define DDRSS_PI_241_DATA 0x11090000 +#define DDRSS_PI_242_DATA 0x1009000F +#define DDRSS_PI_243_DATA 0x000062B8 +#define DDRSS_PI_244_DATA 0x20030023 +#define DDRSS_PI_245_DATA 0x0C0A0C0C +#define DDRSS_PI_246_DATA 0x00000000 +#define DDRSS_PI_247_DATA 0x00000176 +#define DDRSS_PI_248_DATA 0x00000E9C +#define DDRSS_PI_249_DATA 0x00001856 +#define DDRSS_PI_250_DATA 0x0000F35C +#define DDRSS_PI_251_DATA 0x00001856 +#define DDRSS_PI_252_DATA 0x0000F35C +#define DDRSS_PI_253_DATA 0x0096000A +#define DDRSS_PI_254_DATA 0x03030096 +#define DDRSS_PI_255_DATA 0x00000003 +#define DDRSS_PI_256_DATA 0x00000000 +#define DDRSS_PI_257_DATA 0x05030503 +#define DDRSS_PI_258_DATA 0x00000503 +#define DDRSS_PI_259_DATA 0x00002710 +#define DDRSS_PI_260_DATA 0x000186A0 +#define DDRSS_PI_261_DATA 0x00000005 +#define DDRSS_PI_262_DATA 0x00000064 +#define DDRSS_PI_263_DATA 0x0000000A +#define DDRSS_PI_264_DATA 0x00027100 +#define DDRSS_PI_265_DATA 0x000186A0 +#define DDRSS_PI_266_DATA 0x00000005 +#define DDRSS_PI_267_DATA 0x00000640 +#define DDRSS_PI_268_DATA 0x00000096 +#define DDRSS_PI_269_DATA 0x00027100 +#define DDRSS_PI_270_DATA 0x000186A0 +#define DDRSS_PI_271_DATA 0x00000005 +#define DDRSS_PI_272_DATA 0x00000640 +#define DDRSS_PI_273_DATA 0x01000096 +#define DDRSS_PI_274_DATA 0x00320040 +#define DDRSS_PI_275_DATA 0x00010008 +#define DDRSS_PI_276_DATA 0x03200040 +#define DDRSS_PI_277_DATA 0x00010018 +#define DDRSS_PI_278_DATA 0x03200040 +#define DDRSS_PI_279_DATA 0x00000318 +#define DDRSS_PI_280_DATA 0x00280028 +#define DDRSS_PI_281_DATA 0x03040404 +#define DDRSS_PI_282_DATA 0x00000303 +#define DDRSS_PI_283_DATA 0x02020101 +#define DDRSS_PI_284_DATA 0x67676767 +#define DDRSS_PI_285_DATA 0x00000000 +#define DDRSS_PI_286_DATA 0x55000000 +#define DDRSS_PI_287_DATA 0x00000000 +#define DDRSS_PI_288_DATA 0x3C00005A +#define DDRSS_PI_289_DATA 0x00005500 +#define DDRSS_PI_290_DATA 0x00005A00 +#define DDRSS_PI_291_DATA 0x0D100F3C +#define DDRSS_PI_292_DATA 0x0003020E +#define DDRSS_PI_293_DATA 0x00000001 +#define DDRSS_PI_294_DATA 0x01000000 +#define DDRSS_PI_295_DATA 0x00020201 +#define DDRSS_PI_296_DATA 0x00000000 +#define DDRSS_PI_297_DATA 0x00000000 +#define DDRSS_PI_298_DATA 0x00000004 +#define DDRSS_PI_299_DATA 0x00000000 +#define DDRSS_PI_300_DATA 0x00000031 +#define DDRSS_PI_301_DATA 0x00000000 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00100F27 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x00000024 +#define DDRSS_PI_307_DATA 0x00000012 +#define DDRSS_PI_308_DATA 0x000000B1 +#define DDRSS_PI_309_DATA 0x00000000 +#define DDRSS_PI_310_DATA 0x00000000 +#define DDRSS_PI_311_DATA 0x65000000 +#define DDRSS_PI_312_DATA 0x00150F27 +#define DDRSS_PI_313_DATA 0x00000000 +#define DDRSS_PI_314_DATA 0x00000024 +#define DDRSS_PI_315_DATA 0x00000012 +#define DDRSS_PI_316_DATA 0x000000B1 +#define DDRSS_PI_317_DATA 0x00000000 +#define DDRSS_PI_318_DATA 0x00000000 +#define DDRSS_PI_319_DATA 0x65000000 +#define DDRSS_PI_320_DATA 0x00150F27 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000004 +#define DDRSS_PI_323_DATA 0x00000000 +#define DDRSS_PI_324_DATA 0x00000031 +#define DDRSS_PI_325_DATA 0x00000000 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00100F27 +#define DDRSS_PI_329_DATA 0x00000000 +#define DDRSS_PI_330_DATA 0x00000024 +#define DDRSS_PI_331_DATA 0x00000012 +#define DDRSS_PI_332_DATA 0x000000B1 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x65000000 +#define DDRSS_PI_336_DATA 0x00150F27 +#define DDRSS_PI_337_DATA 0x00000000 +#define DDRSS_PI_338_DATA 0x00000024 +#define DDRSS_PI_339_DATA 0x00000012 +#define DDRSS_PI_340_DATA 0x000000B1 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x00000000 +#define DDRSS_PI_343_DATA 0x65000000 +#define DDRSS_PI_344_DATA 0x00150F27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01000000 +#define DDRSS_PHY_6_DATA 0x03000400 +#define DDRSS_PHY_7_DATA 0x00000001 +#define DDRSS_PHY_8_DATA 0x00000001 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x01010000 +#define DDRSS_PHY_12_DATA 0x00010000 +#define DDRSS_PHY_13_DATA 0x00C00001 +#define DDRSS_PHY_14_DATA 0x00CC0008 +#define DDRSS_PHY_15_DATA 0x00660601 +#define DDRSS_PHY_16_DATA 0x00000003 +#define DDRSS_PHY_17_DATA 0x00000000 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x0000AAAA +#define DDRSS_PHY_20_DATA 0x00005555 +#define DDRSS_PHY_21_DATA 0x0000B5B5 +#define DDRSS_PHY_22_DATA 0x00004A4A +#define DDRSS_PHY_23_DATA 0x00005656 +#define DDRSS_PHY_24_DATA 0x0000A9A9 +#define DDRSS_PHY_25_DATA 0x0000B7B7 +#define DDRSS_PHY_26_DATA 0x00004848 +#define DDRSS_PHY_27_DATA 0x00000000 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x08000000 +#define DDRSS_PHY_30_DATA 0x0F000008 +#define DDRSS_PHY_31_DATA 0x00000F0F +#define DDRSS_PHY_32_DATA 0x00E4E400 +#define DDRSS_PHY_33_DATA 0x00071020 +#define DDRSS_PHY_34_DATA 0x000C0020 +#define DDRSS_PHY_35_DATA 0x00062000 +#define DDRSS_PHY_36_DATA 0x00000000 +#define DDRSS_PHY_37_DATA 0x55555555 +#define DDRSS_PHY_38_DATA 0xAAAAAAAA +#define DDRSS_PHY_39_DATA 0x55555555 +#define DDRSS_PHY_40_DATA 0xAAAAAAAA +#define DDRSS_PHY_41_DATA 0x00005555 +#define DDRSS_PHY_42_DATA 0x01000100 +#define DDRSS_PHY_43_DATA 0x00800180 +#define DDRSS_PHY_44_DATA 0x00000000 +#define DDRSS_PHY_45_DATA 0x00000000 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000004 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000000 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x041F07FF +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x01CC0B01 +#define DDRSS_PHY_75_DATA 0x1003CC0B +#define DDRSS_PHY_76_DATA 0x20000140 +#define DDRSS_PHY_77_DATA 0x07FF0200 +#define DDRSS_PHY_78_DATA 0x0000DD01 +#define DDRSS_PHY_79_DATA 0x00100303 +#define DDRSS_PHY_80_DATA 0x00000000 +#define DDRSS_PHY_81_DATA 0x00000000 +#define DDRSS_PHY_82_DATA 0x00021000 +#define DDRSS_PHY_83_DATA 0x00100010 +#define DDRSS_PHY_84_DATA 0x00100010 +#define DDRSS_PHY_85_DATA 0x00100010 +#define DDRSS_PHY_86_DATA 0x00100010 +#define DDRSS_PHY_87_DATA 0x02020010 +#define DDRSS_PHY_88_DATA 0x51516041 +#define DDRSS_PHY_89_DATA 0x31C06000 +#define DDRSS_PHY_90_DATA 0x07AB0340 +#define DDRSS_PHY_91_DATA 0x0000C0C0 +#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_93_DATA 0x00000504 +#define DDRSS_PHY_94_DATA 0x42100010 +#define DDRSS_PHY_95_DATA 0x010C053E +#define DDRSS_PHY_96_DATA 0x000F0C1D +#define DDRSS_PHY_97_DATA 0x01000140 +#define DDRSS_PHY_98_DATA 0x007A0120 +#define DDRSS_PHY_99_DATA 0x00000C00 +#define DDRSS_PHY_100_DATA 0x000001CC +#define DDRSS_PHY_101_DATA 0x20100200 +#define DDRSS_PHY_102_DATA 0x00000005 +#define DDRSS_PHY_103_DATA 0x56743210 +#define DDRSS_PHY_104_DATA 0x00000008 +#define DDRSS_PHY_105_DATA 0x034C034C +#define DDRSS_PHY_106_DATA 0x034C034C +#define DDRSS_PHY_107_DATA 0x034C034C +#define DDRSS_PHY_108_DATA 0x034C034C +#define DDRSS_PHY_109_DATA 0x0000034C +#define DDRSS_PHY_110_DATA 0x00008000 +#define DDRSS_PHY_111_DATA 0x00800080 +#define DDRSS_PHY_112_DATA 0x00800080 +#define DDRSS_PHY_113_DATA 0x00800080 +#define DDRSS_PHY_114_DATA 0x00800080 +#define DDRSS_PHY_115_DATA 0x00800080 +#define DDRSS_PHY_116_DATA 0x00800080 +#define DDRSS_PHY_117_DATA 0x00800080 +#define DDRSS_PHY_118_DATA 0x00800080 +#define DDRSS_PHY_119_DATA 0x01800080 +#define DDRSS_PHY_120_DATA 0x01000000 +#define DDRSS_PHY_121_DATA 0x00000000 +#define DDRSS_PHY_122_DATA 0x00000000 +#define DDRSS_PHY_123_DATA 0x00080200 +#define DDRSS_PHY_124_DATA 0x00000000 +#define DDRSS_PHY_125_DATA 0x0000F0F0 +#define DDRSS_PHY_126_DATA 0x00000000 +#define DDRSS_PHY_127_DATA 0x00000000 +#define DDRSS_PHY_128_DATA 0x00000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00000000 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x00000000 +#define DDRSS_PHY_134_DATA 0x00000000 +#define DDRSS_PHY_135_DATA 0x00000000 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01000000 +#define DDRSS_PHY_262_DATA 0x03000400 +#define DDRSS_PHY_263_DATA 0x00000001 +#define DDRSS_PHY_264_DATA 0x00000001 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x01010000 +#define DDRSS_PHY_268_DATA 0x00010000 +#define DDRSS_PHY_269_DATA 0x00C00001 +#define DDRSS_PHY_270_DATA 0x00CC0008 +#define DDRSS_PHY_271_DATA 0x00660601 +#define DDRSS_PHY_272_DATA 0x00000003 +#define DDRSS_PHY_273_DATA 0x00000000 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x0000AAAA +#define DDRSS_PHY_276_DATA 0x00005555 +#define DDRSS_PHY_277_DATA 0x0000B5B5 +#define DDRSS_PHY_278_DATA 0x00004A4A +#define DDRSS_PHY_279_DATA 0x00005656 +#define DDRSS_PHY_280_DATA 0x0000A9A9 +#define DDRSS_PHY_281_DATA 0x0000B7B7 +#define DDRSS_PHY_282_DATA 0x00004848 +#define DDRSS_PHY_283_DATA 0x00000000 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x08000000 +#define DDRSS_PHY_286_DATA 0x0F000008 +#define DDRSS_PHY_287_DATA 0x00000F0F +#define DDRSS_PHY_288_DATA 0x00E4E400 +#define DDRSS_PHY_289_DATA 0x00071020 +#define DDRSS_PHY_290_DATA 0x000C0020 +#define DDRSS_PHY_291_DATA 0x00062000 +#define DDRSS_PHY_292_DATA 0x00000000 +#define DDRSS_PHY_293_DATA 0x55555555 +#define DDRSS_PHY_294_DATA 0xAAAAAAAA +#define DDRSS_PHY_295_DATA 0x55555555 +#define DDRSS_PHY_296_DATA 0xAAAAAAAA +#define DDRSS_PHY_297_DATA 0x00005555 +#define DDRSS_PHY_298_DATA 0x01000100 +#define DDRSS_PHY_299_DATA 0x00800180 +#define DDRSS_PHY_300_DATA 0x00000001 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000004 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000000 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x041F07FF +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x01CC0B01 +#define DDRSS_PHY_331_DATA 0x1003CC0B +#define DDRSS_PHY_332_DATA 0x20000140 +#define DDRSS_PHY_333_DATA 0x07FF0200 +#define DDRSS_PHY_334_DATA 0x0000DD01 +#define DDRSS_PHY_335_DATA 0x00100303 +#define DDRSS_PHY_336_DATA 0x00000000 +#define DDRSS_PHY_337_DATA 0x00000000 +#define DDRSS_PHY_338_DATA 0x00021000 +#define DDRSS_PHY_339_DATA 0x00100010 +#define DDRSS_PHY_340_DATA 0x00100010 +#define DDRSS_PHY_341_DATA 0x00100010 +#define DDRSS_PHY_342_DATA 0x00100010 +#define DDRSS_PHY_343_DATA 0x02020010 +#define DDRSS_PHY_344_DATA 0x51516041 +#define DDRSS_PHY_345_DATA 0x31C06000 +#define DDRSS_PHY_346_DATA 0x07AB0340 +#define DDRSS_PHY_347_DATA 0x0000C0C0 +#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_349_DATA 0x00000504 +#define DDRSS_PHY_350_DATA 0x42100010 +#define DDRSS_PHY_351_DATA 0x010C053E +#define DDRSS_PHY_352_DATA 0x000F0C1D +#define DDRSS_PHY_353_DATA 0x01000140 +#define DDRSS_PHY_354_DATA 0x007A0120 +#define DDRSS_PHY_355_DATA 0x00000C00 +#define DDRSS_PHY_356_DATA 0x000001CC +#define DDRSS_PHY_357_DATA 0x20100200 +#define DDRSS_PHY_358_DATA 0x00000005 +#define DDRSS_PHY_359_DATA 0x01324567 +#define DDRSS_PHY_360_DATA 0x00000008 +#define DDRSS_PHY_361_DATA 0x034C034C +#define DDRSS_PHY_362_DATA 0x034C034C +#define DDRSS_PHY_363_DATA 0x034C034C +#define DDRSS_PHY_364_DATA 0x034C034C +#define DDRSS_PHY_365_DATA 0x0000034C +#define DDRSS_PHY_366_DATA 0x00008000 +#define DDRSS_PHY_367_DATA 0x00800080 +#define DDRSS_PHY_368_DATA 0x00800080 +#define DDRSS_PHY_369_DATA 0x00800080 +#define DDRSS_PHY_370_DATA 0x00800080 +#define DDRSS_PHY_371_DATA 0x00800080 +#define DDRSS_PHY_372_DATA 0x00800080 +#define DDRSS_PHY_373_DATA 0x00800080 +#define DDRSS_PHY_374_DATA 0x00800080 +#define DDRSS_PHY_375_DATA 0x01800080 +#define DDRSS_PHY_376_DATA 0x01000000 +#define DDRSS_PHY_377_DATA 0x00000000 +#define DDRSS_PHY_378_DATA 0x00000000 +#define DDRSS_PHY_379_DATA 0x00080200 +#define DDRSS_PHY_380_DATA 0x00000000 +#define DDRSS_PHY_381_DATA 0x0000F0F0 +#define DDRSS_PHY_382_DATA 0x00000000 +#define DDRSS_PHY_383_DATA 0x00000000 +#define DDRSS_PHY_384_DATA 0x00000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00000000 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x00000000 +#define DDRSS_PHY_390_DATA 0x00000000 +#define DDRSS_PHY_391_DATA 0x00000000 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x00000000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00000000 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x00000100 +#define DDRSS_PHY_518_DATA 0x00000200 +#define DDRSS_PHY_519_DATA 0x00000000 +#define DDRSS_PHY_520_DATA 0x00000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00400000 +#define DDRSS_PHY_524_DATA 0x00000080 +#define DDRSS_PHY_525_DATA 0x00DCBA98 +#define DDRSS_PHY_526_DATA 0x03000000 +#define DDRSS_PHY_527_DATA 0x00200000 +#define DDRSS_PHY_528_DATA 0x00000000 +#define DDRSS_PHY_529_DATA 0x00000000 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000000 +#define DDRSS_PHY_532_DATA 0x0000002A +#define DDRSS_PHY_533_DATA 0x00000015 +#define DDRSS_PHY_534_DATA 0x00000015 +#define DDRSS_PHY_535_DATA 0x0000002A +#define DDRSS_PHY_536_DATA 0x00000033 +#define DDRSS_PHY_537_DATA 0x0000000C +#define DDRSS_PHY_538_DATA 0x0000000C +#define DDRSS_PHY_539_DATA 0x00000033 +#define DDRSS_PHY_540_DATA 0x0A418820 +#define DDRSS_PHY_541_DATA 0x003F0000 +#define DDRSS_PHY_542_DATA 0x000F013F +#define DDRSS_PHY_543_DATA 0x0000000F +#define DDRSS_PHY_544_DATA 0x020002CC +#define DDRSS_PHY_545_DATA 0x00030000 +#define DDRSS_PHY_546_DATA 0x00000300 +#define DDRSS_PHY_547_DATA 0x00000300 +#define DDRSS_PHY_548_DATA 0x00000300 +#define DDRSS_PHY_549_DATA 0x00000300 +#define DDRSS_PHY_550_DATA 0x00000300 +#define DDRSS_PHY_551_DATA 0x42080010 +#define DDRSS_PHY_552_DATA 0x0000803E +#define DDRSS_PHY_553_DATA 0x00000003 +#define DDRSS_PHY_554_DATA 0x00000002 +#define DDRSS_PHY_555_DATA 0x00000000 +#define DDRSS_PHY_556_DATA 0x00000000 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000000 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x00000000 +#define DDRSS_PHY_587_DATA 0x00000000 +#define DDRSS_PHY_588_DATA 0x00000000 +#define DDRSS_PHY_589_DATA 0x00000000 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x00000000 +#define DDRSS_PHY_592_DATA 0x00000000 +#define DDRSS_PHY_593_DATA 0x00000000 +#define DDRSS_PHY_594_DATA 0x00000000 +#define DDRSS_PHY_595_DATA 0x00000000 +#define DDRSS_PHY_596_DATA 0x00000000 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00000000 +#define DDRSS_PHY_600_DATA 0x00000000 +#define DDRSS_PHY_601_DATA 0x00000000 +#define DDRSS_PHY_602_DATA 0x00000000 +#define DDRSS_PHY_603_DATA 0x00000000 +#define DDRSS_PHY_604_DATA 0x00000000 +#define DDRSS_PHY_605_DATA 0x00000000 +#define DDRSS_PHY_606_DATA 0x00000000 +#define DDRSS_PHY_607_DATA 0x00000000 +#define DDRSS_PHY_608_DATA 0x00000000 +#define DDRSS_PHY_609_DATA 0x00000000 +#define DDRSS_PHY_610_DATA 0x00000000 +#define DDRSS_PHY_611_DATA 0x00000000 +#define DDRSS_PHY_612_DATA 0x00000000 +#define DDRSS_PHY_613_DATA 0x00000000 +#define DDRSS_PHY_614_DATA 0x00000000 +#define DDRSS_PHY_615_DATA 0x00000000 +#define DDRSS_PHY_616_DATA 0x00000000 +#define DDRSS_PHY_617_DATA 0x00000000 +#define DDRSS_PHY_618_DATA 0x00000000 +#define DDRSS_PHY_619_DATA 0x00000000 +#define DDRSS_PHY_620_DATA 0x00000000 +#define DDRSS_PHY_621_DATA 0x00000000 +#define DDRSS_PHY_622_DATA 0x00000000 +#define DDRSS_PHY_623_DATA 0x00000000 +#define DDRSS_PHY_624_DATA 0x00000000 +#define DDRSS_PHY_625_DATA 0x00000000 +#define DDRSS_PHY_626_DATA 0x00000000 +#define DDRSS_PHY_627_DATA 0x00000000 +#define DDRSS_PHY_628_DATA 0x00000000 +#define DDRSS_PHY_629_DATA 0x00000000 +#define DDRSS_PHY_630_DATA 0x00000000 +#define DDRSS_PHY_631_DATA 0x00000000 +#define DDRSS_PHY_632_DATA 0x00000000 +#define DDRSS_PHY_633_DATA 0x00000000 +#define DDRSS_PHY_634_DATA 0x00000000 +#define DDRSS_PHY_635_DATA 0x00000000 +#define DDRSS_PHY_636_DATA 0x00000000 +#define DDRSS_PHY_637_DATA 0x00000000 +#define DDRSS_PHY_638_DATA 0x00000000 +#define DDRSS_PHY_639_DATA 0x00000000 +#define DDRSS_PHY_640_DATA 0x00000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00000000 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x00000000 +#define DDRSS_PHY_646_DATA 0x00000000 +#define DDRSS_PHY_647_DATA 0x00000000 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x00000000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00000000 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x00000100 +#define DDRSS_PHY_774_DATA 0x00000200 +#define DDRSS_PHY_775_DATA 0x00000000 +#define DDRSS_PHY_776_DATA 0x00000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00400000 +#define DDRSS_PHY_780_DATA 0x00000080 +#define DDRSS_PHY_781_DATA 0x00DCBA98 +#define DDRSS_PHY_782_DATA 0x03000000 +#define DDRSS_PHY_783_DATA 0x00200000 +#define DDRSS_PHY_784_DATA 0x00000000 +#define DDRSS_PHY_785_DATA 0x00000000 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000000 +#define DDRSS_PHY_788_DATA 0x0000002A +#define DDRSS_PHY_789_DATA 0x00000015 +#define DDRSS_PHY_790_DATA 0x00000015 +#define DDRSS_PHY_791_DATA 0x0000002A +#define DDRSS_PHY_792_DATA 0x00000033 +#define DDRSS_PHY_793_DATA 0x0000000C +#define DDRSS_PHY_794_DATA 0x0000000C +#define DDRSS_PHY_795_DATA 0x00000033 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x000F0000 +#define DDRSS_PHY_799_DATA 0x0000000F +#define DDRSS_PHY_800_DATA 0x020002CC +#define DDRSS_PHY_801_DATA 0x00030000 +#define DDRSS_PHY_802_DATA 0x00000300 +#define DDRSS_PHY_803_DATA 0x00000300 +#define DDRSS_PHY_804_DATA 0x00000300 +#define DDRSS_PHY_805_DATA 0x00000300 +#define DDRSS_PHY_806_DATA 0x00000300 +#define DDRSS_PHY_807_DATA 0x42080010 +#define DDRSS_PHY_808_DATA 0x0000803E +#define DDRSS_PHY_809_DATA 0x00000003 +#define DDRSS_PHY_810_DATA 0x00000002 +#define DDRSS_PHY_811_DATA 0x00000000 +#define DDRSS_PHY_812_DATA 0x00000000 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000000 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x00000000 +#define DDRSS_PHY_843_DATA 0x00000000 +#define DDRSS_PHY_844_DATA 0x00000000 +#define DDRSS_PHY_845_DATA 0x00000000 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x00000000 +#define DDRSS_PHY_848_DATA 0x00000000 +#define DDRSS_PHY_849_DATA 0x00000000 +#define DDRSS_PHY_850_DATA 0x00000000 +#define DDRSS_PHY_851_DATA 0x00000000 +#define DDRSS_PHY_852_DATA 0x00000000 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00000000 +#define DDRSS_PHY_856_DATA 0x00000000 +#define DDRSS_PHY_857_DATA 0x00000000 +#define DDRSS_PHY_858_DATA 0x00000000 +#define DDRSS_PHY_859_DATA 0x00000000 +#define DDRSS_PHY_860_DATA 0x00000000 +#define DDRSS_PHY_861_DATA 0x00000000 +#define DDRSS_PHY_862_DATA 0x00000000 +#define DDRSS_PHY_863_DATA 0x00000000 +#define DDRSS_PHY_864_DATA 0x00000000 +#define DDRSS_PHY_865_DATA 0x00000000 +#define DDRSS_PHY_866_DATA 0x00000000 +#define DDRSS_PHY_867_DATA 0x00000000 +#define DDRSS_PHY_868_DATA 0x00000000 +#define DDRSS_PHY_869_DATA 0x00000000 +#define DDRSS_PHY_870_DATA 0x00000000 +#define DDRSS_PHY_871_DATA 0x00000000 +#define DDRSS_PHY_872_DATA 0x00000000 +#define DDRSS_PHY_873_DATA 0x00000000 +#define DDRSS_PHY_874_DATA 0x00000000 +#define DDRSS_PHY_875_DATA 0x00000000 +#define DDRSS_PHY_876_DATA 0x00000000 +#define DDRSS_PHY_877_DATA 0x00000000 +#define DDRSS_PHY_878_DATA 0x00000000 +#define DDRSS_PHY_879_DATA 0x00000000 +#define DDRSS_PHY_880_DATA 0x00000000 +#define DDRSS_PHY_881_DATA 0x00000000 +#define DDRSS_PHY_882_DATA 0x00000000 +#define DDRSS_PHY_883_DATA 0x00000000 +#define DDRSS_PHY_884_DATA 0x00000000 +#define DDRSS_PHY_885_DATA 0x00000000 +#define DDRSS_PHY_886_DATA 0x00000000 +#define DDRSS_PHY_887_DATA 0x00000000 +#define DDRSS_PHY_888_DATA 0x00000000 +#define DDRSS_PHY_889_DATA 0x00000000 +#define DDRSS_PHY_890_DATA 0x00000000 +#define DDRSS_PHY_891_DATA 0x00000000 +#define DDRSS_PHY_892_DATA 0x00000000 +#define DDRSS_PHY_893_DATA 0x00000000 +#define DDRSS_PHY_894_DATA 0x00000000 +#define DDRSS_PHY_895_DATA 0x00000000 +#define DDRSS_PHY_896_DATA 0x00000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00000000 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x00000000 +#define DDRSS_PHY_902_DATA 0x00000000 +#define DDRSS_PHY_903_DATA 0x00000000 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x0000002A +#define DDRSS_PHY_1045_DATA 0x00000015 +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x0000002A +#define DDRSS_PHY_1048_DATA 0x00000033 +#define DDRSS_PHY_1049_DATA 0x0000000C +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x00000033 +#define DDRSS_PHY_1052_DATA 0x2307B9AC +#define DDRSS_PHY_1053_DATA 0x10000000 +#define DDRSS_PHY_1054_DATA 0x000F0000 +#define DDRSS_PHY_1055_DATA 0x0000000F +#define DDRSS_PHY_1056_DATA 0x020002CC +#define DDRSS_PHY_1057_DATA 0x00030000 +#define DDRSS_PHY_1058_DATA 0x00000300 +#define DDRSS_PHY_1059_DATA 0x00000300 +#define DDRSS_PHY_1060_DATA 0x00000300 +#define DDRSS_PHY_1061_DATA 0x00000300 +#define DDRSS_PHY_1062_DATA 0x00000300 +#define DDRSS_PHY_1063_DATA 0x42080010 +#define DDRSS_PHY_1064_DATA 0x0000803E +#define DDRSS_PHY_1065_DATA 0x00000003 +#define DDRSS_PHY_1066_DATA 0x00000002 +#define DDRSS_PHY_1067_DATA 0x00000000 +#define DDRSS_PHY_1068_DATA 0x00000000 +#define DDRSS_PHY_1069_DATA 0x00000000 +#define DDRSS_PHY_1070_DATA 0x00000000 +#define DDRSS_PHY_1071_DATA 0x00000000 +#define DDRSS_PHY_1072_DATA 0x00000000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00010100 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000000 +#define DDRSS_PHY_1286_DATA 0x00050000 +#define DDRSS_PHY_1287_DATA 0x04000000 +#define DDRSS_PHY_1288_DATA 0x00000055 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00000000 +#define DDRSS_PHY_1292_DATA 0x00000000 +#define DDRSS_PHY_1293_DATA 0x00002001 +#define DDRSS_PHY_1294_DATA 0x00004001 +#define DDRSS_PHY_1295_DATA 0x00020028 +#define DDRSS_PHY_1296_DATA 0x01010100 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x0F0F0E06 +#define DDRSS_PHY_1300_DATA 0x00010101 +#define DDRSS_PHY_1301_DATA 0x010F0004 +#define DDRSS_PHY_1302_DATA 0x00000000 +#define DDRSS_PHY_1303_DATA 0x00000000 +#define DDRSS_PHY_1304_DATA 0x00000064 +#define DDRSS_PHY_1305_DATA 0x00000000 +#define DDRSS_PHY_1306_DATA 0x00000000 +#define DDRSS_PHY_1307_DATA 0x01020103 +#define DDRSS_PHY_1308_DATA 0x0F020102 +#define DDRSS_PHY_1309_DATA 0x03030303 +#define DDRSS_PHY_1310_DATA 0x03030303 +#define DDRSS_PHY_1311_DATA 0x00041B42 +#define DDRSS_PHY_1312_DATA 0x00005201 +#define DDRSS_PHY_1313_DATA 0x00000000 +#define DDRSS_PHY_1314_DATA 0x00000000 +#define DDRSS_PHY_1315_DATA 0x00000000 +#define DDRSS_PHY_1316_DATA 0x00000000 +#define DDRSS_PHY_1317_DATA 0x00000000 +#define DDRSS_PHY_1318_DATA 0x00000000 +#define DDRSS_PHY_1319_DATA 0x07030101 +#define DDRSS_PHY_1320_DATA 0x00005400 +#define DDRSS_PHY_1321_DATA 0x000040A2 +#define DDRSS_PHY_1322_DATA 0x00024410 +#define DDRSS_PHY_1323_DATA 0x00004410 +#define DDRSS_PHY_1324_DATA 0x00004410 +#define DDRSS_PHY_1325_DATA 0x00004410 +#define DDRSS_PHY_1326_DATA 0x00004410 +#define DDRSS_PHY_1327_DATA 0x00004410 +#define DDRSS_PHY_1328_DATA 0x00004410 +#define DDRSS_PHY_1329_DATA 0x00004410 +#define DDRSS_PHY_1330_DATA 0x00004410 +#define DDRSS_PHY_1331_DATA 0x00004410 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000076 +#define DDRSS_PHY_1334_DATA 0x00000400 +#define DDRSS_PHY_1335_DATA 0x00000008 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x03000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x04102006 +#define DDRSS_PHY_1346_DATA 0x00041020 +#define DDRSS_PHY_1347_DATA 0x01C98C98 +#define DDRSS_PHY_1348_DATA 0x3F400000 +#define DDRSS_PHY_1349_DATA 0x3F3F1F3F +#define DDRSS_PHY_1350_DATA 0x0000001F +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000001 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x76543201 +#define DDRSS_PHY_1360_DATA 0x00040198 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00040700 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000002 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x0001F7C2 +#define DDRSS_PHY_1372_DATA 0x00020002 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00001142 +#define DDRSS_PHY_1375_DATA 0x03020000 +#define DDRSS_PHY_1376_DATA 0x00000080 +#define DDRSS_PHY_1377_DATA 0x03900390 +#define DDRSS_PHY_1378_DATA 0x03900390 +#define DDRSS_PHY_1379_DATA 0x03900390 +#define DDRSS_PHY_1380_DATA 0x03900390 +#define DDRSS_PHY_1381_DATA 0x03000300 +#define DDRSS_PHY_1382_DATA 0x03000300 +#define DDRSS_PHY_1383_DATA 0x00000300 +#define DDRSS_PHY_1384_DATA 0x00000300 +#define DDRSS_PHY_1385_DATA 0x00000300 +#define DDRSS_PHY_1386_DATA 0x00000300 +#define DDRSS_PHY_1387_DATA 0x3183BF77 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x0C000DFF +#define DDRSS_PHY_1390_DATA 0x30000DFF +#define DDRSS_PHY_1391_DATA 0x3F0DFF11 +#define DDRSS_PHY_1392_DATA 0x01990000 +#define DDRSS_PHY_1393_DATA 0x780DFFCC +#define DDRSS_PHY_1394_DATA 0x00000C11 +#define DDRSS_PHY_1395_DATA 0x00018011 +#define DDRSS_PHY_1396_DATA 0x0089FF00 +#define DDRSS_PHY_1397_DATA 0x000C3F11 +#define DDRSS_PHY_1398_DATA 0x01990000 +#define DDRSS_PHY_1399_DATA 0x000C3F91 +#define DDRSS_PHY_1400_DATA 0x01990000 +#define DDRSS_PHY_1401_DATA 0x3F0DFF11 +#define DDRSS_PHY_1402_DATA 0x01990000 +#define DDRSS_PHY_1403_DATA 0x00018011 +#define DDRSS_PHY_1404_DATA 0x0089FF00 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am6254atl-sk-u-boot.dtsi b/arch/arm/dts/k3-am6254atl-sk-u-boot.dtsi new file mode 100644 index 00000000000..d9cf2464691 --- /dev/null +++ b/arch/arm/dts/k3-am6254atl-sk-u-boot.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common AM6254atl SK dts file for SPLs + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am625-sk-u-boot.dtsi" + +#ifdef CONFIG_TARGET_AM625_A53_EVM + +#define SPL_AM6254ATL_SK_DTB "spl/dts/ti/k3-am6254atl-sk.dtb" + +&spl_am625_sk_dtb { + filename = SPL_AM6254ATL_SK_DTB; +}; + +&spl_am625_sk_dtb_unsigned { + filename = SPL_AM6254ATL_SK_DTB; +}; + +#endif diff --git a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi index 9bcdf74ffe4..a284226320c 100644 --- a/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi +++ b/arch/arm/dts/k3-am62a-phycore-som-binman.dtsi @@ -101,43 +101,6 @@ }; }; -&binman { - tiboot3-am62ax-gp-phycore-som.bin { - filename = "tiboot3-am62ax-gp-phycore-som.bin"; - ti-secure-rom { - content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, - <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; - combined; - dm-data; - content-sbl = <&u_boot_spl_unsigned>; - load = <CONFIG_SPL_TEXT_BASE>; - content-sysfw = <&ti_fs_gp>; - load-sysfw = <0x40000>; - content-sysfw-data = <&combined_tifs_cfg_gp>; - load-sysfw-data = <0x67000>; - content-dm-data = <&combined_dm_cfg_gp>; - load-dm-data = <0x43c3a800>; - sw-rev = <1>; - keyfile = "ti-degenerate-key.pem"; - }; - u_boot_spl_unsigned: u-boot-spl { - no-expanded; - }; - ti_fs_gp: ti-fs-gp.bin { - filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; - type = "blob-ext"; - }; - combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { - filename = "combined-tifs-cfg.bin"; - type = "blob-ext"; - }; - combined_dm_cfg_gp: combined-dm-cfg-gp.bin { - filename = "combined-dm-cfg.bin"; - type = "blob-ext"; - }; - }; -}; - #include "k3-binman-capsule-r5.dtsi" &capsule_tiboot3 { @@ -197,23 +160,6 @@ }; - tifsstub-gp { - filename = "tifsstub.bin_gp"; - ti-secure-rom { - content = <&tifsstub_gp>; - core = "secure"; - load = <0x60000>; - sw-rev = <CONFIG_K3_X509_SWRV>; - keyfile = "ti-degenerate-key.pem"; - tifsstub; - }; - tifsstub_gp: tifsstub-gp.bin { - filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin"; - type = "blob-ext"; - optional; - }; - }; - ti-spl { insert-template = <&ti_spl_template>; @@ -245,18 +191,6 @@ }; }; - tifsstub-gp { - description = "TIFSSTUB"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-gp"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_gp"; - }; - }; dm { ti-secure { content = <&dm>; @@ -289,7 +223,7 @@ description = "k3-am62a7-phyboard-lyra-rdk"; firmware = "atf"; loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; + "tifsstub-hs", "tifsstub-fs"; fdt = "fdt-0"; }; }; @@ -403,120 +337,6 @@ }; }; -&binman { - ti-spl_unsigned { - insert-template = <&ti_spl_unsigned_template>; - - fit { - images { - tifsstub-hs { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-hs"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_hs"; - }; - }; - - tifsstub-fs { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-fs"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_fs"; - }; - }; - - tifsstub-gp { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-gp"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_gp"; - }; - }; - dm { - ti-dm { - filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; - }; - }; - - fdt-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - spl_am62a7_phyboard_lyra_dtb_unsigned: blob { - filename = SPL_AM62A7_PHYBOARD_LYRA_DTB; - }; - }; - }; - - configurations { - default = "conf-0"; - - conf-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; - firmware = "atf"; - loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; - fdt = "fdt-0"; - }; - }; - }; - }; -}; - -&binman { - u-boot_unsigned { - insert-template = <&u_boot_unsigned_template>; - - fit { - images { - uboot { - description = "U-Boot for AM62Ax board"; - }; - - fdt-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - blob { - filename = AM62A7_PHYBOARD_LYRA_DTB; - }; - hash { - algo = "crc32"; - }; - }; - }; - - configurations { - default = "conf-0"; - - conf-0 { - description = "k3-am62a7-phyboard-lyra-rdk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-0"; - }; - }; - }; - }; -}; - #include "k3-binman-capsule.dtsi" &capsule_tispl { diff --git a/arch/arm/dts/k3-am62a-sk-binman.dtsi b/arch/arm/dts/k3-am62a-sk-binman.dtsi index 0685bdd7e0c..cb9a56b8c37 100644 --- a/arch/arm/dts/k3-am62a-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62a-sk-binman.dtsi @@ -5,7 +5,7 @@ #include "k3-binman.dtsi" -#ifdef CONFIG_TARGET_AM62A7_R5_EVM +#if defined(CONFIG_TARGET_AM62A7_R5_EVM) || defined(CONFIG_TARGET_AM62D2_R5_EVM) &rcfg_yaml_tifs { config = "tifs-rm-cfg.yaml"; @@ -98,46 +98,9 @@ }; }; -&binman { - tiboot3-am62ax-gp-evm.bin { - filename = "tiboot3-am62ax-gp-evm.bin"; - ti-secure-rom { - content = <&u_boot_spl_unsigned>, <&ti_fs_gp>, - <&combined_tifs_cfg_gp>, <&combined_dm_cfg_gp>; - combined; - dm-data; - content-sbl = <&u_boot_spl_unsigned>; - load = <CONFIG_SPL_TEXT_BASE>; - content-sysfw = <&ti_fs_gp>; - load-sysfw = <0x40000>; - content-sysfw-data = <&combined_tifs_cfg_gp>; - load-sysfw-data = <0x67000>; - content-dm-data = <&combined_dm_cfg_gp>; - load-dm-data = <0x43c3a800>; - sw-rev = <1>; - keyfile = "ti-degenerate-key.pem"; - }; - u_boot_spl_unsigned: u-boot-spl { - no-expanded; - }; - ti_fs_gp: ti-fs-gp.bin { - filename = "ti-sysfw/ti-fs-firmware-am62ax-gp.bin"; - type = "blob-ext"; - }; - combined_tifs_cfg_gp: combined-tifs-cfg-gp.bin { - filename = "combined-tifs-cfg.bin"; - type = "blob-ext"; - }; - combined_dm_cfg_gp: combined-dm-cfg-gp.bin { - filename = "combined-dm-cfg.bin"; - type = "blob-ext"; - }; - }; -}; - #endif -#ifdef CONFIG_TARGET_AM62A7_A53_EVM +#if defined(CONFIG_TARGET_AM62A7_A53_EVM) || defined(CONFIG_TARGET_AM62D2_A53_EVM) #define SPL_AM62A7_SK_DTB "spl/dts/ti/k3-am62a7-sk.dtb" #define AM62A7_SK_DTB "u-boot.dtb" @@ -181,25 +144,8 @@ }; - tifsstub-gp { - filename = "tifsstub.bin_gp"; - ti-secure-rom { - content = <&tifsstub_gp>; - core = "secure"; - load = <0x60000>; - sw-rev = <CONFIG_K3_X509_SWRV>; - keyfile = "ti-degenerate-key.pem"; - tifsstub; - }; - tifsstub_gp: tifsstub-gp.bin { - filename = "ti-sysfw/ti-fs-stub-firmware-am62ax-gp.bin"; - type = "blob-ext"; - optional; - }; - }; - - ti-spl { - insert-template = <&ti_spl_template>; + ti-falcon { + insert-template = <&ti_falcon_template>; fit { images { @@ -215,7 +161,6 @@ filename = "tifsstub.bin_hs"; }; }; - tifsstub-fs { description = "TIFSSTUB"; type = "firmware"; @@ -228,112 +173,35 @@ filename = "tifsstub.bin_fs"; }; }; - - tifsstub-gp { - description = "TIFSSTUB"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-gp"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_gp"; - }; - }; dm { ti-secure { - content = <&dm>; + content = <&dm_falcon>; keyfile = "custMpk.pem"; }; - dm: ti-dm { + dm_falcon: ti-dm { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; - - fdt-0 { - description = "k3-am62a7-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&spl_am62a7_sk_dtb>; - keyfile = "custMpk.pem"; - }; - spl_am62a7_sk_dtb: blob-ext { - filename = SPL_AM62A7_SK_DTB; - }; - - }; - }; configurations { default = "conf-0"; - conf-0 { - description = "k3-am62a7-sk"; + description = "k3-am62a7-sk-falcon"; firmware = "atf"; - loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; - fdt = "fdt-0"; + loadables = "tee", "dm", "tifsstub-hs", "tifsstub-fs"; }; }; }; }; -}; -&binman { - u-boot { - insert-template = <&u_boot_template>; - - fit { - images { - uboot { - description = "U-Boot for AM62Ax Board"; - }; - - fdt-0 { - description = "k3-am62a7-sk"; - type = "flat_dt"; - arch = "arm"; - compression = "none"; - ti-secure { - content = <&am62a7_sk_dtb>; - keyfile = "custMpk.pem"; - }; - am62a7_sk_dtb: blob-ext { - filename = AM62A7_SK_DTB; - }; - hash { - algo = "crc32"; - }; - }; - }; - - configurations { - default = "conf-0"; - - conf-0 { - description = "k3-am62a7-sk"; - firmware = "uboot"; - loadables = "uboot"; - fdt = "fdt-0"; - }; - - }; - }; - }; -}; - -&binman { - ti-spl_unsigned { - insert-template = <&ti_spl_unsigned_template>; + ti-spl { + insert-template = <&ti_spl_template>; fit { images { tifsstub-hs { - description = "tifsstub"; + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; @@ -346,7 +214,7 @@ }; tifsstub-fs { - description = "tifsstub"; + description = "TIFSSTUB"; type = "firmware"; arch = "arm32"; compression = "none"; @@ -358,43 +226,41 @@ }; }; - tifsstub-gp { - description = "tifsstub"; - type = "firmware"; - arch = "arm32"; - compression = "none"; - os = "tifsstub-gp"; - load = <0x9ca00000>; - entry = <0x9ca00000>; - blob-ext { - filename = "tifsstub.bin_gp"; - }; - }; dm { - ti-dm { + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + dm: ti-dm { filename = "ti-dm/am62axx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; }; }; - fdt-0 { + ti_spl_fdt_0: fdt-0 { description = "k3-am62a7-sk"; type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + ti-secure { + content = <&spl_am62a7_sk_dtb>; + keyfile = "custMpk.pem"; + }; + spl_am62a7_sk_dtb: blob-ext { filename = SPL_AM62A7_SK_DTB; }; + }; + }; configurations { default = "conf-0"; - conf-0 { + ti_spl_conf_0: conf-0 { description = "k3-am62a7-sk"; firmware = "atf"; loadables = "tee", "dm", "spl", - "tifsstub-hs", "tifsstub-fs", "tifsstub-gp"; + "tifsstub-hs", "tifsstub-fs"; fdt = "fdt-0"; }; }; @@ -403,8 +269,8 @@ }; &binman { - u-boot_unsigned { - insert-template = <&u_boot_unsigned_template>; + u-boot { + insert-template = <&u_boot_template>; fit { images { @@ -412,12 +278,16 @@ description = "U-Boot for AM62Ax Board"; }; - fdt-0 { + u_boot_fdt_0: fdt-0 { description = "k3-am62a7-sk"; type = "flat_dt"; arch = "arm"; compression = "none"; - blob { + ti-secure { + content = <&am62a7_sk_dtb>; + keyfile = "custMpk.pem"; + }; + am62a7_sk_dtb: blob-ext { filename = AM62A7_SK_DTB; }; hash { @@ -429,14 +299,16 @@ configurations { default = "conf-0"; - conf-0 { + u_boot_conf_0: conf-0 { description = "k3-am62a7-sk"; firmware = "uboot"; loadables = "uboot"; fdt = "fdt-0"; }; + }; }; }; }; + #endif diff --git a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi index 73255a18e9b..8afd844460a 100644 --- a/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am62a7-phyboard-lyra-rdk-u-boot.dtsi @@ -156,6 +156,22 @@ bootph-all; }; +&main_rti1 { + status = "disabled"; +}; + +&main_rti2 { + status = "disabled"; +}; + +&main_rti3 { + status = "disabled"; +}; + +&main_rti4 { + status = "disabled"; +}; + &main_uart0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts index 63b7864a469..96860e80e9a 100644 --- a/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am62a7-r5-phycore-som-2gb.dts @@ -70,7 +70,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am62a7-r5-sk.dts b/arch/arm/dts/k3-am62a7-r5-sk.dts index 49e62533a95..64923c2c710 100644 --- a/arch/arm/dts/k3-am62a7-r5-sk.dts +++ b/arch/arm/dts/k3-am62a7-r5-sk.dts @@ -63,7 +63,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>; diff --git a/arch/arm/dts/k3-am62d-ddr-1866mhz-32bit.dtsi b/arch/arm/dts/k3-am62d-ddr-1866mhz-32bit.dtsi new file mode 100644 index 00000000000..2493e9bad69 --- /dev/null +++ b/arch/arm/dts/k3-am62d-ddr-1866mhz-32bit.dtsi @@ -0,0 +1,2802 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62Dx SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, + * AM62Px, AM62Dx, AM62Lx v0.10.32 + * Tue May 13 2025 19:31:24 GMT+0530 (India Standard Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1866MHz + * Density (per channel): 16Gb + * Number of Ranks: 1 + */ + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 933000000 +#define DDRSS_PLL_FREQUENCY_2 933000000 +#define DDRSS_SDRAM_IDX 16 +#define DDRSS_REGION_IDX 17 +#define DDRSS_TOOL_VERSION "0.10.32" + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0005B18F +#define DDRSS_CTL_12_DATA 0x0038EF90 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000E94 +#define DDRSS_CTL_15_DATA 0x0005B18F +#define DDRSS_CTL_16_DATA 0x0038EF90 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000E94 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004B4B +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00001040 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00001040 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000700 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000303 +#define DDRSS_CTL_50_DATA 0x00720014 +#define DDRSS_CTL_51_DATA 0x09140050 +#define DDRSS_CTL_52_DATA 0x00004D22 +#define DDRSS_CTL_53_DATA 0x00720014 +#define DDRSS_CTL_54_DATA 0x09140050 +#define DDRSS_CTL_55_DATA 0x09004D22 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040006DB +#define DDRSS_CTL_58_DATA 0x090F2005 +#define DDRSS_CTL_59_DATA 0x00001B13 +#define DDRSS_CTL_60_DATA 0x0E00FFCD +#define DDRSS_CTL_61_DATA 0x090F200F +#define DDRSS_CTL_62_DATA 0x00001B13 +#define DDRSS_CTL_63_DATA 0x0E00FFCD +#define DDRSS_CTL_64_DATA 0x0304200F +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x24232423 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x04464607 +#define DDRSS_CTL_69_DATA 0x03282803 +#define DDRSS_CTL_70_DATA 0x00002828 +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x00130803 +#define DDRSS_CTL_75_DATA 0x000000BB +#define DDRSS_CTL_76_DATA 0x000002C5 +#define DDRSS_CTL_77_DATA 0x00001C64 +#define DDRSS_CTL_78_DATA 0x000002C5 +#define DDRSS_CTL_79_DATA 0x00001C64 +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x0000000A +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x00000163 +#define DDRSS_CTL_84_DATA 0x00000386 +#define DDRSS_CTL_85_DATA 0x00000163 +#define DDRSS_CTL_86_DATA 0x00000386 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000E0005 +#define DDRSS_CTL_90_DATA 0x2608000E +#define DDRSS_CTL_91_DATA 0x0A050526 +#define DDRSS_CTL_92_DATA 0x1B0E0A03 +#define DDRSS_CTL_93_DATA 0x1B0E0A04 +#define DDRSS_CTL_94_DATA 0x04010104 +#define DDRSS_CTL_95_DATA 0x00010401 +#define DDRSS_CTL_96_DATA 0x00140014 +#define DDRSS_CTL_97_DATA 0x02D302D3 +#define DDRSS_CTL_98_DATA 0x02D302D3 +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x04041C04 +#define DDRSS_CTL_103_DATA 0x0E0A0E0A +#define DDRSS_CTL_104_DATA 0x0A04041C +#define DDRSS_CTL_105_DATA 0x030E0A0E +#define DDRSS_CTL_106_DATA 0x00000404 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00071900 +#define DDRSS_CTL_127_DATA 0x00071900 +#define DDRSS_CTL_128_DATA 0x00071900 +#define DDRSS_CTL_129_DATA 0x00071900 +#define DDRSS_CTL_130_DATA 0x00071900 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000C6BC +#define DDRSS_CTL_133_DATA 0x00071900 +#define DDRSS_CTL_134_DATA 0x00071900 +#define DDRSS_CTL_135_DATA 0x00071900 +#define DDRSS_CTL_136_DATA 0x00071900 +#define DDRSS_CTL_137_DATA 0x00071900 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000C6BC +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x040A040A +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x08010000 +#define DDRSS_CTL_162_DATA 0x000E0808 +#define DDRSS_CTL_163_DATA 0x01000000 +#define DDRSS_CTL_164_DATA 0x0E080808 +#define DDRSS_CTL_165_DATA 0x00000000 +#define DDRSS_CTL_166_DATA 0x08080801 +#define DDRSS_CTL_167_DATA 0x0000080E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00BB0176 +#define DDRSS_CTL_199_DATA 0x0E0E01D3 +#define DDRSS_CTL_200_DATA 0x000001D3 +#define DDRSS_CTL_201_DATA 0x00BB0176 +#define DDRSS_CTL_202_DATA 0x0E0E01D3 +#define DDRSS_CTL_203_DATA 0x000001D3 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000004 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000064 +#define DDRSS_CTL_212_DATA 0x00000036 +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000064 +#define DDRSS_CTL_215_DATA 0x00000036 +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000004 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000064 +#define DDRSS_CTL_221_DATA 0x00000036 +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000064 +#define DDRSS_CTL_224_DATA 0x00000036 +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 +#define DDRSS_CTL_230_DATA 0x00000031 +#define DDRSS_CTL_231_DATA 0x000000B1 +#define DDRSS_CTL_232_DATA 0x000000B1 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x35003535 +#define DDRSS_CTL_258_DATA 0x00002735 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000002B +#define DDRSS_CTL_267_DATA 0x0000002B +#define DDRSS_CTL_268_DATA 0x0000002B +#define DDRSS_CTL_269_DATA 0x0000002B +#define DDRSS_CTL_270_DATA 0x0000002B +#define DDRSS_CTL_271_DATA 0x0000002B +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000016 +#define DDRSS_CTL_275_DATA 0x00000016 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00000016 +#define DDRSS_CTL_278_DATA 0x00000016 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x074A0040 +#define DDRSS_CTL_316_DATA 0x00020038 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x0038074A +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x005E005E +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000000 +#define DDRSS_CTL_324_DATA 0x3FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0xFFFFFFFF +#define DDRSS_CTL_327_DATA 0x00FFFF00 +#define DDRSS_CTL_328_DATA 0x0B000000 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C01 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x7FFFFFFF +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0xFFFFFFFF +#define DDRSS_CTL_361_DATA 0xFFFF0000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0xFFFFFFFF +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00FFFFFF +#define DDRSS_CTL_366_DATA 0xFFFF00FF +#define DDRSS_CTL_367_DATA 0x0000FFFF +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01090903 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0E081B1B +#define DDRSS_CTL_389_DATA 0x0008040E +#define DDRSS_CTL_390_DATA 0x0B0C0406 +#define DDRSS_CTL_391_DATA 0x0B0C0406 +#define DDRSS_CTL_392_DATA 0x0C0C0806 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x07030701 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x00000176 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000693 +#define DDRSS_CTL_403_DATA 0x00000E9C +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x37200404 +#define DDRSS_CTL_406_DATA 0x000038C8 +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x0000FF84 +#define DDRSS_CTL_412_DATA 0x000237D0 +#define DDRSS_CTL_413_DATA 0x111A0402 +#define DDRSS_CTL_414_DATA 0x37200C09 +#define DDRSS_CTL_415_DATA 0x000038C8 +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x0000FF84 +#define DDRSS_CTL_421_DATA 0x000237D0 +#define DDRSS_CTL_422_DATA 0x111A0402 +#define DDRSS_CTL_423_DATA 0x00200C09 +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00002222 +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x00050001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x05000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x00050500 +#define DDRSS_PI_49_DATA 0x0000001A +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00001705 +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010500 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x00010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F10 +#define DDRSS_PI_101_DATA 0x080A1413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x01180118 +#define DDRSS_PI_178_DATA 0x00262601 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x0000005E +#define DDRSS_PI_181_DATA 0x0002005E +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x0000100C +#define DDRSS_PI_185_DATA 0x00104000 +#define DDRSS_PI_186_DATA 0x00400000 +#define DDRSS_PI_187_DATA 0x00000013 +#define DDRSS_PI_188_DATA 0x000000BB +#define DDRSS_PI_189_DATA 0x000002C5 +#define DDRSS_PI_190_DATA 0x00001C64 +#define DDRSS_PI_191_DATA 0x000002C5 +#define DDRSS_PI_192_DATA 0x04001C64 +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00270027 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05090903 +#define DDRSS_PI_200_DATA 0x01011B1B +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0C021212 +#define DDRSS_PI_207_DATA 0x0404020C +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x001B0043 +#define DDRSS_PI_210_DATA 0x001B0043 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x000301D3 +#define DDRSS_PI_214_DATA 0x010001D3 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01D40100 +#define DDRSS_PI_217_DATA 0x010001D4 +#define DDRSS_PI_218_DATA 0x01D401D4 +#define DDRSS_PI_219_DATA 0x301B3200 +#define DDRSS_PI_220_DATA 0x0101301B +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x1C11090D +#define DDRSS_PI_223_DATA 0x1C110913 +#define DDRSS_PI_224_DATA 0x000C0013 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x0021000D +#define DDRSS_PI_231_DATA 0x002101D3 +#define DDRSS_PI_232_DATA 0x000001D3 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000101 +#define DDRSS_PI_236_DATA 0x00250204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x17000101 +#define DDRSS_PI_239_DATA 0x00250C12 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x17000101 +#define DDRSS_PI_242_DATA 0x00000C12 +#define DDRSS_PI_243_DATA 0x05030900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x0000062B +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x280F0000 +#define DDRSS_PI_249_DATA 0x24090023 +#define DDRSS_PI_250_DATA 0x0000E638 +#define DDRSS_PI_251_DATA 0x20070050 +#define DDRSS_PI_252_DATA 0x1B131B1C +#define DDRSS_PI_253_DATA 0x280F0000 +#define DDRSS_PI_254_DATA 0x24090023 +#define DDRSS_PI_255_DATA 0x0000E638 +#define DDRSS_PI_256_DATA 0x20070050 +#define DDRSS_PI_257_DATA 0x1B131B1C +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x00000176 +#define DDRSS_PI_260_DATA 0x00000E9C +#define DDRSS_PI_261_DATA 0x000038C8 +#define DDRSS_PI_262_DATA 0x000237D0 +#define DDRSS_PI_263_DATA 0x000038C8 +#define DDRSS_PI_264_DATA 0x000237D0 +#define DDRSS_PI_265_DATA 0x02D30014 +#define DDRSS_PI_266_DATA 0x030302D3 +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x0A040503 +#define DDRSS_PI_270_DATA 0x00000A04 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x00000014 +#define DDRSS_PI_276_DATA 0x0005B18F +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000E94 +#define DDRSS_PI_280_DATA 0x000002D3 +#define DDRSS_PI_281_DATA 0x0005B18F +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000E94 +#define DDRSS_PI_285_DATA 0x010002D3 +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x074A0040 +#define DDRSS_PI_289_DATA 0x00010038 +#define DDRSS_PI_290_DATA 0x074A0040 +#define DDRSS_PI_291_DATA 0x00000338 +#define DDRSS_PI_292_DATA 0x0028005D +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13121118 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000004 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000031 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x20002B27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000064 +#define DDRSS_PI_338_DATA 0x00000036 +#define DDRSS_PI_339_DATA 0x000000B1 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x35000000 +#define DDRSS_PI_343_DATA 0x20162B27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x00000064 +#define DDRSS_PI_346_DATA 0x00000036 +#define DDRSS_PI_347_DATA 0x000000B1 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x35000000 +#define DDRSS_PI_351_DATA 0x20162B27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000004 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000031 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x00000000 +#define DDRSS_PI_359_DATA 0x20002B27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x00000064 +#define DDRSS_PI_362_DATA 0x00000036 +#define DDRSS_PI_363_DATA 0x000000B1 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x35000000 +#define DDRSS_PI_367_DATA 0x20162B27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x00000064 +#define DDRSS_PI_370_DATA 0x00000036 +#define DDRSS_PI_371_DATA 0x000000B1 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x35000000 +#define DDRSS_PI_375_DATA 0x20162B27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000004 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000031 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x00000000 +#define DDRSS_PI_383_DATA 0x20002B27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x00000064 +#define DDRSS_PI_386_DATA 0x00000036 +#define DDRSS_PI_387_DATA 0x000000B1 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x35000000 +#define DDRSS_PI_391_DATA 0x20162B27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x00000064 +#define DDRSS_PI_394_DATA 0x00000036 +#define DDRSS_PI_395_DATA 0x000000B1 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x35000000 +#define DDRSS_PI_399_DATA 0x20162B27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000004 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000031 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x00000000 +#define DDRSS_PI_407_DATA 0x20002B27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x00000064 +#define DDRSS_PI_410_DATA 0x00000036 +#define DDRSS_PI_411_DATA 0x000000B1 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x35000000 +#define DDRSS_PI_415_DATA 0x20162B27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x00000064 +#define DDRSS_PI_418_DATA 0x00000036 +#define DDRSS_PI_419_DATA 0x000000B1 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x35000000 +#define DDRSS_PI_423_DATA 0x20162B27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000001 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071020 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000104 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0C01 +#define DDRSS_PHY_80_DATA 0x1003CC0C +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00041000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02000010 +#define DDRSS_PHY_93_DATA 0x00000005 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0D000000 +#define DDRSS_PHY_99_DATA 0x000D0C0C +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C32 +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x011E0120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x000002DD +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000D2010 +#define DDRSS_PHY_111_DATA 0x76543210 +#define DDRSS_PHY_112_DATA 0x00000008 +#define DDRSS_PHY_113_DATA 0x045D045D +#define DDRSS_PHY_114_DATA 0x045D045D +#define DDRSS_PHY_115_DATA 0x045D045D +#define DDRSS_PHY_116_DATA 0x045D045D +#define DDRSS_PHY_117_DATA 0x0000045D +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x00B200A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000001 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071020 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000104 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0C01 +#define DDRSS_PHY_336_DATA 0x1003CC0C +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00041000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02000010 +#define DDRSS_PHY_349_DATA 0x00000005 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0D000000 +#define DDRSS_PHY_355_DATA 0x000D0C0C +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C32 +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x011E0120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x000002DD +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000D2010 +#define DDRSS_PHY_367_DATA 0x76543210 +#define DDRSS_PHY_368_DATA 0x00000008 +#define DDRSS_PHY_369_DATA 0x045D045D +#define DDRSS_PHY_370_DATA 0x045D045D +#define DDRSS_PHY_371_DATA 0x045D045D +#define DDRSS_PHY_372_DATA 0x045D045D +#define DDRSS_PHY_373_DATA 0x0000045D +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x00B200A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000001 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071020 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000001 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000104 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0C01 +#define DDRSS_PHY_592_DATA 0x1003CC0C +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00041000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02000010 +#define DDRSS_PHY_605_DATA 0x00000005 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0D000000 +#define DDRSS_PHY_611_DATA 0x000D0C0C +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C32 +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x011E0120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x000002DD +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000D2010 +#define DDRSS_PHY_623_DATA 0x76543210 +#define DDRSS_PHY_624_DATA 0x00000008 +#define DDRSS_PHY_625_DATA 0x045D045D +#define DDRSS_PHY_626_DATA 0x045D045D +#define DDRSS_PHY_627_DATA 0x045D045D +#define DDRSS_PHY_628_DATA 0x045D045D +#define DDRSS_PHY_629_DATA 0x0000045D +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x00B200A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000001 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071020 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000000 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000104 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0C01 +#define DDRSS_PHY_848_DATA 0x1003CC0C +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00041000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02000010 +#define DDRSS_PHY_861_DATA 0x00000005 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0D000000 +#define DDRSS_PHY_867_DATA 0x000D0C0C +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C32 +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x011E0120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x000002DD +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000D2010 +#define DDRSS_PHY_879_DATA 0x76543210 +#define DDRSS_PHY_880_DATA 0x00000008 +#define DDRSS_PHY_881_DATA 0x045D045D +#define DDRSS_PHY_882_DATA 0x045D045D +#define DDRSS_PHY_883_DATA 0x045D045D +#define DDRSS_PHY_884_DATA 0x045D045D +#define DDRSS_PHY_885_DATA 0x0000045D +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x00B200A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000405CC +#define DDRSS_PHY_1062_DATA 0x03000004 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000405CC +#define DDRSS_PHY_1318_DATA 0x03000004 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000405CC +#define DDRSS_PHY_1574_DATA 0x03000004 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F01 +#define DDRSS_PHY_1822_DATA 0x0F0F0F02 +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x0F0F0804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76543210 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C4 +#define DDRSS_PHY_1889_DATA 0x04000004 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000005 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F91 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040006 diff --git a/arch/arm/dts/k3-am62d-evm-binman.dtsi b/arch/arm/dts/k3-am62d-evm-binman.dtsi new file mode 100644 index 00000000000..7bf0e955645 --- /dev/null +++ b/arch/arm/dts/k3-am62d-evm-binman.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-binman.dtsi" +#include "k3-am62a-sk-binman.dtsi" + +#ifdef CONFIG_TARGET_AM62D2_R5_EVM + +&bcfg_yaml { + config = "board/ti/am62ax/board-cfg.yaml"; +}; + +&rcfg_yaml { + config = "board/ti/am62ax/rm-cfg.yaml"; +}; + +&scfg_yaml { + config = "board/ti/am62ax/sec-cfg.yaml"; +}; + +&pcfg_yaml { + config = "board/ti/am62ax/pm-cfg.yaml"; +}; + +&bcfg_yaml_tifs { + config = "board/ti/am62ax/board-cfg.yaml"; +}; + +&scfg_yaml_tifs { + config = "board/ti/am62ax/sec-cfg.yaml"; +}; + +&pcfg_yaml_tifs { + config = "board/ti/am62ax/pm-cfg.yaml"; +}; + +&rcfg_yaml_tifs { + config = "board/ti/am62ax/tifs-rm-cfg.yaml"; +}; + +&pcfg_yaml_dm { + config = "board/ti/am62ax/pm-cfg.yaml"; +}; + +&rcfg_yaml_dm { + config = "board/ti/am62ax/rm-cfg.yaml"; +}; + +&bcfg_yaml_sysfw { + config = "board/ti/am62ax/board-cfg.yaml"; +}; + +&scfg_yaml_sysfw { + config = "board/ti/am62ax/sec-cfg.yaml"; +}; + +&pcfg_yaml_sysfw { + config = "board/ti/am62ax/pm-cfg.yaml"; +}; + +&rcfg_yaml_sysfw { + config = "board/ti/am62ax/rm-cfg.yaml"; +}; + +#endif + +#ifdef CONFIG_TARGET_AM62D2_A53_EVM + +&ti_spl_fdt_0 { + description = "k3-am62d2-evm"; + + ti-secure { + content = <&spl_am62a7_sk_dtb>; + keyfile = "custMpk.pem"; + }; + + spl_am62d2_evm_dtb: blob-ext { + filename = "spl/dts/ti/k3-am62d2-evm.dtb"; + }; +}; + +&ti_spl_conf_0 { + description = "k3-am62d2-evm"; +}; + +&u_boot_fdt_0 { + description = "k3-am62d2-evm"; + + ti-secure { + content = <&am62d2_evm_dtb>; + keyfile = "custMpk.pem"; + }; + am62d2_evm_dtb: blob-ext { + filename = AM62A7_SK_DTB; + }; +}; + +&u_boot_conf_0 { + description = "k3-am62d2-evm"; +}; + +#endif diff --git a/arch/arm/dts/k3-am62d2-evm-u-boot.dtsi b/arch/arm/dts/k3-am62d2-evm-u-boot.dtsi new file mode 100644 index 00000000000..bddcfa6770c --- /dev/null +++ b/arch/arm/dts/k3-am62d2-evm-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common AM62D EVM dts file for SPLs + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62d-evm-binman.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; +}; diff --git a/arch/arm/dts/k3-am62d2-r5-evm.dts b/arch/arm/dts/k3-am62d2-r5-evm.dts new file mode 100644 index 00000000000..a3213d00145 --- /dev/null +++ b/arch/arm/dts/k3-am62d2-r5-evm.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AM62D2 EVM dts file for R5 SPL + * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include "k3-am62d2-evm.dts" +#include "k3-am62d-ddr-1866mhz-32bit.dtsi" +#include "k3-am62a-ddr.dtsi" + +#include "k3-am62d2-evm-u-boot.dtsi" + +/ { + aliases { + tick-timer = &main_timer0; + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + assigned-clock-parents = <&k3_clks 61 2>; + assigned-clock-rates = <200000000>, <1200000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-pre-ram; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 22>, + <&secure_proxy_main 23>; + bootph-pre-ram; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&secure_proxy_sa3 { + /* Needed for initial handshake with ROM */ + status = "okay"; + bootph-pre-ram; +}; + +&cbass_main { + sysctrler: sysctrler { + compatible = "ti,am654-tisci-rproc-r5"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&secure_proxy_sa3 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-pre-ram; + }; +}; + +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/k3-am62p-sk-binman.dtsi b/arch/arm/dts/k3-am62p-sk-binman.dtsi index feb59edcd83..e1443d6226b 100644 --- a/arch/arm/dts/k3-am62p-sk-binman.dtsi +++ b/arch/arm/dts/k3-am62p-sk-binman.dtsi @@ -161,6 +161,57 @@ }; + ti-falcon { + insert-template = <&ti_falcon_template>; + + fit { + images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + dm { + ti-secure { + content = <&dm_falcon>; + keyfile = "custMpk.pem"; + }; + dm_falcon: ti-dm { + filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + }; + }; + }; + + configurations { + default = "conf-0"; + conf-0 { + description = "k3-am62p5-sk-falcon"; + firmware = "atf"; + loadables = "tee", "dm", "tifsstub-hs", "tifsstub-fs"; + }; + }; + }; + }; + ti-spl { insert-template = <&ti_spl_template>; diff --git a/arch/arm/dts/k3-am62p-verdin-dev.dtsi b/arch/arm/dts/k3-am62p-verdin-dev.dtsi deleted file mode 100644 index 4cf38226077..00000000000 --- a/arch/arm/dts/k3-am62p-verdin-dev.dtsi +++ /dev/null @@ -1,243 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2025 Toradex - * - * Common dtsi for Verdin AM62P SoM on Development carrier board - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p - * https://www.toradex.com/products/carrier-board/verdin-development-board-kit - */ - -/ { - aliases { - eeprom1 = &carrier_eeprom; - }; - - sound { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&codec_dai>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&codec_dai>; - simple-audio-card,mclk-fs = <256>; - simple-audio-card,name = "verdin-nau8822"; - simple-audio-card,routing = - "Headphones", "LHP", - "Headphones", "RHP", - "Speaker", "LSPK", - "Speaker", "RSPK", - "Line Out", "AUXOUT1", - "Line Out", "AUXOUT2", - "LAUX", "Line In", - "RAUX", "Line In", - "LMICP", "Mic In", - "RMICP", "Mic In"; - simple-audio-card,widgets = - "Headphones", "Headphones", - "Line Out", "Line Out", - "Speaker", "Speaker", - "Microphone", "Mic In", - "Line", "Line In"; - - codec_dai: simple-audio-card,codec { - sound-dai = <&nau8822_1a>; - }; - - simple-audio-card,cpu { - sound-dai = <&mcasp0>; - }; - }; -}; - -/* Verdin ETHs */ -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; - status = "okay"; -}; - -/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ -&cpsw3g_mdio { - status = "okay"; - - carrier_eth_phy: ethernet-phy@7 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth2_rgmii_int>; - interrupt-parent = <&main_gpio0>; - interrupts = <42 IRQ_TYPE_EDGE_FALLING>; - micrel,led-mode = <0>; - }; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&cpsw_port1 { - status = "okay"; -}; - -/* Verdin ETH_2_RGMII */ -&cpsw_port2 { - phy-handle = <&carrier_eth_phy>; - phy-mode = "rgmii-rxid"; - status = "okay"; -}; - -/* Verdin PWM_3_DSI */ -&epwm0 { - status = "okay"; -}; - -/* Verdin PWM_1, PWM_2 */ -&epwm2 { - status = "okay"; -}; - -&main_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_1_reset>, - <&pinctrl_gpio_5>, - <&pinctrl_gpio_6>, - <&pinctrl_gpio_7>, - <&pinctrl_gpio_8>; -}; - -/* Verdin I2C_1 */ -&main_i2c0 { - status = "okay"; - - nau8822_1a: audio-codec@1a { - compatible = "nuvoton,nau8822"; - reg = <0x1a>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s1_mclk>; - #sound-dai-cells = <0>; - }; - - carrier_gpio_expander: gpio@21 { - compatible = "nxp,pcal6416"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - }; - - /* Current measurement into module VCC */ - hwmon@40 { - compatible = "ti,ina219"; - reg = <0x40>; - shunt-resistor = <10000>; - }; - - temperature-sensor@4f { - compatible = "ti,tmp75c"; - reg = <0x4f>; - }; - - carrier_eeprom: eeprom@57 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x57>; - pagesize = <16>; - }; -}; - -/* Verdin I2C_2_DSI */ -&main_i2c1 { - status = "okay"; -}; - -/* Verdin I2C_4_CSI */ -&main_i2c3 { - status = "okay"; -}; - -/* Verdin CAN_1 */ -&main_mcan0 { - status = "okay"; -}; - -/* Verdin SPI_1 */ -&main_spi1 { - status = "okay"; -}; - -/* Verdin UART_3, used as the Linux console */ -&main_uart0 { - status = "okay"; -}; - -/* Verdin UART_1, connector X50 through RS485 transceiver */ -&main_uart1 { - rs485-rx-during-tx; - linux,rs485-enabled-at-boot-time; - status = "okay"; -}; - -/* Verdin I2S_1 */ -&mcasp0 { - status = "okay"; -}; - -&mcu_gpio0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_1>, - <&pinctrl_gpio_2>, - <&pinctrl_gpio_3>, - <&pinctrl_gpio_4>; -}; - -/* Verdin I2C_3_HDMI */ -&mcu_i2c0 { - status = "okay"; -}; - -/* Verdin CAN_2 */ -&mcu_mcan0 { - status = "okay"; -}; - -/* Verdin UART_4 */ -&mcu_uart0 { - status = "okay"; -}; - -/* Verdin QSPI_1 */ -&ospi0 { - status = "okay"; -}; - -/* Verdin SD_1 */ -&sdhci1 { - status = "okay"; -}; - -/* Verdin USB_1 */ -&usbss0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -/* Verdin USB_2 */ -&usbss1 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -/* Verdin CTRL_WAKE1_MICO# */ -&verdin_gpio_keys { - status = "okay"; -}; - -/* Verdin PCIE_1_RESET# */ -&verdin_pcie_1_reset_hog { - status = "okay"; -}; - -/* Verdin UART_2 */ -&wkup_uart0 { - status = "okay"; -}; diff --git a/arch/arm/dts/k3-am62p-verdin-wifi.dtsi b/arch/arm/dts/k3-am62p-verdin-wifi.dtsi deleted file mode 100644 index 04d3124b5e0..00000000000 --- a/arch/arm/dts/k3-am62p-verdin-wifi.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2025 Toradex - * - * Common dtsi for Verdin AM62P SoM WB variant - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p - */ - -/* On-module Bluetooth */ -&main_uart6 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart6>; - uart-has-rtscts; - status = "okay"; - - bluetooth { - compatible = "nxp,88w8987-bt"; - fw-init-baudrate = <3000000>; - }; -}; - -/* On-module Wi-Fi */ -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci2>; - keep-power-in-suspend; - non-removable; - ti,fails-without-test-cd; - status = "okay"; -}; diff --git a/arch/arm/dts/k3-am62p-verdin.dtsi b/arch/arm/dts/k3-am62p-verdin.dtsi deleted file mode 100644 index b78b2ac76f3..00000000000 --- a/arch/arm/dts/k3-am62p-verdin.dtsi +++ /dev/null @@ -1,1399 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2025 Toradex - * - * Common dtsi for Verdin AM62P SoM - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p - */ - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/net/ti-dp83867.h> - -/ { - aliases { - can0 = &main_mcan0; - can1 = &mcu_mcan0; - eeprom0 = &som_eeprom; - ethernet0 = &cpsw_port1; - ethernet1 = &cpsw_port2; - i2c0 = &wkup_i2c0; - i2c1 = &main_i2c0; - i2c2 = &main_i2c1; - i2c3 = &mcu_i2c0; - i2c4 = &main_i2c3; - mmc0 = &sdhci0; - mmc1 = &sdhci1; - mmc2 = &sdhci2; - rtc0 = &som_rtc_i2c; - rtc1 = &wkup_rtc0; - serial0 = &main_uart1; - serial1 = &wkup_uart0; - serial2 = &main_uart0; - serial3 = &mcu_uart0; - serial4 = &main_uart6; - usb0 = &usb0; - usb1 = &usb1; - }; - - chosen { - stdout-path = "serial2:115200n8"; - }; - - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_id>; - id-gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; - label = "USB_1"; - self-powered; - vbus-supply = <®_usb0_vbus>; - - port { - usb_dr_connector: endpoint { - remote-endpoint = <&usb0_ep>; - }; - }; - }; - - verdin_gpio_keys: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; - status = "disabled"; - - key-wakeup { - debounce-interval = <10>; - /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ - gpios = <&main_gpio0 1 GPIO_ACTIVE_LOW>; - label = "Wake-Up"; - linux,code = <KEY_WAKEUP>; - wakeup-source; - }; - }; - - memory@80000000 { - /* 2G RAM */ - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; - device_type = "memory"; - }; - - opp-table { - /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ - opp-1400000000 { - opp-hz = /bits/ 64 <1400000000>; - opp-supported-hw = <0x01 0x0004>; - clock-latency-ns = <6000000>; - }; - }; - - reg_force_sleep_moci: regulator-force-sleep-moci { - compatible = "regulator-fixed"; - /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ - gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - regulator-name = "CTRL_SLEEP_MOCI#"; - }; - - /* Verdin SD_1 Power Supply */ - reg_sd1_vmmc: regulator-sdhci1-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd1_pwr_en>; - /* Verdin SD_1_PWR_EN (SODIMM 76) */ - gpios = <&main_gpio0 47 GPIO_ACTIVE_HIGH>; - enable-active-high; - off-on-delay-us = <100000>; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_SD"; - startup-delay-us = <2000>; - }; - - reg_sd1_vqmmc: regulator-sdhci1-vqmmc { - compatible = "regulator-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sd_vsel>; - /* PMIC_VSEL_SD */ - gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; - regulator-name = "LDO1-VSEL-SD (PMIC)"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - states = <1800000 0x0>, - <3300000 0x1>; - vin-supply = <®_sd_3v3_1v8>; - }; - - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_en>; - /* Verdin USB_1_EN (SODIMM 155) */ - gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "USB_1_EN"; - }; - - /* Module Power Supply */ - reg_vsodimm: regulator-vsodimm { - compatible = "regulator-fixed"; - regulator-name = "+V_SODIMM"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - secure_tfa_ddr: tfa@9e780000 { - reg = <0x00 0x9e780000 0x00 0x80000>; - no-map; - }; - - secure_ddr: optee@9e800000 { - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ - no-map; - }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible = "shared-dma-pool"; - reg = <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; - }; -}; - -&main_pmx0 { - /* Verdin PWM_3_DSI */ - pinctrl_epwm0_b: main-epwm0b-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */ /* SODIMM 19 */ - >; - }; - - /* Verdin PWM_2 */ - pinctrl_epwm2_a: main-epwm2a-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0124, PIN_OUTPUT, 4) /* (J25) MMC2_SDCD.EHRPWM2_A */ /* SODIMM 16 */ - >; - }; - - /* Verdin PWM_1 */ - pinctrl_epwm2_b: main-epwm2b-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0128, PIN_OUTPUT, 4) /* (K25) MMC2_SDWP.EHRPWM2_B */ /* SODIMM 15 */ - >; - }; - - /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0000, PIN_INPUT, 7) /* (P23) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ - >; - }; - - /* Verdin CTRL_WAKE1_MICO# */ - pinctrl_ctrl_wake1_mico: main-gpio0-1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0004, PIN_INPUT, 7) /* (N23) OSPI0_LBCLKO.GPIO0_1 */ /* SODIMM 252 */ - >; - }; - - /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_dqs_gpio: main-gpio0-2-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0008, PIN_INPUT, 7) /* (P22) OSPI0_DQS.GPIO0_2 */ /* SODIMM 66 */ - >; - }; - - /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x000c, PIN_INPUT, 7) /* (L25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ - >; - }; - - /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0010, PIN_INPUT, 7) /* (N24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ - >; - }; - - /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0014, PIN_INPUT, 7) /* (N25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ - >; - }; - - /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0018, PIN_INPUT, 7) /* (M24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ - >; - }; - - /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x002c, PIN_INPUT, 7) /* (M25) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ - >; - }; - - /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ - pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0030, PIN_INPUT, 7) /* (L24) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ - >; - }; - - /* Verdin MSP_37 as GPIO */ - pinctrl_msp37_gpio: main-gpio0-13-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0034, PIN_INPUT, 7) /* (L22) OSPI0_CSn2.GPIO0_13 */ /* SODIMM 174 - WiFi_W_WKUP_HOST# */ - >; - }; - - /* Verdin PCIE_1_RESET# */ - pinctrl_pcie_1_reset: main-gpio0-14-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0038, PIN_INPUT, 7) /* (L23) OSPI0_CSn3.GPIO0_14 */ /* SODIMM 244 */ - >; - }; - - pinctrl_sd_vsel: main-gpio0-21-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0054, PIN_INPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */ /* PMIC_SD_VSEL */ - >; - }; - - pinctrl_tpm_extint: main-gpio0-25-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0064, PIN_INPUT, 7) /* (AA25) GPMC0_AD10.GPIO0_25 */ /* TPM_EXTINT# */ - >; - }; - - pinctrl_wifi_wkup_bt: main-gpio0-29-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0074, PIN_INPUT, 7) /* (AB24) GPMC0_AD14.GPIO0_29 */ /* WiFi_WKUP_BT# */ - >; - }; - - pinctrl_wifi_wkup_wlan: main-gpio0-30-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0078, PIN_INPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */ /* WiFi_WKUP_WLAN# */ - >; - }; - - /* Verdin USB_1_ID */ - pinctrl_usb0_id: main-gpio0-31-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 161 */ - >; - }; - - /* Verdin USB_1_OC# */ - pinctrl_usb1_oc: main-gpio0-32-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0084, PIN_INPUT, 7) /* (R25) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 157 */ - >; - }; - - /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_d_in_gpio: main-gpio0-33-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ - >; - }; - - /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x008c, PIN_INPUT, 7) /* (T25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ - >; - }; - - /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0090, PIN_INPUT, 7) /* (U24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ - >; - }; - - pinctrl_eth_int: main-gpio0-36-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0094, PIN_INPUT, 7) /* (T24) GPMC0_BE1n.GPIO0_36 */ /* ETH_INT# */ - >; - }; - - /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2 interface) */ - pinctrl_i2s_2_sync_gpio: main-gpio0-37-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0098, PIN_INPUT, 7) /* (AA24) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ - >; - }; - - /* Verdin DSI_1_INT# */ - pinctrl_dsi1_int: main-gpio0-38-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x009c, PIN_INPUT, 7) /* (AD24) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 17 */ - >; - }; - - /* Verdin DSI_1_BLK_EN# */ - pinctrl_dsi1_bkl_en: main-gpio0-39-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00a0, PIN_INPUT, 7) /* (P24) GPMC0_WPn.GPIO0_39 */ /* SODIMM 21 */ - >; - }; - - /* Verdin USB_2_OC# */ - pinctrl_usb2_oc: main-gpio0-41-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00a8, PIN_INPUT, 7) /* (T23) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 187 */ - >; - }; - - /* Verdin ETH_2_RGMII_INT# */ - pinctrl_eth2_rgmii_int: main-gpio0-42-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00ac, PIN_INPUT, 7) /* (U23) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 189 */ - >; - }; - - /* Verdin SD_1_PWR_EN */ - pinctrl_sd1_pwr_en: main-gpio0-47-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00c0, PIN_INPUT, 7) /* (AA23) VOUT0_DATA2.GPIO0_47 */ /* SODIMM 76 */ - >; - }; - - /* Verdin GPIO_5 */ - pinctrl_gpio_5: main-gpio0-49-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00c8, PIN_INPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */ /* SODIMM 216 */ - >; - }; - - /* Verdin GPIO_6 */ - pinctrl_gpio_6: main-gpio0-50-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00cc, PIN_INPUT, 7) /* (AD23) VOUT0_DATA5.GPIO0_50 */ /* SODIMM 218 */ - >; - }; - - /* Verdin GPIO_7 */ - pinctrl_gpio_7: main-gpio0-51-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00d0, PIN_INPUT, 7) /* (AC23) VOUT0_DATA6.GPIO0_51 */ /* SODIMM 220 */ - >; - }; - - /* Verdin GPIO_8 */ - pinctrl_gpio_8: main-gpio0-52-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00d4, PIN_INPUT, 7) /* (AE23) VOUT0_DATA7.GPIO0_52 */ /* SODIMM 222 */ - >; - }; - - /* Verdin MSP_36 as GPIO */ - pinctrl_msp36_gpio: main-gpio0-57-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00e8, PIN_INPUT, 7) /* (AD21) VOUT0_DATA12.GPIO0_57 */ /* SODIMM 172 - WiFi_BT_WKUP_HOST# */ - >; - }; - - pinctrl_wifi_sd_int: main-gpio0-59-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00f0, PIN_INPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 */ /* WIFI_SD_INT */ - >; - }; - - pinctrl_wifi_spi_cs: main-gpio0-60-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00f4, PIN_INPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 */ /* WIFI_SPI_CS# */ - >; - }; - - /* Verdin PWM_3_DSI as GPIO */ - pinctrl_pwm3_dsi_gpio: main-gpio1-16-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 7) /* (E20) SPI0_CS1.GPIO1_16 */ /* SODIMM 19 */ - >; - }; - - /* Verdin SD_1_CD# */ - pinctrl_sd1_cd: main-gpio1-48-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0240, PIN_INPUT, 7) /* (D23) MMC1_SDCD.GPIO1_48 */ /* SODIMM 84 */ - >; - }; - - /* Verdin MSP_29 as GPIO */ - pinctl_msp29_gpio: main-gpio1-49-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0244, PIN_INPUT, 7) /* (D24) MMC1_SDWP.GPIO1_49 */ /* SODIMM 154 */ - >; - }; - - /* Verdin USB_1_EN */ - pinctrl_usb0_en: main-gpio1-50-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0254, PIN_INPUT, 7) /* (G22) USB0_DRVVBUS.GPIO1_50 */ /* SODIMM 155 */ - >; - }; - - /* Verdin I2C_1 */ - pinctrl_main_i2c0: main-i2c0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ /* SODIMM 14 */ - AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ /* SODIMM 12 */ - >; - }; - - /* Verdin I2C_2_DSI */ - pinctrl_main_i2c1: main-i2c1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ /* SODIMM 55 */ - AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ /* SODIMM 53 */ - >; - }; - - /* Verdin I2C_4_CSI */ - pinctrl_main_i2c3: main-i2c3-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ - AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ - >; - }; - - /* Verdin CAN_1 */ - pinctrl_main_mcan0: main-mcan0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ /* SODIMM 22 */ - AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ /* SODIMM 20 */ - >; - }; - - /* Verdin MSP_3/MSP_8 as CAN */ - pinctrl_main_mcan1: main-mcan1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00b4, PIN_INPUT, 5) /* (U25) GPMC0_CSn3.MCAN1_RX */ /* SODIMM 92 */ - AM62PX_IOPAD(0x00b0, PIN_OUTPUT, 5) /* (T22) GPMC0_CSn2.MCAN1_TX */ /* SODIMM 104 */ - >; - }; - - /* Verdin SD_1 */ - pinctrl_sdhci1: main-mmc1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ /* SODIMM 74 */ - AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ /* SODIMM 78 */ - AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ /* SODIMM 80 */ - AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */ /* SODIMM 82 */ - AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */ /* SODIMM 70 */ - AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ /* SODIMM 72 */ - >; - }; - - /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ - pinctrl_sdhci2: main-mmc2-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */ - AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */ - AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ - AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */ - AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */ - AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */ - AM62PX_IOPAD(0x0108, PIN_INPUT, 0) /* (L21) MMC2_DAT3 */ /* SODIMM 168, WiFi_SDIO_DATA3 */ - >; - }; - - /* Verdin QSPI_1 */ - pinctrl_ospi0: main-ospi0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ /* SODIMM 52 */ - AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ /* SODIMM 54 */ - AM62PX_IOPAD(0x0030, PIN_OUTPUT, 0) /* (L24) OSPI0_CSn1 */ /* SODIMM 64 */ - AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ /* SODIMM 56 */ - AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ /* SODIMM 58 */ - AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ /* SODIMM 60 */ - AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ /* SODIMM 62 */ - AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ /* SODIMM 66 */ - >; - }; - - /* Verdin ETH_1 RGMII (On-module PHY) */ - pinctrl_rgmii1: main-rgmii1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ /* RGMII_RXD0 */ - AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ /* RGMII_RXD1 */ - AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ /* RGMII_RXD2 */ - AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ /* RGMII_RXD3 */ - AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ /* RGMII_RXC */ - AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ /* RGMII_RX_CTL */ - AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ /* RGMII_TXD0 */ - AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ /* RGMII_TXD1 */ - AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ /* RGMII_TXD2 */ - AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ /* RGMII_TXD3 */ - AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ /* RGMII_TXC */ - AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ /* RGMII_TX_CTL */ - >; - }; - - /* Verdin ETH_2 RGMII */ - pinctrl_rgmii2: main-rgmii2-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ /* SODIMM 201 */ - AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ /* SODIMM 203 */ - AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ /* SODIMM 205 */ - AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ /* SODIMM 207 */ - AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ /* SODIMM 197 */ - AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ /* SODIMM 199 */ - AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ /* SODIMM 221 */ - AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ /* SODIMM 219 */ - AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ /* SODIMM 217 */ - AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ /* SODIMM 215 */ - AM62PX_IOPAD(0x0168, PIN_INPUT, 0) /* (D16) RGMII2_TXC */ /* SODIMM 213 */ - AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ /* SODIMM 211 */ - >; - }; - - /* TPM SPI, Optional Module Specific SPI */ - pinctrl_main_spi0: main-spi0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01bc, PIN_INPUT, 0) /* (B21) SPI0_CLK */ /* TPM_SPI_CLK - SODIMM 148 */ - AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */ /* TPM_SPI_MOSI - SODIMM 150 */ - AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */ /* TPM_SPI_MISO - SODIMM 152 */ - AM62PX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D20) SPI0_CS0 */ /* TPM_SPI_CS */ - >; - }; - - /* Verdin SPI_1 */ - pinctrl_main_spi1: main-spi1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0020, PIN_INPUT, 1) /* (N22) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ - AM62PX_IOPAD(0x0024, PIN_OUTPUT, 1) /* (P21) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ - AM62PX_IOPAD(0x0028, PIN_INPUT, 1) /* (N20) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ - >; - }; - - /* Verdin SPI_1_CS */ - pinctrl_main_spi1_cs0: main-spi1-cs0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x001c, PIN_OUTPUT, 1) /* (N21) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ - >; - }; - - /* Verdin I2S_1 MCLK */ - pinctrl_i2s1_mclk: main-system-audio-ext-reflock0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 5) /* (Y23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */ /* SODIMM 38 */ - >; - }; - - pinctrl_eth_clock: main-system-clkout0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (C25) EXT_REFCLK1.CLKOUT0 */ /* ETH_25MHz_CLK */ - >; - }; - - pinctrl_pmic_extint: main-system-extint-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01f4, PIN_INPUT, 0) /* (C23) EXTINTn */ /* PMIC_EXTINT# */ - >; - }; - - /* Verdin UART_3, used as the Linux console */ - pinctrl_uart0: main-uart0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ /* SODIMM 147 */ - AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ /* SODIMM 149 */ - >; - }; - - /* Verdin UART_1 */ - pinctrl_uart1: main-uart1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ - AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ - AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ - AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ - >; - }; - - /* Verdin MSP 41, 42, 44 and 45 as UART */ - pinctrl_uart2: main-uart2-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00b8, PIN_INPUT, 4) /* (AE24) VOUT0_DATA0.UART2_RXD */ /* SODIMM 192 */ - AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 4) /* (W23) VOUT0_DATA1.UART2_TXD */ /* SODIMM 190 */ - AM62PX_IOPAD(0x0104, PIN_INPUT, 4) /* (Y21) VOUT0_PCLK.UART2_CTSn */ /* SODIMM 184 */ - AM62PX_IOPAD(0x0100, PIN_OUTPUT, 4) /* (W20) VOUT0_VSYNC.UART2_RTSn */ /* SODIMM 186 */ - >; - }; - - /* Bluetooth on WB SKUs */ - pinctrl_uart6: main-uart6-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x00d8, PIN_INPUT, 4) /* (AE22) VOUT0_DATA8.UART6_RXD */ /* WiFi_UART_RXD */ - AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (AC22) VOUT0_DATA9.UART6_TXD */ /* WiFi_UART_TXD */ - AM62PX_IOPAD(0x00e4, PIN_INPUT, 4) /* (AE21) VOUT0_DATA11.UART6_CTSn */ /* WiFi_UART_CTS */ - AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (W22) VOUT0_DATA10.UART6_RTSn */ /* WiFi_UART_RTS */ - >; - }; - - /* Verdin USB_2_EN */ - pinctrl_usb1: main-usb1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */ /* SODIMM 185 */ - >; - }; - - /* Verdin I2S_1 */ - pinctrl_mcasp0: mcasp0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x01a4, PIN_INPUT, 0) /* (F24) MCASP0_ACLKX */ /* SODIMM 30 */ - AM62PX_IOPAD(0x01a8, PIN_INPUT, 0) /* (F25) MCASP0_AFSX */ /* SODIMM 32 */ - AM62PX_IOPAD(0x01a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ /* SODIMM 34 */ - AM62PX_IOPAD(0x019c, PIN_INPUT, 0) /* (E24) MCASP0_AXR1 */ /* SODIMM 36 */ - >; - }; - - /* Verdin I2S_2 */ - pinctrl_mcasp1: mcasp1-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ - AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ - AM62PX_IOPAD(0x008c, PIN_INPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ - AM62PX_IOPAD(0x0088, PIN_INPUT, 2) /* (R24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ - >; - }; - - /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ - pinctrl_mdio: mdio0-default-pins { - pinctrl-single,pins = < - AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ /* SODIMM 193 */ - AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ /* SODIMM 191 */ - >; - }; -}; - -&mcu_pmx0 { - /* Verdin GPIO_1 */ - pinctrl_gpio_1: mcu-gpio0-1-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (E10) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ - >; - }; - - /* Verdin GPIO_2 */ - pinctrl_gpio_2: mcu-gpio0-2-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (C10) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ - >; - }; - - /* Verdin GPIO_3 */ - pinctrl_gpio_3: mcu-gpio0-3-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (B11) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ - >; - }; - - /* Verdin GPIO_4 */ - pinctrl_gpio_4: mcu-gpio0-4-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (D10) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ - >; - }; - - /* Verdin I2C_3_HDMI */ - pinctrl_mcu_i2c0: mcu-i2c0-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (E11) MCU_I2C0_SCL */ /* SODIMM 59 */ - AM62PX_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D11) MCU_I2C0_SDA */ /* SODIMM 57 */ - >; - }; - - /* Verdin CAN_2 */ - pinctrl_mcu_mcan0: mcu-mcan0-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */ /* SODIMM 22 */ - AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */ /* SODIMM 20 */ - >; - }; - - /* Verdin MSP_13/MSP_18 as CAN */ - pinctrl_mcu_mcan1: mcu-mcan1-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */ /* SODIMM 116 */ - AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (F8) MCU_MCAN1_TX */ /* SODIMM 128 */ - >; - }; - - /* Verdin UART_4 */ - pinctrl_mcu_uart0: mcu-uart0-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x0014, PIN_INPUT, 0) /* (B6) MCU_UART0_RXD */ /* SODIMM 151 */ - AM62PX_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (C8) MCU_UART0_TXD */ /* SODIMM 153 */ - >; - }; - - /* On-module I2C - PMIC_I2C */ - pinctrl_wkup_i2c0: wkup-i2c0-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x004c, PIN_INPUT, 0) /* (A13) WKUP_I2C0_SCL */ /* PMIC_I2C_SCL */ - AM62PX_MCU_IOPAD(0x0050, PIN_INPUT, 0) /* (C11) WKUP_I2C0_SDA */ /* PMIC_I2C_SDA */ - >; - }; - - /* Verdin CSI_1_MCLK */ - pinctrl_wkup_clkout0: wkup-system-clkout0-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ /* SODIMM 91 */ - >; - }; - - /* Verdin UART_2 */ - pinctrl_wkup_uart0: wkup-uart0-default-pins { - pinctrl-single,pins = < - AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ /* SODIMM 143 */ - AM62PX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ /* SODIMM 141 */ - AM62PX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ /* SODIMM 137 */ - AM62PX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ /* SODIMM 139 */ - >; - }; -}; - -&cpsw3g { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rgmii1>; - status = "disabled"; -}; - -/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ -&cpsw3g_mdio { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mdio>, <&pinctrl_eth_clock>; - assigned-clocks = <&k3_clks 157 36>; - assigned-clock-parents = <&k3_clks 157 38>; - assigned-clock-rates = <25000000>; - status = "disabled"; - - som_eth_phy: ethernet-phy@0 { - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eth_int>; - interrupt-parent = <&main_gpio0>; - interrupts = <36 IRQ_TYPE_EDGE_FALLING>; - ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; - }; -}; - -/* Verdin ETH_1 (On-module PHY) */ -&cpsw_port1 { - phy-handle = <&som_eth_phy>; - phy-mode = "rgmii-rxid"; - status = "disabled"; -}; - -/* Verdin ETH_2_RGMII */ -&cpsw_port2 { - status = "disabled"; -}; - -/* Verdin PWM_3_DSI */ -&epwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_epwm0_b>; - status = "disabled"; -}; - -/* Verdin PWM_1, PWM_2 */ -&epwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_epwm2_a>, <&pinctrl_epwm2_b>; - status = "disabled"; -}; - -&mailbox0_cluster0 { - status = "okay"; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&mailbox0_cluster1 { - status = "okay"; - - mbox_mcu_r5_0: mbox-mcu-r5-0 { - ti,mbox-rx = <0 0 0>; - ti,mbox-tx = <1 0 0>; - }; -}; - -&main_gpio0 { - gpio-line-names = - "SODIMM_52", - "SODIMM_252", - "SODIMM_66", - "SODIMM_56", - "SODIMM_58", - "SODIMM_60", - "SODIMM_62", - "", - "", - "", - "", /* 10 */ - "SODIMM_54", - "SODIMM_64", - "SODIMM_174", - "SODIMM_244", - "", - "", - "", - "", - "", - "", /* 20 */ - "PMIC_SD_VSEL", - "", - "", - "", - "TPM_EXTINT#", - "", - "", - "", - "WiFi_WKUP_BT#", - "WiFi_WKUP_WLAN#", /* 30 */ - "SODIMM_161", - "SODIMM_157", - "", - "", - "", - "ETH_INT#", - "", - "SODIMM_17", - "SODIMM_21", - "", /* 40 */ - "SODIMM_187", - "SODIMM_189", - "", - "", - "", - "", - "SODIMM_76", - "", - "SODIMM_216", - "SODIMM_218", /* 50 */ - "SODIMM_220", - "SODIMM_222", - "", - "", - "", - "", - "SODIMM_172", - "", - "WIFI_SD_INT", - "WIFI_SPI_CS#", /* 60 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 70 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 80 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 90 */ - ""; - - verdin_pcie_1_reset_hog: pcie-1-reset-hog { - gpio-hog; - /* Verdin PCIE_1_RESET# (SODIMM 244) */ - gpios = <14 GPIO_ACTIVE_LOW>; - line-name = "PCIE_1_RESET#"; - output-low; - status = "disabled"; - }; -}; - -&main_gpio1 { - gpio-line-names = - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 20 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 30 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 40 */ - "", - "", - "", - "", - "", - "", - "", - "SODIMM_84", - "SODIMM_154", - "SODIMM_155", /* 50 */ - ""; -}; - -/* Verdin I2C_1 */ -&main_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c0>; - status = "disabled"; -}; - -/* Verdin I2C_2_DSI */ -&main_i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c1>; - status = "disabled"; -}; - -/* Verdin I2C_4_CSI */ -&main_i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_i2c3>; - status = "disabled"; -}; - -/* Verdin CAN_1 */ -&main_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_mcan0>; - status = "disabled"; -}; - -/* TPM SPI, optional SPI on module specific pins */ -&main_spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_spi0>; - ti,pindir-d0-out-d1-in; - status = "okay"; - - tpm@0 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tpm_extint>; - interrupt-parent = <&main_gpio0>; - interrupts = <25 IRQ_TYPE_EDGE_FALLING>; - spi-max-frequency = <18500000>; - }; -}; - -/* Verdin SPI_1 */ -&main_spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_main_spi1>, <&pinctrl_main_spi1_cs0>; - ti,pindir-d0-out-d1-in; - status = "disabled"; -}; - -/* Verdin UART_3, used as the Linux console */ -&main_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart0>; - status = "disabled"; -}; - -/* Verdin UART_1 */ -&main_uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "disabled"; -}; - -/* Verdin I2S_1 */ -&mcasp0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcasp0>; - op-mode = <0>; /* I2S mode */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tdm-slots = <2>; - rx-num-evt = <0>; - tx-num-evt = <0>; - #sound-dai-cells = <0>; - status = "disabled"; -}; - -/* Verdin I2S_2 */ -&mcasp1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcasp1>; - op-mode = <0>; /* I2S mode */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 - >; - tdm-slots = <2>; - rx-num-evt = <0>; - tx-num-evt = <0>; - #sound-dai-cells = <0>; - status = "disabled"; -}; - -&mcu_gpio0 { - gpio-line-names = - "", - "SODIMM_206", - "SODIMM_208", - "SODIMM_210", - "SODIMM_212", - "", - "", - "", - "", - "", - "", /* 10 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", /* 20 */ - "", - "", - ""; -}; - -/* Verdin I2C_3_HDMI */ -&mcu_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_i2c0>; - status = "disabled"; -}; - -/* Verdin CAN_2 */ -&mcu_mcan0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_mcan0>; - status = "disabled"; -}; - -/* Verdin UART_4 */ -&mcu_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mcu_uart0>; - status = "disabled"; -}; - -/* Verdin QSPI_1 */ -&ospi0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ospi0>; - status = "disabled"; -}; - -/* On-module eMMC */ -&sdhci0 { - no-mmc-hs400; - non-removable; - ti,driver-strength-ohm = <50>; - status = "okay"; -}; - -/* Verdin SD_1 */ -&sdhci1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhci1>, <&pinctrl_sd1_cd>; - cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; - disable-wp; - vmmc-supply = <®_sd1_vmmc>; - vqmmc-supply = <®_sd1_vqmmc>; - ti,fails-without-test-cd; - status = "disabled"; -}; - -/* Verdin USB_1 */ -&usbss0 { - ti,vbus-divider; - status = "disabled"; -}; - -&usb0 { - adp-disable; - usb-role-switch; - status = "disabled"; - - port { - usb0_ep: endpoint { - remote-endpoint = <&usb_dr_connector>; - }; - }; -}; - -/* Verdin USB_2 */ -&usbss1 { - ti,vbus-divider; - status = "disabled"; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - dr_mode = "host"; - status = "disabled"; -}; - -/* On-module I2C - PMIC_I2C */ -&wkup_i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_i2c0>; - clock-frequency = <400000>; - status = "okay"; - - som_gpio_expander: gpio@21 { - compatible = "nxp,pcal6408"; - reg = <0x21>; - #gpio-cells = <2>; - gpio-controller; - gpio-line-names = "SODIMM_256"; - }; - - pmic@30 { - compatible = "ti,tps65219"; - reg = <0x30>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic_extint>; - interrupt-parent = <&gic500>; - interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; - - buck1-supply = <®_vsodimm>; - buck2-supply = <®_vsodimm>; - buck3-supply = <®_vsodimm>; - ldo1-supply = <®_3v3>; - ldo2-supply = <®_1v8>; - ldo3-supply = <®_3v3>; - ldo4-supply = <®_3v3>; - system-power-controller; - ti,power-button; - - regulators { - reg_3v3: buck1 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3 (PMIC BUCK1)"; - }; - - reg_1v8: buck2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ - }; - - buck3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1100000>; - regulator-min-microvolt = <1100000>; - regulator-name = "+VDD_DDR (PMIC BUCK3)"; - }; - - reg_sd_3v3_1v8: ldo1 { - regulator-allow-bypass; - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; - }; - - ldo2 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <850000>; - regulator-min-microvolt = <850000>; - regulator-name = "+V_PMIC_LDO2 (PMIC LDO4)"; // +VDDR_CORE - }; - - ldo3 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <1800000>; - regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8A (PMIC LDO3)"; - }; - - ldo4 { - regulator-always-on; - regulator-boot-on; - regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <2500000>; - regulator-name = "+V2.5_ETH (PMIC LDO4)"; - }; - }; - }; - - som_rtc_i2c: rtc@32 { - compatible = "epson,rx8130"; - reg = <0x32>; - }; - - temperature-sensor@48 { - compatible = "ti,tmp1075"; - reg = <0x48>; - }; - - som_adc: adc@49 { - compatible = "ti,tla2024"; - reg = <0x49>; - #address-cells = <1>; - #size-cells = <0>; - #io-channel-cells = <1>; - - /* Verdin (ADC_4 - ADC_3) */ - channel@0 { - reg = <0>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin (ADC_4 - ADC_1) */ - channel@1 { - reg = <1>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin (ADC_3 - ADC_1) */ - channel@2 { - reg = <2>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin (ADC_2 - ADC_1) */ - channel@3 { - reg = <3>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin ADC_4 */ - channel@4 { - reg = <4>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin ADC_3 */ - channel@5 { - reg = <5>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin ADC_2 */ - channel@6 { - reg = <6>; - ti,datarate = <4>; - ti,gain = <2>; - }; - - /* Verdin ADC_1 */ - channel@7 { - reg = <7>; - ti,datarate = <4>; - ti,gain = <2>; - }; - }; - - som_eeprom: eeprom@50 { - compatible = "st,24c02", "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -/* Verdin UART_2 */ -&wkup_uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wkup_uart0>; - uart-has-rtscts; - status = "disabled"; -}; diff --git a/arch/arm/dts/k3-am62p5-r5-sk.dts b/arch/arm/dts/k3-am62p5-r5-sk.dts index b18b4ce1272..e45d2bf6a0b 100644 --- a/arch/arm/dts/k3-am62p5-r5-sk.dts +++ b/arch/arm/dts/k3-am62p5-r5-sk.dts @@ -69,7 +69,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am62p5-verdin-r5.dts b/arch/arm/dts/k3-am62p5-verdin-r5.dts index 983a3bfe670..17739086935 100644 --- a/arch/arm/dts/k3-am62p5-verdin-r5.dts +++ b/arch/arm/dts/k3-am62p5-verdin-r5.dts @@ -57,7 +57,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi index b1591faaf0a..57ce3c0b41c 100644 --- a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi @@ -112,7 +112,7 @@ #if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_A53) -#define SPL_VERDIN_AM62P_DTB "spl/dts/k3-am62p5-verdin-wifi-dev.dtb" +#define SPL_VERDIN_AM62P_DTB "spl/dts/ti/k3-am62p5-verdin-wifi-dev.dtb" #define VERDIN_AM62P_DTB "u-boot.dtb" &binman { diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts b/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts deleted file mode 100644 index bbc2770d5f5..00000000000 --- a/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright 2025 Toradex - * - * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p - * https://www.toradex.com/products/carrier-board/verdin-development-board-kit - */ - -/dts-v1/; - -#include "k3-am62p5.dtsi" -#include "k3-am62p-verdin.dtsi" -#include "k3-am62p-verdin-wifi.dtsi" -#include "k3-am62p-verdin-dev.dtsi" - -/ { - model = "Toradex Verdin AM62P WB on Verdin Development Board"; - compatible = "toradex,verdin-am62p-wifi-dev", - "toradex,verdin-am62p-wifi", - "toradex,verdin-am62p", - "ti,am62p5"; -}; diff --git a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi index c68a48678a2..56547cbd28a 100644 --- a/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-phyboard-electra-rdk-u-boot.dtsi @@ -156,6 +156,10 @@ bootph-all; }; +&main_rti1 { + status = "disabled"; +}; + &sdhci0 { bootph-all; }; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index 933f75095b1..67b8587d3b2 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -43,7 +43,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts index 40c25d5dbb6..32a10b24327 100644 --- a/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts +++ b/arch/arm/dts/k3-am642-r5-phycore-som-2gb.dts @@ -63,7 +63,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 6e31dfd97c5..cfc548a1cea 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -43,7 +43,7 @@ &cbass_main { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 4fd188fa191..baf5dd562f9 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -17,6 +17,14 @@ bootph-all; }; +&evm_12v0 { + bootph-all; +}; + +&vcc3v3_io { + bootph-all; +}; + &vtt_supply { bootph-all; }; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index ab5195eb15c..99eb8a2d442 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -47,7 +47,7 @@ &cbass_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-am67a-r5-beagley-ai.dts b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts index 664be358a97..45d104e8e3f 100644 --- a/arch/arm/dts/k3-am67a-r5-beagley-ai.dts +++ b/arch/arm/dts/k3-am67a-r5-beagley-ai.dts @@ -69,7 +69,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-binman.dtsi b/arch/arm/dts/k3-binman.dtsi index 5163161b94d..761b1730464 100644 --- a/arch/arm/dts/k3-binman.dtsi +++ b/arch/arm/dts/k3-binman.dtsi @@ -489,6 +489,60 @@ end_address = <0x0 0x9fffffff>; }; + ti_falcon_template: template-9 { + filename = "tifalcon.bin"; + pad-byte = <0xff>; + + fit { + description = "Configuration for falcon boot"; + #address-cells = <1>; + + images { + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; + os = "arm-trusted-firmware"; + load = <CONFIG_K3_ATF_LOAD_ADDR>; + entry = <CONFIG_K3_ATF_LOAD_ADDR>; + ti-secure { + content = <&atf_falcon>; + keyfile = "custMpk.pem"; + }; + atf_falcon: atf-bl31 { + }; + }; + tee { + description = "OP-TEE"; + type = "tee"; + arch = "arm64"; + compression = "none"; + os = "tee"; + load = <CONFIG_K3_OPTEE_LOAD_ADDR>; + entry = <CONFIG_K3_OPTEE_LOAD_ADDR>; + ti-secure { + content = <&tee_falcon>; + keyfile = "custMpk.pem"; + }; + tee_falcon: tee-os { + optional; + }; + }; + dm { + description = "DM binary"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "DM"; + load = <0x89000000>; + entry = <0x89000000>; + }; + + }; + }; + }; + }; #endif diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 9ac29110324..e35b767a7e3 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -69,7 +69,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index c775432505b..e4f799dfb27 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -52,6 +52,7 @@ }; &hbmc { + status = "okay"; reg = <0x0 0x47040000 0x0 0x100>, <0x0 0x50000000 0x0 0x8000000>; ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, diff --git a/arch/arm/dts/k3-j721e-r5.dtsi b/arch/arm/dts/k3-j721e-r5.dtsi index 786a41c5e90..7398f9b05ec 100644 --- a/arch/arm/dts/k3-j721e-r5.dtsi +++ b/arch/arm/dts/k3-j721e-r5.dtsi @@ -66,7 +66,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { bootph-pre-ram; - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>; mbox-names = "tx", "rx"; }; diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi index a820f516015..c1c12e217d2 100644 --- a/arch/arm/dts/k3-j721s2-r5.dtsi +++ b/arch/arm/dts/k3-j721s2-r5.dtsi @@ -63,7 +63,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; mbox-names = "tx", "rx", "boot_notify"; bootph-pre-ram; diff --git a/arch/arm/dts/k3-j722s-r5-evm.dts b/arch/arm/dts/k3-j722s-r5-evm.dts index 286ab50d3da..02a3494a877 100644 --- a/arch/arm/dts/k3-j722s-r5-evm.dts +++ b/arch/arm/dts/k3-j722s-r5-evm.dts @@ -68,7 +68,7 @@ }; sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&sa3_secproxy 0>; diff --git a/arch/arm/dts/k3-j784s4-r5.dtsi b/arch/arm/dts/k3-j784s4-r5.dtsi index a1394115b8b..78444dc4e14 100644 --- a/arch/arm/dts/k3-j784s4-r5.dtsi +++ b/arch/arm/dts/k3-j784s4-r5.dtsi @@ -61,7 +61,7 @@ &cbass_mcu_wakeup { sysctrler: sysctrler { - compatible = "ti,am654-system-controller"; + compatible = "ti,am654-tisci-rproc-r5"; mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>, <&secure_proxy_sa3 5>; diff --git a/arch/arm/dts/mt7981-rfb.dts b/arch/arm/dts/mt7981-rfb.dts index 17e6b5af7a2..ad149a34437 100644 --- a/arch/arm/dts/mt7981-rfb.dts +++ b/arch/arm/dts/mt7981-rfb.dts @@ -139,7 +139,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; @@ -162,7 +161,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi2_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts index e01ae4c3dc7..ab6f84a3ece 100644 --- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts +++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts @@ -173,7 +173,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986a-rfb.dts b/arch/arm/dts/mt7986a-rfb.dts index d4bbb23204a..0d628a2e715 100644 --- a/arch/arm/dts/mt7986a-rfb.dts +++ b/arch/arm/dts/mt7986a-rfb.dts @@ -178,7 +178,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986a-sd-rfb.dts b/arch/arm/dts/mt7986a-sd-rfb.dts index 11823e05bda..632f8b9446d 100644 --- a/arch/arm/dts/mt7986a-sd-rfb.dts +++ b/arch/arm/dts/mt7986a-sd-rfb.dts @@ -138,7 +138,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986b-rfb.dts b/arch/arm/dts/mt7986b-rfb.dts index 0a731fe87fd..44524345468 100644 --- a/arch/arm/dts/mt7986b-rfb.dts +++ b/arch/arm/dts/mt7986b-rfb.dts @@ -165,7 +165,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7986b-sd-rfb.dts b/arch/arm/dts/mt7986b-sd-rfb.dts index e5fb4d73e70..d5c4273047a 100644 --- a/arch/arm/dts/mt7986b-sd-rfb.dts +++ b/arch/arm/dts/mt7986b-sd-rfb.dts @@ -134,7 +134,6 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi index 54cf72b3bf8..dc3f70aad64 100644 --- a/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi +++ b/arch/arm/dts/mt7987a-emmc-rfb-u-boot.dtsi @@ -42,7 +42,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi index f1ed51e21c4..fa02ff59f6a 100644 --- a/arch/arm/dts/mt7987a-rfb-u-boot.dtsi +++ b/arch/arm/dts/mt7987a-rfb-u-boot.dtsi @@ -28,7 +28,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; @@ -52,7 +51,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi index b07e6da41e2..cf1114e7d99 100644 --- a/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi +++ b/arch/arm/dts/mt7987a-sd-rfb-u-boot.dtsi @@ -40,7 +40,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7988-rfb.dts b/arch/arm/dts/mt7988-rfb.dts index 1694ef8d9c3..6176ef923b2 100644 --- a/arch/arm/dts/mt7988-rfb.dts +++ b/arch/arm/dts/mt7988-rfb.dts @@ -181,7 +181,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; @@ -204,7 +203,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/mt7988-sd-rfb.dts b/arch/arm/dts/mt7988-sd-rfb.dts index 63e923137c2..e29a9764187 100644 --- a/arch/arm/dts/mt7988-sd-rfb.dts +++ b/arch/arm/dts/mt7988-sd-rfb.dts @@ -108,7 +108,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - must_tx; enhance_timing; dma_ext; ipm_design; diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi index db7517cc9ba..6866005336f 100644 --- a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi @@ -62,6 +62,11 @@ reg = <0x0 0xf0801000 0x0 0x1000>; }; + timer0: timer@f0801068 { + compatible = "nuvoton,npcm845-timer"; + reg = <0x0 0xf0801068 0x0 0x8>; + }; + sdhci0: sdhci@f0842000 { compatible = "nuvoton,npcm845-sdhci"; reg = <0x0 0xf0842000 0x0 0x100>; @@ -136,7 +141,7 @@ host_intf: host_intf@9f000 { compatible = "nuvoton,npcm845-host-intf"; - reg = <0x9f000 0x1000>; + reg = <0x9f000 0x1000>, <0x7000 0x40>; type = "espi"; ioaddr = <0x4e>; channel-support = <0xf>; @@ -157,14 +162,6 @@ status = "disabled"; }; - timer0: timer@8000 { - compatible = "nuvoton,npcm845-timer"; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x8000 0x1C>; - clocks = <&clk NPCM8XX_CLK_REFCLK>; - clock-names = "refclk"; - }; - serial0: serial@0 { compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart"; reg = <0x0 0x1000>; diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi index bc047d4b443..6f933355d9e 100644 --- a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi +++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi @@ -1056,5 +1056,9 @@ groups = "jtag2"; function = "jtag2"; }; + vcdhs_pins: vcdhs-pins { + groups = "vcdhs"; + function = "vcdhs"; + }; }; }; diff --git a/arch/arm/dts/px30-u-boot.dtsi b/arch/arm/dts/px30-u-boot.dtsi index 157d0ea6930..2f726b0aaba 100644 --- a/arch/arm/dts/px30-u-boot.dtsi +++ b/arch/arm/dts/px30-u-boot.dtsi @@ -27,6 +27,10 @@ }; }; +&otp { + bootph-some-ram; +}; + &uart2 { clock-frequency = <24000000>; bootph-all; diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte-u-boot.dtsi b/arch/arm/dts/pxa1908-samsung-coreprimevelte-u-boot.dtsi new file mode 100644 index 00000000000..2e5ec5c597d --- /dev/null +++ b/arch/arm/dts/pxa1908-samsung-coreprimevelte-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 Duje Mihanović <duje@dujemihanovic.xyz> + */ + +/ { + pxa,rev-id = <3928 0>, <3928 1>, <3928 2>; + + memory@0 { + reg = <0 0x1000000 0 0x3f000000>; + }; +}; + +&uart0 { + clock-frequency = <14745600>; +}; + +&pmx { + compatible = "marvell,pxa1908-padconf", "pinctrl-single"; +}; diff --git a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts b/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts deleted file mode 100644 index 588e39e9265..00000000000 --- a/arch/arm/dts/pxa1908-samsung-coreprimevelte.dts +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -#include "pxa1908.dtsi" - -/ { - pxa,rev-id = <3928 2>; - model = "Samsung Galaxy Core Prime VE LTE"; - compatible = "samsung,coreprimevelte", "marvell,pxa1908"; - - aliases { - serial0 = &uart0; - }; - - chosen { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - stdout-path = "serial0:115200n8"; - - /* S-Boot places the initramfs here */ - linux,initrd-start = <0x4d70000>; - linux,initrd-end = <0x5000000>; - - fb0: framebuffer@17177000 { - compatible = "simple-framebuffer"; - reg = <0 0x17177000 0 (480 * 800 * 4)>; - width = <480>; - height = <800>; - stride = <(480 * 4)>; - format = "a8r8g8b8"; - }; - }; - - memory { - device_type = "memory"; - reg = <0 0x1000000 0 0x3f000000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - framebuffer@17000000 { - reg = <0 0x17000000 0 0x1800000>; - no-map; - }; - - gpu@9000000 { - reg = <0 0x9000000 0 0x1000000>; - }; - - /* Communications processor, aka modem */ - cp@5000000 { - reg = <0 0x5000000 0 0x3000000>; - }; - - cm3@a000000 { - reg = <0 0xa000000 0 0x80000>; - }; - - seclog@8000000 { - reg = <0 0x8000000 0 0x100000>; - }; - - ramoops@8100000 { - compatible = "ramoops"; - reg = <0 0x8100000 0 0x40000>; - record-size = <0x8000>; - console-size = <0x20000>; - max-reason = <5>; - }; - }; -}; diff --git a/arch/arm/dts/pxa1908.dtsi b/arch/arm/dts/pxa1908.dtsi deleted file mode 100644 index e8ec2606c25..00000000000 --- a/arch/arm/dts/pxa1908.dtsi +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -/ { - model = "Marvell Armada PXA1908"; - compatible = "marvell,pxa1908"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 0>; - enable-method = "psci"; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 1>; - enable-method = "psci"; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 2>; - enable-method = "psci"; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - reg = <0 3>; - enable-method = "psci"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - gic: interrupt-controller@d1df9000 { - compatible = "arm,gic-400"; - reg = <0 0xd1df9000 0 0x1000>, - <0 0xd1dfa000 0 0x2000>, - /* The subsequent registers are guesses. */ - <0 0xd1dfc000 0 0x2000>, - <0 0xd1dfe000 0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - apb@d4000000 { - compatible = "simple-bus"; - reg = <0 0xd4000000 0 0x200000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xd4000000 0x200000>; - - uart0: serial@17000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0x17000 0x1000>; - clock-frequency = <14745600>; - reg-shift = <2>; - }; - - uart1: serial@18000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0x18000 0x1000>; - clock-frequency = <14745600>; - reg-shift = <2>; - }; - - uart2: serial@36000 { - compatible = "mrvl,mmp-uart", "intel,xscale-uart"; - reg = <0x36000 0x1000>; - clock-frequency = <117000000>; - reg-shift = <2>; - }; - }; - }; -}; diff --git a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi index 85e32208b29..8e4307ff87d 100644 --- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi @@ -23,6 +23,8 @@ &rpc { bootph-all; + status = "disabled"; + flash@0 { bootph-all; spi-tx-bus-width = <1>; diff --git a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi index c9f302799f1..dff0355150d 100644 --- a/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi +++ b/arch/arm/dts/r8a779g3-sparrow-hawk-u-boot.dtsi @@ -7,6 +7,13 @@ #include "r8a779g0-u-boot.dtsi" +&avb0_pins { + pins-vddq18-25-avb { + pins = "PIN_VDDQ_AVB0", "PIN_VDDQ_AVB1", "PIN_VDDQ_AVB2", "PIN_VDDQ_TSN0"; + power-source = <1800>; + }; +}; + /* Page 31 / FAN */ &gpio1 { pwm-fan-hog { @@ -44,7 +51,16 @@ &rpc { flash@0 { + /* + * EVTA1 is populated with Spansion S25FS512S + * EVTB1 is populated with Winbond W77Q51NW + */ + compatible = "jedec,spi-nor"; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; }; }; + +&vcc_sdhi { + states = <1800000 0>, <3300000 1>; +}; diff --git a/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi new file mode 100644 index 00000000000..c04d2ae2be4 --- /dev/null +++ b/arch/arm/dts/r8a779h0-gray-hawk-single-u-boot.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Gray Hawk board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include "r8a779h0-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&pfc { + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <40000000>; + status = "disabled"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; +}; diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi b/arch/arm/dts/r8a779h0-u-boot.dtsi new file mode 100644 index 00000000000..40e070be9a8 --- /dev/null +++ b/arch/arm/dts/r8a779h0-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +&rpc { + bank-width = <2>; + num-cs = <1>; +}; diff --git a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi index a0ab8b69f2e..170e0f7d847 100644 --- a/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi +++ b/arch/arm/dts/rk3326-odroid-go2-u-boot.dtsi @@ -3,83 +3,33 @@ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH */ -#include "rockchip-u-boot.dtsi" +#include "rk3326-u-boot.dtsi" -/ { - chosen { - u-boot,spl-boot-order = &sdmmc; - }; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdmmc; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &sfc; - }; - - dmc { - bootph-all; - compatible = "rockchip,px30-dmc", "syscon"; - reg = <0x0 0xff2a0000 0x0 0x1000>; - }; - - rng: rng@ff0b0000 { - compatible = "rockchip,cryptov2-rng"; - reg = <0x0 0xff0b0000 0x0 0x4000>; - status = "okay"; - }; -}; - -/* U-Boot clk driver for px30 cannot set GPU_CLK */ -&cru { - bootph-all; - assigned-clocks = <&cru PLL_NPLL>, - <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, - <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, - <&cru PCLK_BUS_PRE>, <&cru PLL_CPLL>; - - assigned-clock-rates = <1188000000>, - <200000000>, <200000000>, - <150000000>, <150000000>, - <100000000>, <17000000>; -}; - -&gpio0 { - bootph-all; - gpio-ranges = <&pinctrl 0 0 32>; -}; - -&gpio1 { - bootph-all; - gpio-ranges = <&pinctrl 0 32 32>; -}; - -&gpio2 { - bootph-all; - gpio-ranges = <&pinctrl 0 64 32>; +&blue_led { + default-state = "on"; + u-boot,default-brightness = <127>; }; -&gpio3 { - bootph-all; - gpio-ranges = <&pinctrl 0 96 32>; +&i2c0_xfer { + bootph-pre-ram; }; -&grf { - bootph-all; +&i2s1_2ch_mclk { + bootph-pre-ram; }; -&pmucru { - bootph-all; +&pcfg_pull_none_smt { + bootph-pre-ram; }; -&pmugrf { - bootph-all; +&pmic_int { + bootph-pre-ram; }; &rk817 { regulators { + bootph-pre-ram; + vcc_cam: LDO_REG9 { regulator-name = "vcc_cam"; regulator-min-microvolt = <3000000>; @@ -94,35 +44,28 @@ }; &saradc { - bootph-all; - status = "okay"; -}; - -&sdmmc { - bootph-all; - - /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ - u-boot,spl-fifo-mode; + bootph-pre-ram; + vdd-microvolts = <1800000>; }; &sfc { - bootph-all; -}; - -&{/spi@ff3a0000/flash@0} { - bootph-all; + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; }; &uart1 { - clock-frequency = <24000000>; bootph-all; + clock-frequency = <24000000>; }; -&uart2 { - clock-frequency = <24000000>; - bootph-all; +&uart1_cts { + bootph-pre-sram; + bootph-pre-ram; }; -&xin24m { - bootph-all; +&uart1_xfer { + bootph-pre-sram; + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi new file mode 100644 index 00000000000..89b2d9573ad --- /dev/null +++ b/arch/arm/dts/rk3326-odroid-go2-v11-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3326-odroid-go2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi b/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi new file mode 100644 index 00000000000..89b2d9573ad --- /dev/null +++ b/arch/arm/dts/rk3326-odroid-go3-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3326-odroid-go2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3326-u-boot.dtsi b/arch/arm/dts/rk3326-u-boot.dtsi new file mode 100644 index 00000000000..6503a9382b9 --- /dev/null +++ b/arch/arm/dts/rk3326-u-boot.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + */ + +#include "rockchip-u-boot.dtsi" + +/ { + aliases { + spi2 = &sfc; + }; + + chosen { + u-boot,spl-boot-order = "same-as-spl", &sdmmc; + }; + + dmc { + compatible = "rockchip,px30-dmc", "syscon"; + reg = <0x0 0xff2a0000 0x0 0x1000>; + bootph-all; + }; + + rng: rng@ff0b0000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff0b0000 0x0 0x4000>; + }; +}; + +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x10000>; + }; + }; +}; +#endif + +&cru { + bootph-all; +}; + +&gpio0 { + gpio-ranges = <&pinctrl 0 0 32>; +}; + +&gpio1 { + gpio-ranges = <&pinctrl 0 32 32>; +}; + +&gpio2 { + gpio-ranges = <&pinctrl 0 64 32>; +}; + +&gpio3 { + gpio-ranges = <&pinctrl 0 96 32>; +}; + +&grf { + bootph-all; +}; + +&otp { + bootph-some-ram; +}; + +&pcfg_pull_none { + bootph-all; +}; + +&pcfg_pull_none_8ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pcfg_pull_up { + bootph-all; +}; + +&pcfg_pull_up_8ma { + bootph-pre-ram; + bootph-some-ram; +}; + +&pmucru { + bootph-all; +}; + +&pmugrf { + bootph-all; +}; + +&sdmmc { + bootph-pre-ram; + bootph-some-ram; + + /* mmc to sram can't do dma, prevent aborts transferring TF-A parts */ + u-boot,spl-fifo-mode; +}; + +&sdmmc_bus4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_cmd { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdmmc_det { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc { + bootph-some-ram; + u-boot,spl-sfc-no-dma; +}; + +&sfc_bus2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc_clk { + bootph-pre-ram; + bootph-some-ram; +}; + +&sfc_cs0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&uart2 { + bootph-all; + clock-frequency = <24000000>; +}; + +&uart2m1_xfer { + bootph-pre-sram; + bootph-pre-ram; +}; + +&xin24m { + bootph-all; +}; diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi index 582d6ba49b4..c47d29c59de 100644 --- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi +++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi @@ -4,7 +4,7 @@ */ #include "rk3328-u-boot.dtsi" -#include "rk3328-sdram-ddr4-666.dtsi" +#include "rk3328-sdram-ddr4-1600.dtsi" / { smbios { diff --git a/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi new file mode 100644 index 00000000000..9594bb42839 --- /dev/null +++ b/arch/arm/dts/rk3328-sdram-ddr4-1600.dtsi @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xA + 0x2 + 0x1 + 0x0 + 0x0 + 0x11 + 0x0 + 0x11 + 0x0 + 0 + + 0x94496354 + 0x00000000 + 0x0000002a + 0x000004e2 + 0x00000015 + 0x0000034a + 0x000000ff + + 800 + 0 + 1 + 0 + 0 + + 0x00000000 + 0x43041010 + 0x00000064 + 0x0061008c + 0x000000d0 + 0x000200c5 + 0x000000d4 + 0x00500000 + 0x000000d8 + 0x00000100 + 0x000000dc + 0x03140401 + 0x000000e0 + 0x00000000 + 0x000000e4 + 0x00110000 + 0x000000e8 + 0x00000420 + 0x000000ec + 0x00000400 + 0x000000f4 + 0x000f011f + 0x00000100 + 0x0c0e1b0e + 0x00000104 + 0x00030314 + 0x00000108 + 0x0506050b + 0x0000010c + 0x0040400c + 0x00000110 + 0x06030307 + 0x00000114 + 0x04040302 + 0x00000120 + 0x06060b06 + 0x00000124 + 0x00020308 + 0x00000180 + 0x01000040 + 0x00000184 + 0x00000000 + 0x00000190 + 0x07040003 + 0x00000198 + 0x05001100 + 0x000001a0 + 0xc0400003 + 0x00000240 + 0x0600060c + 0x00000244 + 0x00000201 + 0x00000250 + 0x00000f00 + 0x00000490 + 0x00000001 + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + 0xffffffff + + 0x00000004 + 0x0000000c + 0x00000028 + 0x0000000c + 0x0000002c + 0x00000000 + 0x00000030 + 0x00000009 + 0xffffffff + 0xffffffff + + 0x77 + 0x88 + 0x79 + 0x79 + 0x87 + 0x97 + 0x87 + 0x78 + 0x77 + 0x78 + 0x87 + 0x88 + 0x87 + 0x87 + 0x77 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x78 + 0x77 + 0x79 + 0x9 + + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x78 + 0x69 + 0x9 + + 0x77 + 0x78 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x77 + 0x79 + 0x9 + >; +}; diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index b0e50a973a8..8ffc9ed3d57 100644 --- a/arch/arm/dts/rk3328-u-boot.dtsi +++ b/arch/arm/dts/rk3328-u-boot.dtsi @@ -132,6 +132,10 @@ bootph-pre-ram; }; +&spi0 { + bootph-some-ram; +}; + &uart2 { bootph-all; clock-frequency = <24000000>; diff --git a/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi b/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi new file mode 100644 index 00000000000..3e2fbd81da1 --- /dev/null +++ b/arch/arm/dts/rk3528-armsom-sige1-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; diff --git a/arch/arm/dts/rk3528-generic-u-boot.dtsi b/arch/arm/dts/rk3528-generic-u-boot.dtsi index cc830b51456..9e1fb2a7eef 100644 --- a/arch/arm/dts/rk3528-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3528-generic-u-boot.dtsi @@ -1,12 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3528-u-boot.dtsi" - -&sdmmc { - bus-width = <4>; - cap-sd-highspeed; - disable-wp; - no-mmc; - no-sdio; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3528-generic.dts b/arch/arm/dts/rk3528-generic.dts index 3f6f0bed108..637ca03325e 100644 --- a/arch/arm/dts/rk3528-generic.dts +++ b/arch/arm/dts/rk3528-generic.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Minimal generic DT for RK3528 with eMMC enabled + * Minimal generic DT for RK3528 with eMMC and SD-card enabled */ /dts-v1/; @@ -10,6 +10,12 @@ model = "Generic RK3528"; compatible = "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial0 = &uart0; + }; + chosen { stdout-path = "serial0:1500000n8"; }; @@ -25,6 +31,15 @@ status = "okay"; }; +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0m0_xfer>; diff --git a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi index 1372d8f1e38..e8c8dc2f032 100644 --- a/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi +++ b/arch/arm/dts/rk3528-radxa-e20c-u-boot.dtsi @@ -2,15 +2,15 @@ #include "rk3528-u-boot.dtsi" -&sdhci { - mmc-hs200-1_8v; +&saradc { + bootph-pre-ram; + vdd-microvolts = <1800000>; }; -&sdmmc { - bus-width = <4>; - cap-mmc-highspeed; - cap-sd-highspeed; - disable-wp; - vmmc-supply = <&vcc_3v3>; - status = "okay"; +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; }; diff --git a/arch/arm/dts/rk3528-rock-2-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2-u-boot.dtsi new file mode 100644 index 00000000000..e8c8dc2f032 --- /dev/null +++ b/arch/arm/dts/rk3528-rock-2-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-u-boot.dtsi" + +&saradc { + bootph-pre-ram; + vdd-microvolts = <1800000>; +}; + +&vdd_arm { + regulator-init-microvolt = <953000>; +}; + +&vdd_logic { + regulator-init-microvolt = <900000>; +}; diff --git a/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi new file mode 100644 index 00000000000..bd35ef88298 --- /dev/null +++ b/arch/arm/dts/rk3528-rock-2a-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-rock-2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi b/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi new file mode 100644 index 00000000000..bd35ef88298 --- /dev/null +++ b/arch/arm/dts/rk3528-rock-2f-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3528-rock-2-u-boot.dtsi" diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi index eb6a55cd5c9..a18d33b3d36 100644 --- a/arch/arm/dts/rk3528-u-boot.dtsi +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -27,24 +27,6 @@ compatible = "rockchip,rk3528-otp"; reg = <0x0 0xffce0000 0x0 0x4000>; }; - - sdmmc: mmc@ffc30000 { - compatible = "rockchip,rk3528-dw-mshc", - "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xffc30000 0x0 0x4000>; - clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; - clock-names = "biu", "ciu"; - fifo-depth = <0x100>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - max-frequency = <150000000>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, - <&sdmmc_det>; - resets = <&cru SRST_H_SDMMC0>; - reset-names = "reset"; - rockchip,default-sample-phase = <90>; - status = "disabled"; - }; }; }; diff --git a/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi new file mode 100644 index 00000000000..a2b60da6586 --- /dev/null +++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "rk356x-u-boot.dtsi" diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 87186973953..738b9673d35 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -157,6 +157,7 @@ }; &sfc { + bootph-some-ram; u-boot,spl-sfc-no-dma; }; diff --git a/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi new file mode 100644 index 00000000000..7e0530d85d1 --- /dev/null +++ b/arch/arm/dts/rk3576-armsom-sige5-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; +}; + +&red_led { + default-state = "on"; +}; + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3576-generic-u-boot.dtsi b/arch/arm/dts/rk3576-generic-u-boot.dtsi new file mode 100644 index 00000000000..632fabb6af5 --- /dev/null +++ b/arch/arm/dts/rk3576-generic-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" diff --git a/arch/arm/dts/rk3576-generic.dts b/arch/arm/dts/rk3576-generic.dts new file mode 100644 index 00000000000..123be5378d9 --- /dev/null +++ b/arch/arm/dts/rk3576-generic.dts @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Minimal generic DT for RK3576 with eMMC, SD-card and USB OTG enabled + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "rk3576.dtsi" + +/ { + model = "Generic RK3576"; + compatible = "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd0_dwc3 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi b/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi new file mode 100644 index 00000000000..28773696b97 --- /dev/null +++ b/arch/arm/dts/rk3576-luckfox-omni3576-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +&green_led { + default-state = "on"; +}; + +&sdhci { + cap-mmc-highspeed; +}; diff --git a/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi b/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi new file mode 100644 index 00000000000..0767fbb8168 --- /dev/null +++ b/arch/arm/dts/rk3576-nanopi-m5-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +&led1 { + default-state = "off"; +}; + +&led2 { + default-state = "off"; +}; + +&led_sys { + default-state = "on"; +}; + +&sfc1 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi new file mode 100644 index 00000000000..db46553b66a --- /dev/null +++ b/arch/arm/dts/rk3576-rock-4d-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3576-u-boot.dtsi" + +&sfc0 { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi index be99a48a630..dc3771b556a 100644 --- a/arch/arm/dts/rk3576-u-boot.dtsi +++ b/arch/arm/dts/rk3576-u-boot.dtsi @@ -6,6 +6,11 @@ #include "rockchip-u-boot.dtsi" / { + aliases { + spi5 = &sfc0; + spi6 = &sfc1; + }; + chosen { u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci; }; @@ -16,6 +21,17 @@ }; }; +#ifdef CONFIG_ROCKCHIP_SPI_IMAGE +&binman { + simple-bin-spi { + mkimage { + args = "-n", CONFIG_SYS_SOC, "-T", "rksd"; + offset = <0x8000>; + }; + }; +}; +#endif + &cru { bootph-all; }; @@ -45,10 +61,34 @@ bootph-some-ram; }; +&fspi0_csn0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&fspi0_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&fspi1m1_csn0 { + bootph-pre-ram; + bootph-some-ram; +}; + +&fspi1m1_pins { + bootph-pre-ram; + bootph-some-ram; +}; + &ioc_grf { bootph-all; }; +&otp { + bootph-some-ram; +}; + &pcfg_pull_none { bootph-all; }; @@ -112,6 +152,16 @@ bootph-some-ram; }; +&sfc0 { + bootph-some-ram; + u-boot,spl-sfc-no-dma; +}; + +&sfc1 { + bootph-some-ram; + u-boot,spl-sfc-no-dma; +}; + &sys_grf { bootph-all; }; diff --git a/arch/arm/dts/rk3588-generic-u-boot.dtsi b/arch/arm/dts/rk3588-generic-u-boot.dtsi index f67301d87a6..853ed58cfe5 100644 --- a/arch/arm/dts/rk3588-generic-u-boot.dtsi +++ b/arch/arm/dts/rk3588-generic-u-boot.dtsi @@ -1,21 +1,3 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) #include "rk3588s-u-boot.dtsi" - -&u2phy0 { - status = "okay"; -}; - -&u2phy0_otg { - status = "okay"; -}; - -&usbdp_phy0 { - status = "okay"; -}; - -&usb_host0_xhci { - dr_mode = "peripheral"; - maximum-speed = "high-speed"; - status = "okay"; -}; diff --git a/arch/arm/dts/rk3588-generic.dts b/arch/arm/dts/rk3588-generic.dts index 95d757676f1..6740f9866f1 100644 --- a/arch/arm/dts/rk3588-generic.dts +++ b/arch/arm/dts/rk3588-generic.dts @@ -39,7 +39,23 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_xhci { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; diff --git a/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi new file mode 100644 index 00000000000..1ab31a4ec5a --- /dev/null +++ b/arch/arm/dts/rk3588-orangepi-5-ultra-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588-u-boot.dtsi" + +&fspim1_pins { + bootph-pre-ram; + bootph-some-ram; +}; + +&sdhci { + cap-mmc-highspeed; + mmc-hs200-1_8v; +}; + +&sfc { + flash@0 { + bootph-pre-ram; + bootph-some-ram; + }; +}; diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index 5eeb138f351..71fd352f640 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -140,6 +140,7 @@ }; &sfc { + bootph-some-ram; u-boot,spl-sfc-no-dma; }; diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts index 90e3405040a..6c15a87ffb0 100644 --- a/arch/arm/dts/s5pc1xx-goni.dts +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -45,7 +45,7 @@ compatible = "maxim,max8998"; reg = <0x66 0 0>; - voltage-regulators { + regulators { ldo2_reg: LDO2 { regulator-compatible = "LDO2"; regulator-name = "VALIVE_1.1V"; diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi b/arch/arm/dts/sam9x60ek-u-boot.dtsi index fd2afa8a2fa..ef329b33b7e 100644 --- a/arch/arm/dts/sam9x60ek-u-boot.dtsi +++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi @@ -8,6 +8,7 @@ / { chosen { bootph-all; + tick-timer = &pit; }; ahb { diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 4d7680455b7..770f6cad292 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -3,20 +3,40 @@ * U-Boot additions * * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ +#include "socfpga_soc64_u-boot.dtsi" #include "socfpga_soc64_fit-u-boot.dtsi" /{ - memory { + aliases { + spi0 = &qspi; + i2c0 = &i2c1; + sysmgr = &sysmgr; + freeze_br0 = &freeze_controller; + }; + + memory@0 { + device_type = "memory"; #address-cells = <2>; #size-cells = <2>; bootph-all; }; - soc { + pmu { + compatible = "arm,armv8-pmuv3"; + }; + + soc@0 { bootph-all; + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; + ccu: cache-controller@f7000000 { compatible = "arteris,ncore-ccu"; reg = <0xf7000000 0x100900>; @@ -29,11 +49,39 @@ bootph-all; }; +&gmac0 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr AGILEX_EMAC0_CLK>; + clock-names = "stmmaceth"; + phy-mode = "rgmii"; + max-frame-size = <0x2328>; + status = "okay"; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + &gmac1 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reset-names = "stmmaceth", "stmmaceth-ocp"; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + clocks = <&clkmgr AGILEX_EMAC1_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; altr,sysmgr-syscon = <&sysmgr 0x48 0>; }; &gmac2 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reset-names = "stmmaceth", "stmmaceth-ocp"; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + clocks = <&clkmgr AGILEX_EMAC2_CLK>; + clock-names = "stmmaceth"; + status = "disabled"; altr,sysmgr-syscon = <&sysmgr 0x4c 0>; }; @@ -43,6 +91,7 @@ &i2c1 { reset-names = "i2c"; + status = "okay"; }; &i2c2 { @@ -67,6 +116,15 @@ &qspi { bootph-all; + compatible = "cdns,qspi-nor"; + flash0: flash@0 { + }; +}; + +&flash0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; }; &rst { @@ -84,6 +142,79 @@ bootph-all; }; +&socfpga_l3interconnect_firewall { + CCU_coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 { + reg = <0xf7100200 0x00000014>; + intel,offset-settings = + /* Disable ocram security at CCU for non secure access */ + <0x0000004 0x8000ffff 0xe003ffff>, + <0x0000008 0x8000ffff 0xe003ffff>, + <0x000000c 0x8000ffff 0xe003ffff>, + <0x0000010 0x8000ffff 0xe003ffff>; + bootph-all; + }; + + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + reg = <0xf8020000 0x0000001c>; + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>, + /* Disable MPFE firewall for HMC adapter */ + <0x00000004 0x00000001 0x00010101>; + bootph-all; + }; + + /* + * Below are all fpga2sdram firewall settings with default + * reset value for the sake of easy reference by users. + * Users may choose to remove any of these register + * configurations that they do not require in their specific + * implementation. + */ + soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr@f8020100 { + reg = <0xf8020100 0x00000050>; + intel,offset-settings = + <0x0000000 0x00000000 0x0000000f>, + <0x0000004 0x00000000 0x0000000f>, + <0x0000008 0x00000000 0x0000000f>, + <0x0000010 0x00000000 0xffff0000>, + <0x0000014 0x00000000 0x000000ff>, + <0x0000018 0x00000000 0xffff0000>, + <0x000001c 0x00000000 0x000000ff>, + <0x0000020 0x00000000 0xffff0000>, + <0x0000024 0x00000000 0x000000ff>, + <0x0000028 0x00000000 0xffff0000>, + <0x000002c 0x00000000 0x000000ff>, + <0x0000030 0x00000000 0xffff0000>, + <0x0000034 0x00000000 0x000000ff>, + <0x0000038 0x00000000 0xffff0000>, + <0x000003c 0x00000000 0x000000ff>, + <0x0000040 0x00000000 0xffff0000>, + <0x0000044 0x00000000 0x000000ff>, + <0x0000048 0x00000000 0xffff0000>, + <0x000004c 0x00000000 0x000000ff>; + bootph-all; + }; + + /* + * Example of ccu_mem0_I_main QOS settings with + * default reset value for the sake of easy reference + * by users. Users may choose to remove any of these register + * configurations that they do not require in their specific + * implementation. + */ + soc_mpfe_noc_inst_0_ccu_mem0_I_main_QosGenerator@f8022080 { + reg = <0xf8022080 0x0000001c>; + intel,offset-settings = + <0x0000008 0x00000200 0x00000303>, + <0x000000c 0x00000003 0x00000003>, + <0x0000010 0x00000BFE 0x00007fff>, + <0x0000014 0x00000008 0x000003ff>, + <0x0000018 0x00000000 0x0000000f>; + bootph-all; + }; +}; + &sysmgr { compatible = "altr,sys-mgr", "syscon"; bootph-all; @@ -91,8 +222,51 @@ &uart0 { bootph-all; + clock-frequency = <100000000>; }; &watchdog0 { bootph-all; }; + +&nand { + clocks = <&clkmgr AGILEX_NAND_CLK>, + <&clkmgr AGILEX_NAND_X_CLK>; + clock-names = "nand", "nand_x"; +}; + +&usb0 { + compatible = "snps,dwc2"; +}; + +&usb1 { + compatible = "snps,dwc2"; +}; + +&spi0 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; +}; + +&spi1 { + compatible = "intel,agilex-spi", + "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; +}; + +&pdma { + #dma-channels = <8>; + #dma-requests = <32>; +}; + +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&binman { + /delete-node/ kernel; +}; +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +&sdr { + compatible = "intel,sdr-ctl-agilex7m"; + reg = <0xf8020000 0x100>; +}; +#endif diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi deleted file mode 100644 index 712304d07a4..00000000000 --- a/arch/arm/dts/socfpga_agilex.dtsi +++ /dev/null @@ -1,624 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019-2023 Intel Corporation <www.intel.com> - */ - -/dts-v1/; -#include <dt-bindings/reset/altr,rst-mgr-s10.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clock/agilex-clock.h> - -/ { - compatible = "intel,socfpga-agilex"; - #address-cells = <2>; - #size-cells = <2>; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible = "shared-dma-pool"; - reg = <0x0 0x0 0x0 0x2000000>; - alignment = <0x1000>; - no-map; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - enable-method = "psci"; - reg = <0x3>; - }; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <0 170 4>, - <0 171 4>, - <0 172 4>, - <0 173 4>; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - interrupt-parent = <&intc>; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - intc: intc@fffc1000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0xfffc1000 0x0 0x1000>, - <0x0 0xfffc2000 0x0 0x2000>, - <0x0 0xfffc4000 0x0 0x2000>, - <0x0 0xfffc6000 0x0 0x2000>; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - device_type = "soc"; - interrupt-parent = <&intc>; - ranges = <0 0 0 0xffffffff>; - - base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - compatible = "fpga-region"; - fpga-mgr = <&fpga_mgr>; - }; - - clkmgr: clock-controller@ffd10000 { - compatible = "intel,agilex-clkmgr"; - reg = <0xffd10000 0x1000>; - #clock-cells = <1>; - }; - - clocks { - cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - cb_intosc_ls_clk: cb-intosc-ls-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - f2s_free_clk: f2s-free-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - osc1: osc1 { - #clock-cells = <0>; - compatible = "fixed-clock"; - }; - - qspi_clk: qspi-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <200000000>; - }; - }; - gmac0: ethernet@ff800000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff800000 0x2000>; - interrupts = <0 90 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 1>; - altr,sysmgr-syscon = <&sysmgr 0x44 0>; - clocks = <&clkmgr AGILEX_EMAC0_CLK>; - clock-names = "stmmaceth"; - status = "disabled"; - }; - - gmac1: ethernet@ff802000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff802000 0x2000>; - interrupts = <0 91 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 2>; - altr,sysmgr-syscon = <&sysmgr 0x48 8>; - clocks = <&clkmgr AGILEX_EMAC1_CLK>; - clock-names = "stmmaceth"; - status = "disabled"; - }; - - gmac2: ethernet@ff804000 { - compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; - reg = <0xff804000 0x2000>; - interrupts = <0 92 4>; - interrupt-names = "macirq"; - mac-address = [00 00 00 00 00 00]; - resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; - tx-fifo-depth = <16384>; - rx-fifo-depth = <16384>; - snps,multicast-filter-bins = <256>; - iommus = <&smmu 3>; - altr,sysmgr-syscon = <&sysmgr 0x4c 16>; - clocks = <&clkmgr AGILEX_EMAC2_CLK>; - clock-names = "stmmaceth"; - status = "disabled"; - }; - - gpio0: gpio@ffc03200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03200 0x100>; - resets = <&rst GPIO0_RESET>; - status = "disabled"; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 110 4>; - }; - }; - - gpio1: gpio@ffc03300 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dw-apb-gpio"; - reg = <0xffc03300 0x100>; - resets = <&rst GPIO1_RESET>; - status = "disabled"; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - snps,nr-gpios = <24>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 111 4>; - }; - }; - - i2c0: i2c@ffc02800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02800 0x100>; - interrupts = <0 103 4>; - resets = <&rst I2C0_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c1: i2c@ffc02900 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02900 0x100>; - interrupts = <0 104 4>; - resets = <&rst I2C1_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c2: i2c@ffc02a00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02a00 0x100>; - interrupts = <0 105 4>; - resets = <&rst I2C2_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c3: i2c@ffc02b00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02b00 0x100>; - interrupts = <0 106 4>; - resets = <&rst I2C3_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - i2c4: i2c@ffc02c00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,designware-i2c"; - reg = <0xffc02c00 0x100>; - interrupts = <0 107 4>; - resets = <&rst I2C4_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - mmc: dwmmc0@ff808000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-dw-mshc"; - reg = <0xff808000 0x1000>; - interrupts = <0 96 4>; - fifo-depth = <0x400>; - resets = <&rst SDMMC_RESET>; - reset-names = "reset"; - clocks = <&clkmgr AGILEX_L4_MP_CLK>, - <&clkmgr AGILEX_SDMMC_CLK>; - clock-names = "biu", "ciu"; - iommus = <&smmu 5>; - status = "disabled"; - }; - - nand: nand@ffb90000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xffb90000 0x10000>, - <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - interrupts = <0 97 4>; - resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; - status = "disabled"; - }; - - ocram: sram@ffe00000 { - compatible = "mmio-sram"; - reg = <0xffe00000 0x40000>; - }; - - pdma: pdma@ffda0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0xffda0000 0x1000>; - interrupts = <0 81 4>, - <0 82 4>, - <0 83 4>, - <0 84 4>, - <0 85 4>, - <0 86 4>, - <0 87 4>, - <0 88 4>, - <0 89 4>; - #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; - resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; - reset-names = "dma", "dma-ocp"; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - clock-names = "apb_pclk"; - }; - - rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; - reg = <0xffd11000 0x100>; - }; - - smmu: iommu@fa000000 { - compatible = "arm,mmu-500", "arm,smmu-v2"; - reg = <0xfa000000 0x40000>; - #global-interrupts = <2>; - #iommu-cells = <1>; - interrupt-parent = <&intc>; - interrupts = <0 128 4>, /* Global Secure Fault */ - <0 129 4>, /* Global Non-secure Fault */ - /* Non-secure Context Interrupts (32) */ - <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, - <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, - <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, - <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, - <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, - <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, - <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, - <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; - stream-match-mask = <0x7ff0>; - status = "disabled"; - }; - - spi0: spi@ffda4000 { - compatible = "intel,agilex-spi", - "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda4000 0x1000>; - interrupts = <0 99 4>; - resets = <&rst SPIM0_RESET>; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - status = "disabled"; - }; - - spi1: spi@ffda5000 { - compatible = "intel,agilex-spi", - "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xffda5000 0x1000>; - interrupts = <0 100 4>; - resets = <&rst SPIM1_RESET>; - reg-io-width = <4>; - num-cs = <4>; - clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; - status = "disabled"; - }; - - sysmgr: sysmgr@ffd12000 { - compatible = "altr,sys-mgr-s10","altr,sys-mgr"; - reg = <0xffd12000 0x500>; - }; - - /* Local timer */ - timer { - compatible = "arm,armv8-timer"; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; - }; - - timer0: timer0@ffc03000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 113 4>; - reg = <0xffc03000 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer1: timer1@ffc03100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 114 4>; - reg = <0xffc03100 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer2: timer2@ffd00000 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 115 4>; - reg = <0xffd00000 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - timer3: timer3@ffd00100 { - compatible = "snps,dw-apb-timer"; - interrupts = <0 116 4>; - reg = <0xffd00100 0x100>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-names = "timer"; - }; - - uart0: serial0@ffc02000 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02000 0x100>; - interrupts = <0 108 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART0_RESET>; - status = "disabled"; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - clock-frequency = <100000000>; - }; - - uart1: serial1@ffc02100 { - compatible = "snps,dw-apb-uart"; - reg = <0xffc02100 0x100>; - interrupts = <0 109 4>; - reg-shift = <2>; - reg-io-width = <4>; - resets = <&rst UART1_RESET>; - clocks = <&clkmgr AGILEX_L4_SP_CLK>; - status = "disabled"; - }; - - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - - usb0: usb@ffb00000 { - compatible = "snps,dwc2"; - reg = <0xffb00000 0x40000>; - interrupts = <0 93 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - clocks = <&clkmgr AGILEX_USB_CLK>; - iommus = <&smmu 6>; - status = "disabled"; - }; - - usb1: usb@ffb40000 { - compatible = "snps,dwc2"; - reg = <0xffb40000 0x40000>; - interrupts = <0 94 4>; - phys = <&usbphy0>; - phy-names = "usb2-phy"; - resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; - reset-names = "dwc2", "dwc2-ecc"; - iommus = <&smmu 7>; - clocks = <&clkmgr AGILEX_USB_CLK>; - status = "disabled"; - }; - - watchdog0: watchdog@ffd00200 { - compatible = "snps,dw-wdt"; - reg = <0xffd00200 0x100>; - interrupts = <0 117 4>; - resets = <&rst WATCHDOG0_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog1: watchdog@ffd00300 { - compatible = "snps,dw-wdt"; - reg = <0xffd00300 0x100>; - interrupts = <0 118 4>; - resets = <&rst WATCHDOG1_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog2: watchdog@ffd00400 { - compatible = "snps,dw-wdt"; - reg = <0xffd00400 0x100>; - interrupts = <0 125 4>; - resets = <&rst WATCHDOG2_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - watchdog3: watchdog@ffd00500 { - compatible = "snps,dw-wdt"; - reg = <0xffd00500 0x100>; - interrupts = <0 126 4>; - resets = <&rst WATCHDOG3_RESET>; - clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; - status = "disabled"; - }; - - sdr: sdr@f8011100 { - compatible = "altr,sdr-ctl", "syscon"; - reg = <0xf8011100 0xc0>; - }; - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager", - "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 15 4>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - altr,sdr-syscon = <&sdr>; - interrupts = <16 4>; - }; - - ocram-ecc@ff8cc000 { - compatible = "altr,socfpga-s10-ocram-ecc", - "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8cc000 0x100>; - altr,ecc-parent = <&ocram>; - interrupts = <1 4>; - }; - - usb0-ecc@ff8c4000 { - compatible = "altr,socfpga-s10-usb-ecc", - "altr,socfpga-usb-ecc"; - reg = <0xff8c4000 0x100>; - altr,ecc-parent = <&usb0>; - interrupts = <2 4>; - }; - - emac0-rx-ecc@ff8c0000 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0000 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 4>; - }; - - emac0-tx-ecc@ff8c0400 { - compatible = "altr,socfpga-s10-eth-mac-ecc", - "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0400 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 4>; - }; - - sdmmca-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc", - "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 4>, - <15 4>; - }; - }; - - qspi: spi@ff8d2000 { - compatible = "cdns,qspi-nor"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xff8d2000 0x100>, - <0xff900000 0x100000>; - interrupts = <0 3 4>; - cdns,fifo-depth = <128>; - cdns,fifo-width = <4>; - cdns,trigger-address = <0x00000000>; - clocks = <&qspi_clk>; - - status = "disabled"; - }; - - firmware { - svc { - compatible = "intel,stratix10-svc"; - method = "smc"; - memory-region = <&service_reserved>; - - fpga_mgr: fpga-mgr { - compatible = "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; - }; -}; diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index 402f0bec173..d51a9e2ff7f 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -209,7 +209,7 @@ /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, <0x00000300 0x00000003 0x00000003>, - <0x00000308 0x00000004 0x0000001F>; + <0x00000308 0x0000000C 0x0000001F>; bootph-all; }; @@ -220,7 +220,7 @@ /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, <0x00000300 0x00000003 0x00000003>, - <0x00000308 0x00000004 0x0000001F>; + <0x00000308 0x0000000C 0x0000001F>; bootph-all; }; }; diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi index 9bc3864022b..7f4266dd5f1 100644 --- a/arch/arm/dts/socfpga_agilex5.dtsi +++ b/arch/arm/dts/socfpga_agilex5.dtsi @@ -596,4 +596,8 @@ }; }; }; + + aliases { + sysmgr = &sysmgr; + }; }; diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts index 2ab143e38f8..886cc89fdb6 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk.dts +++ b/arch/arm/dts/socfpga_agilex5_socdk.dts @@ -87,6 +87,10 @@ disable-over-current; }; +&usb31 { + status = "okay"; +}; + &watchdog0 { status = "okay"; }; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 63df28e8364..6f2fe7bf746 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -3,41 +3,139 @@ * U-Boot additions * * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #include "socfpga_agilex-u-boot.dtsi" +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX /{ - aliases { - spi0 = &qspi; - i2c0 = &i2c1; - freeze_br0 = &freeze_controller; + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,&nand; }; - soc { - freeze_controller: freeze_controller@f9000450 { - compatible = "altr,freeze-bridge-controller"; - reg = <0xf9000450 0x00000010>; - status = "disabled"; - }; - }; - - memory { + memory@0 { /* 8GB */ reg = <0 0x00000000 0 0x80000000>, <2 0x80000000 1 0x80000000>; }; }; -&flash0 { - compatible = "jedec,spi-nor"; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - bootph-all; +&qspi { + status = "okay"; +}; +#endif + +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +/{ + model = "SoCFPGA Agilex7-M SoCDK"; + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc; + }; + + memory@0 { + /* + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>; + * }; + * + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>, + * <0x1 0x00000000 0x1 0x80000000>; + * }; + * + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x00000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x00000000 0x0 0x80000000>, + * <0x1 0x00000000 0x1 0x40000000>; + * }; + */ + + /* Default memory size is 2GB */ + reg = <0x0 0x00000000 0x0 0x80000000>; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy2: ethernet-phy@2 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&qspi { + status = "disabled"; +}; + +&socfpga_l3interconnect_firewall { + soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f8020000 { + intel,offset-settings = + /* Disable MPFE firewall for SMMU */ + <0x00000000 0x00010101 0x00010101>; + }; +}; +#endif + +&gmac0 { + mdio0 { + ethernet_phy0: ethernet-phy@0 { + reg = <4>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + rxd0-skew-ps = <0x1a4>; + rxd1-skew-ps = <0x1a4>; + rxd2-skew-ps = <0x1a4>; + rxd3-skew-ps = <0x1a4>; + txen-skew-ps = <0>; + txc-skew-ps = <0x384>; + rxdv-skew-ps = <0x1a4>; + rxc-skew-ps = <0x690>; + }; + }; }; -&i2c1 { +&nand { status = "okay"; + nand-bus-width = <16>; + bootph-all; }; &mmc { @@ -47,9 +145,39 @@ }; &qspi { - status = "okay"; + /delete-property/ clocks; }; -&watchdog0 { +&flash0 { + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-max-frequency = <100000000>; bootph-all; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + /delete-property/ cdns,read-delay; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x04200000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x04200000 0x0BE00000>; + }; + }; }; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex_socdk.dts deleted file mode 100644 index bcdeecc0e02..00000000000 --- a/arch/arm/dts/socfpga_agilex_socdk.dts +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019, Intel Corporation - */ -#include "socfpga_agilex.dtsi" - -/ { - model = "SoCFPGA Agilex SoCDK"; - - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - ethernet2 = &gmac2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - hps0 { - label = "hps_led0"; - gpios = <&portb 20 GPIO_ACTIVE_HIGH>; - }; - - hps1 { - label = "hps_led1"; - gpios = <&portb 19 GPIO_ACTIVE_HIGH>; - }; - - hps2 { - label = "hps_led2"; - gpios = <&portb 21 GPIO_ACTIVE_HIGH>; - }; - }; - - memory { - device_type = "memory"; - /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; - }; - - soc { - clocks { - osc1 { - clock-frequency = <25000000>; - }; - }; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&gmac0 { - status = "okay"; - phy-mode = "rgmii"; - phy-handle = <&phy0>; - - max-frame-size = <9000>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <4>; - - txd0-skew-ps = <0>; /* -420ps */ - txd1-skew-ps = <0>; /* -420ps */ - txd2-skew-ps = <0>; /* -420ps */ - txd3-skew-ps = <0>; /* -420ps */ - rxd0-skew-ps = <420>; /* 0ps */ - rxd1-skew-ps = <420>; /* 0ps */ - rxd2-skew-ps = <420>; /* 0ps */ - rxd3-skew-ps = <420>; /* 0ps */ - txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <900>; /* 0ps */ - rxdv-skew-ps = <420>; /* 0ps */ - rxc-skew-ps = <1680>; /* 780ps */ - }; - }; -}; - -&mmc { - status = "okay"; - cap-sd-highspeed; - broken-cd; - bus-width = <4>; -}; - -&uart0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; - disable-over-current; -}; - -&watchdog0 { - status = "okay"; -}; - -&qspi { - flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mt25qu02g"; - reg = <0>; - spi-max-frequency = <100000000>; - - m25p,fast-read; - cdns,page-size = <256>; - cdns,block-size = <16>; - cdns,read-delay = <1>; - cdns,tshsl-ns = <50>; - cdns,tsd2d-ns = <50>; - cdns,tchsh-ns = <4>; - cdns,tslch-ns = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - qspi_boot: partition@0 { - label = "Boot and fpga data"; - reg = <0x0 0x034B0000>; - }; - - qspi_rootfs: partition@34B0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x034B0000 0x0EB50000>; - }; - }; - }; -}; diff --git a/arch/arm/dts/socfpga_soc64_u-boot.dtsi b/arch/arm/dts/socfpga_soc64_u-boot.dtsi new file mode 100644 index 00000000000..ce5b37ef547 --- /dev/null +++ b/arch/arm/dts/socfpga_soc64_u-boot.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +/ { + soc@0 { + socfpga-system-mgr-firewall { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + i_sys_mgr_core@ffd12000 { + reg = <0xffd12000 0x00000230>; + intel,offset-settings = + /* Enable non-secure interface to DMA */ + <0x00000020 0xff010000 0xff010011>, + /* Enable non-secure interface to DMA periph */ + <0x00000024 0xffffffff 0xffffffff>; + bootph-all; + }; + }; + + socfpga_l3interconnect_firewall:socfpga-l3interconnect-firewall { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + noc_fw_l4_per_l4_per_scr@ffd21000 { + reg = <0xffd21000 0x00000074>; + intel,offset-settings = + /* Disable L4 periphs firewall */ + <0x00000000 0x01010001 0x01010001>, + <0x00000004 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010101>, + <0x00000020 0x01010001 0x01010101>, + <0x00000024 0x01010001 0x01010101>, + <0x00000028 0x01010001 0x01010101>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010101>, + <0x00000048 0x01010001 0x01010101>, + <0x00000050 0x01010001 0x01010101>, + <0x00000054 0x01010001 0x01010101>, + <0x00000058 0x01010001 0x01010101>, + <0x0000005c 0x01010001 0x01010101>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>; + bootph-all; + }; + + noc_fw_l4_sys_l4_sys_scr@ffd21100 { + reg = <0xffd21100 0x00000098>; + intel,offset-settings = + /* Disable L4 system firewall */ + <0x00000008 0x01010001 0x01010001>, + <0x0000000c 0x01010001 0x01010001>, + <0x00000010 0x01010001 0x01010001>, + <0x00000014 0x01010001 0x01010001>, + <0x00000018 0x01010001 0x01010001>, + <0x0000001c 0x01010001 0x01010001>, + <0x00000020 0x01010001 0x01010001>, + <0x0000002c 0x01010001 0x01010001>, + <0x00000030 0x01010001 0x01010001>, + <0x00000034 0x01010001 0x01010001>, + <0x00000038 0x01010001 0x01010001>, + <0x00000040 0x01010001 0x01010001>, + <0x00000044 0x01010001 0x01010001>, + <0x00000048 0x01010001 0x01010001>, + <0x0000004c 0x01010001 0x01010001>, + <0x00000054 0x01010001 0x01010001>, + <0x00000058 0x01010001 0x01010001>, + <0x0000005c 0x01010001 0x01010001>, + <0x00000060 0x01010001 0x01010101>, + <0x00000064 0x01010001 0x01010101>, + <0x00000068 0x01010001 0x01010101>, + <0x0000006c 0x01010001 0x01010101>, + <0x00000070 0x01010001 0x01010101>, + <0x00000074 0x01010001 0x01010101>, + <0x00000078 0x01010001 0x03010001>, + <0x00000090 0x01010001 0x01010001>, + <0x00000094 0x01010001 0x01010001>; + bootph-all; + }; + + noc_fw_soc2fpga_soc2fpga_scr@ffd21200 { + reg = <0xffd21200 0x00000004>; + /* Disable soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + bootph-all; + }; + + noc_fw_lwsoc2fpga_lwsoc2fpga_scr@ffd21300 { + reg = <0xffd21300 0x00000004>; + /* Disable lightweight soc2fpga security access */ + intel,offset-settings = <0x00000000 0x0ffe0101 0x0ffe0101>; + bootph-all; + }; + + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + /* Disable DMA ECC security access, for SMMU use */ + intel,offset-settings = <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + + noc_fw_priv_MemoryMap_priv@ffd24800 { + reg = <0xffd24800 0x0000000c>; + intel,offset-settings = + /* Enable non-prviledged access to various periphs */ + <0x00000000 0xfff73ffb 0xfff73ffb>; + bootph-all; + }; + }; + + socfpga_smmu_secure_config: socfpga-smmu-secure-config { + compatible = "intel,socfpga-dtreg"; + #address-cells = <1>; + #size-cells = <1>; + bootph-all; + + /* TCU */ + noc_fw_tcu_tcu_scr@ffd21400 { + reg = <0xffd21400 0x00000004>; + intel,offset-settings = + <0x00000000 0x01010001 0x01010001>; + bootph-all; + }; + + /* System manager */ + i_sys_mgt_sysmgr_csr@ffd12000 { + reg = <0xffd12000 0x00000500>; + intel,offset-settings = + /* i_sys_mgr_core_emac0 */ + <0x00000044 0x0a000000 0xffff0103>, + /* i_sys_mgr_core_emac1 */ + <0x00000048 0x0a000000 0xffff0103>, + /* i_sys_mgr_core_emac2 */ + <0x0000004c 0x0a000000 0xffff0103>, + /* i_sys_mgr_core_nand_l3master */ + <0x00000034 0x00220000 0x007733ff>, + /* i_sys_mgr_core_sdmmc_l3master */ + <0x0000002c 0x00000020 0x03ff03ff>, + /* i_sys_mgr_core_usb0_l3master */ + <0x00000038 0x00000200 0x03ff30ff>, + /* i_sys_mgr_core_usb1_l3master */ + <0x0000003c 0x00000200 0x03ff30ff>; + bootph-all; + }; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index eb82d663204..ea80d1bed15 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -232,6 +232,18 @@ status = "disabled"; }; + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index e6d8fe6a907..864f4093ef8 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -137,3 +137,7 @@ &usb0 { status = "okay"; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp1-ddr.dtsi b/arch/arm/dts/stm32mp1-ddr.dtsi new file mode 100644 index 00000000000..748271c546d --- /dev/null +++ b/arch/arm/dts/stm32mp1-ddr.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2018-2025 + */ +#include <linux/stringify.h> + +#ifdef CONFIG_SPL +&ddr { + config-DDR_MEM_COMPATIBLE { + bootph-all; + + compatible = __stringify(st,DDR_MEM_COMPATIBLE); + + st,mem-name = DDR_MEM_NAME; + st,mem-speed = <DDR_MEM_SPEED>; + st,mem-size = <DDR_MEM_SIZE>; + + st,ctl-reg = < + DDR_MSTR + DDR_MRCTRL0 + DDR_MRCTRL1 + DDR_DERATEEN + DDR_DERATEINT + DDR_PWRCTL + DDR_PWRTMG + DDR_HWLPCTL + DDR_RFSHCTL0 + DDR_RFSHCTL3 + DDR_CRCPARCTL0 + DDR_ZQCTL0 + DDR_DFITMG0 + DDR_DFITMG1 + DDR_DFILPCFG0 + DDR_DFIUPD0 + DDR_DFIUPD1 + DDR_DFIUPD2 + DDR_DFIPHYMSTR + DDR_ODTMAP + DDR_DBG0 + DDR_DBG1 + DDR_DBGCMD + DDR_POISONCFG + DDR_PCCFG + >; + + st,ctl-timing = < + DDR_RFSHTMG + DDR_DRAMTMG0 + DDR_DRAMTMG1 + DDR_DRAMTMG2 + DDR_DRAMTMG3 + DDR_DRAMTMG4 + DDR_DRAMTMG5 + DDR_DRAMTMG6 + DDR_DRAMTMG7 + DDR_DRAMTMG8 + DDR_DRAMTMG14 + DDR_ODTCFG + >; + + st,ctl-map = < + DDR_ADDRMAP1 + DDR_ADDRMAP2 + DDR_ADDRMAP3 + DDR_ADDRMAP4 + DDR_ADDRMAP5 + DDR_ADDRMAP6 + DDR_ADDRMAP9 + DDR_ADDRMAP10 + DDR_ADDRMAP11 + >; + + + /* + * Both st,ctl-perf and st,phy-reg differ + * between STM32MP13xx and STM32MP15xx due + * to 16bit and 32bit DRAM bus respectively + * on these SoCs. + */ + + st,phy-timing = < + DDR_PTR0 + DDR_PTR1 + DDR_PTR2 + DDR_DTPR0 + DDR_DTPR1 + DDR_DTPR2 + DDR_MR0 + DDR_MR1 + DDR_MR2 + DDR_MR3 + >; + + status = "okay"; + }; +}; +#endif + +#undef DDR_MEM_COMPATIBLE +#undef DDR_MEM_NAME +#undef DDR_MEM_SPEED +#undef DDR_MEM_SIZE + +#undef DDR_MSTR +#undef DDR_MRCTRL0 +#undef DDR_MRCTRL1 +#undef DDR_DERATEEN +#undef DDR_DERATEINT +#undef DDR_PWRCTL +#undef DDR_PWRTMG +#undef DDR_HWLPCTL +#undef DDR_RFSHCTL0 +#undef DDR_RFSHCTL3 +#undef DDR_RFSHTMG +#undef DDR_CRCPARCTL0 +#undef DDR_DRAMTMG0 +#undef DDR_DRAMTMG1 +#undef DDR_DRAMTMG2 +#undef DDR_DRAMTMG3 +#undef DDR_DRAMTMG4 +#undef DDR_DRAMTMG5 +#undef DDR_DRAMTMG6 +#undef DDR_DRAMTMG7 +#undef DDR_DRAMTMG8 +#undef DDR_DRAMTMG14 +#undef DDR_ZQCTL0 +#undef DDR_DFITMG0 +#undef DDR_DFITMG1 +#undef DDR_DFILPCFG0 +#undef DDR_DFIUPD0 +#undef DDR_DFIUPD1 +#undef DDR_DFIUPD2 +#undef DDR_DFIPHYMSTR +#undef DDR_ADDRMAP1 +#undef DDR_ADDRMAP2 +#undef DDR_ADDRMAP3 +#undef DDR_ADDRMAP4 +#undef DDR_ADDRMAP5 +#undef DDR_ADDRMAP6 +#undef DDR_ADDRMAP9 +#undef DDR_ADDRMAP10 +#undef DDR_ADDRMAP11 +#undef DDR_ODTCFG +#undef DDR_ODTMAP +#undef DDR_SCHED +#undef DDR_SCHED1 +#undef DDR_PERFHPR1 +#undef DDR_PERFLPR1 +#undef DDR_PERFWR1 +#undef DDR_DBG0 +#undef DDR_DBG1 +#undef DDR_DBGCMD +#undef DDR_POISONCFG +#undef DDR_PCCFG +#undef DDR_PCFGR_0 +#undef DDR_PCFGW_0 +#undef DDR_PCFGQOS0_0 +#undef DDR_PCFGQOS1_0 +#undef DDR_PCFGWQOS0_0 +#undef DDR_PCFGWQOS1_0 +#undef DDR_PCFGR_1 +#undef DDR_PCFGW_1 +#undef DDR_PCFGQOS0_1 +#undef DDR_PCFGQOS1_1 +#undef DDR_PCFGWQOS0_1 +#undef DDR_PCFGWQOS1_1 +#undef DDR_PGCR +#undef DDR_PTR0 +#undef DDR_PTR1 +#undef DDR_PTR2 +#undef DDR_ACIOCR +#undef DDR_DXCCR +#undef DDR_DSGCR +#undef DDR_DCR +#undef DDR_DTPR0 +#undef DDR_DTPR1 +#undef DDR_DTPR2 +#undef DDR_MR0 +#undef DDR_MR1 +#undef DDR_MR2 +#undef DDR_MR3 +#undef DDR_ODTCR +#undef DDR_ZQ0CR1 +#undef DDR_DX0GCR +#undef DDR_DX1GCR +#undef DDR_DX2GCR +#undef DDR_DX3GCR diff --git a/arch/arm/dts/stm32mp13-ddr.dtsi b/arch/arm/dts/stm32mp13-ddr.dtsi new file mode 100644 index 00000000000..952e45b047f --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2018-2025 + */ +#ifdef CONFIG_SPL +&ddr { + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + + config-DDR_MEM_COMPATIBLE { + st,ctl-perf = < + DDR_SCHED + DDR_SCHED1 + DDR_PERFHPR1 + DDR_PERFLPR1 + DDR_PERFWR1 + DDR_PCFGR_0 + DDR_PCFGW_0 + DDR_PCFGQOS0_0 + DDR_PCFGQOS1_0 + DDR_PCFGWQOS0_0 + DDR_PCFGWQOS1_0 + >; + + st,phy-reg = < + DDR_PGCR + DDR_ACIOCR + DDR_DXCCR + DDR_DSGCR + DDR_DCR + DDR_ODTCR + DDR_ZQ0CR1 + DDR_DX0GCR + DDR_DX1GCR + >; + }; +}; +#endif + +#include "stm32mp1-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi new file mode 100644 index 00000000000..7b344541c3e --- /dev/null +++ b/arch/arm/dts/stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2025, DH electronics - All Rights Reserved + * + * STM32MP13xx DHSOM configuration + * 1x DDR3L 1Gb, 16-bit, 533MHz, Single Die Package in flyby topology. + * Reference used W631GU6MB15I from Winbond + * + * DDR type / Platform DDR3/3L + * freq 533MHz + * width 16 + * datasheet 0 = W631GU6MB15I / DDR3-1333 + * DDR density 2 + * timing mode optimized + * address mapping : RBC + * Tc > + 85C : J + */ +#define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-1x2gb-533mhz +#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000kHz" +#define DDR_MEM_SPEED 533000 +#define DDR_MEM_SIZE 0x20000000 + +#define DDR_MSTR 0x00040401 +#define DDR_MRCTRL0 0x00000010 +#define DDR_MRCTRL1 0x00000000 +#define DDR_DERATEEN 0x00000000 +#define DDR_DERATEINT 0x00800000 +#define DDR_PWRCTL 0x00000000 +#define DDR_PWRTMG 0x00400010 +#define DDR_HWLPCTL 0x00000000 +#define DDR_RFSHCTL0 0x00210000 +#define DDR_RFSHCTL3 0x00000000 +#define DDR_RFSHTMG 0x0081008B +#define DDR_CRCPARCTL0 0x00000000 +#define DDR_DRAMTMG0 0x121B2414 +#define DDR_DRAMTMG1 0x000A041B +#define DDR_DRAMTMG2 0x0607080F +#define DDR_DRAMTMG3 0x0050400C +#define DDR_DRAMTMG4 0x07040607 +#define DDR_DRAMTMG5 0x06060403 +#define DDR_DRAMTMG6 0x02020002 +#define DDR_DRAMTMG7 0x00000202 +#define DDR_DRAMTMG8 0x00001005 +#define DDR_DRAMTMG14 0x000000A0 +#define DDR_ZQCTL0 0xC2000040 +#define DDR_DFITMG0 0x02050105 +#define DDR_DFITMG1 0x00000202 +#define DDR_DFILPCFG0 0x07000000 +#define DDR_DFIUPD0 0xC0400003 +#define DDR_DFIUPD1 0x00000000 +#define DDR_DFIUPD2 0x00000000 +#define DDR_DFIPHYMSTR 0x00000000 +#define DDR_ADDRMAP1 0x00080808 +#define DDR_ADDRMAP2 0x00000000 +#define DDR_ADDRMAP3 0x00000000 +#define DDR_ADDRMAP4 0x00001F1F +#define DDR_ADDRMAP5 0x07070707 +#define DDR_ADDRMAP6 0x0F070707 +#define DDR_ADDRMAP9 0x00000000 +#define DDR_ADDRMAP10 0x00000000 +#define DDR_ADDRMAP11 0x00000000 +#define DDR_ODTCFG 0x06000600 +#define DDR_ODTMAP 0x00000001 +#define DDR_SCHED 0x00000F01 +#define DDR_SCHED1 0x00000000 +#define DDR_PERFHPR1 0x00000001 +#define DDR_PERFLPR1 0x04000200 +#define DDR_PERFWR1 0x08000400 +#define DDR_DBG0 0x00000000 +#define DDR_DBG1 0x00000000 +#define DDR_DBGCMD 0x00000000 +#define DDR_POISONCFG 0x00000000 +#define DDR_PCCFG 0x00000010 +#define DDR_PCFGR_0 0x00000000 +#define DDR_PCFGW_0 0x00000000 +#define DDR_PCFGQOS0_0 0x00100009 +#define DDR_PCFGQOS1_0 0x00000020 +#define DDR_PCFGWQOS0_0 0x01100B03 +#define DDR_PCFGWQOS1_0 0x01000200 +#define DDR_PGCR 0x01442E02 +#define DDR_PTR0 0x0022AA5B +#define DDR_PTR1 0x04841104 +#define DDR_PTR2 0x042DA068 +#define DDR_ACIOCR 0x10400812 +#define DDR_DXCCR 0x00000C40 +#define DDR_DSGCR 0xF200011F +#define DDR_DCR 0x0000000B +#define DDR_DTPR0 0x36D477D0 +#define DDR_DTPR1 0x098B00D8 +#define DDR_DTPR2 0x10023600 +#define DDR_MR0 0x00000830 +#define DDR_MR1 0x00000000 +#define DDR_MR2 0x00000208 +#define DDR_MR3 0x00000000 +#define DDR_ODTCR 0x00010000 +#define DDR_ZQ0CR1 0x00000038 +#define DDR_DX0GCR 0x0000CE81 +#define DDR_DX1GCR 0x0000CE81 + +#include "stm32mp13-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 1fe6966781c..ad63d5027b2 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -17,6 +17,7 @@ pinctrl0 = &pinctrl; }; +#if defined(CONFIG_TFABOOT) firmware { optee { bootph-all; @@ -27,6 +28,86 @@ psci { bootph-some-ram; }; +#else + binman: binman { + multiple-images; + + spl-stm32 { + filename = "u-boot-spl.stm32"; + mkimage { + args = "-T stm32imagev2 -a 0x2ffe0000 -e 0x2ffe0000"; + u-boot-spl { + no-write-symbols; + }; + }; + }; + }; + + clocks { + bootph-all; + + clk_hse: ck_hse { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: ck_hsi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: ck_lse { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: ck_lsi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: ck_csi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + bootph-pre-ram; + opp-650000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; + opp-1000000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1350000>; + opp-supported-hw = <0x2>; + }; + }; + + reboot { + bootph-all; + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x114>; + mask = <0x1>; + }; +#endif soc { bootph-all; @@ -52,6 +133,14 @@ bootph-all; }; +#if !defined(CONFIG_TFABOOT) +&cpu0 { + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + operating-points-v2 = <&cpu0_opp_table>; +}; +#endif + &gpioa { bootph-all; }; diff --git a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi index 9ff42ab8248..699ba15d6ea 100644 --- a/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13xx-dhcor-u-boot.dtsi @@ -3,7 +3,9 @@ * Copyright (C) 2024 Marek Vasut <marex@denx.de> */ +#include <dt-bindings/clock/stm32mp13-clksrc.h> #include "stm32mp13-u-boot.dtsi" +#include "stm32mp13-ddr3-dhsom-1x2Gb-1066-binG.dtsi" / { aliases { @@ -18,8 +20,12 @@ }; }; +&etzpc { + compatible = "simple-bus"; +}; + &flash0 { - bootph-pre-ram; + bootph-all; partitions { compatible = "fixed-partitions"; @@ -48,6 +54,138 @@ }; }; +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; +}; + +&qspi { + bootph-all; +}; + +&qspi_clk_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_bk1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&qspi_cs1_pins_a { + bootph-all; + pins { + bootph-all; + }; +}; + +&pinctrl { + bootph-all; + i2c3_pins_a: i2c3-0 { + bootph-all; + pins { + bootph-all; + pinmux = <STM32_PINMUX('B', 8, AF5)>, /* I2C3_SCL */ + <STM32_PINMUX('H', 14, AF4)>; /* I2C3_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; +}; + +#if !defined(CONFIG_TFABOOT) +&rcc { + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, <&clk_lse>, <&clk_lsi>; + + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MLAHBS_PLL3 + CLK_PLL12_HSE + CLK_PLL3_HSE + CLK_PLL4_HSE + CLK_CKPER_HSE + CLK_RTC_LSE + CLK_MCO1_LSI + CLK_MCO2_HSI + >; + + st,clkdiv = < + 0 /*AXI*/ + 0 /*MLHAB*/ + 1 /*APB1*/ + 1 /*APB2*/ + 1 /*APB3*/ + 1 /*APB4*/ + 2 /*APB5*/ + 1 /*APB6*/ + 0 /*RTC*/ + >; + + st,pkcs = < + CLK_I2C12_HSI + CLK_I2C3_HSI + CLK_QSPI_PLL3R + CLK_SAES_AXI + CLK_SDMMC1_PLL3R + CLK_SDMMC2_PLL3R + CLK_STGEN_HSE + CLK_UART2_HSI + CLK_UART4_HSI + CLK_USBO_USBPHY + CLK_USBPHY_HSE + >; + + /* + * cfg = < DIVM1 DIVN P Q R PQR(p,q,r) >; + * frac = < f >; + * + * PRQ(p,q,r) ... for p,q,r: 0-output disabled / 1-output enabled + * DIVN ... actually multiplier, but RCC_PLL1CFGR1 calls the field DIVN + * m ... for PLL1,2: m=2 ; for PLL3,4: m=1 + * XTAL = 24 MHz + * + * VCO = ( XTAL / (DIVM1 + 1) ) * m * ( DIVN + 1 + ( f / 8192 ) ) + * P = VCO / (P + 1) + * Q = VCO / (Q + 1) + * R = VCO / (R + 1) + */ + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + cfg = < 2 65 1 1 0 PQR(1,1,1) >; + frac = < 0x1400 >; + bootph-all; + }; + + /* VCO = 600 MHz => P = 200, Q = 150, R = 200 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + cfg = < 2 74 2 3 2 PQR(1,1,1) >; + bootph-all; + }; + + /* VCO = 750.0 MHz => P = 125, Q = 83, R = 75 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + cfg = < 3 124 5 8 9 PQR(1,1,1) >; + bootph-all; + }; +}; +#endif + &sdmmc1 { status = "disabled"; }; @@ -55,3 +193,23 @@ &usbotg_hs { u-boot,force-b-session-valid; }; + +&vddcpu { + bootph-all; +}; + +&vdd_ddr { + bootph-all; +}; + +&vdd { + bootph-all; +}; + +&vddcore { + bootph-all; +}; + +&vref_ddr { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 48b0828828f..f18fdaeab68 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -2,8 +2,6 @@ /* * Copyright : STMicroelectronics 2018 */ -#include <linux/stringify.h> - #ifdef CONFIG_SPL &ddr { clocks = <&rcc AXIDCG>, @@ -21,69 +19,6 @@ "ddrphycapb"; config-DDR_MEM_COMPATIBLE { - bootph-all; - - compatible = __stringify(st,DDR_MEM_COMPATIBLE); - - st,mem-name = DDR_MEM_NAME; - st,mem-speed = <DDR_MEM_SPEED>; - st,mem-size = <DDR_MEM_SIZE>; - - st,ctl-reg = < - DDR_MSTR - DDR_MRCTRL0 - DDR_MRCTRL1 - DDR_DERATEEN - DDR_DERATEINT - DDR_PWRCTL - DDR_PWRTMG - DDR_HWLPCTL - DDR_RFSHCTL0 - DDR_RFSHCTL3 - DDR_CRCPARCTL0 - DDR_ZQCTL0 - DDR_DFITMG0 - DDR_DFITMG1 - DDR_DFILPCFG0 - DDR_DFIUPD0 - DDR_DFIUPD1 - DDR_DFIUPD2 - DDR_DFIPHYMSTR - DDR_ODTMAP - DDR_DBG0 - DDR_DBG1 - DDR_DBGCMD - DDR_POISONCFG - DDR_PCCFG - >; - - st,ctl-timing = < - DDR_RFSHTMG - DDR_DRAMTMG0 - DDR_DRAMTMG1 - DDR_DRAMTMG2 - DDR_DRAMTMG3 - DDR_DRAMTMG4 - DDR_DRAMTMG5 - DDR_DRAMTMG6 - DDR_DRAMTMG7 - DDR_DRAMTMG8 - DDR_DRAMTMG14 - DDR_ODTCFG - >; - - st,ctl-map = < - DDR_ADDRMAP1 - DDR_ADDRMAP2 - DDR_ADDRMAP3 - DDR_ADDRMAP4 - DDR_ADDRMAP5 - DDR_ADDRMAP6 - DDR_ADDRMAP9 - DDR_ADDRMAP10 - DDR_ADDRMAP11 - >; - st,ctl-perf = < DDR_SCHED DDR_SCHED1 @@ -117,111 +52,8 @@ DDR_DX2GCR DDR_DX3GCR >; - - st,phy-timing = < - DDR_PTR0 - DDR_PTR1 - DDR_PTR2 - DDR_DTPR0 - DDR_DTPR1 - DDR_DTPR2 - DDR_MR0 - DDR_MR1 - DDR_MR2 - DDR_MR3 - >; - - status = "okay"; }; }; #endif -#undef DDR_MEM_COMPATIBLE -#undef DDR_MEM_NAME -#undef DDR_MEM_SPEED -#undef DDR_MEM_SIZE - -#undef DDR_MSTR -#undef DDR_MRCTRL0 -#undef DDR_MRCTRL1 -#undef DDR_DERATEEN -#undef DDR_DERATEINT -#undef DDR_PWRCTL -#undef DDR_PWRTMG -#undef DDR_HWLPCTL -#undef DDR_RFSHCTL0 -#undef DDR_RFSHCTL3 -#undef DDR_RFSHTMG -#undef DDR_CRCPARCTL0 -#undef DDR_DRAMTMG0 -#undef DDR_DRAMTMG1 -#undef DDR_DRAMTMG2 -#undef DDR_DRAMTMG3 -#undef DDR_DRAMTMG4 -#undef DDR_DRAMTMG5 -#undef DDR_DRAMTMG6 -#undef DDR_DRAMTMG7 -#undef DDR_DRAMTMG8 -#undef DDR_DRAMTMG14 -#undef DDR_ZQCTL0 -#undef DDR_DFITMG0 -#undef DDR_DFITMG1 -#undef DDR_DFILPCFG0 -#undef DDR_DFIUPD0 -#undef DDR_DFIUPD1 -#undef DDR_DFIUPD2 -#undef DDR_DFIPHYMSTR -#undef DDR_ADDRMAP1 -#undef DDR_ADDRMAP2 -#undef DDR_ADDRMAP3 -#undef DDR_ADDRMAP4 -#undef DDR_ADDRMAP5 -#undef DDR_ADDRMAP6 -#undef DDR_ADDRMAP9 -#undef DDR_ADDRMAP10 -#undef DDR_ADDRMAP11 -#undef DDR_ODTCFG -#undef DDR_ODTMAP -#undef DDR_SCHED -#undef DDR_SCHED1 -#undef DDR_PERFHPR1 -#undef DDR_PERFLPR1 -#undef DDR_PERFWR1 -#undef DDR_DBG0 -#undef DDR_DBG1 -#undef DDR_DBGCMD -#undef DDR_POISONCFG -#undef DDR_PCCFG -#undef DDR_PCFGR_0 -#undef DDR_PCFGW_0 -#undef DDR_PCFGQOS0_0 -#undef DDR_PCFGQOS1_0 -#undef DDR_PCFGWQOS0_0 -#undef DDR_PCFGWQOS1_0 -#undef DDR_PCFGR_1 -#undef DDR_PCFGW_1 -#undef DDR_PCFGQOS0_1 -#undef DDR_PCFGQOS1_1 -#undef DDR_PCFGWQOS0_1 -#undef DDR_PCFGWQOS1_1 -#undef DDR_PGCR -#undef DDR_PTR0 -#undef DDR_PTR1 -#undef DDR_PTR2 -#undef DDR_ACIOCR -#undef DDR_DXCCR -#undef DDR_DSGCR -#undef DDR_DCR -#undef DDR_DTPR0 -#undef DDR_DTPR1 -#undef DDR_DTPR2 -#undef DDR_MR0 -#undef DDR_MR1 -#undef DDR_MR2 -#undef DDR_MR3 -#undef DDR_ODTCR -#undef DDR_ZQ0CR1 -#undef DDR_DX0GCR -#undef DDR_DX1GCR -#undef DDR_DX2GCR -#undef DDR_DX3GCR +#include "stm32mp1-ddr.dtsi" diff --git a/arch/arm/dts/stm32mp23-u-boot.dtsi b/arch/arm/dts/stm32mp23-u-boot.dtsi new file mode 100644 index 00000000000..872a8739c54 --- /dev/null +++ b/arch/arm/dts/stm32mp23-u-boot.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2024 + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio25 = &gpioz; + pinctrl0 = &pinctrl; + pinctrl1 = &pinctrl_z; + }; + + firmware { + optee { + bootph-all; + }; + + scmi { + bootph-all; + }; + }; + + /* need PSCI for sysreset during board_f */ + psci { + bootph-all; + }; + + soc@0 { + bootph-all; + }; +}; + +&bsec { + bootph-all; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&rcc { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&syscfg { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp235f-dk-u-boot.dtsi b/arch/arm/dts/stm32mp235f-dk-u-boot.dtsi new file mode 100644 index 00000000000..1bc77874050 --- /dev/null +++ b/arch/arm/dts/stm32mp235f-dk-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) STMicroelectronics 2024 - All Rights Reserved + */ + +#include "stm32mp23-u-boot.dtsi" + +/ { + config { + u-boot,boot-led = "led-blue"; + u-boot,mmc-env-partition = "u-boot-env"; + }; +}; + +&usart2 { + bootph-all; +}; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi index 9a566e18d3f..7bbb3e00351 100644 --- a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi @@ -12,6 +12,47 @@ }; }; +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fsbla1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbla2"; + reg = <0x00040000 0x00040000>; + }; + partition@80000 { + label = "metadata1"; + reg = <0x00080000 0x00040000>; + }; + partition@C0000 { + label = "metadata2"; + reg = <0x000C0000 0x00040000>; + }; + partition@100000 { + label = "fip-a"; + reg = <0x00100000 0x00400000>; + }; + partition@500000 { + label = "fip-b"; + reg = <0x00500000 0x00400000>; + }; + partition@900000 { + label = "u-boot-env"; + reg = <0x00900000 0x00080000>; + }; + partition@980000 { + label = "nor-user"; + reg = <0x00980000 0x03680000>; + }; + }; +}; + &usart2 { bootph-all; }; diff --git a/arch/arm/dts/sun50i-a64-pine64-lts.dts b/arch/arm/dts/sun50i-a64-pine64-lts.dts index 596a2590743..709fe650a36 100644 --- a/arch/arm/dts/sun50i-a64-pine64-lts.dts +++ b/arch/arm/dts/sun50i-a64-pine64-lts.dts @@ -5,7 +5,7 @@ #include "sun50i-a64-sopine-baseboard.dts" / { - model = "Pine64 LTS"; + model = "Pine64 PINE A64 LTS"; compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", "allwinner,sun50i-a64"; diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts index b54099b654c..026d843cd7e 100644 --- a/arch/arm/dts/sun50i-a64-pine64-plus.dts +++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts @@ -4,7 +4,7 @@ #include "sun50i-a64-pine64.dts" / { - model = "Pine64+"; + model = "Pine64 PINE A64+"; compatible = "pine64,pine64-plus", "allwinner,sun50i-a64"; /* TODO: Camera, touchscreen, etc. */ diff --git a/arch/arm/dts/sun50i-a64-pine64.dts b/arch/arm/dts/sun50i-a64-pine64.dts index 329cf276561..a406e8f92d0 100644 --- a/arch/arm/dts/sun50i-a64-pine64.dts +++ b/arch/arm/dts/sun50i-a64-pine64.dts @@ -9,7 +9,7 @@ #include <dt-bindings/gpio/gpio.h> / { - model = "Pine64"; + model = "Pine64 PINE A64"; compatible = "pine64,pine64", "allwinner,sun50i-a64"; aliases { @@ -124,6 +124,17 @@ status = "okay"; }; +/* On Wifi/BT connector */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo4>; + vqmmc-supply = <®_eldo1>; + bus-width = <4>; + non-removable; + status = "disabled"; +}; + &ohci0 { status = "okay"; }; @@ -286,6 +297,7 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; status = "disabled"; }; diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts index 1a85d5f60c3..5b7568edc32 100644 --- a/arch/arm/dts/sun50i-a64-pinebook.dts +++ b/arch/arm/dts/sun50i-a64-pinebook.dts @@ -13,7 +13,7 @@ #include <dt-bindings/pwm/pwm.h> / { - model = "Pinebook"; + model = "Pine64 Pinebook"; compatible = "pine64,pinebook", "allwinner,sun50i-a64"; chassis-type = "laptop"; @@ -390,6 +390,8 @@ &tcon0 { pinctrl-names = "default"; pinctrl-0 = <&lcd_rgb666_pins>; + assigned-clocks = <&ccu CLK_TCON0>; + assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi index c62dc937def..31b1f99898c 100644 --- a/arch/arm/dts/sun50i-a64-pinephone.dtsi +++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi @@ -188,12 +188,30 @@ &i2c1 { status = "okay"; + /* Alternative magnetometer */ + af8133j: magnetometer@1c { + compatible = "voltafield,af8133j"; + reg = <0x1c>; + reset-gpios = <&pio 1 1 GPIO_ACTIVE_LOW>; + avdd-supply = <®_dldo1>; + dvdd-supply = <®_dldo1>; + mount-matrix = "0", "-1", "0", + "-1", "0", "0", + "0", "0", "-1"; + + /* status will be fixed up in firmware */ + status = "disabled"; + }; + /* Magnetometer */ lis3mdl: magnetometer@1e { compatible = "st,lis3mdl-magn"; reg = <0x1e>; vdd-supply = <®_dldo1>; vddio-supply = <®_dldo1>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; }; /* Light/proximity sensor */ @@ -212,6 +230,9 @@ interrupts = <7 5 IRQ_TYPE_EDGE_RISING>; /* PH5 */ vdd-supply = <®_dldo1>; vddio-supply = <®_dldo1>; + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; }; }; diff --git a/arch/arm/dts/sun50i-a64-pinetab-early-adopter.dts b/arch/arm/dts/sun50i-a64-pinetab-early-adopter.dts index 6265360ce62..86cc85eb3d4 100644 --- a/arch/arm/dts/sun50i-a64-pinetab-early-adopter.dts +++ b/arch/arm/dts/sun50i-a64-pinetab-early-adopter.dts @@ -9,7 +9,7 @@ #include "sun50i-a64-pinetab.dts" / { - model = "PineTab, Early Adopter's version"; + model = "Pine64 PineTab Early Adopter"; compatible = "pine64,pinetab-early-adopter", "allwinner,sun50i-a64"; }; diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts index b6f42357b45..c66e0bd52ab 100644 --- a/arch/arm/dts/sun50i-a64-pinetab.dts +++ b/arch/arm/dts/sun50i-a64-pinetab.dts @@ -14,7 +14,7 @@ #include <dt-bindings/pwm/pwm.h> / { - model = "PineTab, Development Sample"; + model = "Pine64 PineTab Developer Sample"; compatible = "pine64,pinetab", "allwinner,sun50i-a64"; chassis-type = "tablet"; diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts index 5e66ce1a334..231e652cab6 100644 --- a/arch/arm/dts/sun50i-a64-sopine-baseboard.dts +++ b/arch/arm/dts/sun50i-a64-sopine-baseboard.dts @@ -8,7 +8,7 @@ #include "sun50i-a64-sopine.dtsi" / { - model = "SoPine with baseboard"; + model = "Pine64 SOPINE on Baseboard carrier board"; compatible = "pine64,sopine-baseboard", "pine64,sopine", "allwinner,sun50i-a64"; @@ -103,6 +103,17 @@ }; }; +/* On Wifi/BT connector */ +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_dldo4>; + vqmmc-supply = <®_eldo1>; + bus-width = <4>; + non-removable; + status = "disabled"; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_pins>; @@ -175,6 +186,14 @@ status = "okay"; }; +/* On Wifi/BT connector, with RTS/CTS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "disabled"; +}; + /* On Pi-2 connector */ &uart2 { pinctrl-names = "default"; diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts index 065b1861633..527bc4b46cd 100644 --- a/arch/arm/dts/sun50i-a64-teres-i.dts +++ b/arch/arm/dts/sun50i-a64-teres-i.dts @@ -369,6 +369,8 @@ &tcon0 { pinctrl-names = "default"; pinctrl-0 = <&lcd_rgb666_pins>; + assigned-clocks = <&ccu CLK_TCON0>; + assigned-clock-parents = <&ccu CLK_PLL_VIDEO0_2X>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index b6928cc668d..7c978b38f5b 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -51,10 +51,16 @@ device_type = "cpu"; reg = <0>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -62,10 +68,16 @@ device_type = "cpu"; reg = <1>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -73,10 +85,16 @@ device_type = "cpu"; reg = <2>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -84,16 +102,25 @@ device_type = "cpu"; reg = <3>; enable-method = "psci"; - next-level-cache = <&L2>; clocks = <&ccu CLK_CPUX>; clock-names = "cpu"; #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; - L2: l2-cache { + l2_cache: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; @@ -236,6 +263,14 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 1>; + + trips { + gpu0_crit: gpu0-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; gpu1_thermal: gpu1-thermal { @@ -243,6 +278,14 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-sensors = <&ths 2>; + + trips { + gpu1_crit: gpu1-crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; @@ -402,6 +445,8 @@ clock-names = "ahb", "tcon-ch0"; clock-output-names = "tcon-data-clock"; #clock-cells = <0>; + assigned-clocks = <&ccu CLK_TCON0>; + assigned-clock-parents = <&ccu CLK_PLL_MIPI>; resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; reset-names = "lcd", "lvds"; diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts index b69032c4455..18fa541795a 100644 --- a/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts +++ b/arch/arm/dts/sun50i-h5-nanopi-neo-plus2.dts @@ -45,16 +45,40 @@ startup-delay-us = <100000>; enable-active-high; gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + vin-supply = <®_vcc3v3>; + }; + + reg_gmac_2v5: gmac-2v5 { + /* 2V5 supply for GMAC PHY IO */ + compatible = "regulator-fixed"; + regulator-name = "gmac-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + vin-supply = <®_vcc3v3>; + }; + + reg_vcc5v: regulator-vcc5v { + /* board 5V supply from micro USB or pin headers */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; }; reg_vcc3v3: vcc3v3 { + /* board 3V3 supply by SY8089A */ compatible = "regulator-fixed"; regulator-name = "vcc3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vcc5v>; }; vdd_cpux: gpio-regulator { + /* cpu voltage regulator MP2143DJ */ compatible = "regulator-gpio"; regulator-name = "vdd-cpux"; regulator-type = "voltage"; @@ -66,6 +90,7 @@ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; gpios-states = <0x1>; states = <1100000 0>, <1300000 1>; + vin-supply = <®_vcc5v>; }; wifi_pwrseq: pwrseq { @@ -111,6 +136,7 @@ vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; status = "okay"; }; @@ -146,6 +172,18 @@ status = "okay"; }; +&pio { + vcc-pa-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pd-supply = <®_gmac_2v5>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; +}; + +&r_pio { + vcc-pl-supply = <®_vcc3v3>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pa_pins>; diff --git a/arch/arm/dts/sun50i-h5-nanopi-neo2.dts b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts index 05486cccee1..128295f5a5d 100644 --- a/arch/arm/dts/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm/dts/sun50i-h5-nanopi-neo2.dts @@ -88,6 +88,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; + disable-wp; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts index 3a7ee44708a..44fdc8b3f79 100644 --- a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts +++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts @@ -157,6 +157,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; + disable-wp; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts index ce3ae19e72d..0f29da7d51e 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-pc2.dts @@ -153,6 +153,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; + disable-wp; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; diff --git a/arch/arm/dts/sun50i-h5-orangepi-prime.dts b/arch/arm/dts/sun50i-h5-orangepi-prime.dts index b699bb900e1..d4fc4e60e4e 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-prime.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-prime.dts @@ -153,6 +153,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; + disable-wp; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts index ae85131aac9..3322cc4d9aa 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts @@ -82,6 +82,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; + disable-wp; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ status = "okay"; diff --git a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts index 734481e998b..3eb986c354a 100644 --- a/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts +++ b/arch/arm/dts/sun50i-h5-orangepi-zero-plus2.dts @@ -79,6 +79,7 @@ &mmc0 { vmmc-supply = <®_vcc3v3>; + disable-wp; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi index 9b3462b13cc..14c7c74c4ad 100644 --- a/arch/arm/dts/sun50i-h5.dtsi +++ b/arch/arm/dts/sun50i-h5.dtsi @@ -16,7 +16,6 @@ reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -26,7 +25,6 @@ reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -36,7 +34,6 @@ reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; @@ -46,7 +43,6 @@ reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; }; }; @@ -207,7 +203,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu_hot_trip>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts index 529285fc34f..6b4b621ef38 100644 --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -129,6 +129,7 @@ &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; bus-width = <4>; status = "okay"; }; @@ -151,28 +152,12 @@ vcc-pg-supply = <®_aldo1>; }; -&r_ir { - linux,rc-map-name = "rc-beelink-gs1"; - status = "okay"; -}; - -&r_pio { - /* - * FIXME: We can't add that supply for now since it would - * create a circular dependency between pinctrl, the regulator - * and the RSB Bus. - * - * vcc-pl-supply = <®_aldo1>; - */ - vcc-pm-supply = <®_aldo1>; -}; - -&r_rsb { +&r_i2c { status = "okay"; - axp805: pmic@745 { + axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x745>; + reg = <0x36>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -290,6 +275,22 @@ }; }; +&r_ir { + linux,rc-map-name = "rc-beelink-gs1"; + status = "okay"; +}; + +&r_pio { + /* + * PL0 and PL1 are used for PMIC I2C + * don't enable the pl-supply else + * it will fail at boot + * + * vcc-pl-supply = <®_aldo1>; + */ + vcc-pm-supply = <®_aldo1>; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&spdif_tx_pin>; diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts index bdcec466246..007e74e9604 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-3.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts @@ -131,6 +131,7 @@ &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; bus-width = <4>; status = "okay"; }; @@ -143,7 +144,7 @@ non-removable; status = "okay"; - brcm: sdio-wifi@1 { + brcm: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&r_pio>; @@ -175,16 +176,12 @@ vcc-pg-supply = <®_vcc_wifi_io>; }; -&r_ir { - status = "okay"; -}; - -&r_rsb { +&r_i2c { status = "okay"; - axp805: pmic@745 { + axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x745>; + reg = <0x36>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -295,6 +292,10 @@ }; }; +&r_ir { + status = "okay"; +}; + &rtc { clocks = <&ext_osc32k>; }; diff --git a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts index a3f65a45bd2..0911c537cc6 100644 --- a/arch/arm/dts/sun50i-h6-orangepi-lite2.dts +++ b/arch/arm/dts/sun50i-h6-orangepi-lite2.dts @@ -28,7 +28,7 @@ non-removable; status = "okay"; - brcm: sdio-wifi@1 { + brcm: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&r_pio>; diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi index 4403769fc36..f69658bde88 100644 --- a/arch/arm/dts/sun50i-h6-orangepi.dtsi +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi @@ -94,6 +94,7 @@ &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; bus-width = <4>; status = "okay"; }; @@ -112,20 +113,12 @@ vcc-pg-supply = <®_aldo1>; }; -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pm-supply = <®_bldo3>; -}; - -&r_rsb { +&r_i2c { status = "okay"; - axp805: pmic@745 { + axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x745>; + reg = <0x36>; interrupt-parent = <&r_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; @@ -240,6 +233,14 @@ }; }; +&r_ir { + status = "okay"; +}; + +&r_pio { + vcc-pm-supply = <®_bldo3>; +}; + &rtc { clocks = <&ext_osc32k>; }; diff --git a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts index 66fe03910d5..066fbeff8bf 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts @@ -8,7 +8,7 @@ /delete-node/ ®_gmac_3v3; / { - model = "Pine H64 model B"; + model = "Pine64 PINE H64 Model B"; compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6"; wifi_pwrseq: pwrseq { diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts index bfb46572bda..108dad2b072 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts @@ -9,7 +9,7 @@ #include <dt-bindings/gpio/gpio.h> / { - model = "Pine H64 model A"; + model = "Pine64 PINE H64 Model A"; compatible = "pine64,pine-h64", "allwinner,sun50i-h6"; aliases { @@ -133,6 +133,7 @@ &mmc0 { vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h6-tanix.dtsi b/arch/arm/dts/sun50i-h6-tanix.dtsi index 855b7d43bc5..bb7de37c0d5 100644 --- a/arch/arm/dts/sun50i-h6-tanix.dtsi +++ b/arch/arm/dts/sun50i-h6-tanix.dtsi @@ -124,6 +124,7 @@ pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_vcc3v3>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index 82aa5679fc4..6febed20cb4 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -27,8 +27,14 @@ reg = <0>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu1: cpu@1 { @@ -37,8 +43,14 @@ reg = <1>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu2: cpu@2 { @@ -47,8 +59,14 @@ reg = <2>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; }; cpu3: cpu@3 { @@ -57,8 +75,23 @@ reg = <3>; enable-method = "psci"; clocks = <&ccu CLK_CPUX>; - clock-latency-ns = <244144>; /* 8 32k periods */ #cooling-cells = <2>; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache>; + }; + + l2_cache: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; }; }; diff --git a/arch/arm/dts/sun7i-a20-bananapi.dts b/arch/arm/dts/sun7i-a20-bananapi.dts index 46ecf9db232..d8b362c9661 100644 --- a/arch/arm/dts/sun7i-a20-bananapi.dts +++ b/arch/arm/dts/sun7i-a20-bananapi.dts @@ -48,6 +48,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/leds/common.h> / { model = "LeMaker Banana Pi"; @@ -169,6 +170,32 @@ &gmac_mdio { phy1: ethernet-phy@1 { reg = <1>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; }; diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index 4ebb0a7a78f..cca585c3829 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -433,6 +433,11 @@ function = "pwm0"; }; + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + uart0_pf_pins: uart0-pf-pins { pins = "PF2", "PF4"; function = "uart0"; @@ -610,6 +615,21 @@ assigned-clock-rates = <384000000>; }; + spi0: spi@1c68000 { + compatible = "allwinner,sun8i-a23-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm/dts/sun8i-a33-vstar-core1.dtsi b/arch/arm/dts/sun8i-a33-vstar-core1.dtsi new file mode 100644 index 00000000000..ba794b842ec --- /dev/null +++ b/arch/arm/dts/sun8i-a33-vstar-core1.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Icenowy Zheng <uwu@icenowy.me> + */ + +#include "sun8i-a33.dtsi" + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_dcdc1>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + drive-strength = <40>; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&r_intc>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp223.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-avcc"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; diff --git a/arch/arm/dts/sun8i-a33-vstar.dts b/arch/arm/dts/sun8i-a33-vstar.dts new file mode 100644 index 00000000000..9f5c29b3df4 --- /dev/null +++ b/arch/arm/dts/sun8i-a33-vstar.dts @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Icenowy Zheng <uwu@icenowy.me> + */ + +/dts-v1/; +#include "sun8i-a33-vstar-core1.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Rervision A33-Vstar"; + compatible = "rervision,a33-vstar", + "rervision,a33-core1", + "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + ethernet0 = &r8152; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ + }; + + wifi_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "ext_clock"; + }; +}; + +&ac_power_supply { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&dai { + status = "okay"; +}; + +&ehci0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub@1 { + /* Onboard GL850G hub which needs no extra power sequence */ + compatible = "usb5e3,608"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + r8152: ethernet@4 { + /* + * Onboard Realtek RTL8152 USB Ethernet, + * with no MAC address programmed + */ + compatible = "usbbda,8152"; + reg = <4>; + }; + }; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button-191 { + label = "V+"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <191011>; + }; + + button-391 { + label = "V-"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <391304>; + }; + + button-600 { + label = "BACK"; + linux,code = <KEY_BACK>; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */ + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pg_pins>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <0 7 IRQ_TYPE_LEVEL_LOW>; /* PL7 */ + interrupt-names = "host-wake"; + }; +}; + +/* + * Our WiFi chip needs both DLDO1 and DLDO2 to be powered at the same + * time, with the two being in sync. Since this is not really + * supported right now, just use the two as always on, and we will fix + * it later. + */ +®_dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi0"; +}; + +®_dldo2 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi1"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +&sound { + /* TODO: on-board microphone */ + + simple-audio-card,widgets = "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Left DAC", "DACL", + "Right DAC", "DACR", + "Headphone Jack", "HP"; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_dldo1>; + device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */ + shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + }; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi index 90f2c08d051..be01620a2c5 100644 --- a/arch/arm/dts/sun8i-a83t.dtsi +++ b/arch/arm/dts/sun8i-a83t.dtsi @@ -1222,7 +1222,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu0_hot>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -1252,7 +1252,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu1_hot>; cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index 1b001f2ad0e..b23cec5b89e 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -112,6 +112,20 @@ }; }; +/* + * Audio input/output is exposed on the 13-pin header and can't be used for + * anything else. However, adapter boards may use different audio routing. + * - https://linux-sunxi.org/Xunlong_Orange_Pi_Zero#Expansion_Port + * - Allwinner H3 Datasheet, section 3.1. Pin Characteristics + */ +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "disabled"; +}; + &cpu0 { cpu-supply = <®_vdd_cpux>; }; diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts index 6d85370e04f..9a2742363cd 100644 --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts @@ -94,7 +94,7 @@ non-removable; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts index 7a6444a10e2..97a3565ac7a 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-zero-plus2.dts @@ -99,6 +99,20 @@ }; }; +/* + * Audio input/output is exposed on the 13-pin header and can't be used for + * anything else. However, adapter boards may use different audio routing. + * - http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-Zero-Plus-2.html + * - Allwinner H3 Datasheet, section 3.1. Pin Characteristics + */ +&codec { + allwinner,audio-routing = + "Line Out", "LINEOUT", + "MIC1", "Mic", + "Mic", "MBIAS"; + status = "disabled"; +}; + &de { status = "okay"; }; diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index eac2349a238..cfd039840b4 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -262,7 +262,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu_hot_trip>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, diff --git a/arch/arm/dts/sun8i-orangepi-zero-interface-board.dtso b/arch/arm/dts/sun8i-orangepi-zero-interface-board.dtso new file mode 100644 index 00000000000..e137eefee34 --- /dev/null +++ b/arch/arm/dts/sun8i-orangepi-zero-interface-board.dtso @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright (C) 2025 J. Neuschäfer <j.ne@posteo.net> + * + * Devicetree overlay for the Orange Pi Zero Interface board (OP0014). + * + * https://orangepi.com/index.php?route=product/product&product_id=871 + * + * This overlay applies to the following base files: + * + * - arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts + * - arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts + */ + +/dts-v1/; +/plugin/; + +&codec { + status = "okay"; +}; + +&de { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&r_ir_rx_pin>; + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-q8-common.dtsi b/arch/arm/dts/sun8i-q8-common.dtsi index 272584881bb..a0f787581dd 100644 --- a/arch/arm/dts/sun8i-q8-common.dtsi +++ b/arch/arm/dts/sun8i-q8-common.dtsi @@ -82,7 +82,7 @@ }; &ehci0 { - status = "okay"; + status = "okay"; }; &mmc1 { diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index a5b1f1e3900..f0ed802a9d0 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -146,7 +146,7 @@ }; cooling-maps { - cpu-hot-limit { + map0 { trip = <&cpu_hot_trip>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -705,7 +705,7 @@ }; /omit-if-no-ref/ - uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{ + uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins { pins = "PI16", "PI17"; function = "uart2"; }; diff --git a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi deleted file mode 100644 index 052b010a560..00000000000 --- a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io> - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Elimo Impetus SoM"; - compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-s3-elimo-initium.dts b/arch/arm/dts/sun8i-s3-elimo-initium.dts deleted file mode 100644 index 039677c2cc6..00000000000 --- a/arch/arm/dts/sun8i-s3-elimo-initium.dts +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io> - */ - -/dts-v1/; -#include "sun8i-s3-elimo-impetus.dtsi" - -/ { - model = "Elimo Initium"; - compatible = "elimo,initium", "elimo,impetus", "sochip,s3", - "allwinner,sun8i-v3"; - - aliases { - serial1 = &uart1; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pg_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts deleted file mode 100644 index d18192d51d1..00000000000 --- a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Sipeed Lichee Zero Plus"; - compatible = "sipeed,lichee-zero-plus", "sochip,s3", - "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - reg_vcc3v3: vcc3v3 { - compatible = "regulator-fixed"; - regulator-name = "vcc3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts deleted file mode 100644 index e0d4404b595..00000000000 --- a/arch/arm/dts/sun8i-s3-pinecube.dts +++ /dev/null @@ -1,228 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2019 Icenowy Zheng <icenowy@aosc.io> - */ - -/dts-v1/; -#include "sun8i-v3.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "PineCube IP Camera"; - compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart2; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led1 { - label = "pine64:ir:led1"; - gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */ - }; - - led2 { - label = "pine64:ir:led2"; - gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */ - }; - }; - - reg_vcc5v0: vcc5v0 { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_vcc_wifi: vcc-wifi { - compatible = "regulator-fixed"; - regulator-name = "vcc-wifi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */ - vin-supply = <®_dcdc3>; - startup-delay-us = <200000>; - }; - - wifi_pwrseq: pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */ - post-power-on-delay-ms = <200>; - }; -}; - -&csi1 { - pinctrl-names = "default"; - pinctrl-0 = <&csi1_8bit_pins>; - status = "okay"; - - port { - csi1_ep: endpoint { - remote-endpoint = <&ov5640_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; -}; - -&emac { - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pe_pins>; - status = "okay"; - - ov5640: camera@3c { - compatible = "ovti,ov5640"; - reg = <0x3c>; - pinctrl-names = "default"; - pinctrl-0 = <&csi1_mclk_pin>; - clocks = <&ccu CLK_CSI1_MCLK>; - clock-names = "xclk"; - - AVDD-supply = <®_ldo3>; - DOVDD-supply = <®_ldo3>; - DVDD-supply = <®_ldo4>; - reset-gpios = <&pio 4 23 GPIO_ACTIVE_LOW>; /* PE23 */ - powerdown-gpios = <&pio 4 24 GPIO_ACTIVE_HIGH>; /* PE24 */ - - port { - ov5640_ep: endpoint { - remote-endpoint = <&csi1_ep>; - bus-width = <8>; - hsync-active = <1>; /* Active high */ - vsync-active = <0>; /* Active low */ - data-active = <1>; /* Active high */ - pclk-sample = <1>; /* Rising */ - }; - }; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-200 { - label = "Setup"; - linux,code = <KEY_SETUP>; - channel = <0>; - voltage = <190000>; - }; -}; - -&mmc0 { - vmmc-supply = <®_dcdc3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&mmc1 { - vmmc-supply = <®_vcc_wifi>; - vqmmc-supply = <®_dcdc3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&pio { - vcc-pd-supply = <®_dcdc3>; - vcc-pe-supply = <®_ldo3>; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-sys-cpu-ephy"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-3v3"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "avdd-dovdd-2v8-csi"; - regulator-soft-start; - regulator-ramp-delay = <1600>; -}; - -®_ldo4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "dvdd-1v8-csi"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "winbond,w25q128", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart2 { - status = "okay"; -}; - -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - -&usbphy { - usb0_vbus-supply = <®_vcc5v0>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts deleted file mode 100644 index 8b3a7538381..00000000000 --- a/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts +++ /dev/null @@ -1,35 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2022 Arm Ltd. - -#include <dt-bindings/interrupt-controller/irq.h> - -/dts-v1/; - -#include "sun8i-t113s.dtsi" -#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" - -/ { - model = "MangoPi MQ-R-T113"; - compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s"; - - aliases { - ethernet0 = &rtl8189ftv; - }; -}; - -&cpu0 { - cpu-supply = <®_vcc_core>; -}; - -&cpu1 { - cpu-supply = <®_vcc_core>; -}; - -&mmc1 { - rtl8189ftv: wifi@1 { - reg = <1>; - interrupt-parent = <&pio>; - interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ - interrupt-names = "host-wake"; - }; -}; diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-t113s.dtsi deleted file mode 100644 index b94b69142af..00000000000 --- a/arch/arm/dts/sun8i-t113s.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -// Copyright (C) 2022 Arm Ltd. - -#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <../../riscv/dts/sunxi-d1s-t113.dtsi> -#include <../../riscv/dts/sunxi-d1-t113.dtsi> - -/ { - interrupt-parent = <&gic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <1>; - clocks = <&ccu CLK_CPUX>; - clock-names = "cpu"; - }; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x03021000 0x1000>, - <0x03022000 0x2000>, - <0x03024000 0x2000>, - <0x03026000 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; - interrupt-affinity = <&cpu0>, <&cpu1>; - }; -}; diff --git a/arch/arm/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/dts/sun8i-v3-sl631-imx179.dts deleted file mode 100644 index 117aeece4e5..00000000000 --- a/arch/arm/dts/sun8i-v3-sl631-imx179.dts +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2020 Paul Kocialkowski <contact@paulk.fr> - */ - -#include "sun8i-v3-sl631.dtsi" - -/ { - model = "SL631 Action Camera with IMX179"; - compatible = "allwinner,sl631-imx179", "allwinner,sl631", - "allwinner,sun8i-v3"; -}; diff --git a/arch/arm/dts/sun8i-v3-sl631.dtsi b/arch/arm/dts/sun8i-v3-sl631.dtsi deleted file mode 100644 index 6f93f8c49f8..00000000000 --- a/arch/arm/dts/sun8i-v3-sl631.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR X11) -/* - * Copyright 2020 Paul Kocialkowski <contact@paulk.fr> - */ - -/dts-v1/; - -#include "sun8i-v3.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> - -/ { - model = "SL631 Action Camera"; - compatible = "allwinner,sl631", "allwinner,sun8i-v3"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&i2c0 { - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pb_pins>; - status = "okay"; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button-174 { - label = "Down"; - linux,code = <KEY_DOWN>; - channel = <0>; - voltage = <174603>; - }; - - button-384 { - label = "Up"; - linux,code = <KEY_UP>; - channel = <0>; - voltage = <384126>; - }; - - button-593 { - label = "OK"; - linux,code = <KEY_OK>; - channel = <0>; - voltage = <593650>; - }; -}; - -&mmc0 { - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - vmmc-supply = <®_dcdc3>; - status = "okay"; -}; - -&pio { - vcc-pd-supply = <®_dcdc3>; - vcc-pe-supply = <®_dcdc3>; -}; - -#include "axp209.dtsi" - -&ac_power_supply { - status = "okay"; -}; - -&battery_power_supply { - status = "okay"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-sys-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vdd-3v3"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -&spi0 { - status = "okay"; - - flash@0 { - reg = <0>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - }; -}; - -&uart1 { - pinctrl-0 = <&uart1_pg_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3.dtsi b/arch/arm/dts/sun8i-v3.dtsi deleted file mode 100644 index 186c30cbe6e..00000000000 --- a/arch/arm/dts/sun8i-v3.dtsi +++ /dev/null @@ -1,63 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> - * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org> - */ - -#include "sun8i-v3s.dtsi" - -/ { - soc { - i2s0: i2s@1c22000 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-v3-i2s", - "allwinner,sun8i-h3-i2s"; - reg = <0x01c22000 0x400>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; - clock-names = "apb", "mod"; - dmas = <&dma 3>, <&dma 3>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s0_pins>; - resets = <&ccu RST_BUS_I2S0>; - status = "disabled"; - }; - }; -}; - -&ccu { - compatible = "allwinner,sun8i-v3-ccu"; -}; - -&codec_analog { - compatible = "allwinner,sun8i-v3-codec-analog", - "allwinner,sun8i-h3-codec-analog"; -}; - -&emac { - /delete-property/ phy-handle; - /delete-property/ phy-mode; -}; - -&mdio_mux { - external_mdio: mdio@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&pio { - compatible = "allwinner,sun8i-v3-pinctrl"; - - i2s0_pins: i2s0-pins { - pins = "PG10", "PG11", "PG12", "PG13"; - function = "i2s"; - }; - - uart1_pg_pins: uart1-pg-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; -}; diff --git a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts b/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts deleted file mode 100644 index f34dfdf1566..00000000000 --- a/arch/arm/dts/sun8i-v3s-anbernic-rg-nano.dts +++ /dev/null @@ -1,276 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; -#include <dt-bindings/input/linux-event-codes.h> -#include "sun8i-v3s.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Anbernic RG Nano"; - compatible = "anbernic,rg-nano", "allwinner,sun8i-v3s"; - - aliases { - rtc0 = &pcf8563; - rtc1 = &rtc; - serial0 = &uart0; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 1 2 3 8 14 21 32 46 60 80 100>; - default-brightness-level = <11>; - power-supply = <®_vcc5v0>; - pwms = <&pwm 0 40000 1>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - - button-a { - gpios = <&gpio_expander 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-A"; - linux,code = <BTN_EAST>; - }; - - button-b { - gpios = <&gpio_expander 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-B"; - linux,code = <BTN_SOUTH>; - }; - - button-down { - gpios = <&gpio_expander 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "DPAD-DOWN"; - linux,code = <BTN_DPAD_DOWN>; - }; - - button-left { - gpios = <&gpio_expander 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "DPAD-LEFT"; - linux,code = <BTN_DPAD_LEFT>; - }; - - button-right { - gpios = <&gpio_expander 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "DPAD-RIGHT"; - linux,code = <BTN_DPAD_RIGHT>; - }; - - button-se { - gpios = <&gpio_expander 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-SELECT"; - linux,code = <BTN_SELECT>; - }; - - button-st { - gpios = <&gpio_expander 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-START"; - linux,code = <BTN_START>; - }; - - button-tl { - gpios = <&gpio_expander 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-L"; - linux,code = <BTN_TL>; - }; - - button-tr { - gpios = <&gpio_expander 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-R"; - linux,code = <BTN_TR>; - }; - - button-up { - gpios = <&gpio_expander 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "DPAD-UP"; - linux,code = <BTN_DPAD_UP>; - }; - - button-x { - gpios = <&gpio_expander 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-X"; - linux,code = <BTN_NORTH>; - }; - - button-y { - gpios = <&gpio_expander 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "BTN-Y"; - linux,code = <BTN_WEST>; - }; - }; -}; - -&codec { - allwinner,audio-routing = "Speaker", "HP", - "MIC1", "Mic", - "Mic", "HBIAS"; - allwinner,pa-gpios = <&pio 5 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PF6 */ - status = "okay"; -}; - -&ehci { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - gpio_expander: gpio@20 { - compatible = "nxp,pcal6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - #interrupt-cells = <2>; - interrupt-controller; - interrupt-parent = <&pio>; - interrupts = <1 3 IRQ_TYPE_EDGE_BOTH>; /* PB3/EINT3 */ - vcc-supply = <®_vcc3v3>; - }; - - axp209: pmic@34 { - reg = <0x34>; - interrupt-parent = <&pio>; - interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5/EINT5 */ - }; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -#include "axp209.dtsi" - -&battery_power_supply { - status = "okay"; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - disable-wp; - vmmc-supply = <®_vcc3v3>; - vqmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&ohci { - status = "okay"; -}; - -&pio { - vcc-pb-supply = <®_vcc3v3>; - vcc-pc-supply = <®_vcc3v3>; - vcc-pf-supply = <®_vcc3v3>; - vcc-pg-supply = <®_vcc3v3>; - - spi0_no_miso_pins: spi0-no-miso-pins { - pins = "PC1", "PC2", "PC3"; - function = "spi0"; - }; -}; - -&pwm { - pinctrl-0 = <&pwm0_pin>; - pinctrl-names = "default"; - status = "okay"; -}; - -/* DCDC2 wired into vdd-cpu, vdd-sys, and vdd-ephy. */ -®_dcdc2 { - regulator-always-on; - regulator-max-microvolt = <1250000>; - regulator-min-microvolt = <1250000>; - regulator-name = "vdd-cpu"; -}; - -/* DCDC3 wired into every 3.3v input that isn't the RTC. */ -®_dcdc3 { - regulator-always-on; - regulator-max-microvolt = <3300000>; - regulator-min-microvolt = <3300000>; - regulator-name = "vcc-io"; -}; - -/* LDO1 wired into RTC, voltage is hard-wired at 3.3v. */ -®_ldo1 { - regulator-always-on; - regulator-name = "vcc-rtc"; -}; - -/* LDO2 wired into VCC-PLL and audio codec. */ -®_ldo2 { - regulator-always-on; - regulator-max-microvolt = <3000000>; - regulator-min-microvolt = <3000000>; - regulator-name = "vcc-pll"; -}; - -/* LDO3, LDO4, and LDO5 unused. */ -®_ldo3 { - status = "disabled"; -}; - -®_ldo4 { - status = "disabled"; -}; - -/* RTC uses internal oscillator */ -&rtc { - /delete-property/ clocks; -}; - -&spi0 { - pinctrl-0 = <&spi0_no_miso_pins>; - pinctrl-names = "default"; - status = "okay"; - - display@0 { - compatible = "saef,sftc154b", "panel-mipi-dbi-spi"; - reg = <0>; - backlight = <&backlight>; - dc-gpios = <&pio 2 0 GPIO_ACTIVE_HIGH>; /* PC0 */ - reset-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */ - spi-max-frequency = <100000000>; - - height-mm = <39>; - width-mm = <39>; - - /* Set hb-porch to compensate for non-visible area */ - panel-timing { - hactive = <240>; - vactive = <240>; - hback-porch = <80>; - vback-porch = <0>; - clock-frequency = <0>; - hfront-porch = <0>; - hsync-len = <0>; - vfront-porch = <0>; - vsync-len = <0>; - }; - }; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 6 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG5 */ - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts deleted file mode 100644 index 752ad05c8f8..00000000000 --- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include "sun8i-v3s-licheepi-zero.dts" - -#include <dt-bindings/input/input.h> - -/ { - model = "Lichee Pi Zero with Dock"; - compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero", - "allwinner,sun8i-v3s"; - - aliases { - ethernet0 = &emac; - }; - - leds { - /* The LEDs use PG0~2 pins, which conflict with MMC1 */ - status = "disabled"; - }; -}; - -&emac { - allwinner,leds-active-low; - status = "okay"; -}; - -&lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button-200 { - label = "Volume Up"; - linux,code = <KEY_VOLUMEUP>; - channel = <0>; - voltage = <200000>; - }; - - button-400 { - label = "Volume Down"; - linux,code = <KEY_VOLUMEDOWN>; - channel = <0>; - voltage = <400000>; - }; - - button-600 { - label = "Select"; - linux,code = <KEY_SELECT>; - channel = <0>; - voltage = <600000>; - }; - - button-800 { - label = "Start"; - linux,code = <KEY_OK>; - channel = <0>; - voltage = <800000>; - }; -}; - -&mmc1 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero.dts deleted file mode 100644 index 2e4587d26ce..00000000000 --- a/arch/arm/dts/sun8i-v3s-licheepi-zero.dts +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun8i-v3s.dtsi" -#include "sunxi-common-regulators.dtsi" - -/ { - model = "Lichee Pi Zero"; - compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - blue_led { - label = "licheepi:blue:usr"; - gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */ - }; - - green_led { - label = "licheepi:green:usr"; - gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */ - default-state = "on"; - }; - - red_led { - label = "licheepi:red:usr"; - gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */ - }; - }; -}; - -&mmc0 { - broken-cd; - bus-width = <4>; - vmmc-supply = <®_vcc3v3>; - status = "okay"; -}; - -&uart0 { - pinctrl-0 = <&uart0_pb_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usbphy { - usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi deleted file mode 100644 index b3a32534762..00000000000 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ /dev/null @@ -1,656 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> - * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/sun6i-rtc.h> -#include <dt-bindings/clock/sun8i-v3s-ccu.h> -#include <dt-bindings/reset/sun8i-v3s-ccu.h> -#include <dt-bindings/clock/sun8i-de2.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - chosen { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - framebuffer-lcd { - compatible = "allwinner,simple-framebuffer", - "simple-framebuffer"; - allwinner,pipeline = "mixer0-lcd0"; - clocks = <&display_clocks CLK_MIXER0>, - <&ccu CLK_TCON0>; - status = "disabled"; - }; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0>; - clocks = <&ccu CLK_CPU>; - }; - }; - - de: display-engine { - compatible = "allwinner,sun8i-v3s-display-engine"; - allwinner,pipelines = <&mixer0>; - status = "disabled"; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - osc24M: osc24M-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-accuracy = <50000>; - clock-output-names = "osc24M"; - }; - - osc32k: osc32k-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - clock-accuracy = <50000>; - clock-output-names = "ext-osc32k"; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - display_clocks: clock@1000000 { - compatible = "allwinner,sun8i-v3s-de2-clk"; - reg = <0x01000000 0x10000>; - clocks = <&ccu CLK_BUS_DE>, - <&ccu CLK_DE>; - clock-names = "bus", - "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@1100000 { - compatible = "allwinner,sun8i-v3s-de2-mixer"; - reg = <0x01100000 0x100000>; - clocks = <&display_clocks 0>, - <&display_clocks 6>; - clock-names = "bus", - "mod"; - resets = <&display_clocks 0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_mixer0>; - }; - }; - }; - }; - - syscon: system-control@1c00000 { - compatible = "allwinner,sun8i-v3s-system-control", - "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0xd0>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - }; - - nmi_intc: interrupt-controller@1c000d0 { - compatible = "allwinner,sun8i-v3s-nmi", - "allwinner,sun9i-a80-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x01c000d0 0x0c>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma: dma-controller@1c02000 { - compatible = "allwinner,sun8i-v3s-dma"; - reg = <0x01c02000 0x1000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_DMA>; - resets = <&ccu RST_BUS_DMA>; - #dma-cells = <1>; - }; - - tcon0: lcd-controller@1c0c000 { - compatible = "allwinner,sun8i-v3s-tcon"; - reg = <0x01c0c000 0x1000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_TCON0>, - <&ccu CLK_TCON0>; - clock-names = "ahb", - "tcon-ch0"; - clock-output-names = "tcon-data-clock"; - #clock-cells = <0>; - resets = <&ccu RST_BUS_TCON0>; - reset-names = "lcd"; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - }; - }; - }; - - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&ccu CLK_BUS_MMC0>, - <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&ccu CLK_BUS_MMC1>, - <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun7i-a20-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&ccu CLK_BUS_MMC2>, - <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", - "mmc", - "output", - "sample"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - crypto@1c15000 { - compatible = "allwinner,sun8i-v3s-crypto", - "allwinner,sun8i-a33-crypto"; - reg = <0x01c15000 0x1000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; - clock-names = "ahb", "mod"; - dmas = <&dma 16>, <&dma 16>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_CE>; - reset-names = "ahb"; - }; - - usb_otg: usb@1c19000 { - compatible = "allwinner,sun8i-h3-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@1c19400 { - compatible = "allwinner,sun8i-v3s-usb-phy"; - reg = <0x01c19400 0x2c>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu0"; - clocks = <&ccu CLK_USB_PHY0>; - clock-names = "usb0_phy"; - resets = <&ccu RST_USB_PHY0>; - reset-names = "usb0_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci: usb@1c1a000 { - compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci"; - reg = <0x01c1a000 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; - resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci: usb@1c1a400 { - compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci"; - reg = <0x01c1a400 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ccu: clock@1c20000 { - compatible = "allwinner,sun8i-v3s-ccu"; - reg = <0x01c20000 0x400>; - clocks = <&osc24M>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rtc: rtc@1c20400 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-v3-rtc"; - reg = <0x01c20400 0x54>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc32k>; - clock-output-names = "osc32k", "osc32k-out"; - }; - - pio: pinctrl@1c20800 { - compatible = "allwinner,sun8i-v3s-pinctrl"; - reg = <0x01c20800 0x400>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - #gpio-cells = <3>; - interrupt-controller; - #interrupt-cells = <3>; - - /omit-if-no-ref/ - csi0_mclk_pin: csi0-mclk-pin { - pins = "PE20"; - function = "csi_mipi"; - }; - - /omit-if-no-ref/ - csi1_8bit_pins: csi1-8bit-pins { - pins = "PE0", "PE2", "PE3", "PE8", "PE9", - "PE10", "PE11", "PE12", "PE13", "PE14", - "PE15"; - function = "csi"; - }; - - /omit-if-no-ref/ - csi1_mclk_pin: csi1-mclk-pin { - pins = "PE1"; - function = "csi"; - }; - - i2c0_pins: i2c0-pins { - pins = "PB6", "PB7"; - function = "i2c0"; - }; - - /omit-if-no-ref/ - i2c1_pb_pins: i2c1-pb-pins { - pins = "PB8", "PB9"; - function = "i2c1"; - }; - - /omit-if-no-ref/ - i2c1_pe_pins: i2c1-pe-pins { - pins = "PE21", "PE22"; - function = "i2c1"; - }; - - uart0_pb_pins: uart0-pb-pins { - pins = "PB8", "PB9"; - function = "uart0"; - }; - - uart2_pins: uart2-pins { - pins = "PB0", "PB1"; - function = "uart2"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - /omit-if-no-ref/ - pwm0_pin: pwm0-pin { - pins = "PB4"; - function = "pwm0"; - }; - - /omit-if-no-ref/ - pwm1_pin: pwm1-pin { - pins = "PB5"; - function = "pwm1"; - }; - - spi0_pins: spi0-pins { - pins = "PC0", "PC1", "PC2", "PC3"; - function = "spi0"; - }; - }; - - timer@1c20c00 { - compatible = "allwinner,sun8i-v3s-timer"; - reg = <0x01c20c00 0xa0>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - wdt0: watchdog@1c20ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x01c20ca0 0x20>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - pwm: pwm@1c21400 { - compatible = "allwinner,sun8i-v3s-pwm", - "allwinner,sun7i-a20-pwm"; - reg = <0x01c21400 0xc>; - clocks = <&osc24M>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lradc: lradc@1c22800 { - compatible = "allwinner,sun4i-a10-lradc-keys"; - reg = <0x01c22800 0x400>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - codec: codec@1c22c00 { - #sound-dai-cells = <0>; - compatible = "allwinner,sun8i-v3s-codec"; - reg = <0x01c22c00 0x400>; - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; - clock-names = "apb", "codec"; - resets = <&ccu RST_BUS_CODEC>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; - allwinner,codec-analog-controls = <&codec_analog>; - status = "disabled"; - }; - - codec_analog: codec-analog@1c23000 { - compatible = "allwinner,sun8i-v3s-codec-analog"; - reg = <0x01c23000 0x4>; - }; - - uart0: serial@1c28000 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28000 0x400>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - dmas = <&dma 6>, <&dma 6>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@1c28400 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28400 0x400>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - dmas = <&dma 7>, <&dma 7>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@1c28800 { - compatible = "snps,dw-apb-uart"; - reg = <0x01c28800 0x400>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - dmas = <&dma 8>, <&dma 8>; - dma-names = "tx", "rx"; - resets = <&ccu RST_BUS_UART2>; - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - i2c0: i2c@1c2ac00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2ac00 0x400>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@1c2b000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x01c2b000 0x400>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - emac: ethernet@1c30000 { - compatible = "allwinner,sun8i-v3s-emac"; - syscon = <&syscon>; - reg = <0x01c30000 0x10000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - phy-handle = <&int_mii_phy>; - phy-mode = "mii"; - status = "disabled"; - - mdio: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; - - mdio_mux: mdio-mux { - compatible = "allwinner,sun8i-h3-mdio-mux"; - #address-cells = <1>; - #size-cells = <0>; - - mdio-parent-bus = <&mdio>; - /* Only one MDIO is usable at the time */ - internal_mdio: mdio@1 { - compatible = "allwinner,sun8i-h3-mdio-internal"; - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - int_mii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; - }; - }; - }; - }; - - spi0: spi@1c68000 { - compatible = "allwinner,sun8i-h3-spi"; - reg = <0x01c68000 0x1000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, - <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - csi1: camera@1cb4000 { - compatible = "allwinner,sun8i-v3s-csi"; - reg = <0x01cb4000 0x3000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CSI>, - <&ccu CLK_CSI_SCLK>, - <&ccu CLK_DRAM_CSI>; - clock-names = "bus", "mod", "ram"; - resets = <&ccu RST_BUS_CSI>; - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/sun9i-a80-cubieboard4.dts b/arch/arm/dts/sun9i-a80-cubieboard4.dts deleted file mode 100644 index c8ca8cb7f5c..00000000000 --- a/arch/arm/dts/sun9i-a80-cubieboard4.dts +++ /dev/null @@ -1,508 +0,0 @@ -/* - * Copyright 2015 Tyler Baker - * - * Tyler Baker <tyler.baker@linaro.org> - * Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun9i-a80.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Cubietech Cubieboard4"; - compatible = "cubietech,a80-cubieboard4", "allwinner,sun9i-a80"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "cubieboard4:green:usr"; - gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */ - }; - - led-1 { - label = "cubieboard4:red:usr"; - gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - }; - - vga-connector { - compatible = "vga-connector"; - label = "vga"; - ddc-i2c-bus = <&i2c3>; - - port { - vga_con_in: endpoint { - remote-endpoint = <&vga_dac_out>; - }; - }; - }; - - vga-dac { - compatible = "corpro,gm7123", "adi,adv7123"; - vdd-supply = <®_dcdc1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - vga_dac_in: endpoint { - remote-endpoint = <&tcon0_out_vga>; - }; - }; - - port@1 { - reg = <1>; - - vga_dac_out: endpoint { - remote-endpoint = <&vga_con_in>; - }; - }; - }; - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&de { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_cldo1>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH18 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_cldo3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc1_pins { - bias-pull-up; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; -}; - -&osc32k { - /* osc32k input is from AC100 */ - clocks = <&ac100_rtc 0>; -}; - -&pio { - vcc-pa-supply = <®_ldo_io1>; - vcc-pb-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dc1sw>; - vcc-pe-supply = <®_eldo2>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_ldo_io0>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pl-supply = <®_dldo2>; - vcc-pm-supply = <®_eldo3>; -}; - -&r_rsb { - status = "okay"; - - axp809: pmic@3a3 { - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_aldo1: aldo1 { - /* - * TODO: This should be handled by the - * USB PHY driver. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc33-usbh"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pb-io-cam"; - }; - - aldo3 { - /* unused */ - }; - - reg_dc1sw: dc1sw { - regulator-name = "vcc-pd"; - }; - - reg_dc5ldo: dc5ldo { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus-09-usbh"; - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; - }; - - reg_dcdc2: dcdc2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; - }; - - reg_dcdc4: dcdc4 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys-usb0-hdmi"; - }; - - reg_dcdc5: dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1425000>; - regulator-max-microvolt = <1575000>; - regulator-name = "vcc-dram"; - }; - - reg_dldo1: dldo1 { - /* - * The WiFi chip supports a wide range - * (3.0 ~ 4.8V) of voltages, and so does - * this regulator (3.0 ~ 4.2V), but - * Allwinner SDK always sets it to 3.3V. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_dldo2: dldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pl"; - }; - - reg_eldo1: eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dvdd-cam"; - }; - - reg_eldo2: eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pe"; - }; - - reg_eldo3: eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pm-codec-io1"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa-gmac-2v5"; - }; - - reg_rtc_ldo: rtc_ldo { - regulator-name = "vcc-rtc-vdd1v8-io"; - }; - - sw { - /* unused */ - }; - }; - }; - - axp806: pmic@745 { - compatible = "x-powers,axp806"; - reg = <0x745>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - bldoin-supply = <®_dcdce>; - - regulators { - reg_s_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - aldo2 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo2"; - }; - - aldo3 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo3"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = "vcc18-efuse-adc-display-csi"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = - "vdd18-drampll-vcc18-pll-cpvdd"; - }; - - bldo3 { - /* unused */ - }; - - reg_bldo4: bldo4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vcc12-hsic"; - }; - - reg_cldo1: cldo1 { - /* - * This was 3V in the original design, but - * 3.3V is the recommended supply voltage - * for the Ethernet PHY. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * The PHY requires 20ms after all voltages - * are applied until core logic is ready and - * 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC - * ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-gmac-phy"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-cam"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io-wifi-codec-io2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-vpu"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - regulator-name = "vcc-bldo-codec-ldoin"; - }; - - sw { - /* - * unused, but use a different name to - * avoid name clash with axp809's sw - */ - regulator-name = "s_sw"; - }; - }; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp809.dtsi" - -&tcon0 { - pinctrl-names = "default"; - pinctrl-0 = <&lcd0_rgb888_pins>; -}; - -&tcon0_out { - tcon0_out_vga: endpoint { - remote-endpoint = <&vga_dac_in>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun9i-a80-optimus.dts b/arch/arm/dts/sun9i-a80-optimus.dts deleted file mode 100644 index 5c3580d712e..00000000000 --- a/arch/arm/dts/sun9i-a80-optimus.dts +++ /dev/null @@ -1,510 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -#include "sun9i-a80.dtsi" - -#include <dt-bindings/gpio/gpio.h> - -/ { - model = "Merrii A80 Optimus Board"; - compatible = "merrii,a80-optimus", "allwinner,sun9i-a80"; - - aliases { - serial0 = &uart0; - serial1 = &uart4; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - /* The LED names match those found on the board */ - led2 { - label = "optimus:led2:usr"; - gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; - }; - - led3 { - label = "optimus:led3:usr"; - gpios = <&r_pio 1 15 GPIO_ACTIVE_HIGH>; /* PM15 */ - }; - - led4 { - label = "optimus:led4:usr"; - gpios = <&pio 7 0 GPIO_ACTIVE_HIGH>; - }; - }; - - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ - }; - - reg_usb3_vbus: usb3-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb3-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ - }; - - wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - clocks = <&ac100_rtc 1>; - clock-names = "ext_clock"; - /* enables internal regulator and de-asserts reset */ - reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ - }; -}; - -&ehci0 { - status = "okay"; -}; - -&ehci1 { - /* Enable if HSIC peripheral is connected */ - status = "disabled"; -}; - -&ehci2 { - status = "okay"; -}; - -&gmac { - pinctrl-names = "default"; - pinctrl-0 = <&gmac_rgmii_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - phy-supply = <®_cldo1>; - status = "okay"; -}; - -&mdio { - phy1: ethernet-phy@1 { - reg = <1>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 7 18 GPIO_ACTIVE_LOW>; /* PH8 */ - status = "okay"; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <®_dldo1>; - vqmmc-supply = <®_cldo3>; - mmc-pwrseq = <&wifi_pwrseq>; - bus-width = <4>; - non-removable; - status = "okay"; -}; - -&mmc1_pins { - bias-pull-up; -}; - -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_8bit_pins>; - vmmc-supply = <®_dcdc1>; - bus-width = <8>; - non-removable; - cap-mmc-hw-reset; - status = "okay"; -}; - -&mmc2_8bit_pins { - /* Increase drive strength for DDR modes */ - drive-strength = <40>; -}; - -&ohci0 { - status = "okay"; -}; - -&ohci2 { - status = "okay"; -}; - -&osc32k { - /* osc32k input is from AC100 */ - clocks = <&ac100_rtc 0>; -}; - -&pio { - vcc-pa-supply = <®_ldo_io1>; - vcc-pb-supply = <®_aldo2>; - vcc-pc-supply = <®_dcdc1>; - vcc-pd-supply = <®_dcdc1>; - vcc-pe-supply = <®_eldo2>; - vcc-pf-supply = <®_dcdc1>; - vcc-pg-supply = <®_ldo_io0>; - vcc-ph-supply = <®_dcdc1>; -}; - -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pl-supply = <®_dldo2>; - vcc-pm-supply = <®_eldo3>; -}; - -&r_rsb { - status = "okay"; - - axp809: pmic@3a3 { - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - regulators { - reg_aldo1: aldo1 { - /* - * TODO: This should be handled by the - * USB PHY driver. - */ - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc33-usbh"; - }; - - reg_aldo2: aldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pb-io-cam"; - }; - - aldo3 { - /* unused */ - }; - - reg_dc5ldo: dc5ldo { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpus-09-usbh"; - }; - - dc1sw { - /* unused */ - }; - - reg_dcdc1: dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v"; - }; - - reg_dcdc2: dcdc2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-gpu"; - }; - - reg_dcdc3: dcdc3 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpua"; - }; - - reg_dcdc4: dcdc4 { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-sys-usb0-hdmi"; - }; - - reg_dcdc5: dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1425000>; - regulator-max-microvolt = <1575000>; - regulator-name = "vcc-dram"; - }; - - reg_dldo1: dldo1 { - /* - * The WiFi chip supports a wide range - * (3.0 ~ 4.8V) of voltages, and so does - * this regulator (3.0 ~ 4.2V), but - * Allwinner SDK always sets it to 3.3V. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; - }; - - reg_dldo2: dldo2 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pl"; - }; - - reg_eldo1: eldo1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-name = "vcc-dvdd-cam"; - }; - - reg_eldo2: eldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc-pe"; - }; - - reg_eldo3: eldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pm-codec-io1"; - }; - - reg_ldo_io0: ldo_io0 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-pg"; - }; - - reg_ldo_io1: ldo_io1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-name = "vcc-pa-gmac-2v5"; - }; - - reg_rtc_ldo: rtc_ldo { - regulator-name = "vcc-rtc-vdd1v8-io"; - }; - - sw { - /* unused */ - }; - }; - }; - - axp806: pmic@745 { - compatible = "x-powers,axp806"; - reg = <0x745>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - #interrupt-cells = <1>; - bldoin-supply = <®_dcdce>; - - regulators { - reg_s_aldo1: aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; - }; - - aldo2 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo2"; - }; - - aldo3 { - /* - * unused, but use a different name to - * avoid name clash with axp809's aldo's - */ - regulator-name = "s_aldo3"; - }; - - reg_bldo1: bldo1 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = "vcc18-efuse-adc-display-csi"; - }; - - reg_bldo2: bldo2 { - regulator-always-on; - regulator-min-microvolt = <1700000>; - regulator-max-microvolt = <1900000>; - regulator-name = - "vdd18-drampll-vcc18-pll-cpvdd"; - }; - - bldo3 { - /* unused */ - }; - - reg_bldo4: bldo4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-name = "vcc12-hsic"; - }; - - reg_cldo1: cldo1 { - /* - * This was 3V in the original design, but - * 3.3V is the recommended supply voltage - * for the Ethernet PHY. - */ - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - /* - * The PHY requires 20ms after all voltages - * are applied until core logic is ready and - * 30ms after the reset pin is de-asserted. - * Set a 100ms delay to account for PMIC - * ramp time and board traces. - */ - regulator-enable-ramp-delay = <100000>; - regulator-name = "vcc-gmac-phy"; - }; - - reg_cldo2: cldo2 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-name = "afvcc-cam"; - }; - - reg_cldo3: cldo3 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io-wifi-codec-io2"; - }; - - reg_dcdca: dcdca { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-cpub"; - }; - - reg_dcdcd: dcdcd { - regulator-always-on; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1100000>; - regulator-name = "vdd-vpu"; - }; - - reg_dcdce: dcdce { - regulator-always-on; - regulator-min-microvolt = <2100000>; - regulator-max-microvolt = <2100000>; - regulator-name = "vcc-bldo-codec-ldoin"; - }; - - sw { - /* - * unused, but use a different name to - * avoid name clash with axp809's sw - */ - regulator-name = "s_sw"; - }; - }; - }; - - ac100: codec@e89 { - compatible = "x-powers,ac100"; - reg = <0xe89>; - - ac100_codec: codec { - compatible = "x-powers,ac100-codec"; - interrupt-parent = <&r_pio>; - interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ - #clock-cells = <0>; - clock-output-names = "4M_adda"; - }; - - ac100_rtc: rtc { - compatible = "x-powers,ac100-rtc"; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - clocks = <&ac100_codec>; - #clock-cells = <1>; - clock-output-names = "cko1_rtc", - "cko2_rtc", - "cko3_rtc"; - }; - }; -}; - -#include "axp809.dtsi" - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbphy1 { - phy-supply = <®_usb1_vbus>; - status = "okay"; -}; - -&usbphy2 { - phy-supply = <®_bldo4>; - /* Enable if HSIC peripheral is connected */ - status = "disabled"; -}; - -&usbphy3 { - phy-supply = <®_usb3_vbus>; - status = "okay"; -}; diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi deleted file mode 100644 index a1ae0929cec..00000000000 --- a/arch/arm/dts/sun9i-a80.dtsi +++ /dev/null @@ -1,1253 +0,0 @@ -/* - * Copyright 2014 Chen-Yu Tsai - * - * Chen-Yu Tsai <wens@csie.org> - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> - -#include <dt-bindings/clock/sun9i-a80-ccu.h> -#include <dt-bindings/clock/sun9i-a80-de.h> -#include <dt-bindings/clock/sun9i-a80-usb.h> -#include <dt-bindings/reset/sun9i-a80-ccu.h> -#include <dt-bindings/reset/sun9i-a80-de.h> -#include <dt-bindings/reset/sun9i-a80-usb.h> - -/ { - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - aliases { - ethernet0 = &gmac; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x1>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x2>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - cci-control-port = <&cci_control0>; - clock-frequency = <12000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x3>; - }; - - cpu4: cpu@100 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x100>; - }; - - cpu5: cpu@101 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x101>; - }; - - cpu6: cpu@102 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x102>; - }; - - cpu7: cpu@103 { - compatible = "arm,cortex-a15"; - device_type = "cpu"; - cci-control-port = <&cci_control1>; - clock-frequency = <18000000>; - enable-method = "allwinner,sun9i-a80-smp"; - reg = <0x103>; - }; - }; - - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <24000000>; - arm,cpu-registers-not-fw-configured; - }; - - clocks { - #address-cells = <1>; - #size-cells = <1>; - /* - * map 64 bit address range down to 32 bits, - * as the peripherals are all under 512MB. - */ - ranges = <0 0 0 0x20000000>; - - /* - * This clock is actually configurable from the PRCM address - * space. The external 24M oscillator can be turned off, and - * the clock switched to an internal 16M RC oscillator. Under - * normal operation there's no reason to do this, and the - * default is to use the external good one, so just model this - * as a fixed clock. Also it is not entirely clear if the - * osc24M mux in the PRCM affects the entire clock tree, which - * would also throw all the PLL clock rates off, or just the - * downstream clocks in the PRCM. - */ - osc24M: clk-24M { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "osc24M"; - }; - - /* - * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This serves as a placeholder for - * board dts files to specify the source. - */ - osc32k: clk-32k { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clock-output-names = "osc32k"; - }; - - /* - * The following two are dummy clocks, placeholders - * used in the gmac_tx clock. The gmac driver will - * choose one parent depending on the PHY interface - * mode, using clk_set_rate auto-reparenting. - * - * The actual TX clock rate is not controlled by the - * gmac_tx clock. - */ - mii_phy_tx_clk: mii-phy-tx-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <25000000>; - clock-output-names = "mii_phy_tx"; - }; - - gmac_int_tx_clk: gmac-int-tx-clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "gmac_int_tx"; - }; - - gmac_tx_clk: clk@800030 { - #clock-cells = <0>; - compatible = "allwinner,sun7i-a20-gmac-clk"; - reg = <0x00800030 0x4>; - clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>; - clock-output-names = "gmac_tx"; - }; - - cpus_clk: clk@8001410 { - compatible = "allwinner,sun9i-a80-cpus-clk"; - reg = <0x08001410 0x4>; - #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, - <&ccu CLK_PLL_PERIPH0>, - <&ccu CLK_PLL_AUDIO>; - clock-output-names = "cpus"; - }; - - ahbs: clk-ahbs { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - clocks = <&cpus_clk>; - clock-output-names = "ahbs"; - }; - - apbs: clk@800141c { - compatible = "allwinner,sun8i-a23-apb0-clk"; - reg = <0x0800141c 0x4>; - #clock-cells = <0>; - clocks = <&ahbs>; - clock-output-names = "apbs"; - }; - - apbs_gates: clk@8001428 { - compatible = "allwinner,sun9i-a80-apbs-gates-clk"; - reg = <0x08001428 0x4>; - #clock-cells = <1>; - clocks = <&apbs>; - clock-indices = <0>, <1>, - <2>, <3>, - <4>, <5>, - <6>, <7>, - <12>, <13>, - <16>, <17>, - <18>, <20>; - clock-output-names = "apbs_pio", "apbs_ir", - "apbs_timer", "apbs_rsb", - "apbs_uart", "apbs_1wire", - "apbs_i2c0", "apbs_i2c1", - "apbs_ps2_0", "apbs_ps2_1", - "apbs_dma", "apbs_i2s0", - "apbs_i2s1", "apbs_twd"; - }; - - r_1wire_clk: clk@8001450 { - reg = <0x08001450 0x4>; - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "r_1wire"; - }; - - r_ir_clk: clk@8001454 { - reg = <0x08001454 0x4>; - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - clocks = <&osc32k>, <&osc24M>; - clock-output-names = "r_ir"; - }; - }; - - de: display-engine { - compatible = "allwinner,sun9i-a80-display-engine"; - allwinner,pipelines = <&fe0>, <&fe1>; - status = "disabled"; - }; - - soc@20000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - /* - * map 64 bit address range down to 32 bits, - * as the peripherals are all under 512MB. - */ - ranges = <0 0 0 0x20000000>; - - sram_b: sram@20000 { - /* 256 KiB secure SRAM at 0x20000 */ - compatible = "mmio-sram"; - reg = <0x00020000 0x40000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x00020000 0x40000>; - - smp-sram@1000 { - /* - * This is checked by BROM to determine if - * cpu0 should jump to SMP entry vector - */ - compatible = "allwinner,sun9i-a80-smp-sram"; - reg = <0x1000 0x8>; - }; - }; - - gmac: ethernet@830000 { - compatible = "allwinner,sun7i-a20-gmac"; - reg = <0x00830000 0x1054>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>; - clock-names = "stmmaceth", "allwinner_gmac_tx"; - resets = <&ccu RST_BUS_GMAC>; - reset-names = "stmmaceth"; - snps,pbl = <2>; - snps,fixed-burst; - snps,force_sf_dma_mode; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - ehci0: usb@a00000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a00000 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clocks CLK_BUS_HCI0>; - resets = <&usb_clocks RST_USB0_HCI>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@a00400 { - compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; - reg = <0x00a00400 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clocks CLK_BUS_HCI0>, - <&usb_clocks CLK_USB_OHCI0>; - resets = <&usb_clocks RST_USB0_HCI>; - phys = <&usbphy1>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy1: phy@a00800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a00800 0x4>; - clocks = <&usb_clocks CLK_USB0_PHY>; - clock-names = "phy"; - resets = <&usb_clocks RST_USB0_PHY>; - reset-names = "phy"; - status = "disabled"; - #phy-cells = <0>; - }; - - ehci1: usb@a01000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a01000 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clocks CLK_BUS_HCI1>; - resets = <&usb_clocks RST_USB1_HCI>; - phys = <&usbphy2>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy2: phy@a01800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a01800 0x4>; - clocks = <&usb_clocks CLK_USB1_PHY>, - <&usb_clocks CLK_USB_HSIC>, - <&usb_clocks CLK_USB1_HSIC>; - clock-names = "phy", - "hsic_12M", - "hsic_480M"; - resets = <&usb_clocks RST_USB1_PHY>, - <&usb_clocks RST_USB1_HSIC>; - reset-names = "phy", - "hsic"; - status = "disabled"; - #phy-cells = <0>; - /* usb1 is always used with HSIC */ - phy_type = "hsic"; - }; - - ehci2: usb@a02000 { - compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; - reg = <0x00a02000 0x100>; - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clocks CLK_BUS_HCI2>; - resets = <&usb_clocks RST_USB2_HCI>; - phys = <&usbphy3>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci2: usb@a02400 { - compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; - reg = <0x00a02400 0x100>; - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&usb_clocks CLK_BUS_HCI2>, - <&usb_clocks CLK_USB_OHCI2>; - resets = <&usb_clocks RST_USB2_HCI>; - phys = <&usbphy3>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy3: phy@a02800 { - compatible = "allwinner,sun9i-a80-usb-phy"; - reg = <0x00a02800 0x4>; - clocks = <&usb_clocks CLK_USB2_PHY>, - <&usb_clocks CLK_USB_HSIC>, - <&usb_clocks CLK_USB2_HSIC>; - clock-names = "phy", - "hsic_12M", - "hsic_480M"; - resets = <&usb_clocks RST_USB2_PHY>, - <&usb_clocks RST_USB2_HSIC>; - reset-names = "phy", - "hsic"; - status = "disabled"; - #phy-cells = <0>; - }; - - usb_clocks: clock@a08000 { - compatible = "allwinner,sun9i-a80-usb-clks"; - reg = <0x00a08000 0x8>; - clocks = <&ccu CLK_BUS_USB>, <&osc24M>; - clock-names = "bus", "hosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - cpucfg@1700000 { - compatible = "allwinner,sun9i-a80-cpucfg"; - reg = <0x01700000 0x100>; - }; - - crypto: crypto@1c02000 { - compatible = "allwinner,sun9i-a80-crypto"; - reg = <0x01c02000 0x1000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - resets = <&ccu RST_BUS_SS>; - clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; - clock-names = "bus", "mod"; - }; - - mmc0: mmc@1c0f000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c0f000 0x1000>; - clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, - <&ccu CLK_MMC0_OUTPUT>, - <&ccu CLK_MMC0_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 0>; - reset-names = "ahb"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@1c10000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c10000 0x1000>; - clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, - <&ccu CLK_MMC1_OUTPUT>, - <&ccu CLK_MMC1_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 1>; - reset-names = "ahb"; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@1c11000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c11000 0x1000>; - clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, - <&ccu CLK_MMC2_OUTPUT>, - <&ccu CLK_MMC2_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 2>; - reset-names = "ahb"; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc3: mmc@1c12000 { - compatible = "allwinner,sun9i-a80-mmc"; - reg = <0x01c12000 0x1000>; - clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, - <&ccu CLK_MMC3_OUTPUT>, - <&ccu CLK_MMC3_SAMPLE>; - clock-names = "ahb", "mmc", "output", "sample"; - resets = <&mmc_config_clk 3>; - reset-names = "ahb"; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc_config_clk: clk@1c13000 { - compatible = "allwinner,sun9i-a80-mmc-config-clk"; - reg = <0x01c13000 0x10>; - clocks = <&ccu CLK_BUS_MMC>; - resets = <&ccu RST_BUS_MMC>; - #clock-cells = <1>; - #reset-cells = <1>; - clock-output-names = "mmc0_config", "mmc1_config", - "mmc2_config", "mmc3_config"; - }; - - gic: interrupt-controller@1c41000 { - compatible = "arm,gic-400"; - reg = <0x01c41000 0x1000>, - <0x01c42000 0x2000>, - <0x01c44000 0x2000>, - <0x01c46000 0x2000>; - interrupt-controller; - #interrupt-cells = <3>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - cci: cci@1c90000 { - compatible = "arm,cci-400"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x01c90000 0x1000>; - ranges = <0x0 0x01c90000 0x10000>; - - cci_control0: slave-if@4000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x4000 0x1000>; - }; - - cci_control1: slave-if@5000 { - compatible = "arm,cci-400-ctrl-if"; - interface-type = "ace"; - reg = <0x5000 0x1000>; - }; - - pmu@9000 { - compatible = "arm,cci-400-pmu,r1"; - reg = <0x9000 0x5000>; - interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - de_clocks: clock@3000000 { - compatible = "allwinner,sun9i-a80-de-clks"; - reg = <0x03000000 0x30>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_SDRAM>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "dram", - "bus"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - fe0: display-frontend@3100000 { - compatible = "allwinner,sun9i-a80-display-frontend"; - reg = <0x03100000 0x40000>; - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>, - <&de_clocks CLK_DRAM_FE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe0_out: port@1 { - reg = <1>; - - fe0_out_deu0: endpoint { - remote-endpoint = <&deu0_in_fe0>; - }; - }; - }; - }; - - fe1: display-frontend@3140000 { - compatible = "allwinner,sun9i-a80-display-frontend"; - reg = <0x03140000 0x40000>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>, - <&de_clocks CLK_DRAM_FE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_FE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - fe1_out: port@1 { - reg = <1>; - - fe1_out_deu1: endpoint { - remote-endpoint = <&deu1_in_fe1>; - }; - }; - }; - }; - - be0: display-backend@3200000 { - compatible = "allwinner,sun9i-a80-display-backend"; - reg = <0x03200000 0x40000>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>, - <&de_clocks CLK_DRAM_BE0>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_BE0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be0_in_deu0: endpoint@0 { - reg = <0>; - remote-endpoint = <&deu0_out_be0>; - }; - - be0_in_deu1: endpoint@1 { - reg = <1>; - remote-endpoint = <&deu1_out_be0>; - }; - }; - - be0_out: port@1 { - reg = <1>; - - be0_out_drc0: endpoint { - remote-endpoint = <&drc0_in_be0>; - }; - }; - }; - }; - - be1: display-backend@3240000 { - compatible = "allwinner,sun9i-a80-display-backend"; - reg = <0x03240000 0x40000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>, - <&de_clocks CLK_DRAM_BE1>; - clock-names = "ahb", "mod", - "ram"; - resets = <&de_clocks RST_BE1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - be1_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - be1_in_deu0: endpoint@0 { - reg = <0>; - remote-endpoint = <&deu0_out_be1>; - }; - - be1_in_deu1: endpoint@1 { - reg = <1>; - remote-endpoint = <&deu1_out_be1>; - }; - }; - - be1_out: port@1 { - reg = <1>; - - be1_out_drc1: endpoint { - remote-endpoint = <&drc1_in_be1>; - }; - }; - }; - }; - - deu0: deu@3300000 { - compatible = "allwinner,sun9i-a80-deu"; - reg = <0x03300000 0x40000>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&de_clocks CLK_BUS_DEU0>, - <&de_clocks CLK_IEP_DEU0>, - <&de_clocks CLK_DRAM_DEU0>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DEU0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - deu0_in: port@0 { - reg = <0>; - - deu0_in_fe0: endpoint { - remote-endpoint = <&fe0_out_deu0>; - }; - }; - - deu0_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - deu0_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_deu0>; - }; - - deu0_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_deu0>; - }; - }; - }; - }; - - deu1: deu@3340000 { - compatible = "allwinner,sun9i-a80-deu"; - reg = <0x03340000 0x40000>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&de_clocks CLK_BUS_DEU1>, - <&de_clocks CLK_IEP_DEU1>, - <&de_clocks CLK_DRAM_DEU1>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DEU1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - deu1_in: port@0 { - reg = <0>; - - deu1_in_fe1: endpoint { - remote-endpoint = <&fe1_out_deu1>; - }; - }; - - deu1_out: port@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - deu1_out_be0: endpoint@0 { - reg = <0>; - remote-endpoint = <&be0_in_deu1>; - }; - - deu1_out_be1: endpoint@1 { - reg = <1>; - remote-endpoint = <&be1_in_deu1>; - }; - }; - }; - }; - - drc0: drc@3400000 { - compatible = "allwinner,sun9i-a80-drc"; - reg = <0x03400000 0x40000>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&de_clocks CLK_BUS_DRC0>, - <&de_clocks CLK_IEP_DRC0>, - <&de_clocks CLK_DRAM_DRC0>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DRC0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc0_in: port@0 { - reg = <0>; - - drc0_in_be0: endpoint { - remote-endpoint = <&be0_out_drc0>; - }; - }; - - drc0_out: port@1 { - reg = <1>; - - drc0_out_tcon0: endpoint { - remote-endpoint = <&tcon0_in_drc0>; - }; - }; - }; - }; - - drc1: drc@3440000 { - compatible = "allwinner,sun9i-a80-drc"; - reg = <0x03440000 0x40000>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&de_clocks CLK_BUS_DRC1>, - <&de_clocks CLK_IEP_DRC1>, - <&de_clocks CLK_DRAM_DRC1>; - clock-names = "ahb", - "mod", - "ram"; - resets = <&de_clocks RST_DRC1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - drc1_in: port@0 { - reg = <0>; - - drc1_in_be1: endpoint { - remote-endpoint = <&be1_out_drc1>; - }; - }; - - drc1_out: port@1 { - reg = <1>; - - drc1_out_tcon1: endpoint { - remote-endpoint = <&tcon1_in_drc1>; - }; - }; - }; - }; - - tcon0: lcd-controller@3c00000 { - compatible = "allwinner,sun9i-a80-tcon-lcd"; - reg = <0x03c00000 0x10000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; - clock-names = "ahb", "tcon-ch0"; - resets = <&ccu RST_BUS_LCD0>, - <&ccu RST_BUS_EDP>, - <&ccu RST_BUS_LVDS>; - reset-names = "lcd", - "edp", - "lvds"; - clock-output-names = "tcon0-pixel-clock"; - #clock-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon0_in: port@0 { - reg = <0>; - - tcon0_in_drc0: endpoint { - remote-endpoint = <&drc0_out_tcon0>; - }; - }; - - tcon0_out: port@1 { - reg = <1>; - }; - }; - }; - - tcon1: lcd-controller@3c10000 { - compatible = "allwinner,sun9i-a80-tcon-tv"; - reg = <0x03c10000 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>; - reset-names = "lcd", "edp"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon1_in: port@0 { - reg = <0>; - - tcon1_in_drc1: endpoint { - remote-endpoint = <&drc1_out_tcon1>; - }; - }; - - tcon1_out: port@1 { - reg = <1>; - }; - }; - }; - - ccu: clock@6000000 { - compatible = "allwinner,sun9i-a80-ccu"; - reg = <0x06000000 0x800>; - clocks = <&osc24M>, <&osc32k>; - clock-names = "hosc", "losc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - timer@6000c00 { - compatible = "allwinner,sun4i-a10-timer"; - reg = <0x06000c00 0xa0>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - - clocks = <&osc24M>; - }; - - wdt: watchdog@6000ca0 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x06000ca0 0x20>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - pio: pinctrl@6000800 { - compatible = "allwinner,sun9i-a80-pinctrl"; - reg = <0x06000800 0x400>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - gmac_rgmii_pins: gmac-rgmii-pins { - pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", - "PA7", "PA8", "PA9", "PA10", "PA12", - "PA13", "PA15", "PA16", "PA17"; - function = "gmac"; - /* - * data lines in RGMII mode use DDR mode - * and need a higher signal drive strength - */ - drive-strength = <40>; - }; - - i2c3_pins: i2c3-pins { - pins = "PG10", "PG11"; - function = "i2c3"; - }; - - lcd0_rgb888_pins: lcd0-rgb888-pins { - pins = "PD0", "PD1", "PD2", "PD3", - "PD4", "PD5", "PD6", "PD7", - "PD8", "PD9", "PD10", "PD11", - "PD12", "PD13", "PD14", "PD15", - "PD16", "PD17", "PD18", "PD19", - "PD20", "PD21", "PD22", "PD23", - "PD24", "PD25", "PD26", "PD27"; - function = "lcd0"; - }; - - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1" ,"PF2", "PF3", - "PF4", "PF5"; - function = "mmc0"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1" ,"PG2", "PG3", - "PG4", "PG5"; - function = "mmc1"; - drive-strength = <30>; - bias-pull-up; - }; - - mmc2_8bit_pins: mmc2-8bit-pins { - pins = "PC6", "PC7", "PC8", "PC9", - "PC10", "PC11", "PC12", - "PC13", "PC14", "PC15", - "PC16"; - function = "mmc2"; - drive-strength = <30>; - bias-pull-up; - }; - - uart0_ph_pins: uart0-ph-pins { - pins = "PH12", "PH13"; - function = "uart0"; - }; - - uart4_pins: uart4-pins { - pins = "PG12", "PG13", "PG14", "PG15"; - function = "uart4"; - }; - }; - - uart0: serial@7000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000000 0x400>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - status = "disabled"; - }; - - uart1: serial@7000400 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000400 0x400>; - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - status = "disabled"; - }; - - uart2: serial@7000800 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000800 0x400>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - status = "disabled"; - }; - - uart3: serial@7000c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x07000c00 0x400>; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - status = "disabled"; - }; - - uart4: serial@7001000 { - compatible = "snps,dw-apb-uart"; - reg = <0x07001000 0x400>; - interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - status = "disabled"; - }; - - uart5: serial@7001400 { - compatible = "snps,dw-apb-uart"; - reg = <0x07001400 0x400>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&ccu CLK_BUS_UART5>; - resets = <&ccu RST_BUS_UART5>; - status = "disabled"; - }; - - i2c0: i2c@7002800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07002800 0x400>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@7002c00 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07002c00 0x400>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@7003000 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003000 0x400>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@7003400 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003400 0x400>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C3>; - resets = <&ccu RST_BUS_I2C3>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c4: i2c@7003800 { - compatible = "allwinner,sun6i-a31-i2c"; - reg = <0x07003800 0x400>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C4>; - resets = <&ccu RST_BUS_I2C4>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - r_wdt: watchdog@8001000 { - compatible = "allwinner,sun6i-a31-wdt"; - reg = <0x08001000 0x20>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc24M>; - }; - - prcm@8001400 { - compatible = "allwinner,sun9i-a80-prcm"; - reg = <0x08001400 0x200>; - }; - - apbs_rst: reset@80014b0 { - reg = <0x080014b0 0x4>; - compatible = "allwinner,sun6i-a31-clock-reset"; - #reset-cells = <1>; - }; - - nmi_intc: interrupt-controller@80015a0 { - compatible = "allwinner,sun9i-a80-nmi"; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x080015a0 0xc>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - }; - - r_ir: ir@8002000 { - compatible = "allwinner,sun6i-a31-ir"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&r_ir_pins>; - clocks = <&apbs_gates 1>, <&r_ir_clk>; - clock-names = "apb", "ir"; - resets = <&apbs_rst 1>; - reg = <0x08002000 0x40>; - status = "disabled"; - }; - - r_uart: serial@8002800 { - compatible = "snps,dw-apb-uart"; - reg = <0x08002800 0x400>; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; - reg-shift = <2>; - reg-io-width = <4>; - clocks = <&apbs_gates 4>; - resets = <&apbs_rst 4>; - status = "disabled"; - }; - - r_pio: pinctrl@8002c00 { - compatible = "allwinner,sun9i-a80-r-pinctrl"; - reg = <0x08002c00 0x400>; - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #interrupt-cells = <3>; - #gpio-cells = <3>; - - r_ir_pins: r-ir-pins { - pins = "PL6"; - function = "s_cir_rx"; - }; - - r_rsb_pins: r-rsb-pins { - pins = "PN0", "PN1"; - function = "s_rsb"; - drive-strength = <20>; - bias-pull-up; - }; - }; - - r_rsb: rsb@8003400 { - compatible = "allwinner,sun8i-a23-rsb"; - reg = <0x08003400 0x400>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apbs_gates 3>; - clock-frequency = <3000000>; - resets = <&apbs_rst 3>; - pinctrl-names = "default"; - pinctrl-0 = <&r_rsb_pins>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts b/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts new file mode 100644 index 00000000000..2007aae8737 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-0b.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra114-microsoft-surface-2-common.dtsi" + +/ { + backlight: backlight { + enable-gpios = <&gpio TEGRA_GPIO(CC, 2) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-13.dts b/arch/arm/dts/tegra114-microsoft-surface-2-13.dts new file mode 100644 index 00000000000..da121d5a101 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-13.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra114-microsoft-surface-2-common.dtsi" + +/ { + backlight: backlight { + enable-gpios = <&gpio TEGRA_GPIO(EE, 3) GPIO_ACTIVE_HIGH>; + }; +}; diff --git a/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi new file mode 100644 index 00000000000..f8f71262538 --- /dev/null +++ b/arch/arm/dts/tegra114-microsoft-surface-2-common.dtsi @@ -0,0 +1,905 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/input.h> +#include "tegra114.dtsi" + +/ { + model = "Microsoft Surface 2"; + compatible = "microsoft,surface-2", "nvidia,tegra114"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + usb0 = &usb1; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + host1x@50000000 { + dsia: dsi@54300000 { + status = "okay"; + + avdd-dsi-csi-supply = <&avdd_dsi_csi>; + + panel@0 { + compatible = "samsung,ltl106hl02-001"; + reg = <0>; + + vdd-supply = <&tps65090_fet4>; + + backlight = <&backlight>; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* ULPI pinmux */ + ulpi-data0 { + nvidia,pins = "ulpi_data0_po1", + "ulpi_data3_po4", + "ulpi_data4_po5"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi-data1 { + nvidia,pins = "ulpi_data1_po2"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ulpi-data2 { + nvidia,pins = "ulpi_data2_po3"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ulpi-data7 { + nvidia,pins = "ulpi_data7_po0", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "ulpi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2S pinmux */ + dap1-din { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap1-dout { + nvidia,pins = "dap1_dout_pn2"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap2-i2s1 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap3-i2s2 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + dap4-din { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + dap4-dout { + nvidia,pins = "dap4_dout_pp6"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC1 pinmux */ + sdmmc1-wp-clk { + nvidia,pins = "sdmmc1_wp_n_pv3", + "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1-cmd { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC3 pinmux */ + sdmmc3-clk { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-cmd { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_cd_n_pv2", + "sdmmc3_clk_lb_in_pee5"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc3-clk-lb-out { + nvidia,pins = "sdmmc3_clk_lb_out_pee4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4-clk { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc4-cmd { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI pinmux */ + hdmi-int { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + hdmi-cec { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1-i2c { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen2-i2c { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + cam-i2c { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + ddc-scl-pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + pwr-i2c { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + + /* UARTA pinmux */ + uarta-out { + nvidia,pins = "pu0", "pu3"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uarta-in { + nvidia,pins = "pu1", "pu2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UARTB pinmux */ + uart2-txd-pc2 { + nvidia,pins = "uart2_txd_pc2"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uart2-rxd-pc3 { + nvidia,pins = "uart2_rxd_pc3"; + nvidia,function = "irda"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart2-cts-n-pj5 { + nvidia,pins = "uart2_cts_n_pj5", + "uart2_rts_n_pj6"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UARTC pinmux */ + uart3-cts-rxd { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + uart3-rts-txd { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UARTD pinmux */ + uartd-out { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + uartd-in { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GMI section */ + gmi-a17 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1", + "gmi_iordy_pi5", + "kb_col1_pq1", + "kb_row8_ps0", + "pbb6"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-wp-n { + nvidia,pins = "gmi_wp_n_pc7", + "gmi_cs0_n_pj0", + "gpio_x7_aud_px7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_oe_n_pi1", + "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-ad8 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad9 { + nvidia,pins = "gmi_ad9_ph1", + "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad15_ph7", + "gmi_cs4_n_pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad12 { + nvidia,pins = "gmi_ad12_ph4", + "gmi_ad13_ph5", + "gpio_x1_aud_px1", + "pcc1", + "clk3_req_pee1", + "clk1_req_pee2"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-ad14 { + nvidia,pins = "gmi_ad14_ph6", + "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-wr-n { + nvidia,pins = "gmi_wr_n_pi0"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-cs6-n { + nvidia,pins = "gmi_cs6_n_pi3", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-rst-n { + nvidia,pins = "gmi_rst_n_pi4", + "spdif_out_pk5", + "spdif_in_pk6", + "clk2_out_pw5", + "dvfs_pwm_px0", + "dvfs_clk_px2", + "pbb7", + "pcc2", + "clk2_req_pcc5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-wait { + nvidia,pins = "gmi_wait_pi7"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-cs1-n { + nvidia,pins = "gmi_cs1_n_pj2"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-dqs-p { + nvidia,pins = "gmi_dqs_p_pj3"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gmi-adv-n { + nvidia,pins = "gmi_adv_n_pk0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gmi-clk { + nvidia,pins = "gmi_clk_pk1", + "gmi_cs2_n_pk3", + "gmi_cs3_n_pk4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + jtag-rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC pinmux */ + kb-col0 { + nvidia,pins = "kb_col0_pq0", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_row4_pr4"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-col2 { + nvidia,pins = "kb_col2_pq2", + "kb_col6_pq6", + "kb_col7_pq7", + "kb_row0_pr0", + "kb_row2_pr2", + "pv0", + "sys_clk_req_pz5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-col5 { + nvidia,pins = "kb_col5_pq5", + "kb_row5_pr5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row1 { + nvidia,pins = "kb_row1_pr1"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb-row3 { + nvidia,pins = "kb_row3_pr3", + "kb_row9_ps1"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb-row6 { + nvidia,pins = "kb_row6_pr6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb-row7 { + nvidia,pins = "kb_row7_pr7", + "pbb3", + "pbb4", + "pbb5"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + kb-row10 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* CORE pinmux */ + clk-32k-out { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + clk-32k-in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + core-pwr-req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + cpu-pwr-req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pwr-int-n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + owr { + nvidia,pins = "owr"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; + }; + reset-out-n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* AUD pinmux */ + gpio-w2-aud { + nvidia,pins = "gpio_w2_aud_pw2"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-w3-aud { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x3-aud { + nvidia,pins = "gpio_x3_aud_px3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x4-aud { + nvidia,pins = "gpio_x4_aud_px4"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + gpio-x5-aud { + nvidia,pins = "gpio_x5_aud_px5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + gpio-x6-aud { + nvidia,pins = "gpio_x6_aud_px6"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "pwm3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pbb0 { + nvidia,pins = "pbb0", + "cam_mclk_pcc0"; + nvidia,function = "vi_alt1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1-out { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + clk3-out { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* USB pinmux */ + usb-vbus-en0 { + nvidia,pins = "usb_vbus_en0_pn4"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + usb-vbus-en1 { + nvidia,pins = "usb_vbus_en1_pn5"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS65090 PMIC */ + tps65090@48 { + compatible = "ti,tps65090"; + reg = <0x48>; + + regulators { + tps65090_fet1: fet1 { + regulator-name = "vcd_led"; + regulator-boot-on; + }; + + tps65090_fet4: fet4 { + regulator-name = "vdd_lcd"; + regulator-boot-on; + }; + + tps65090_fet6: fet6 { + regulator-name = "vdd_usd"; + regulator-boot-on; + }; + }; + }; + + /* Texas Instruments TPS65913 PMIC */ + pmic: tps65913@58 { + compatible = "ti,tps65913"; + reg = <0x58>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + pmic { + compatible = "ti,tps65913-pmic"; + + regulators { + vdd_1v8_vio: smps8 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <5000>; + }; + + avdd_dsi_csi: ldo3 { + regulator-name = "avdd_dsi_csi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + }; + + vddio_usd: ldo9 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + }; + + sdmmc3: sdhci@78000400 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + + nvidia,default-tap = <0x3>; + nvidia,default-trim = <0x3>; + + vmmc-supply = <&tps65090_fet6>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d000000 { + status = "okay"; + + nvidia,xcvr-setup = <7>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + power-supply = <&tps65090_fet1>; + pwms = <&pwm 0 1000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + extcon-keys { + compatible = "gpio-keys"; + + switch-hall-sensor { + label = "Hall Sensor"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_HIGH>; + linux,code = <SW_LID>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power Button"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-windows { + label = "Windows Button"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + }; + }; +}; diff --git a/arch/arm/dts/tegra20-acer-a500-picasso.dts b/arch/arm/dts/tegra20-acer-a500-picasso.dts index 0c301483180..4afde766330 100644 --- a/arch/arm/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/dts/tegra20-acer-a500-picasso.dts @@ -40,6 +40,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra20-asus-sl101.dts b/arch/arm/dts/tegra20-asus-sl101.dts index b4709c3e9a4..9f78b0febf3 100644 --- a/arch/arm/dts/tegra20-asus-sl101.dts +++ b/arch/arm/dts/tegra20-asus-sl101.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Slider SL101"; compatible = "asus,sl101", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-tablet-mode { + label = "Tablet Mode"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = <SW_TABLET_MODE>; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-tf101.dts b/arch/arm/dts/tegra20-asus-tf101.dts index 7c734fb5b19..03ba78c5dc2 100644 --- a/arch/arm/dts/tegra20-asus-tf101.dts +++ b/arch/arm/dts/tegra20-asus-tf101.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Transformer TF101"; compatible = "asus,tf101", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-tf101g.dts b/arch/arm/dts/tegra20-asus-tf101g.dts index f49a358a267..44d5fdfc2b5 100644 --- a/arch/arm/dts/tegra20-asus-tf101g.dts +++ b/arch/arm/dts/tegra20-asus-tf101g.dts @@ -6,4 +6,14 @@ / { model = "ASUS EeePad Transformer TF101G"; compatible = "asus,tf101g", "nvidia,tegra20"; + + extcon-keys { + compatible = "gpio-keys"; + + switch-dock-hall-sensor { + label = "Lid sensor"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,code = <SW_LID>; + }; + }; }; diff --git a/arch/arm/dts/tegra20-asus-transformer.dtsi b/arch/arm/dts/tegra20-asus-transformer.dtsi index 49efabbfd92..df078a6fcdc 100644 --- a/arch/arm/dts/tegra20-asus-transformer.dtsi +++ b/arch/arm/dts/tegra20-asus-transformer.dtsi @@ -36,6 +36,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -493,12 +497,6 @@ gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; linux,code = <KEY_UP>; }; - - switch-dock-hall-sensor { - label = "Lid sensor"; - gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; - linux,code = <SW_LID>; - }; }; panel: panel { diff --git a/arch/arm/dts/tegra20-lg-star.dts b/arch/arm/dts/tegra20-lg-star.dts index 3045bc3135f..083598b1b92 100644 --- a/arch/arm/dts/tegra20-lg-star.dts +++ b/arch/arm/dts/tegra20-lg-star.dts @@ -46,6 +46,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra20-motorola-mot.dtsi b/arch/arm/dts/tegra20-motorola-mot.dtsi index f00707c2859..db2cce1cc0d 100644 --- a/arch/arm/dts/tegra20-motorola-mot.dtsi +++ b/arch/arm/dts/tegra20-motorola-mot.dtsi @@ -62,6 +62,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra20-samsung-bose.dts b/arch/arm/dts/tegra20-samsung-bose.dts new file mode 100644 index 00000000000..5bb9a33adf2 --- /dev/null +++ b/arch/arm/dts/tegra20-samsung-bose.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-samsung-n1-common.dtsi" + +/ { + model = "Samsung Captivate Glide (SGH-i927)"; + compatible = "samsung,bose", "nvidia,tegra20"; + + aliases { + spi0 = &panel_spi; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port { + dpi_output: endpoint { + remote-endpoint = <&panel_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + conf-dtf { + nvidia,pins = "dtf", "spdi", "spib", "spih"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-gpv { + nvidia,pins = "gpv"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-kbcd { + nvidia,pins = "kbcd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + drive-dap { + nvidia,pins = "drive_dap2", "drive_dap3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + }; + }; + + panel_spi: spi@7000d800 { + status = "okay"; + spi-max-frequency = <1000000>; + + panel: panel@2 { + /* 480x800 AMOLED panel */ + compatible = "samsung,bose-panel", "samsung,s6e63m0"; + reg = <2>; + + spi-max-frequency = <1000000>; + + spi-cpol; + spi-cpha; + + reset-gpios = <&gpio TEGRA_GPIO(C, 1) GPIO_ACTIVE_LOW>; + + vdd3-supply = <&vlcd_1v8_reg>; + vci-supply = <&vlcd_3v0_reg>; + + panel-width-mm = <52>; + panel-height-mm = <87>; + + port { + panel_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + }; + }; + + sdhci@c8000400 { + broken-cd; + }; + + gpio-keys { + compatible = "gpio-keys"; + + switch-hall { + label = "Keyboard Slide"; + gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>; + linux,input-type = <EV_SW>; + linux,code = <SW_KEYPAD_SLIDE>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-kbd { + label = "Keyboard backlight"; + gpios = <&gpio TEGRA_GPIO(L, 5) GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; diff --git a/arch/arm/dts/tegra20-samsung-n1-common.dtsi b/arch/arm/dts/tegra20-samsung-n1-common.dtsi new file mode 100644 index 00000000000..8223c5ece54 --- /dev/null +++ b/arch/arm/dts/tegra20-samsung-n1-common.dtsi @@ -0,0 +1,428 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <dt-bindings/input/input.h> +#include "tegra20.dtsi" + +/ { + chosen { + stdout-path = &uartb; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc3; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = µ_usb; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata", "atc", "atd", "ate", + "gmb", "gmd", "irrx", "irtx", + "spid", "spie"; + nvidia,function = "gmi"; + }; + + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + + spif { + nvidia,pins = "spif", "uac"; + nvidia,function = "rsvd4"; + }; + + dta { + nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; + nvidia,function = "vi"; + }; + + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + + gpu { + nvidia,pins = "gpu", "uaa", "uab"; + nvidia,function = "uarta"; + }; + + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + + hdint { + nvidia,pins = "hdint", "spdi", "spdo"; + nvidia,function = "rsvd2"; + }; + + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + + lcsn { + nvidia,pins = "lcsn", "lsck", "lsda", "lsdi"; + nvidia,function = "spi3"; + }; + + ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldc", "ldi", + "lhp0", "lhp1", "lhp2", "lhs", "lm0", + "lm1", "lpp", "lpw0", "lpw1", "lpw2", + "lsc0", "lsc1", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + + owc { + nvidia,pins = "owc"; + nvidia,function = "owr"; + }; + + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "sdio3"; + }; + + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spi4"; + }; + + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + + uda { + nvidia,pins = "uda"; + nvidia,function = "spi1"; + }; + + spia { + nvidia,pins = "spia", "spib", "spic"; + nvidia,function = "spi2"; + }; + + conf-cdev1 { + nvidia,pins = "cdev1", "cdev2", "dap1", "dap2", + "dap3", "dap4", "ddc", "dte", "gma", + "gmc", "gmd", "gme", "gpu7", "hdint", + "i2cp", "lcsn", "lhs", "lm0", "lm1", + "lpw1", "lsc0", "lsck", "lsda", "lsdi", + "lspi", "lvs", "pmc", "pta", "rm", + "sdb", "sdio1", "uac", "uda", "ck32", + "ddrc", "pmca", "pmcb", "pmcc", "pmcd", + "xm2c", "xm2d"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-crtp { + nvidia,pins = "crtp", "lvp0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-csus { + nvidia,pins = "csus", "spid"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-ata { + nvidia,pins = "ata", "atb", "atc", "ate", + "gmb", "gpu", "irrx", "irtx", + "kbca", "kbcc", "kbce", "kbcf", + "ldc", "lpw0", "lpw2", "lsc1", "sdc", + "sdd", "spig", "uaa", "uab", + "uad", "uca", "ucb", "pmce"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-owc { + nvidia,pins = "owc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + }; + + conf-atd { + nvidia,pins = "atd", "dta", "dtb", "dtc", "dtd", + "kbcb", "ld0", "ld1", "ld10", "ld11", + "ld12", "ld13", "ld14", "ld15", "ld16", + "ld17", "ld2", "ld3", "ld4", "ld5", + "ld6", "ld7", "ld8", "ld9", "ldi", + "lhp0", "lhp1", "lhp2", "lpp", "lvp1", + "slxa", "slxc", "slxd", "slxk", "spdo", + "spia", "spic", "spie", "spif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + drive-ao1 { + nvidia,pins = "drive_ao1", "drive_at1", "drive_dbg", + "drive_vi1", "drive_vi2"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + drive-sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + drive-ddc { + nvidia,pins = "drive_ddc"; + nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uartb: serial@70006040 { + clocks = <&tegra_car 7>; + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: max8907@3c { + compatible = "maxim,max8907"; + reg = <0x3c>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + maxim,system-power-controller; + + regulators { + vlcd_1v8_reg: ldo3 { + regulator-name = "vlcd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + usb_phy_reg: ldo4 { + regulator-name = "vap_usb_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vlcd_3v0_reg: ldo12 { + regulator-name = "vlcd_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + vmmc_usd_reg: ldo16 { + regulator-name = "vmmc_usd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; + + micro_usb: usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + usb-phy@c5000000 { + status = "okay"; + vbus-supply = <&usb_phy_reg>; + }; + + sdmmc3: sdhci@c8000400 { + status = "okay"; + bus-width = <4>; + + vmmc-supply = <&vmmc_usd_reg>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + sdmmc4: sdhci@c8000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_3v3_sys>; + }; + + /* 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k-in { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ref-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(U, 5) GPIO_ACTIVE_HIGH>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; diff --git a/arch/arm/dts/tegra20-samsung-n1.dts b/arch/arm/dts/tegra20-samsung-n1.dts new file mode 100644 index 00000000000..930a3195aa0 --- /dev/null +++ b/arch/arm/dts/tegra20-samsung-n1.dts @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra20-samsung-n1-common.dtsi" + +/ { + model = "Samsung Galaxy R (GT-I9103)"; + compatible = "samsung,n1", "nvidia,tegra20"; + + aliases { + i2c10 = &cmc_i2c; + spi0 = &panel_spi; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000014 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + conf-dtf { + nvidia,pins = "dtf", "spdi", "spih"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-gpv { + nvidia,pins = "gpv", "spib"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + conf-kbcd { + nvidia,pins = "kbcd"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + }; + + i2c@7000d000 { + max8907@3c { + regulators { + vcmc623_io_1v8: ldo15 { + regulator-name = "vcmc623_io_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + cmc_i2c: i2c-10 { + compatible = "i2c-gpio"; + + sda-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + + i2c-gpio,scl-output-only; + i2c-gpio,delay-us = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + cmc623: bridge@38 { + compatible = "samsung,cmc623"; + reg = <0x38>; + + enable-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio TEGRA_GPIO(J, 6) GPIO_ACTIVE_HIGH>; + + bypass-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>; + sleep-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; + + vdd3v0-supply = <&vcmc623_3v0>; + vdd1v2-supply = <&vcmc623_1v2>; + vddio1v8-supply = <&vcmc623_io_1v8>; + + cmc623_backlight: backlight { + compatible = "samsung,cmc623-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + }; + + panel_spi: spi@7000d800 { + status = "okay"; + spi-max-frequency = <1000000>; + + panel: panel@2 { + /* 480x800 TFT LCD panel */ + compatible = "sony,l4f00430t01"; + reg = <2>; + + spi-max-frequency = <1000000>; + + spi-cpol; + spi-cpha; + + reset-gpios = <&gpio TEGRA_GPIO(C, 1) GPIO_ACTIVE_LOW>; + + vdd1v8-supply = <&vlcd_1v8_reg>; + vdd3v0-supply = <&vlcd_3v0_reg>; + + panel-width-mm = <55>; + panel-height-mm = <91>; + + backlight = <&cmc623_backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + }; + + sdhci@c8000400 { + /* battery blocks the sdcard slot and the device lacks CD pin */ + non-removable; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-home { + label = "Home"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + }; + + vcmc623_3v0: regulator-cmc623-3v0 { + compatible = "regulator-fixed"; + regulator-name = "vcmc623_3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcmc623_1v2: regulator-cmc623-1v2 { + compatible = "regulator-fixed"; + regulator-name = "vcmc623_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&gpio TEGRA_GPIO(L, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index 275b3432bd8..4a40edfdfbe 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -249,6 +249,35 @@ */ }; + /* Audio Bitstream Engine */ + bsea@60011000 { + compatible = "nvidia,tegra20-bsea"; + reg = <0x60011000 0x1000>, <0x4000c000 0x4000>; + reg-names = "bsea", "iram-buffer"; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bsea"; + clocks = <&tegra_car TEGRA20_CLK_BSEA>; + resets = <&tegra_car 62>; + reset-names = "bsea"; + status = "disabled"; + }; + + /* Video Bitstream Engine */ + bsev@6001b000 { + compatible = "nvidia,tegra20-bsev"; + reg = <0x6001b000 0x1000>, <0x40008000 0x4000>; + reg-names = "bsev", "iram-buffer"; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bsev"; + clocks = <&tegra_car TEGRA20_CLK_BSEV>, + <&tegra_car TEGRA20_CLK_VDE>; + clock-names = "bsev", "vde"; + resets = <&tegra_car 63>, + <&tegra_car 61>; + reset-names = "bsev", "vde"; + status = "disabled"; + }; + apbmisc@70000800 { compatible = "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64 /* Chip revision */ diff --git a/arch/arm/dts/tegra210-p3450-0000.dts b/arch/arm/dts/tegra210-p3450-0000.dts index 9ef744ac8b0..ddeeb232de2 100644 --- a/arch/arm/dts/tegra210-p3450-0000.dts +++ b/arch/arm/dts/tegra210-p3450-0000.dts @@ -124,7 +124,14 @@ spi@70410000 { status = "okay"; - spi-max-frequency = <80000000>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; }; usb@7d000000 { diff --git a/arch/arm/dts/tegra210.dtsi b/arch/arm/dts/tegra210.dtsi index 28ecd2b467a..92eb4f67bf5 100644 --- a/arch/arm/dts/tegra210.dtsi +++ b/arch/arm/dts/tegra210.dtsi @@ -762,10 +762,10 @@ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; - clocks = <&tegra_car TEGRA210_CLK_QSPI>; - clock-names = "qspi"; + clocks = <&tegra_car TEGRA210_CLK_QSPI>, + <&tegra_car TEGRA210_CLK_QSPI_PM>; + clock-names = "qspi", "qspi_out"; resets = <&tegra_car 211>; - reset-names = "qspi"; dmas = <&apbdma 5>, <&apbdma 5>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm/dts/tegra30-asus-grouper-common.dtsi b/arch/arm/dts/tegra30-asus-grouper-common.dtsi index d437ddc4dce..ddacdbb85c8 100644 --- a/arch/arm/dts/tegra30-asus-grouper-common.dtsi +++ b/arch/arm/dts/tegra30-asus-grouper-common.dtsi @@ -44,6 +44,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-asus-p1801-t.dts b/arch/arm/dts/tegra30-asus-p1801-t.dts index 58f1499cb92..31cbef1b93c 100644 --- a/arch/arm/dts/tegra30-asus-p1801-t.dts +++ b/arch/arm/dts/tegra30-asus-p1801-t.dts @@ -50,6 +50,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-asus-tf600t.dts b/arch/arm/dts/tegra30-asus-tf600t.dts index 1b5729c65f4..5135b8c666c 100644 --- a/arch/arm/dts/tegra30-asus-tf600t.dts +++ b/arch/arm/dts/tegra30-asus-tf600t.dts @@ -53,6 +53,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-asus-transformer.dtsi b/arch/arm/dts/tegra30-asus-transformer.dtsi index 032fb3d00ac..47a44fbc9dd 100644 --- a/arch/arm/dts/tegra30-asus-transformer.dtsi +++ b/arch/arm/dts/tegra30-asus-transformer.dtsi @@ -37,6 +37,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-htc-endeavoru.dts b/arch/arm/dts/tegra30-htc-endeavoru.dts index db8ac457880..79f423bd22a 100644 --- a/arch/arm/dts/tegra30-htc-endeavoru.dts +++ b/arch/arm/dts/tegra30-htc-endeavoru.dts @@ -60,6 +60,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts index 876fac7b661..53f42089d30 100644 --- a/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts +++ b/arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts @@ -43,6 +43,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-lg-x3.dtsi b/arch/arm/dts/tegra30-lg-x3.dtsi index 40b0ee07787..09c5d04a225 100644 --- a/arch/arm/dts/tegra30-lg-x3.dtsi +++ b/arch/arm/dts/tegra30-lg-x3.dtsi @@ -42,6 +42,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-ouya.dts b/arch/arm/dts/tegra30-ouya.dts index 04453eb2432..e6b2824d783 100644 --- a/arch/arm/dts/tegra30-ouya.dts +++ b/arch/arm/dts/tegra30-ouya.dts @@ -56,6 +56,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30-pegatron-chagall.dts b/arch/arm/dts/tegra30-pegatron-chagall.dts new file mode 100644 index 00000000000..98eb369f7a8 --- /dev/null +++ b/arch/arm/dts/tegra30-pegatron-chagall.dts @@ -0,0 +1,1291 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra30.dtsi" + +/ { + model = "Pegatron Chagall"; + compatible = "pegatron,chagall", "nvidia,tegra30"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + i2c0 = &pwr_i2c; + + mmc0 = &sdmmc4; /* eMMC */ + mmc1 = &sdmmc1; /* uSD slot */ + + rtc0 = &pmic; + rtc1 = "/rtc@7000e000"; + + usb0 = &usb1; + usb1 = &usb3; /* Dock USB */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + host1x@50000000 { + dc@54200000 { + rgb { + status = "okay"; + + port { + dpi_output: endpoint { + remote-endpoint = <&bridge_input>; + bus-width = <24>; + }; + }; + }; + }; + }; + + pinmux@70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + /* SDMMC1 pinmux */ + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc1_dat3_py4 { + nvidia,pins = "sdmmc1_dat3_py4", + "sdmmc1_dat2_py5", + "sdmmc1_dat1_py6", + "sdmmc1_dat0_py7", + "sdmmc1_cmd_pz1"; + nvidia,function = "sdmmc1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC2 pinmux */ + vi_d1_pd5 { + nvidia,pins = "vi_d1_pd5", + "vi_d2_pl0", + "vi_d3_pl1", + "vi_d5_pl3", + "vi_d7_pl5"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d8_pl6 { + nvidia,pins = "vi_d8_pl6", + "vi_d9_pl7"; + nvidia,function = "sdmmc2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + /* SDMMC3 pinmux */ + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat3_pb4", + "sdmmc3_dat2_pb5", + "sdmmc3_dat1_pb6", + "sdmmc3_dat0_pb7", + "sdmmc3_dat5_pd0", + "sdmmc3_dat4_pd1", + "sdmmc3_dat6_pd3", + "sdmmc3_dat7_pd4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* SDMMC4 pinmux */ + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2C pinmux */ + gen1_i2c_scl_pc4 { + nvidia,pins = "gen1_i2c_scl_pc4", + "gen1_i2c_sda_pc5"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + /* HDMI-CEC pinmux */ + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + }; + + /* UART-A */ + ulpi_data0_po1 { + nvidia,pins = "ulpi_data0_po1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ulpi_data1_po2 { + nvidia,pins = "ulpi_data1_po2", + "ulpi_data2_po3", + "ulpi_data3_po4", + "ulpi_data4_po5", + "ulpi_data5_po6", + "ulpi_data6_po7"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + ulpi_data7_po0 { + nvidia,pins = "ulpi_data7_po0"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-B */ + uart2_txd_pc2 { + nvidia,pins = "uart2_txd_pc2", + "uart2_rts_n_pj6"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + uart2_rxd_pc3 { + nvidia,pins = "uart2_rxd_pc3", + "uart2_cts_n_pj5"; + nvidia,function = "uartb"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* UART-C */ + uart3_cts_n_pa1 { + nvidia,pins = "uart3_cts_n_pa1", + "uart3_rxd_pw7"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + uart3_rts_n_pc0 { + nvidia,pins = "uart3_rts_n_pc0", + "uart3_txd_pw6"; + nvidia,function = "uartc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* UART-D */ + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_stp_py3"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1", + "ulpi_nxt_py2"; + nvidia,function = "uartd"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* I2S pinmux */ + dap1_fs_pn0 { + nvidia,pins = "dap1_fs_pn0", + "dap1_din_pn1", + "dap1_dout_pn2", + "dap1_sclk_pn3"; + nvidia,function = "i2s0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap2_fs_pa2 { + nvidia,pins = "dap2_fs_pa2", + "dap2_sclk_pa3", + "dap2_din_pa4", + "dap2_dout_pa5"; + nvidia,function = "i2s1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap3_fs_pp0 { + nvidia,pins = "dap3_fs_pp0", + "dap3_din_pp1", + "dap3_dout_pp2", + "dap3_sclk_pp3"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + dap4_fs_pp4 { + nvidia,pins = "dap4_fs_pp4", + "dap4_din_pp5", + "dap4_dout_pp6", + "dap4_sclk_pp7"; + nvidia,function = "i2s3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pcc2 { + nvidia,pins = "pcc2"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* PCI-e pinmux */ + pex_l2_rst_n_pcc6 { + nvidia,pins = "pex_l2_rst_n_pcc6", + "pex_l0_rst_n_pdd1", + "pex_l1_rst_n_pdd5"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pex_l2_clkreq_n_pcc7 { + nvidia,pins = "pex_l2_clkreq_n_pcc7", + "pex_l0_prsnt_n_pdd0", + "pex_l0_clkreq_n_pdd2", + "pex_l2_prsnt_n_pdd7"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pcie"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* SPI pinmux */ + spi1_mosi_px4 { + nvidia,pins = "spi1_mosi_px4", + "spi1_sck_px5", + "spi1_cs0_n_px6", + "spi1_miso_px7"; + nvidia,function = "spi1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_cs1_n_pw2 { + nvidia,pins = "spi2_cs1_n_pw2", + "spi2_cs2_n_pw3"; + nvidia,function = "spi2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + spi2_sck_px2 { + nvidia,pins = "spi2_sck_px2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_a16_pj7 { + nvidia,pins = "gmi_a16_pj7", + "gmi_a19_pk7"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_a17_pb0 { + nvidia,pins = "gmi_a17_pb0", + "gmi_a18_pb1"; + nvidia,function = "spi4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spi2_mosi_px0 { + nvidia,pins = "spi2_mosi_px0"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spdif_out_pk5 { + nvidia,pins = "spdif_out_pk5"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + spdif_in_pk6 { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* Display A pinmux */ + lcd_pwr0_pb2 { + nvidia,pins = "lcd_pwr0_pb2", + "lcd_pclk_pb3", + "lcd_pwr1_pc1", + "lcd_pwr2_pc6", + "lcd_d0_pe0", + "lcd_d1_pe1", + "lcd_d2_pe2", + "lcd_d3_pe3", + "lcd_d4_pe4", + "lcd_d5_pe5", + "lcd_d6_pe6", + "lcd_d7_pe7", + "lcd_d8_pf0", + "lcd_d9_pf1", + "lcd_d10_pf2", + "lcd_d11_pf3", + "lcd_d12_pf4", + "lcd_d13_pf5", + "lcd_d14_pf6", + "lcd_d15_pf7", + "lcd_de_pj1", + "lcd_hsync_pj3", + "lcd_vsync_pj4", + "lcd_d16_pm0", + "lcd_d17_pm1", + "lcd_d18_pm2", + "lcd_d19_pm3", + "lcd_d20_pm4", + "lcd_d21_pm5", + "lcd_d22_pm6", + "lcd_d23_pm7", + "lcd_cs0_n_pn4", + "lcd_sdout_pn5", + "lcd_dc0_pn6", + "lcd_sdin_pz2", + "lcd_wr_n_pz3", + "lcd_sck_pz4", + "lcd_cs1_n_pw0", + "lcd_m1_pw1"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + lcd_dc1_pd2 { + nvidia,pins = "lcd_dc1_pd2"; + nvidia,function = "displaya"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk_32k_out_pa0 { + nvidia,pins = "clk_32k_out_pa0"; + nvidia,function = "blink"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + /* KBC keys */ + kb_row0_pr0 { + nvidia,pins = "kb_row0_pr0", + "kb_row1_pr1", + "kb_row2_pr2", + "kb_row3_pr3", + "kb_row8_ps0", + "kb_col0_pq0", + "kb_col1_pq1", + "kb_col2_pq2", + "kb_col3_pq3", + "kb_col4_pq4", + "kb_col5_pq5", + "kb_col7_pq7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row4_pr4 { + nvidia,pins = "kb_row4_pr4", + "kb_row7_pr7", + "kb_row10_ps2", + "kb_row13_ps5"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row11_ps3 { + nvidia,pins = "kb_row11_ps3", + "kb_row12_ps4", + "kb_row15_ps7"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + kb_row14_ps6 { + nvidia,pins = "kb_row14_ps6"; + nvidia,function = "kbc"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_iordy_pi5 { + nvidia,pins = "gmi_iordy_pi5"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_pclk_pt0 { + nvidia,pins = "vi_pclk_pt0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + pu1 { + nvidia,pins = "pu1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu2 { + nvidia,pins = "pu2"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pv0 { + nvidia,pins = "pv0"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pv1 { + nvidia,pins = "pv1"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pcc1 { + nvidia,pins = "pcc1"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + sdmmc4_rst_n_pcc3 { + nvidia,pins = "sdmmc4_rst_n_pcc3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pv3 { + nvidia,pins = "pv3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_vsync_pd6 { + nvidia,pins = "vi_vsync_pd6", + "vi_hsync_pd7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_d10_pt2 { + nvidia,pins = "vi_d10_pt2", + "vi_d0_pt4", "pbb0"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + vi_d11_pt3 { + nvidia,pins = "vi_d11_pt3"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu0 { + nvidia,pins = "pu0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu3 { + nvidia,pins = "pu3"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu6 { + nvidia,pins = "pu6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pex_l1_prsnt_n_pdd4 { + nvidia,pins = "pex_l1_prsnt_n_pdd4", + "pex_l1_clkreq_n_pdd6"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_wait_pi7 { + nvidia,pins = "gmi_wait_pi7", + "gmi_cs0_n_pj0", + "gmi_cs1_n_pj2", + "gmi_cs4_n_pk2"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad0_pg0 { + nvidia,pins = "gmi_ad0_pg0", + "gmi_ad1_pg1", + "gmi_ad2_pg2", + "gmi_ad3_pg3", + "gmi_ad4_pg4", + "gmi_ad5_pg5", + "gmi_ad6_pg6", + "gmi_ad7_pg7", + "gmi_wr_n_pi0", + "gmi_oe_n_pi1", + "gmi_dqs_pi2", + "gmi_adv_n_pk0", + "gmi_clk_pk1"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_cs2_n_pk3 { + nvidia,pins = "gmi_cs2_n_pk3"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs3_n_pk4 { + nvidia,pins = "gmi_cs3_n_pk4"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad10_ph2 { + nvidia,pins = "gmi_ad10_ph2", + "gmi_ad11_ph3", + "gmi_ad14_ph6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad13_ph5 { + nvidia,pins = "gmi_ad13_ph5", + "gmi_ad12_ph4", + "gmi_cs7_n_pi6"; + nvidia,function = "nand"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_rst_n_pi4 { + nvidia,pins = "gmi_rst_n_pi4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_ad8_ph0 { + nvidia,pins = "gmi_ad8_ph0"; + nvidia,function = "pwm0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_ad9_ph1 { + nvidia,pins = "gmi_ad9_ph1"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + gmi_wp_n_pc7 { + nvidia,pins = "gmi_wp_n_pc7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + gmi_cs6_n_pi3 { + nvidia,pins = "gmi_cs6_n_pi3"; + nvidia,function = "sata"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_d4_pl2 { + nvidia,pins = "vi_d4_pl2"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + vi_d6_pl4 { + nvidia,pins = "vi_d6_pl4"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,lock = <0>; + nvidia,io-reset = <0>; + }; + + vi_mclk_pt1 { + nvidia,pins = "vi_mclk_pt1"; + nvidia,function = "vi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* HDMI hot-plug-detect */ + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "hdmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pu4 { + nvidia,pins = "pu4"; + nvidia,function = "pwm1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pu5 { + nvidia,pins = "pu5"; + nvidia,function = "pwm2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + jtag_rtck_pu7 { + nvidia,pins = "jtag_rtck_pu7"; + nvidia,function = "rtck"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + crt_hsync_pv6 { + nvidia,pins = "crt_hsync_pv6", + "crt_vsync_pv7"; + nvidia,function = "crt"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk1_out_pw4 { + nvidia,pins = "clk1_out_pw4"; + nvidia,function = "extperiph1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk2_out_pw5 { + nvidia,pins = "clk2_out_pw5"; + nvidia,function = "extperiph2"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + sys_clk_req_pz5 { + nvidia,pins = "sys_clk_req_pz5"; + nvidia,function = "sysclk"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb4 { + nvidia,pins = "pbb4"; + nvidia,function = "vgp4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb5 { + nvidia,pins = "pbb5"; + nvidia,function = "vgp5"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb6 { + nvidia,pins = "pbb6"; + nvidia,function = "vgp6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + clk1_req_pee2 { + nvidia,pins = "clk1_req_pee2"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk2_req_pcc5 { + nvidia,pins = "clk2_req_pcc5"; + nvidia,function = "dap"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + clk3_req_pee1 { + nvidia,pins = "clk3_req_pee1"; + nvidia,function = "dev3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + owr { + nvidia,pins = "owr"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pv2 { + nvidia,pins = "pv2", + "kb_row5_pr5"; + nvidia,function = "owr"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + + pbb3 { + nvidia,pins = "pbb3"; + nvidia,function = "vgp3"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + pbb7 { + nvidia,pins = "pbb7"; + nvidia,function = "i2s4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + cam_mclk_pcc0 { + nvidia,pins = "cam_mclk_pcc0"; + nvidia,function = "vi_alt3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + + /* GPIO power/drive control */ + drive_dap1 { + nvidia,pins = "drive_dap1", + "drive_dap2", + "drive_dbg", + "drive_at5", + "drive_gme", + "drive_ddc", + "drive_ao1", + "drive_uart3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <5>; + nvidia,pull-up-strength = <5>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>; + }; + + drive_gma { + nvidia,pins = "drive_gma", + "drive_gmb", + "drive_gmc", + "drive_gmd"; + nvidia,pull-down-strength = <9>; + nvidia,pull-up-strength = <9>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; + }; + + drive_lcd2 { + nvidia,pins = "drive_lcd2"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <TEGRA_PIN_ENABLE>; + nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>; + nvidia,pull-down-strength = <20>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + }; + }; + + uarta: serial@70006000 { + status = "okay"; + }; + + pwm: pwm@7000a000 { + status = "okay"; + }; + + pwr_i2c: i2c@7000d000 { + status = "okay"; + clock-frequency = <400000>; + + /* Texas Instruments TPS659110 PMIC */ + pmic: tps65911@2d { + compatible = "ti,tps65911"; + reg = <0x2d>; + + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + #gpio-cells = <2>; + gpio-controller; + + regulators { + vdd_1v8_vio: vddio { + regulator-name = "vdd_1v8_gen"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* eMMC VDD */ + vcore_emmc: ldo1 { + regulator-name = "vdd_emmc_core"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + /* uSD slot VDD */ + vdd_usd: ldo2 { + regulator-name = "vdd_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-boot-on; + }; + + /* uSD slot VDDIO */ + vddio_usd: ldo3 { + regulator-name = "vddio_usd"; + regulator-min-microvolt = <3100000>; + regulator-max-microvolt = <3100000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + }; + + sdmmc1: sdhci@78000000 { + status = "okay"; + bus-width = <4>; + + cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vdd_usd>; + vqmmc-supply = <&vddio_usd>; + }; + + sdmmc4: sdhci@78000600 { + status = "okay"; + bus-width = <8>; + non-removable; + + vmmc-supply = <&vcore_emmc>; + vqmmc-supply = <&vdd_1v8_vio>; + }; + + usb1: usb@7d000000 { + status = "okay"; + dr_mode = "otg"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d000000 { + status = "okay"; + nvidia,hssync-start-delay = <0>; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb3: usb@7d008000 { + status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 6) GPIO_ACTIVE_HIGH>; + }; + + usb-phy@7d008000 { + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_5v0_bl>; + pwms = <&pwm 0 5000000>; + + brightness-levels = <1 35 70 105 140 175 210 255>; + default-brightness-level = <5>; + }; + + /* PMIC has a built-in 32KHz oscillator which is used by PMC */ + clk32k_in: clock-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic-oscillator"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_UP>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = <KEY_DOWN>; + }; + }; + + display-panel { + compatible = "hannstar,hsd101pww2", "simple-panel"; + + power-supply = <&vdd_pnl_reg>; + backlight = <&backlight>; + + display-timings { + timing@0 { + /* 1280x800@60Hz */ + clock-frequency = <68000000>; + + hactive = <1280>; + hfront-porch = <48>; + hback-porch = <18>; + hsync-len = <30>; + + vactive = <800>; + vfront-porch = <3>; + vback-porch = <12>; + vsync-len = <5>; + }; + }; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + + /* Texas Instruments SN75LVDS83B LVDS Transmitter */ + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + + powerdown-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + + vdd_3v3_sys: regulator-3v { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_pnl_reg: regulator-pnl { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA_GPIO(W, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vdd_5v0_bl: regulator-bl { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0_bl"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; diff --git a/arch/arm/dts/tegra30-wexler-qc750.dts b/arch/arm/dts/tegra30-wexler-qc750.dts index b376b91a7fa..ededbf579fd 100644 --- a/arch/arm/dts/tegra30-wexler-qc750.dts +++ b/arch/arm/dts/tegra30-wexler-qc750.dts @@ -44,6 +44,10 @@ }; }; + bsev@6001b000 { + status = "okay"; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index d5de1ecaf05..82e843d05be 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -373,6 +373,35 @@ */ }; + /* Audio Bitstream Engine */ + bsea@60011000 { + compatible = "nvidia,tegra30-bsea"; + reg = <0x60011000 0x1000>, <0x4000c000 0x4000>; + reg-names = "bsea", "iram-buffer"; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bsea"; + clocks = <&tegra_car TEGRA30_CLK_BSEA>; + resets = <&tegra_car 62>; + reset-names = "bsea"; + status = "disabled"; + }; + + /* Video Bitstream Engine */ + bsev@6001b000 { + compatible = "nvidia,tegra30-bsev"; + reg = <0x6001b000 0x1000>, <0x40008000 0x4000>; + reg-names = "bsev", "iram-buffer"; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bsev"; + clocks = <&tegra_car TEGRA30_CLK_BSEV>, + <&tegra_car TEGRA30_CLK_VDE>; + clock-names = "bsev", "vde"; + resets = <&tegra_car 63>, + <&tegra_car 61>; + reset-names = "bsev", "vde"; + status = "disabled"; + }; + apbmisc@70000800 { compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; reg = <0x70000800 0x64 /* Chip revision */ diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 6ef8b1462eb..27ea639b741 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -267,7 +267,7 @@ shunt-resistor = <5000>; }; tps53681@60 { /* u53 - 0xc0 - FIXME name - don't know what it does - also vcc_io_soc */ - compatible = "ti,tps53681", "ti,tps53679"; + compatible = "ti,tps53681"; reg = <0x60>; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index c597adb80cb..ece01e73d29 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -256,7 +256,7 @@ #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ - compatible = "ti,tps53681", "ti,tps53679"; + compatible = "ti,tps53681"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index eefe5ab61e7..021fdce4abb 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -244,7 +244,7 @@ #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ - compatible = "ti,tps53681", "ti,tps53679"; + compatible = "ti,tps53681"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 7ea4eab6a37..c45822e1423 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -248,7 +248,7 @@ #size-cells = <0>; reg = <2>; reg_vccint: tps53681@60 { /* u69 - 0xc0 */ - compatible = "ti,tps53681", "ti,tps53679"; + compatible = "ti,tps53681"; reg = <0x60>; }; reg_vcc_pmc: tps544@7 { /* u80 */ diff --git a/arch/arm/dts/zynqmp-mini-nand.dts b/arch/arm/dts/zynqmp-mini-nand.dts index 1ece3999791..af2cd5b9bd8 100644 --- a/arch/arm/dts/zynqmp-mini-nand.dts +++ b/arch/arm/dts/zynqmp-mini-nand.dts @@ -42,7 +42,6 @@ clock-names = "clk_sys", "clk_flash"; #address-cells = <1>; #size-cells = <0>; - arasan,has-mdma; num-cs = <2>; nand@0 { reg = <0>; diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index fce0d8d5ca1..6aae2ad642d 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -178,7 +178,7 @@ reg = <0xa>; }; reg_vccint: tps53681@60 { /* u70 - FIXME name - don't know what it does - also vcc_io_soc */ - compatible = "ti,tps53681", "ti,tps53679"; + compatible = "ti,tps53681"; reg = <0x60>; /* vccint, vcc_io_soc */ }; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso index 3320bbc11fc..e94b784e8e1 100644 --- a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso @@ -43,6 +43,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; + i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso index 2ce69374c15..fd25731b0b4 100644 --- a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso @@ -44,6 +44,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; + i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; @@ -269,6 +270,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; + i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ddr4_dimm0: i2c@0 { /* wired but NC */ #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso index 8412aecd726..4d0f10e13c3 100644 --- a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso @@ -262,73 +262,73 @@ /* pmbus - j105 - disable main PMBUS - also going to j102 connector */ vcc_pslp: regulator@15 { /* u24 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x15>; }; vccaux_pmc: regulator@17 { /* u26 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x17>; }; vcco_500: regulator@18 { /* u27 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x18>; }; vcco_501: regulator@19 { /* u28 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x19>; }; vcco_502: regulator@1a { /* u29 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x1a>; }; vcco_503: regulator@1b { /* u30 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x1b>; }; vcc_ddr5_rdimm: regulator@1c { /* u31 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x1c>; }; gtm_avcc: regulator@22 { /* u37 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x22>; }; gtm_avtt: regulator@20 { /* u38 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x20>; }; gtm_avccaux: regulator@21 { /* u39 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x21>; }; vccint_gt: regulator@2a { /* u44 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x2a>; }; util_1v8: regulator@2b { /* u1839 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x2b>; }; vcc_pmc: regulator@2c { /* u46 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x2c>; }; /* pmbus via U62 as ext_pmbus - disable via j104 */ vccint: regulator@10 { /* u18 */ - compatible = "ti,tps546b24"; + compatible = "ti,tps546d24"; reg = <0x10>; }; diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso index 620afba06e6..c1945ea6f8d 100644 --- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso @@ -142,7 +142,7 @@ }; /* FMC eeproms at 0x50/0x51 */ - /* via j3/j5 to 0x68 to u32/9FGV1006C + /* via j3/j5 to 0x68 to u32/9FGV1006C */ /* i2c_main_1 - u147 - j157 - disable translation, add 8 */ /* J1 - OE for u43@55 + 8 - 161,132813MHz - QSFP56G_0 */ @@ -356,7 +356,7 @@ }; vcco_503: regulator@12 { /* u1744 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x12>; }; @@ -397,13 +397,13 @@ /* EXT_PMBUS main - J10 - disable extended PMBUS */ vccint: tps53681@60 { /* u1712 - J1770 reset jumper */ - compatible = "ti,tps53681", "ti,tps53679"; + compatible = "ti,tps53681"; reg = <0x60>; /* vccint, vcc_cpm5n */ }; vcc_io_soc: tps53681@61 { /* u1721 - J1772 reset jumper */ - compatible = "ti,tps53681", "ti,tps53679"; + compatible = "ti,tps53681"; reg = <0x61>; /* vcc_io_soc, vcc_fpd */ }; @@ -414,17 +414,17 @@ }; vcco_500: regulator@13 { /* u1738 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x13>; }; vcco_501: regulator@10 { /* u1740 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x10>; }; vcco_502: regulator@11 { /* u1742 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x11>; }; @@ -454,7 +454,7 @@ }; lp5_vddq_0v5: regulator@14 { /* u1763 - FIXME no ina226 */ - compatible = "ti,tps546b24a"; + compatible = "ti,tps546b24"; reg = <0x14>; }; }; diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso index 853d9817dd2..29b3a73fde0 100644 --- a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso @@ -38,6 +38,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; + i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; @@ -232,6 +233,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; + i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */ ref_clk_i2c: i2c@0 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso index ba5484573c9..10466ce99de 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso @@ -44,6 +44,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; + i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso index 3990d053c35..74e1c5c6dc9 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso @@ -44,6 +44,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x74>; + i2c-mux-idle-disconnect; /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */ pmbus_i2c: i2c@0 { #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index fbacfa984d7..88396d089f4 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -71,6 +71,17 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -143,6 +154,14 @@ phy-names = "dp-phy0"; phys = <&psgtr 1 PHY_TYPE_DP 0 1>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + out_dp: port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 0d915d496ca..e041a962d89 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -20,6 +20,11 @@ "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; model = "ZynqMP KR260 revB"; + aliases { + ethernet0 = "/axi/ethernet@ff0b0000"; /* &gem0 */ + ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ + }; + ina260-u14 { compatible = "iio-hwmon"; io-channels = <&u14 0>, <&u14 1>, <&u14 2>; @@ -152,7 +157,7 @@ assigned-clock-rates = <27000000>, <25000000>, <300000000>; ports { - port@5 { + out_dp: port@5 { dpsub_dp_out: endpoint { remote-endpoint = <&dpcon_in>; }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index 3c36eb52e96..fbbebbea80c 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -3,7 +3,7 @@ * dts file for KV260 revA Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. * * SD level shifter: * "A" - A01 board un-modified (NXP) @@ -72,6 +72,17 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -120,6 +131,14 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; + + ports { + out_dp: port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; + }; }; &zynqmp_dpdma { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 078d98e8ff3..87f94f8ef9d 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -3,7 +3,7 @@ * dts file for KV260 revA Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ @@ -118,7 +118,7 @@ assigned-clock-rates = <27000000>, <25000000>, <300000000>; ports { - port@5 { + out_dp: port@5 { dpsub_dp_out: endpoint { remote-endpoint = <&dpcon_in>; }; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 70acd3eb88b..0abec77b3f3 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -90,7 +90,7 @@ }; }; - pwm-fan { + pwm_fan: pwm-fan { compatible = "pwm-fan"; status = "okay"; pwms = <&ttc0 2 40000 1>; @@ -373,7 +373,6 @@ &rtc { status = "okay"; - calibration = <0x7fff>; }; &lpd_dma_chan1 { diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index 7849f8c540b..e9c6d249a8d 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -200,7 +200,7 @@ reg = <0>; /* On connector J325 */ reg_vccint: tps53681@60 { /* u266 - 0xc0 */ - compatible = "ti,tps53681", "ti,tps53679"; + compatible = "ti,tps53681"; reg = <0x60>; }; reg_vcc1v1_lp4: tps544@d { /* u85 */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index ff7069bc124..e3d5cf972e8 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -135,7 +135,6 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; - arasan,has-mdma; nand@0 { reg = <0x0>; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index 48ab619472e..e187818f333 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -129,7 +129,6 @@ /* MT29F64G08AECDBJ4-6 */ &nand0 { status = "okay"; - arasan,has-mdma; num-cs = <2>; nand@0 { diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 3542844e697..4ec8a400494 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -134,6 +134,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &dcc { @@ -607,3 +619,9 @@ phys = <&psgtr 1 PHY_TYPE_DP 0 1>, <&psgtr 0 PHY_TYPE_DP 1 1>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 955810ae717..7fa77b59906 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -151,6 +151,18 @@ #clock-cells = <0>; clock-frequency = <114285000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -1082,3 +1094,9 @@ phy-names = "dp-phy0"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 64d822255ec..135bfa08082 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -60,6 +60,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -545,3 +557,9 @@ phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 3e883d717c2..20d17a07e7e 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -65,6 +65,18 @@ #clock-cells = <0>; clock-frequency = <27000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &can1 { @@ -557,3 +569,9 @@ phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index ba3989cad3e..1ec95c67a7d 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -827,8 +827,8 @@ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; - drive-strength = <4>; - slew-rate = <SLEW_RATE_SLOW>; + drive-strength = <12>; + slew-rate = <SLEW_RATE_FAST>; }; }; @@ -1079,12 +1079,10 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 3>, <&psgtr 0 PHY_TYPE_DP 1 3>; +}; - ports { - port@5 { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; - }; - }; +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 3a1580dfc40..cfb4f648767 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -129,6 +129,18 @@ #clock-cells = <0>; clock-frequency = <48000000>; }; + + dpcon { + compatible = "dp-connector"; + label = "P11"; + type = "full-size"; + + port { + dpcon_in: endpoint { + remote-endpoint = <&dpsub_dp_out>; + }; + }; + }; }; &dcc { @@ -882,3 +894,9 @@ phys = <&psgtr 1 PHY_TYPE_DP 0 1>, <&psgtr 0 PHY_TYPE_DP 1 1>; }; + +&out_dp { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; +}; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 0e0436ecce8..02e1c4615c7 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -187,7 +187,7 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; @@ -547,6 +547,7 @@ reg = <0x0 0xfec10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu0>; + status = "disabled"; }; cpu1_debug: debug@fed10000 { @@ -554,6 +555,7 @@ reg = <0x0 0xfed10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu1>; + status = "disabled"; }; cpu2_debug: debug@fee10000 { @@ -561,6 +563,7 @@ reg = <0x0 0xfee10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu2>; + status = "disabled"; }; cpu3_debug: debug@fef10000 { @@ -568,6 +571,7 @@ reg = <0x0 0xfef10000 0x0 0x1000>; clock-names = "apb_pclk"; cpu = <&cpu3>; + status = "disabled"; }; /* GDMA */ @@ -1316,22 +1320,22 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + live_video: port@0 { reg = <0>; }; - port@1 { + live_gfx: port@1 { reg = <1>; }; - port@2 { + live_audio: port@2 { reg = <2>; }; - port@3 { + out_video: port@3 { reg = <3>; }; - port@4 { + out_audio: port@4 { reg = <4>; }; - port@5 { + out_dp: port@5 { reg = <5>; }; }; diff --git a/arch/arm/include/asm/arch-airoha/scu-regmap.h b/arch/arm/include/asm/arch-airoha/scu-regmap.h new file mode 100644 index 00000000000..31fc23d8c4d --- /dev/null +++ b/arch/arm/include/asm/arch-airoha/scu-regmap.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> + */ +#ifndef __AIROHA_SCU_REGMAP__ +#define __AIROHA_SCU_REGMAP__ + +#include <regmap.h> + +struct regmap *airoha_get_scu_regmap(void); +struct regmap *airoha_get_chip_scu_regmap(void); + +#endif diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h index 0fd52f82f59..316ec09318a 100644 --- a/arch/arm/include/asm/arch-am33xx/mem.h +++ b/arch/arm/include/asm/arch-am33xx/mem.h @@ -29,7 +29,7 @@ * * Currently valid part Names are (PART): * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL + * STNOR - STMicroelectronics M29W128GL */ #define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 diff --git a/arch/arm/include/asm/arch-an7581 b/arch/arm/include/asm/arch-an7581 new file mode 120000 index 00000000000..d2317ed3bc3 --- /dev/null +++ b/arch/arm/include/asm/arch-an7581 @@ -0,0 +1 @@ +arch-airoha
\ No newline at end of file diff --git a/arch/arm/include/asm/arch-bcm235xx/boot0.h b/arch/arm/include/asm/arch-bcm235xx/boot0.h deleted file mode 100644 index 8cde42b89bb..00000000000 --- a/arch/arm/include/asm/arch-bcm235xx/boot0.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Broadcom Corporation. - */ - -/* BOOT0 header information */ -_start: - ARM_VECTORS - .word 0xbabeface - .word _end - _start diff --git a/arch/arm/include/asm/arch-bcm235xx/gpio.h b/arch/arm/include/asm/arch-bcm235xx/gpio.h deleted file mode 100644 index 82c12bb70c2..00000000000 --- a/arch/arm/include/asm/arch-bcm235xx/gpio.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __ARCH_BCM235XX_GPIO_H -#define __ARCH_BCM235XX_GPIO_H - -/* - * Empty file - cmd_gpio.c requires this. The implementation - * is in drivers/gpio/kona_gpio.c instead of inlined here. - */ - -#endif diff --git a/arch/arm/include/asm/arch-bcm235xx/sysmap.h b/arch/arm/include/asm/arch-bcm235xx/sysmap.h deleted file mode 100644 index ff6debc677c..00000000000 --- a/arch/arm/include/asm/arch-bcm235xx/sysmap.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __ARCH_BCM235XX_SYSMAP_H - -#define BSC1_BASE_ADDR 0x3e016000 -#define BSC2_BASE_ADDR 0x3e017000 -#define BSC3_BASE_ADDR 0x3e018000 -#define GPIO2_BASE_ADDR 0x35003000 -#define HSOTG_BASE_ADDR 0x3f120000 -#define HSOTG_CTRL_BASE_ADDR 0x3f130000 -#define KONA_MST_CLK_BASE_ADDR 0x3f001000 -#define KONA_SLV_CLK_BASE_ADDR 0x3e011000 -#define PMU_BSC_BASE_ADDR 0x3500d000 -#define SDIO1_BASE_ADDR 0x3f180000 -#define SDIO2_BASE_ADDR 0x3f190000 -#define SDIO3_BASE_ADDR 0x3f1a0000 -#define SDIO4_BASE_ADDR 0x3f1b0000 -#define TIMER_BASE_ADDR 0x3e00d000 - -#define HSOTG_DCTL_OFFSET 0x00000804 -#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002 - -#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008 -#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002 -#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 - -#endif diff --git a/arch/arm/include/asm/arch-en7523 b/arch/arm/include/asm/arch-en7523 new file mode 120000 index 00000000000..d2317ed3bc3 --- /dev/null +++ b/arch/arm/include/asm/arch-en7523 @@ -0,0 +1 @@ +arch-airoha
\ No newline at end of file diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 1f669c72d00..1af9778f8ce 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -78,6 +78,8 @@ #define MXC_CPU_IMX95 0x1C1 /* dummy ID */ +#define MXC_CPU_IMX94 0x1C2 /* dummy ID */ + #define MXC_SOC_MX6 0x60 #define MXC_SOC_MX7 0x70 #define MXC_SOC_IMX8M 0x80 diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index ffaf6b5f7d8..ddc84d2c9ed 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -111,7 +111,7 @@ struct ccm_reg { u32 reserved_3[192]; struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */ u32 reserved_4[2768]; - struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */ + struct ccm_lpcg_oscpll clk_lpcgs[127]; /* 0x8000 */ }; struct ana_pll_reg_elem { diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h index 5127fe8f286..2d084e5227a 100644 --- a/arch/arm/include/asm/arch-imx9/imx-regs.h +++ b/arch/arm/include/asm/arch-imx9/imx-regs.h @@ -17,19 +17,33 @@ #define ANATOP_BASE_ADDR 0x44480000UL +#ifdef CONFIG_IMX94 +#define WDG3_BASE_ADDR 0x49220000UL +#define WDG4_BASE_ADDR 0x49230000UL +#else #define WDG3_BASE_ADDR 0x42490000UL #define WDG4_BASE_ADDR 0x424a0000UL +#endif #define WDG5_BASE_ADDR 0x424b0000UL #define GPIO2_BASE_ADDR 0x43810000UL #define GPIO3_BASE_ADDR 0x43820000UL #define GPIO4_BASE_ADDR 0x43840000UL #define GPIO5_BASE_ADDR 0x43850000UL +#ifdef CONFIG_IMX94 +#define GPIO6_BASE_ADDR 0x43860000UL +#define GPIO7_BASE_ADDR 0x43870000UL +#endif #define FSB_BASE_ADDR 0x47510000UL #define ANATOP_BASE_ADDR 0x44480000UL +#define USB1_BASE_ADDR 0x4c100000 +#define USB2_BASE_ADDR 0x4c200000 + +#define USB_BASE_ADDR USB2_BASE_ADDR + #define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x42420000 #define BLK_CTRL_NS_ANOMIX_BASE_ADDR 0x44210000 #define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f0000 @@ -48,7 +62,7 @@ #define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8) #define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12) -#define IMG_CONTAINER_BASE (0x80000000UL) +#define IMG_CONTAINER_BASE CFG_SYS_SDRAM_BASE #define BCTRL_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 1) #define BCTRL_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1) diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index df2148a53c7..dead7a99a66 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -18,8 +18,10 @@ enum imx9_soc_voltage_mode { void soc_power_init(void); bool m33_is_rom_kicked(void); int m33_prepare(void); +int low_drive_freq_update(void *blob); enum imx9_soc_voltage_mode soc_target_voltage_mode(void); +int get_reset_reason(bool sys, bool lm); #define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode)) diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h index b2d87524f70..e4005b94b54 100644 --- a/arch/arm/include/asm/arch-lpc32xx/config.h +++ b/arch/arm/include/asm/arch-lpc32xx/config.h @@ -17,25 +17,6 @@ #define CFG_SYS_BAUDRATE_TABLE \ { 9600, 19200, 38400, 57600, 115200, 230400, 460800 } -/* NAND */ -#if defined(CONFIG_NAND_LPC32XX_SLC) -#define NAND_LARGE_BLOCK_PAGE_SIZE 0x800 -#define NAND_SMALL_BLOCK_PAGE_SIZE 0x200 - -#if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE) -#define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } -#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE) -#define CFG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, } -#else -#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value" -#endif - -#define CFG_SYS_NAND_ECCSIZE 0x100 -#define CFG_SYS_NAND_ECCBYTES 3 -#endif /* CONFIG_NAND_LPC32XX_SLC */ - /* NOR Flash */ /* USB OHCI */ diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h index bd72fb611d1..4f26daf1c43 100644 --- a/arch/arm/include/asm/arch-omap5/mem.h +++ b/arch/arm/include/asm/arch-omap5/mem.h @@ -29,7 +29,7 @@ * * Currently valid part Names are (PART): * M_NAND - Micron NAND - * STNOR - STMicrolelctronics M29W128GL + * STNOR - STMicroelectronics M29W128GL */ #define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index e736772fda7..b15938c021d 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -64,4 +64,6 @@ extern const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1]; */ #define BROM_BOOTSOURCE_ID_ADDR (CFG_IRAM_BASE + 0x10) +u32 read_brom_bootsource_id(void); + #endif diff --git a/arch/arm/include/asm/arch-tegra/ap.h b/arch/arm/include/asm/arch-tegra/ap.h index b922b2d30ea..295c3287737 100644 --- a/arch/arm/include/asm/arch-tegra/ap.h +++ b/arch/arm/include/asm/arch-tegra/ap.h @@ -55,6 +55,13 @@ int tegra_get_chip_sku(void); int tegra_get_chip(void); /** + * Returns the pure SOC major version from the HIDREV register + * + * Return: SOC major version + */ +u32 tegra_get_major_version(void); + +/** * Returns the SKU ID from the sku_info register * * Return: SKU ID - see SKU_ID_Txx... diff --git a/arch/arm/include/asm/arch-tegra/crypto.h b/arch/arm/include/asm/arch-tegra/crypto.h index 7646163b97b..930bc842039 100644 --- a/arch/arm/include/asm/arch-tegra/crypto.h +++ b/arch/arm/include/asm/arch-tegra/crypto.h @@ -7,41 +7,36 @@ #ifndef _CRYPTO_H_ #define _CRYPTO_H_ -/** - * Sign a block of data - * - * \param source Source data - * \param length Size of source data - * \param signature Destination address for signature, AES_KEY_LENGTH bytes - */ -int sign_data_block(u8 *source, unsigned int length, u8 *signature); +#define TEGRA_AES_SLOT_SBK 0 /** - * Sign an encrypted block of data + * sign_data_block - Sign a block of data * - * \param source Source data - * \param length Size of source data - * \param signature Destination address for signature, AES_KEY_LENGTH bytes - * \param key AES128 encryption key + * @source Source data + * @length Size of source data in bytes + * @signature Destination address for signature, AES_KEY_LENGTH bytes + * Return: 0 on success, negative value on failure */ -int sign_enc_data_block(u8 *source, unsigned int length, u8 *signature, u8 *key); +int sign_data_block(u8 *source, unsigned int length, u8 *signature); /** - * Encrypt a block of data + * encrypt_data_block - Encrypt a block of data * - * \param source Source data - * \param length Size of source data - * \param key AES128 encryption key + * @source Source data + * @dest Destination data + * @length Size of source data in bytes + * Return: 0 on success, negative value on failure */ -int encrypt_data_block(u8 *source, unsigned int length, u8 *key); +int encrypt_data_block(u8 *source, u8 *dest, unsigned int length); /** - * Decrypt a block of data + * decrypt_data_block - Decrypt a block of data * - * \param source Source data - * \param length Size of source data - * \param key AES128 encryption key + * @source Source data + * @dest Destination data + * @length Size of source data in bytes + * Return: 0 on success, negative value on failure */ -int decrypt_data_block(u8 *source, unsigned int length, u8 *key); +int decrypt_data_block(u8 *source, u8 *dest, unsigned int length); #endif /* #ifndef _CRYPTO_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h index ab12cc9c7d0..22f8f977cc6 100644 --- a/arch/arm/include/asm/arch-tegra/dc.h +++ b/arch/arm/include/asm/arch-tegra/dc.h @@ -448,6 +448,9 @@ enum win_color_depth_id { #define LVS_OUTPUT_POLARITY_LOW BIT(28) #define LSC0_OUTPUT_POLARITY_LOW BIT(24) +/* DC_COM_PIN_OUTPUT_POLARITY3 0x309 */ +#define LSPI_OUTPUT_POLARITY_LOW BIT(8) + /* DC_COM_PIN_OUTPUT_SELECT6 0x31a */ #define LDC_OUTPUT_SELECT_V_PULSE1 BIT(14) /* 100b */ diff --git a/arch/arm/include/asm/arch-tegra/fuse.h b/arch/arm/include/asm/arch-tegra/fuse.h index f3f2ad8e3f2..631ebbb283c 100644 --- a/arch/arm/include/asm/arch-tegra/fuse.h +++ b/arch/arm/include/asm/arch-tegra/fuse.h @@ -17,8 +17,22 @@ struct fuse_regs { u32 fa; /* 0x148: FUSE_FA */ u32 reserved3[21]; /* 0x14C - 0x19C: */ u32 security_mode; /* 0x1A0: FUSE_SECURITY_MODE */ + u32 sbk[4]; /* 0x1A4 - 0x1B4 */ }; +/* Defines the supported operating modes */ +enum fuse_operating_mode { + MODE_UNDEFINED = 0, + MODE_PRODUCTION = 3, + MODE_ODM_PRODUCTION_SECURE = 4, + MODE_ODM_PRODUCTION_OPEN = 5, +}; + +/** + * Initializes fuse hardware + */ +void tegra_fuse_init(void); + /** * Calculate SoC UID * @@ -26,4 +40,11 @@ struct fuse_regs { */ unsigned long long tegra_chip_uid(void); +/** + * Gives the current operating mode from fuses + * + * @return current operating mode + */ +enum fuse_operating_mode tegra_fuse_get_operation_mode(void); + #endif /* ifndef _FUSE_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/warmboot.h b/arch/arm/include/asm/arch-tegra/warmboot.h index 9a53456370f..4352f1dc5e8 100644 --- a/arch/arm/include/asm/arch-tegra/warmboot.h +++ b/arch/arm/include/asm/arch-tegra/warmboot.h @@ -10,12 +10,6 @@ #define STRAP_OPT_A_RAM_CODE_SHIFT 4 #define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) -/* Defines the supported operating modes */ -enum fuse_operating_mode { - MODE_PRODUCTION = 3, - MODE_UNDEFINED, -}; - /* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ enum { HASH_LENGTH = 4 @@ -125,7 +119,6 @@ union scratch3_reg { int warmboot_save_sdram_params(void); int warmboot_prepare_code(u32 seg_address, u32 seg_length); -int sign_data_block(u8 *source, u32 length, u8 *signature); void wb_start(void); /* Start of WB assembly code */ void wb_end(void); /* End of WB assembly code */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index c002998ac0b..bfffbbd5d9a 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -142,6 +142,8 @@ bool armv7_boot_nonsec(void); unsigned int _nonsec_init(void); void _do_nonsec_entry(void *target_pc, unsigned long r0, unsigned long r1, unsigned long r2); +void boot_jump_linux_via_optee(void *target_pc, unsigned long r1, + unsigned long r2, unsigned long tee_entry); void _smp_pen(void); extern char __secure_start[]; diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index e906fdf1bf1..d8f0e16dadd 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -11,6 +11,7 @@ #define MIDR_PARTNUM_CORTEX_A73 0xD09 #define MIDR_PARTNUM_CORTEX_A75 0xD0A #define MIDR_PARTNUM_CORTEX_A76 0xD0B +#define MIDR_PARTNUM_CORTEX_A720 0xD81 #define MIDR_PARTNUM_SHIFT 0x4 #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) @@ -40,3 +41,4 @@ is_cortex_a(72) is_cortex_a(73) is_cortex_a(75) is_cortex_a(76) +is_cortex_a(720) diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 6af8cd111a4..8aa5f9721c4 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -194,9 +194,34 @@ struct mm_region { u64 attrs; }; +/* Used as the memory map for MMU configuration by mmu_setup */ extern struct mm_region *mem_map; void setup_pgtables(void); + +/** + * mem_map_from_dram_banks() - Populate mem_map with entries corresponding to + * dram banks as per the gd. This should be called prior to mmu_setup. + * + * @index: The entry in mem_map to start the over-write + * @len: The size of mem_map + */ +int mem_map_from_dram_banks(unsigned int index, unsigned int len, u64 attrs); + +/** + * mmu_unmap_reserved_mem() - Unmaps a reserved-memory node as PTE_TYPE_FAULT + * once MMU is configured by mmu_setup. + * + * @name: The name of the node under "/reserved-memory/" path + * @check_nomap: Check if the node is marked "no-map" before unmapping it + */ +int mmu_unmap_reserved_mem(const char *name, bool check_nomap); + u64 get_tcr(u64 *pips, u64 *pva_bits); + +/** + * mmu_setup() - Sets up the mmu page tables as per mem_map + */ +void mmu_setup(void); #endif #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 85ec0e6937e..cebed7397d4 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -386,12 +386,14 @@ void __memcpy_fromio(void *to, const volatile void __iomem *from, size_t count) count--; } - if (mmu_status()) { - while (count >= 8) { - *(u64 *)to = __raw_readq(from); - from += 8; - to += 8; - count -= 8; + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + if (mmu_status()) { + while (count >= 8) { + *(u64 *)to = __raw_readq(from); + from += 8; + to += 8; + count -= 8; + } } } @@ -416,12 +418,14 @@ void __memcpy_toio(volatile void __iomem *to, const void *from, size_t count) count--; } - if (mmu_status()) { - while (count >= 8) { - __raw_writeq(*(u64 *)from, to); - from += 8; - to += 8; - count -= 8; + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) { + if (mmu_status()) { + while (count >= 8) { + __raw_writeq(*(u64 *)from, to); + from += 8; + to += 8; + count -= 8; + } } } diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 0780f99b49a..46da7a1eff5 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -97,6 +97,7 @@ struct bd_info; #define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302)) #define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301)) +#define is_imx94() (is_cpu_type(MXC_CPU_IMX94)) #define is_imx95() (is_cpu_type(MXC_CPU_IMX95)) #define is_imx9121() (is_cpu_type(MXC_CPU_IMX9121)) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index ade42d0ca43..11cb3a7145e 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -7,6 +7,10 @@ lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o \ lib1funcs.o uldivmod.o div0.o \ div64.o muldi3.o +obj-$(CONFIG_$(PHASE_)LIB_BOOTI) += image.o +obj-$(CONFIG_$(PHASE_)LIB_BOOTZ) += zimage.o +obj-$(CONFIG_$(PHASE_)LIB_BOOTM) += bootm.o + ifdef CONFIG_CPU_V7M obj-y += vectors_m.o crt0.o else ifdef CONFIG_ARM64 @@ -30,17 +34,14 @@ endif obj-$(CONFIG_CPU_V7M) += cmd_boot.o obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o -obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o -obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o else obj-$(CONFIG_$(PHASE_)FRAMEWORK) += spl.o -ifdef CONFIG_SPL_FRAMEWORK -obj-$(CONFIG_CMD_BOOTI) += image.o -obj-$(CONFIG_CMD_BOOTZ) += zimage.o -endif obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o endif +ifndef CONFIG_ARM64 +obj-$(CONFIG_BOOTM_OPTEE) += bootm-optee.o +endif ifdef CONFIG_ARM64 obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMSET) += memset-arm64.o obj-$(CONFIG_$(PHASE_)USE_ARCH_MEMCPY) += memcpy-arm64.o diff --git a/arch/arm/lib/bootm-optee.S b/arch/arm/lib/bootm-optee.S new file mode 100644 index 00000000000..9d1a77b563d --- /dev/null +++ b/arch/arm/lib/bootm-optee.S @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Marek Vasut + */ +#include <config.h> +#include <linux/linkage.h> + +ENTRY(boot_jump_linux_via_optee) + mov r4, r3 + mov lr, r0 + mov r3, #0 + mov r0, #0 + + /* + * Special TZC handling on this platform, the last + * 'str' has to be immediately before 'bx' and can + * not be interleaved with any return from function + * call, if it is then the system hangs. + */ +#if defined(CONFIG_STM32MP13X) && !defined(CONFIG_TFABOOT) + ldr r6, =STM32_TZC_BASE + 0x114 + (0x20 * 2) + mov r7, #0x0 + str r7, [r6] + ldr r6, =STM32_TZC_BASE + 0x110 + (0x20 * 1) + mov r7, #0x1 + str r7, [r6] +#endif + + bx r4 +ENDPROC(boot_jump_linux_via_optee) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 7eb764e1f4e..019eca95780 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -57,6 +57,7 @@ static void announce_and_cleanup(int fake) #ifdef CONFIG_BOOTSTAGE_FDT bootstage_fdt_add_report(); #endif + bootstage_stash_default(); #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); #endif @@ -183,7 +184,7 @@ __weak void setup_board_tags(struct tag **in_params) {} static void do_nonsec_virt_switch(void) { smp_kick_all_cpus(); - dcache_disable(); /* flush cache before swtiching to EL2 */ + dcache_disable(); /* flush cache before switching to EL2 */ } #endif @@ -258,6 +259,11 @@ bool armv7_boot_nonsec(void) return nonsec; } +#else +bool armv7_boot_nonsec(void) +{ + return false; +} #endif #ifdef CONFIG_ARM64 @@ -283,9 +289,9 @@ static void switch_to_el1(void) #endif /* Subcommand: GO */ +#ifdef CONFIG_ARM64 static void boot_jump_linux(struct bootm_headers *images, int flag) { -#ifdef CONFIG_ARM64 void (*kernel_entry)(void *fdt_addr, void *res0, void *res1, void *res2); int fake = (flag & BOOTM_STATE_OS_FAKE_GO); @@ -323,7 +329,13 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) ES_TO_AARCH64); #endif } +} #else +static __maybe_unused bool boot_jump_via_optee; +static __maybe_unused unsigned long boot_jump_via_optee_addr; + +static void boot_jump_linux(struct bootm_headers *images, int flag) +{ unsigned long machid = gd->bd->bi_arch_number; char *s; void (*kernel_entry)(int zero, int arch, uint params); @@ -335,6 +347,13 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) ulong addr = (ulong)kernel_entry | 1; kernel_entry = (void *)addr; #endif + + if (IS_ENABLED(CONFIG_ARMV7_NONSEC) && armv7_boot_nonsec() && + boot_jump_via_optee) { + printf("Cannot start OPTEE-OS from NS\n"); + return; + } + s = env_get("machid"); if (s) { if (strict_strtoul(s, 16, &machid) < 0) { @@ -354,19 +373,39 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) else r2 = gd->bd->bi_boot_params; - if (!fake) { + if (fake) + return; + #ifdef CONFIG_ARMV7_NONSEC - if (armv7_boot_nonsec()) { - armv7_init_nonsec(); - secure_ram_addr(_do_nonsec_entry)(kernel_entry, - 0, machid, r2); - } else + if (armv7_boot_nonsec()) + armv7_init_nonsec(); #endif - kernel_entry(0, machid, r2); - } + +#ifdef CONFIG_BOOTM_OPTEE + if (boot_jump_via_optee) + boot_jump_linux_via_optee(kernel_entry, machid, r2, boot_jump_via_optee_addr); +#endif + +#ifdef CONFIG_ARMV7_NONSEC + if (armv7_boot_nonsec()) { + secure_ram_addr(_do_nonsec_entry)(kernel_entry, 0, machid, r2); + } else #endif + { + kernel_entry(0, machid, r2); + } } +#ifndef CONFIG_TI_SECURE_DEVICE +static void arch_tee_image_process(ulong image, size_t size) +{ + boot_jump_via_optee = true; + boot_jump_via_optee_addr = image; +} +U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, arch_tee_image_process); +#endif +#endif + /* Main Entry point for arm bootm implementation * * Modeled after the powerpc implementation diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index f3f279f2c39..3e7627aa389 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -158,8 +158,10 @@ relocation_return: /* * Clear BSS section */ - ldr x0, =__bss_start /* this is auto-relocated! */ - ldr x1, =__bss_end /* this is auto-relocated! */ + adrp x0, __bss_start + add x0, x0, #:lo12:__bss_start + adrp x1, __bss_end + add x1, x1, #:lo12:__bss_end clear_loop: str xzr, [x0], #8 cmp x0, x1 diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index c43a63f1819..bce51b9cc7d 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -16,6 +16,9 @@ #include <asm/global_data.h> #include <linux/compiler.h> #include <asm/mach-types.h> +#if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) +#include <asm/armv7.h> +#endif #ifndef CONFIG_SPL_DM /* Pointer to as well as the global data structure for SPL */ @@ -46,8 +49,7 @@ void __weak board_init_f(ulong dummy) } /* - * This function jumps to an image with argument. Normally an FDT or ATAGS - * image. + * This function jumps to an image with argument, usually an FDT. */ #if CONFIG_IS_ENABLED(OS_BOOT) #ifdef CONFIG_ARM64 @@ -72,6 +74,13 @@ void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) image_entry_arg_t image_entry = (image_entry_arg_t)(uintptr_t) spl_image->entry_point; cleanup_before_linux(); +#if defined(CONFIG_BOOTM_OPTEE) && defined(CONFIG_ARM) && !defined(CONFIG_ARM64) + if (spl_image->optee_addr) + boot_jump_linux_via_optee((void *)(spl_image->entry_point), + machid, + (u32)(spl_image->arg), + spl_image->optee_addr); +#endif image_entry(0, machid, spl_image->arg); } #endif /* CONFIG_ARM64 */ diff --git a/arch/arm/mach-airoha/Kconfig b/arch/arm/mach-airoha/Kconfig index be3562ae3ff..b9cd0a413e1 100644 --- a/arch/arm/mach-airoha/Kconfig +++ b/arch/arm/mach-airoha/Kconfig @@ -6,6 +6,17 @@ config SYS_VENDOR choice prompt "Airoha board select" +config TARGET_EN7523 + bool "Airoha EN7523 SoC" + select CPU_V7A + select ARMV7_SET_CORTEX_SMPEN + help + The Airoha EN7523 family (en7523/en7529/en7562) is an ARM-based + SoCs with a dual-core CPU. It comes with Wi-Fi 5/6 support and + connectivity to Ethernet PHY, DDR, PCIe, USB, UART and VoIP. + With advanced hardware design, EN7523 provides high processing + performance and low power consumption. + config TARGET_AN7581 bool "Airoha AN7581 SoC" select ARM64 @@ -20,12 +31,15 @@ config TARGET_AN7581 endchoice config SYS_SOC + default "en7523" if TARGET_EN7523 default "an7581" if TARGET_AN7581 config SYS_BOARD + default "en7523" if TARGET_EN7523 default "an7581" if TARGET_AN7581 config SYS_CONFIG_NAME + default "en7523" if TARGET_EN7523 default "an7581" if TARGET_AN7581 endif diff --git a/arch/arm/mach-airoha/Makefile b/arch/arm/mach-airoha/Makefile index 215a300373b..91395b8a850 100644 --- a/arch/arm/mach-airoha/Makefile +++ b/arch/arm/mach-airoha/Makefile @@ -2,4 +2,5 @@ obj-y += cpu.o +obj-$(CONFIG_TARGET_EN7523) += en7523/ obj-$(CONFIG_TARGET_AN7581) += an7581/ diff --git a/arch/arm/mach-airoha/an7581/Makefile b/arch/arm/mach-airoha/an7581/Makefile index 886ab7e4eb9..51f978aa101 100644 --- a/arch/arm/mach-airoha/an7581/Makefile +++ b/arch/arm/mach-airoha/an7581/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += init.o +obj-y += scu-regmap.o diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c index d149e0ee3c8..ab32706a79d 100644 --- a/arch/arm/mach-airoha/an7581/init.c +++ b/arch/arm/mach-airoha/an7581/init.c @@ -2,10 +2,14 @@ #include <fdtdec.h> #include <init.h> +#include <linux/sizes.h> #include <sysreset.h> #include <asm/armv8/mmu.h> +#include <asm/global_data.h> #include <asm/system.h> +DECLARE_GLOBAL_DATA_PTR; + int print_cpuinfo(void) { printf("CPU: Airoha AN7581\n"); @@ -19,7 +23,15 @@ int dram_init(void) int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = get_effective_memsize(); + + if (gd->ram_size > SZ_2G) { + gd->bd->bi_dram[1].start = gd->ram_base + SZ_2G; + gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; + } + + return 0; } void reset_cpu(void) @@ -29,20 +41,26 @@ void reset_cpu(void) static struct mm_region an7581_mem_map[] = { { - /* DDR */ + /* DDR, 32-bit area */ .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x80000000UL, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + /* DDR, 64-bit area */ + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = SZ_4G + SZ_2G, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, }, { .virt = 0x00000000UL, .phys = 0x00000000UL, - .size = 0x20000000UL, + .size = 0x40000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - 0, + /* List terminator */ } }; struct mm_region *mem_map = an7581_mem_map; diff --git a/arch/arm/mach-airoha/an7581/scu-regmap.c b/arch/arm/mach-airoha/an7581/scu-regmap.c new file mode 100644 index 00000000000..7beeaecccc1 --- /dev/null +++ b/arch/arm/mach-airoha/an7581/scu-regmap.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> + */ + +#include <syscon.h> +#include <linux/err.h> +#include <asm/arch/scu-regmap.h> + +struct regmap *airoha_get_scu_regmap(void) +{ + ofnode node; + + node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-scu"); + if (!ofnode_valid(node)) + return ERR_PTR(-EINVAL); + + return syscon_node_to_regmap(node); +} + +struct regmap *airoha_get_chip_scu_regmap(void) +{ + ofnode node; + + node = ofnode_by_compatible(ofnode_null(), "airoha,en7581-chip-scu"); + if (!ofnode_valid(node)) + return ERR_PTR(-EINVAL); + + return syscon_node_to_regmap(node); +} diff --git a/arch/arm/mach-airoha/en7523/Makefile b/arch/arm/mach-airoha/en7523/Makefile new file mode 100644 index 00000000000..51f978aa101 --- /dev/null +++ b/arch/arm/mach-airoha/en7523/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o +obj-y += scu-regmap.o diff --git a/arch/arm/mach-airoha/en7523/init.c b/arch/arm/mach-airoha/en7523/init.c new file mode 100644 index 00000000000..c1c1eeabdf5 --- /dev/null +++ b/arch/arm/mach-airoha/en7523/init.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> + */ +#include <fdtdec.h> +#include <init.h> +#include <sysreset.h> +#include <asm/system.h> +#include <linux/io.h> + +int print_cpuinfo(void) +{ + printf("CPU: Airoha EN7523/EN7529/EN7562\n"); + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +void __noreturn reset_cpu(void) +{ + writel(0x80000000, 0x1FB00040); + while (1) { + /* loop forever */ + } +} diff --git a/arch/arm/mach-airoha/en7523/scu-regmap.c b/arch/arm/mach-airoha/en7523/scu-regmap.c new file mode 100644 index 00000000000..1e201cb060c --- /dev/null +++ b/arch/arm/mach-airoha/en7523/scu-regmap.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> + */ + +#include <dm/ofnode.h> +#include <linux/err.h> +#include <asm/arch/scu-regmap.h> + +static struct regmap *airoha_scu_node_regmap_by_index(unsigned int index) +{ + struct regmap *map; + ofnode node; + int err; + + node = ofnode_by_compatible(ofnode_null(), "airoha,en7523-scu"); + if (!ofnode_valid(node)) + return ERR_PTR(-EINVAL); + + /* CHIP_SCU (index=0), SCU (index=1) */ + err = regmap_init_mem_index(node, &map, index); + if (err) + return ERR_PTR(err); + + return map; +} + +struct regmap *airoha_get_scu_regmap(void) +{ + /* CHIP_SCU (index=0), SCU (index=1) */ + return airoha_scu_node_regmap_by_index(1); +} + +struct regmap *airoha_get_chip_scu_regmap(void) +{ + /* CHIP_SCU (index=0), SCU (index=1) */ + return airoha_scu_node_regmap_by_index(0); +} diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 28193039cb8..2cd67d02386 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -88,7 +88,7 @@ config TARGET_S5PC210_UNIVERSAL select MISC_COMMON config TARGET_ORIGEN - bool "Exynos4412 Origen board" + bool "Exynos4210 Origen board" select EXYNOS4210 select SUPPORT_SPL diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h index 75d84988b7d..4432deedef7 100644 --- a/arch/arm/mach-exynos/include/mach/dwmmc.h +++ b/arch/arm/mach-exynos/include/mach/dwmmc.h @@ -17,10 +17,16 @@ /* Protector Register */ #define DWMCI_EMMCP_BASE 0x1000 +#define EMMCP_MPSECURITY (DWMCI_EMMCP_BASE + 0x0010) #define EMMCP_MPSBEGIN0 (DWMCI_EMMCP_BASE + 0x0200) #define EMMCP_SEND0 (DWMCI_EMMCP_BASE + 0x0204) #define EMMCP_CTRL0 (DWMCI_EMMCP_BASE + 0x020c) +/* EMMCP_MPSECURITY bits */ +#define MPSECURITY_FMP_ON BIT(29) +#define MPSECURITY_MMC_SFR_PROT_ON BIT(28) + +/* EMMCP_CTRL0 bits */ #define MPSCTRL_SECURE_READ_BIT BIT(7) #define MPSCTRL_SECURE_WRITE_BIT BIT(6) #define MPSCTRL_NON_SECURE_READ_BIT BIT(5) diff --git a/arch/arm/mach-exynos/pinmux.c b/arch/arm/mach-exynos/pinmux.c index 48c325190d5..ed46ea03355 100644 --- a/arch/arm/mach-exynos/pinmux.c +++ b/arch/arm/mach-exynos/pinmux.c @@ -32,7 +32,7 @@ static void exynos5_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < start + count; i++) { @@ -63,7 +63,7 @@ static void exynos5420_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } @@ -97,12 +97,12 @@ static int exynos5_mmc_config(int peripheral, int flags) start_ext = 0; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", - peripheral); + debug("SDMMC device %d does not support 8bit mode\n", + peripheral); return -1; } if (flags & PINMUX_FLAG_8BIT_MODE) { @@ -145,12 +145,12 @@ static int exynos5420_mmc_config(int peripheral, int flags) break; default: start = 0; - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !start_ext) { - debug("SDMMC device %d does not support 8bit mode", + debug("SDMMC device %d does not support 8bit mode\n", peripheral); return -1; } @@ -453,7 +453,7 @@ void exynos5420_spi_config(int peripheral) default: cfg = 0; pin = 0; - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } @@ -522,7 +522,7 @@ static int exynos5_pinmux_config(int peripheral, int flags) gpio_cfg_pin(EXYNOS5_GPIO_B20, S5P_GPIO_FUNC(2)); break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -570,7 +570,7 @@ static int exynos5420_pinmux_config(int peripheral, int flags) gpio_cfg_pin(EXYNOS5420_GPIO_B20, S5P_GPIO_FUNC(2)); break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -683,7 +683,7 @@ static void exynos4_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < (start + count); i++) { @@ -797,7 +797,7 @@ static void exynos4x12_uart_config(int peripheral) count = 2; break; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return; } for (i = start; i < (start + count); i++) { @@ -834,7 +834,7 @@ static int exynos4_pinmux_config(int peripheral, int flags) debug("SDMMC device %d not implemented\n", peripheral); return -1; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -869,7 +869,7 @@ static int exynos4x12_pinmux_config(int peripheral, int flags) debug("SDMMC device %d not implemented\n", peripheral); return -1; default: - debug("%s: invalid peripheral %d", __func__, peripheral); + debug("%s: invalid peripheral %d\n", __func__, peripheral); return -1; } @@ -902,7 +902,7 @@ static int exynos4_pinmux_decode_periph_id(const void *blob, int node) u32 cell[3]; err = fdtdec_get_int_array(blob, node, "interrupts", cell, - ARRAY_SIZE(cell)); + ARRAY_SIZE(cell)); if (err) { debug(" invalid peripheral id\n"); return PERIPH_ID_NONE; @@ -917,7 +917,7 @@ static int exynos5_pinmux_decode_periph_id(const void *blob, int node) u32 cell[3]; err = fdtdec_get_int_array(blob, node, "interrupts", cell, - ARRAY_SIZE(cell)); + ARRAY_SIZE(cell)); if (err) return PERIPH_ID_NONE; diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 8bd85e889ab..1efe690e876 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -223,6 +223,10 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) +ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),) +SPL: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) +else quiet_cmd_cpp_cfg_imx9_check = CHECK $@ cmd_cpp_cfg_imx9_check = $(CPP) $(cpp_flags) -D__ASSEMBLY__ -x c -o $@ $< && $(srctree)/tools/imx9_image.sh $@ @@ -244,6 +248,7 @@ u-boot-container.cfgout: $(IMX_CONTAINER_CFG) FORCE flash.bin: spl/u-boot-spl-ddr.bin container.cfgout FORCE $(call if_changed,mkimage) endif +endif else MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 17de9ff98ec..cc215b771ef 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -230,6 +230,7 @@ int print_cpuinfo(void) ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev); if (!ret) { ret = thermal_get_temp(thermal_dev, &cpu_tmp); + cpu_tmp /= 1000; if (!ret) printf(" at %dC", cpu_tmp); diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c index 647daeb6562..38e671e3935 100644 --- a/arch/arm/mach-imx/ele_ahab.c +++ b/arch/arm/mach-imx/ele_ahab.c @@ -411,6 +411,54 @@ static int do_authenticate(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_SUCCESS; } +#if IS_ENABLED(CONFIG_IMX95) || IS_ENABLED(CONFIG_IMX94) +#define FSB_LC_OFFSET 0x414 +#define LC_OEM_OPEN 0x10 +static void display_life_cycle(u32 lc) +{ + printf("Lifecycle: 0x%08X, ", lc); + switch (lc) { + case 0x1: + printf("BLANK\n\n"); + break; + case 0x2: + printf("FAB Default\n\n"); + break; + case 0x4: + printf("FAB\n\n"); + break; + case 0x8: + printf("NXP Provisioned\n\n"); + break; + case 0x10: + printf("OEM Open\n\n"); + break; + case 0x20: + printf("OEM secure world closed\n\n"); + break; + case 0x40: + printf("OEM closed\n\n"); + break; + case 0x80: + printf("OEM Locked\n\n"); + break; + case 0x100: + printf("Field Return OEM\n\n"); + break; + case 0x200: + printf("Field Return NXP\n\n"); + break; + case 0x400: + printf("BRICKED\n\n"); + break; + default: + printf("Unknown\n\n"); + break; + } +} +#else +#define FSB_LC_OFFSET 0x41c +#define LC_OEM_OPEN 0x8 static void display_life_cycle(u32 lc) { printf("Lifecycle: 0x%08X, ", lc); @@ -447,6 +495,7 @@ static void display_life_cycle(u32 lc) break; } } +#endif static int confirm_close(void) { @@ -474,10 +523,10 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, if (!confirm_close()) return -EACCES; - lc = readl(FSB_BASE_ADDR + 0x41c); + lc = readl(FSB_BASE_ADDR + FSB_LC_OFFSET); lc &= 0x3ff; - if (lc != 0x8) { + if (lc != LC_OEM_OPEN) { puts("Current lifecycle is NOT OEM open, can't move to OEM closed\n"); display_life_cycle(lc); return -EPERM; @@ -540,7 +589,7 @@ static int do_ahab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const u32 cnt = AHAB_MAX_EVENTS; int ret; - lc = readl(FSB_BASE_ADDR + 0x41c); + lc = readl(FSB_BASE_ADDR + FSB_LC_OFFSET); lc &= 0x3ff; display_life_cycle(lc); diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 3a9e6dcf225..78f2488cf6d 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -297,7 +297,7 @@ static ulong get_imageset_end(void *dev, int dev_type) debug("seco container size 0x%x\n", value_container[0]); - if (is_imx95()) { + if (is_imx95() || is_imx94()) { offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0]; value_container[1] = get_dev_container_size(dev, dev_type, offset[1], &hdr_length, &v2x_fw); @@ -321,7 +321,7 @@ static ulong get_imageset_end(void *dev, int dev_type) value_container[2] = get_dev_container_size(dev, dev_type, offset[2], &hdr_length, NULL); if (value_container[2] < 0) { debug("Parse scu container image failed %d, only seco container\n", value_container[2]); - if (is_imx95()) + if (is_imx95() || is_imx94()) return value_container[1] + offset[1]; /* return seco + v2x container total size */ else return value_container[0] + offset[0]; /* return seco container total size */ diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 324e010bb2c..f13baa871cc 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -401,6 +401,29 @@ static int do_ahab_close(struct cmd_tbl *cmdtp, int flag, int argc, return 0; } +static int do_ahab_commit(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 info; + int ret; + + if (argc < 2) + return CMD_RET_USAGE; + + info = simple_strtoul(argv[1], NULL, 16); + printf("Commit index is 0x%x\n", info); + + ret = sc_seco_commit(-1, &info); + if (ret) { + printf("Error in AHAB commit\n"); + return ret; + } + + printf("AHAB commit succeeded.\n"); + + return CMD_RET_SUCCESS; +} + U_BOOT_CMD(auth_cntr, CONFIG_SYS_MAXARGS, 1, do_authenticate, "autenticate OS container via AHAB", "addr\n" @@ -416,3 +439,9 @@ U_BOOT_CMD(ahab_close, CONFIG_SYS_MAXARGS, 1, do_ahab_close, "Change AHAB lifecycle to OEM closed", "" ); + +U_BOOT_CMD(ahab_commit, CONFIG_SYS_MAXARGS, 1, do_ahab_commit, + "commit into the fuses any new SRK revocation information that have been found\n" + "into the NXP (SECO FW) and OEM containers. For SRK revocation use 0x10 for the value.", + "" +); diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 74416a78847..030ed2f0633 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -67,6 +67,10 @@ config TARGET_IMX8MQ_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + select CMD_REMOTEPROC + select REMOTEPROC_IMX + select REGMAP + select SYSCON imply OF_UPSTREAM imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND @@ -95,6 +99,10 @@ config TARGET_IMX8MM_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + select CMD_REMOTEPROC + select REMOTEPROC_IMX + select REGMAP + select SYSCON imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND imply OF_UPSTREAM @@ -171,6 +179,10 @@ config TARGET_IMX8MN_EVK select IMX8M_LPDDR4 select FSL_CAAM select SPL_CRYPTO if SPL + select CMD_REMOTEPROC + select REMOTEPROC_IMX + select REGMAP + select SYSCON imply OF_UPSTREAM imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND @@ -182,6 +194,10 @@ config TARGET_IMX8MN_DDR4_EVK select IMX8M_DDR4 select FSL_CAAM select SPL_CRYPTO if SPL + select CMD_REMOTEPROC + select REMOTEPROC_IMX + select REGMAP + select SYSCON imply OF_UPSTREAM imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND @@ -248,6 +264,10 @@ config TARGET_IMX8MP_EVK select FSL_CAAM select ARCH_MISC_INIT select SPL_CRYPTO if SPL + select CMD_REMOTEPROC + select REMOTEPROC_IMX + select REGMAP + select SYSCON imply OF_UPSTREAM imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND @@ -296,6 +316,7 @@ config TARGET_TORADEX_SMARC_IMX8MP select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + imply OF_UPSTREAM config TARGET_VERDIN_IMX8MM bool "Support Toradex Verdin iMX8M Mini module" @@ -345,6 +366,15 @@ config TARGET_PHYCORE_IMX8MP select IMX8M_LPDDR4 imply OF_UPSTREAM +config TARGET_IMX8MP_LIBRA_FPSC + bool "PHYTEC Libra i.MX 8M Plus FPSC" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + imply OF_UPSTREAM + help + Libra i.MX8M Plus FPSC is an SBC based on the NXP i.MX 8M Plus SoC. + config TARGET_IMX8MM_CL_IOT_GATE bool "CompuLab iot-gate-imx8" select IMX8MM @@ -409,6 +439,7 @@ source "board/kontron/sl-mx8mm/Kconfig" source "board/menlo/mx8menlo/Kconfig" source "board/msc/sm2s_imx8mp/Kconfig" source "board/mntre/imx8mq_reform2/Kconfig" +source "board/phytec/imx8mp-libra-fpsc/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/polyhex/imx8mp_debix_model_a/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index d5745f67262..77c8efc7899 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -55,16 +55,16 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), PLL_1443X_RATE(933000000U, 311, 4, 1, 0), - PLL_1443X_RATE(900000000U, 300, 8, 0, 0), - PLL_1443X_RATE(800000000U, 300, 9, 0, 0), - PLL_1443X_RATE(750000000U, 250, 8, 0, 0), + PLL_1443X_RATE(900000000U, 300, 2, 2, 0), + PLL_1443X_RATE(800000000U, 200, 3, 1, 0), + PLL_1443X_RATE(750000000U, 250, 2, 2, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(600000000U, 300, 3, 2, 0), PLL_1443X_RATE(594000000U, 99, 1, 2, 0), - PLL_1443X_RATE(400000000U, 300, 9, 1, 0), - PLL_1443X_RATE(266000000U, 400, 9, 2, 0), + PLL_1443X_RATE(400000000U, 400, 3, 3, 0), + PLL_1443X_RATE(266000000U, 266, 3, 3, 0), PLL_1443X_RATE(167000000U, 334, 3, 4, 0), - PLL_1443X_RATE(100000000U, 300, 9, 3, 0), + PLL_1443X_RATE(100000000U, 200, 3, 4, 0), }; static int fracpll_configure(enum pll_clocks pll, u32 freq) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index e85cb0dd252..1ee483065e8 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -279,7 +279,7 @@ int print_cpuinfo(void) if (!ret) { ret = thermal_get_temp(udev, &temp); if (!ret) - printf("CPU current temperature: %dC\n", temp); + printf("CPU current temperature: %dC\n", temp / 1000); else debug(" - failed to get CPU current temperature\n"); } else { @@ -384,7 +384,22 @@ static struct mm_region imx8ulp_arm64_mem_map[] = { /* SRAM0 (align with 2M) */ .virt = 0x22000000UL, .phys = 0x22000000UL, - .size = 0x200000UL, + .size = 0x1f000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* SCMI shared memory buffer must be mapped as non-cacheable. */ + .virt = 0x2201f000UL, + .phys = 0x2201f000UL, + .size = 0x1000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x22020000UL, + .phys = 0x22020000UL, + .size = 0x1e0000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -804,6 +819,7 @@ int imx8ulp_dm_post_init(void) return 0; } EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, imx8ulp_dm_post_init); #if defined(CONFIG_XPL_BUILD) __weak void __noreturn jump_to_image(struct spl_image_info *spl_image) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 4e0e194690b..d9725a96043 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -25,6 +25,9 @@ config IMX91 select ARCH_MISC_INIT select ARMV8_SPL_EXCEPTION_VECTORS +config IMX95_A0 + bool "Support for i.MX95 A0 silicon version" + config IMX95 bool select ARCH_MISC_INIT @@ -33,7 +36,16 @@ config IMX95 select DM_MAILBOX select SCMI_FIRMWARE select SPL_IMX_CONTAINER_USE_TRAMPOLINE + select IMX_PQC_SUPPORT if !IMX95_A0 + +config IMX94 + bool + select ARMV8_SPL_EXCEPTION_VECTORS + select DM_MAILBOX + select IMX9 select IMX_PQC_SUPPORT + select SCMI_FIRMWARE + select SPL_IMX_CONTAINER_USE_TRAMPOLINE config SYS_SOC default "imx9" @@ -57,6 +69,10 @@ config TARGET_IMX93_9X9_QSB imply OF_UPSTREAM imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND + select CMD_REMOTEPROC + select REMOTEPROC_IMX + select REGMAP + select SYSCON config TARGET_IMX93_11X11_EVK bool "imx93_11x11_evk" @@ -65,6 +81,10 @@ config TARGET_IMX93_11X11_EVK imply OF_UPSTREAM imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND + select CMD_REMOTEPROC + select REMOTEPROC_IMX + select REGMAP + select SYSCON config TARGET_IMX93_FRDM bool "imx93_frdm" @@ -73,6 +93,10 @@ config TARGET_IMX93_FRDM select IMX9_LPDDR4X imply BOOTSTD_FULL imply BOOTSTD_BOOTCOMMAND + select CMD_REMOTEPROC + select REMOTEPROC_IMX + select REGMAP + select SYSCON config TARGET_IMX93_VAR_SOM bool "imx93_var_som" @@ -94,6 +118,24 @@ config TARGET_IMX95_19X19_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_IMX95_15X15_EVK + bool "imx95_15x15_evk" + select IMX95 + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM + +config TARGET_IMX943_EVK + bool "imx943_evk" + select IMX94 + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM + +config TARGET_TORADEX_SMARC_IMX95 + bool "Support Toradex SMARC iMX95" + select IMX95 + endchoice source "board/freescale/imx91_evk/Kconfig" @@ -102,7 +144,9 @@ source "board/freescale/imx93_frdm/Kconfig" source "board/freescale/imx93_qsb/Kconfig" source "board/phytec/phycore_imx93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" +source "board/freescale/imx94_evk/Kconfig" source "board/freescale/imx95_evk/Kconfig" +source "board/toradex/smarc-imx95/Kconfig" endif diff --git a/arch/arm/mach-imx/imx9/scmi/Makefile b/arch/arm/mach-imx/imx9/scmi/Makefile index 4534db08d28..b98744e1ecb 100644 --- a/arch/arm/mach-imx/imx9/scmi/Makefile +++ b/arch/arm/mach-imx/imx9/scmi/Makefile @@ -2,5 +2,8 @@ # # Copyright 2025 NXP +# Add include path for NXP device tree header files from Linux. +ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/ + obj-y += soc.o obj-y += clock_scmi.o clock.o diff --git a/arch/arm/mach-imx/imx9/scmi/clock.c b/arch/arm/mach-imx/imx9/scmi/clock.c index 6e6541eaa31..951d47bd9d7 100644 --- a/arch/arm/mach-imx/imx9/scmi/clock.c +++ b/arch/arm/mach-imx/imx9/scmi/clock.c @@ -6,16 +6,17 @@ #include <asm/arch/clock.h> #include <dm/uclass.h> #include <scmi_agent.h> -#include "../../../../../dts/upstream/src/arm64/freescale/imx95-clock.h" +#include <scmi_nxp_protocols.h> +#include "common.h" u32 get_arm_core_clk(void) { u32 val; - val = imx_clk_scmi_get_rate(IMX95_CLK_SEL_A55C0); + val = imx_clk_scmi_get_rate(SCMI_CLK(SEL_A55C0)); if (val) return val; - return imx_clk_scmi_get_rate(IMX95_CLK_A55); + return imx_clk_scmi_get_rate(SCMI_CLK(A55)); } void init_uart_clk(u32 index) @@ -24,13 +25,13 @@ void init_uart_clk(u32 index) switch (index) { case 0: - clock_id = IMX95_CLK_LPUART1; + clock_id = SCMI_CLK(LPUART1); break; case 1: - clock_id = IMX95_CLK_LPUART2; + clock_id = SCMI_CLK(LPUART2); break; case 2: - clock_id = IMX95_CLK_LPUART3; + clock_id = SCMI_CLK(LPUART3); break; default: return; @@ -38,7 +39,7 @@ void init_uart_clk(u32 index) /* 24MHz */ imx_clk_scmi_enable(clock_id, false); - imx_clk_scmi_set_parent(clock_id, IMX95_CLK_24M); + imx_clk_scmi_set_parent(clock_id, SCMI_CLK(24M)); imx_clk_scmi_set_rate(clock_id, 24000000); imx_clk_scmi_enable(clock_id, true); } @@ -49,19 +50,19 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_ARM_CLK: return get_arm_core_clk(); case MXC_IPG_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_BUSWAKEUP); + return imx_clk_scmi_get_rate(SCMI_CLK(BUSWAKEUP)); case MXC_CSPI_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_LPSPI1); + return imx_clk_scmi_get_rate(SCMI_CLK(LPSPI1)); case MXC_ESDHC_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_USDHC1); + return imx_clk_scmi_get_rate(SCMI_CLK(USDHC1)); case MXC_ESDHC2_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_USDHC2); + return imx_clk_scmi_get_rate(SCMI_CLK(USDHC2)); case MXC_ESDHC3_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_USDHC3); + return imx_clk_scmi_get_rate(SCMI_CLK(USDHC3)); case MXC_UART_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_LPUART1); + return imx_clk_scmi_get_rate(SCMI_CLK(LPUART1)); case MXC_FLEXSPI_CLK: - return imx_clk_scmi_get_rate(IMX95_CLK_FLEXSPI1); + return imx_clk_scmi_get_rate(SCMI_CLK(FLEXSPI1)); default: return -1; }; diff --git a/arch/arm/mach-imx/imx9/scmi/clock_scmi.c b/arch/arm/mach-imx/imx9/scmi/clock_scmi.c index fa15b5f8df9..b6be20ec674 100644 --- a/arch/arm/mach-imx/imx9/scmi/clock_scmi.c +++ b/arch/arm/mach-imx/imx9/scmi/clock_scmi.c @@ -12,7 +12,7 @@ int imx_clk_scmi_enable(u32 clock_id, bool enable) { struct scmi_clk_state_in in = { .clock_id = clock_id, - .attributes = (enable) ? 1 : 0, + .attributes = !!enable, }; struct scmi_clk_state_out out; struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, diff --git a/arch/arm/mach-imx/imx9/scmi/common.h b/arch/arm/mach-imx/imx9/scmi/common.h new file mode 100644 index 00000000000..dd4675402c7 --- /dev/null +++ b/arch/arm/mach-imx/imx9/scmi/common.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025 NXP + */ + +#ifndef _SCMI_CLOCK_COMMON_H_ +#define _SCMI_CLOCK_COMMON_H_ + +#ifdef CONFIG_IMX94 +#define IMX_PLAT 94 +#include <imx94-clock.h> +#include <imx94-power.h> + +#define IMX94_CLK_FLEXSPI1 IMX94_CLK_XSPI1 +#endif + +#ifdef CONFIG_IMX95 +#define IMX_PLAT 95 +#include <imx95-clock.h> +#include <imx95-power.h> + +#define IMX95_PD_M70 IMX95_PD_M7 +#endif + +#define IMX_PLAT_STR__(plat) # plat +#define IMX_PLAT_STR_(IMX_PLAT) IMX_PLAT_STR__(IMX_PLAT) +#define IMX_PLAT_STR IMX_PLAT_STR_(IMX_PLAT) + +#define SCMI_CLK__(plat, clk) IMX ## plat ## _CLK_ ## clk +#define SCMI_CLK_(plat, clk) SCMI_CLK__(plat, clk) +#define SCMI_CLK(clk) SCMI_CLK_(IMX_PLAT, clk) + +#define SCMI_PD__(plat, pd) IMX ## plat ## _PD_ ## pd +#define SCMI_PD_(plat, pd) SCMI_PD__(plat, pd) +#define SCMI_PD(pd) SCMI_PD_(IMX_PLAT, pd) + +#define SCMI_CPU__(plat) MXC_CPU_IMX ## plat +#define SCMI_CPU_(plat) SCMI_CPU__(plat) +#define SCMI_CPU SCMI_CPU_(IMX_PLAT) + +#endif diff --git a/arch/arm/mach-imx/imx9/scmi/container.cfg b/arch/arm/mach-imx/imx9/scmi/container.cfg deleted file mode 100644 index b25f3b726c5..00000000000 --- a/arch/arm/mach-imx/imx9/scmi/container.cfg +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2025 NXP - */ - -CNTR_VERSION 2 -BOOT_FROM SD -SOC_TYPE IMX9 -CONTAINER -IMAGE A55 bl31.bin 0x8a200000 -IMAGE A55 u-boot.bin CONFIG_TEXT_BASE diff --git a/arch/arm/mach-imx/imx9/scmi/imximage.cfg b/arch/arm/mach-imx/imx9/scmi/imximage.cfg deleted file mode 100644 index c2c92174c1c..00000000000 --- a/arch/arm/mach-imx/imx9/scmi/imximage.cfg +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2025 NXP - */ - -CNTR_VERSION 2 -BOOT_FROM SD -SOC_TYPE IMX9 -APPEND mx95b0-ahab-container.img -CONTAINER -DUMMY_DDR -IMAGE OEI m33-oei-ddrfw.bin 0x1ffc0000 -HOLD 0x10000 -IMAGE M33 m33_image.bin 0x1ffc0000 -IMAGE A55 spl/u-boot-spl.bin 0x20480000 -DUMMY_V2X 0x8b000000 diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 13f13ca7d10..dbaa19a9e6e 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -17,8 +17,11 @@ #include <env_internal.h> #include <fuse.h> #include <imx_thermal.h> +#include <linux/bitfield.h> #include <linux/iopoll.h> #include <scmi_agent.h> +#include <scmi_nxp_protocols.h> +#include "common.h" DECLARE_GLOBAL_DATA_PTR; @@ -174,7 +177,7 @@ u32 get_cpu_rev(void) { u32 rev = (gd->arch.soc_rev >> 24) - 0xa0; - return (MXC_CPU_IMX95 << 12) | (CHIP_REV_1_0 + rev); + return (SCMI_CPU << 12) | (CHIP_REV_1_0 + rev); } #define UNLOCK_WORD 0xD928C520 @@ -254,6 +257,30 @@ static struct mm_region imx9_mem_map[] = { PTE_BLOCK_OUTER_SHARE }, { #endif + /* PCIE2 ECAM */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE1 Outbound */ + .virt = 0x900000000UL, + .phys = 0x900000000UL, + .size = 0x100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE2 Outbound */ + .virt = 0xA00000000UL, + .phys = 0xA00000000UL, + .size = 0x100000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { /* empty entry to split table entry 5 if needed when TEEs are used */ 0, }, { @@ -435,12 +462,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { u32 val[2] = {}; int ret, num_of_macs; + u32 bank = 40; + + if (is_imx94()) + bank = 66; - ret = fuse_read(40, 5, &val[0]); + ret = fuse_read(bank, 5, &val[0]); if (ret) goto err; - ret = fuse_read(40, 6, &val[1]); + ret = fuse_read(bank, 6, &val[1]); if (ret) goto err; @@ -456,10 +487,32 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) mac[3] = (val[0] >> 24) & 0xff; mac[4] = val[1] & 0xff; mac[5] = (val[1] >> 8) & 0xff; - if (dev_id == 1) - mac[5] = mac[5] + 3; - if (dev_id == 2) - mac[5] = mac[5] + 6; + + if (is_imx94()) { + /* + * i.MX94 uses the following mac address offset list: + * | No. | Module | Mac address user | + * |--------|-------------|---------------------------| + * | 0 ~ 1 | ethercat | port0/port1 | + * | 2 | netc switch | internal enetc3 mac/swp0 | + * | 3 ~ 6 | | enetc3 vf1~3/swp1 | + * | 7 | enetc mac | enetc0 pf | + * | 8 | | enetc1 pf | + * | 9 | | enetc2 pf | + * | 10 | netc switch | swp2 | + */ + if (dev_id == 0) + mac[5] = mac[5] + 2; /* enetc3 mac/swp0 */ + if (dev_id == 1) + mac[5] = mac[5] + 8; /* enetc1 */ + if (dev_id == 2) + mac[5] = mac[5] + 9; /* enetc2 */ + } else { + if (dev_id == 1) + mac[5] = mac[5] + 3; + if (dev_id == 2) + mac[5] = mac[5] + 6; + } debug("%s: MAC%d: %pM\n", __func__, dev_id, mac); return; @@ -468,11 +521,149 @@ err: printf("%s: fuse read err: %d\n", __func__, ret); } +static char *rst_string[32] = { + "cm33_lockup", + "cm33_swreq", + "cm7_lockup", + "cm7_swreq", + "fccu", + "jtag_sw", + "ele", + "tempsense", + "wdog1", + "wdog2", + "wdog3", + "wdog4", + "wdog5", + "jtag", + "cm33_exc", + "bbm", + "sw", + "sm_err", "fusa_sreco", "pmic", "unused", "unused", "unused", + "unused", "unused", "unused", "unused", "unused", "unused", + "unused", "unused", + "por" +}; + +static char *rst_string_imx94[32] = { + "cm33_lockup", + "cm33_swreq", + "cm70_lockup", + "cm70_swreq", + "fccu", + "jtag_sw", + "ele", + "tempsense", + "wdog1", + "wdog2", + "wdog3", + "wdog4", + "wdog5", + "jtag", + "wdog6", + "wdog7", + "wdog8", + "wo_netc", "cm33s_lockup", "cm33s_swreq", "cm71_lockup", "cm71_swreq", "cm33_exc", + "bbm", "sw", "sm_err", "fusa_sreco", "pmic", "unused", + "unused", "unused", + "por" +}; + +int get_reset_reason(bool sys, bool lm) +{ + struct scmi_imx_misc_reset_reason_in in = { + .flags = MISC_REASON_FLAG_SYSTEM, + }; + + struct scmi_imx_misc_reset_reason_out out = { 0 }; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC, + .message_id = SCMI_IMX_MISC_RESET_REASON, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + struct udevice *dev; + char **rst; + + if (is_imx94()) + rst = rst_string_imx94; + else + rst = rst_string; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + if (sys) { + ret = devm_scmi_process_msg(dev, &msg); + if (out.status) { + printf("%s:%d for SYS\n", __func__, out.status); + return ret; + } + + if (out.bootflags & MISC_BOOT_FLAG_VLD) { + printf("SYS Boot reason: %s, origin: %ld, errid: %ld\n", + rst[out.bootflags & MISC_BOOT_FLAG_REASON], + out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { + printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n", + rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], + out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + } + + if (lm) { + in.flags = 0; + memset(&out, 0, sizeof(struct scmi_imx_misc_reset_reason_out)); + + ret = devm_scmi_process_msg(dev, &msg); + if (out.status) { + printf("%s:%d for LM\n", __func__, out.status); + return ret; + } + + if (out.bootflags & MISC_BOOT_FLAG_VLD) { + printf("LM Boot reason: %s, origin: %ld, errid: %ld\n", + rst[out.bootflags & MISC_BOOT_FLAG_REASON], + out.bootflags & MISC_BOOT_FLAG_ORG_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_BOOT_FLAG_ERR_VLD ? + FIELD_GET(MISC_BOOT_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + + if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { + printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n", + rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], + out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, + out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + ); + } + } + + return 0; +} + const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_IMX95: - return "95";/* iMX95 FULL */ + case SCMI_CPU: + return IMX_PLAT_STR; default: return "??"; } @@ -553,6 +744,10 @@ int arch_cpu_init(void) gpio_reset(GPIO3_BASE_ADDR); gpio_reset(GPIO4_BASE_ADDR); gpio_reset(GPIO5_BASE_ADDR); +#ifdef CONFIG_IMX94 + gpio_reset(GPIO6_BASE_ADDR); + gpio_reset(GPIO7_BASE_ADDR); +#endif } return 0; @@ -635,7 +830,8 @@ enum env_location env_get_location(enum env_operation op, int prio) switch (dev) { case QSPI_BOOT: - env_loc = ENVL_SPI_FLASH; + if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + env_loc = ENVL_SPI_FLASH; break; case SD1_BOOT: case SD2_BOOT: @@ -643,10 +839,16 @@ enum env_location env_get_location(enum env_operation op, int prio) case MMC1_BOOT: case MMC2_BOOT: case MMC3_BOOT: - env_loc = ENVL_MMC; + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + env_loc = ENVL_MMC; break; default: - env_loc = ENVL_NOWHERE; + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + env_loc = ENVL_NOWHERE; + else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + env_loc = ENVL_SPI_FLASH; + else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + env_loc = ENVL_MMC; break; } diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 02db7cc97ba..3f7dafdcce5 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -641,12 +641,10 @@ static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32 n return -ENOENT; } -static int low_drive_freq_update(void *blob) +int low_drive_freq_update(void *blob) { - int nodeoff, ret; - int i; + int nodeoff, ret, i; - /* Update kernel dtb clocks for low drive mode */ struct low_drive_freq_entry table[] = { {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, @@ -658,8 +656,8 @@ static int low_drive_freq_update(void *blob) if (nodeoff >= 0) { ret = low_drive_fdt_fix_clock(blob, nodeoff, table[i].clk, table[i].new_rate); - if (!ret) - printf("%s freq updated\n", table[i].node_path); + if (ret) + printf("freq update failed for %s\n", table[i].node_path); } } @@ -671,23 +669,8 @@ static int low_drive_freq_update(void *blob) int board_fix_fdt(void *fdt) { /* Update dtb clocks for low drive mode */ - if (is_voltage_mode(VOLT_LOW_DRIVE)) { - int nodeoff; - int i; - - struct low_drive_freq_entry table[] = { - {"/soc@0/bus@42800000/mmc@42850000", 0, 266666667}, - {"/soc@0/bus@42800000/mmc@42860000", 0, 266666667}, - {"/soc@0/bus@42800000/mmc@428b0000", 0, 266666667}, - }; - - for (i = 0; i < ARRAY_SIZE(table); i++) { - nodeoff = fdt_path_offset(fdt, table[i].node_path); - if (nodeoff >= 0) - low_drive_fdt_fix_clock(fdt, nodeoff, table[i].clk, - table[i].new_rate); - } - } + if (is_voltage_mode(VOLT_LOW_DRIVE)) + low_drive_freq_update(fdt); return 0; } @@ -826,7 +809,13 @@ enum env_location env_get_location(enum env_operation op, int prio) return ENVL_FAT; return ENVL_NOWHERE; default: - return ENVL_NOWHERE; + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) + return ENVL_NOWHERE; + else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + return ENVL_MMC; + return ENVL_UNKNOWN; } } diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 50521490b35..02df86156d4 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -360,23 +360,21 @@ static void init_bandgap(void) /* * On i.MX6ULL,we need to set VBGADJ bits according to the * REFTOP_TRIM[3:0] in fuse table - * 000 - set REFTOP_VBGADJ[2:0] to 3b'110, - * 110 - set REFTOP_VBGADJ[2:0] to 3b'000, - * 001 - set REFTOP_VBGADJ[2:0] to 3b'001, - * 010 - set REFTOP_VBGADJ[2:0] to 3b'010, - * 011 - set REFTOP_VBGADJ[2:0] to 3b'011, - * 100 - set REFTOP_VBGADJ[2:0] to 3b'100, - * 101 - set REFTOP_VBGADJ[2:0] to 3b'101, - * 111 - set REFTOP_VBGADJ[2:0] to 3b'111, + * 000 - set REFTOP_VBGADJ[2:0] to 3'b000 + * 001 - set REFTOP_VBGADJ[2:0] to 3'b001 + * 010 - set REFTOP_VBGADJ[2:0] to 3'b010 + * 011 - set REFTOP_VBGADJ[2:0] to 3'b011 + * 100 - set REFTOP_VBGADJ[2:0] to 3'b100 + * 101 - set REFTOP_VBGADJ[2:0] to 3'b101 + * 110 - set REFTOP_VBGADJ[2:0] to 3'b110 + * 111 - set REFTOP_VBGADJ[2:0] to 3'b111 */ if (is_mx6ull()) { - static const u32 map[] = {6, 1, 2, 3, 4, 5, 0, 7}; - val = readl(&fuse->mem0); val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT; val &= 0x7; - writel(map[val] << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, + writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT, &anatop->ana_misc0_set); } } diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 518d9cb1262..57ae81c7834 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -21,6 +21,8 @@ #include <g_dnl.h> #include <linux/libfdt.h> #include <memalign.h> +#include <asm/setup.h> +#include <asm/bootm.h> DECLARE_GLOBAL_DATA_PTR; @@ -184,6 +186,16 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_USB_GADGET int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifdef CONFIG_IMX94 + struct tag_serialnr serialnr; + char serial_string[0x21] = {0}; + + get_board_serial(&serialnr); + snprintf(serial_string, sizeof(serial_string), "%08x%08x", serialnr.high, serialnr.low); + g_dnl_set_serialnumber(serial_string); +#endif +#endif put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM + 0xfff, &dev->idProduct); return 0; diff --git a/arch/arm/mach-k3/am62ax/Kconfig b/arch/arm/mach-k3/am62ax/Kconfig index f8cdcdca57a..6a3969343ec 100644 --- a/arch/arm/mach-k3/am62ax/Kconfig +++ b/arch/arm/mach-k3/am62ax/Kconfig @@ -50,9 +50,30 @@ config TARGET_PHYCORE_AM62AX_R5 select BINMAN imply SYS_K3_SPL_ATF +config TARGET_AM62D2_A53_EVM + bool "TI K3 based AM62D2 EVM running on A53" + select ARM64 + select BINMAN + imply BOARD + imply SPL_BOARD + imply TI_I2C_BOARD_DETECT + +config TARGET_AM62D2_R5_EVM + bool "TI K3 based AM62D2 EVM running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT + endchoice source "board/ti/am62ax/Kconfig" source "board/phytec/phycore_am62ax/Kconfig" +source "board/ti/am62dx/Kconfig" endif diff --git a/arch/arm/mach-k3/am62ax/am62a7_init.c b/arch/arm/mach-k3/am62ax/am62a7_init.c index 00173e6836b..7de23461163 100644 --- a/arch/arm/mach-k3/am62ax/am62a7_init.c +++ b/arch/arm/mach-k3/am62ax/am62a7_init.c @@ -218,6 +218,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) @@ -235,5 +240,9 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 spl_boot_device(void) { +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) + return k3_r5_falcon_bootmode(); +#else return get_boot_device(); +#endif } diff --git a/arch/arm/mach-k3/am62px/am62p5_init.c b/arch/arm/mach-k3/am62px/am62p5_init.c index 44a2d445d24..4c215d5cebe 100644 --- a/arch/arm/mach-k3/am62px/am62p5_init.c +++ b/arch/arm/mach-k3/am62px/am62p5_init.c @@ -264,6 +264,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) @@ -370,6 +375,10 @@ u32 spl_boot_device(void) u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT); u32 bootmedia; +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) + return k3_r5_falcon_bootmode(); +#endif + if (bootindex == K3_PRIMARY_BOOTMODE) bootmedia = __get_primary_bootmedia(devstat); else diff --git a/arch/arm/mach-k3/am62x/Kconfig b/arch/arm/mach-k3/am62x/Kconfig index 81199ada3a1..f7ad52db7d8 100644 --- a/arch/arm/mach-k3/am62x/Kconfig +++ b/arch/arm/mach-k3/am62x/Kconfig @@ -14,6 +14,8 @@ config TARGET_AM625_A53_EVM select ARM64 select BINMAN select OF_SYSTEM_SETUP + imply TI_COMMON_CMD_OPTIONS + imply TI_I2C_BOARD_DETECT config TARGET_AM625_R5_EVM bool "TI K3 based AM625 EVM running on R5" @@ -25,6 +27,7 @@ config TARGET_AM625_R5_EVM select K3_DDRSS select BINMAN imply SYS_K3_SPL_ATF + imply TI_I2C_BOARD_DETECT config TARGET_PHYCORE_AM62X_A53 bool "PHYTEC phyCORE-AM62x running on A53" diff --git a/arch/arm/mach-k3/am62x/am625_init.c b/arch/arm/mach-k3/am62x/am625_init.c index a422919fab1..02b7414e21c 100644 --- a/arch/arm/mach-k3/am62x/am625_init.c +++ b/arch/arm/mach-k3/am62x/am625_init.c @@ -294,15 +294,6 @@ void board_init_f(ulong dummy) } spl_enable_cache(); - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && - spl_boot_device() == BOOT_DEVICE_ETHERNET) { - struct udevice *cpswdev; - - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), - &cpswdev)) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } - fixup_a53_cpu_freq_by_speed_grade(); } @@ -314,6 +305,11 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >> MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT; + if (bootindex != K3_PRIMARY_BOOTMODE) { + pr_alert("Fallback to backup bootmode MMCSD_MODE_FS\n"); + return MMCSD_MODE_FS; + } + switch (bootmode) { case BOOT_DEVICE_EMMC: if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) @@ -331,5 +327,9 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) u32 spl_boot_device(void) { +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) + return k3_r5_falcon_bootmode(); +#else return get_boot_device(); +#endif } diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index 41812b7dbf7..219798315db 100644 --- a/arch/arm/mach-k3/am64x/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -263,13 +263,6 @@ void board_init_f(ulong dummy) if (ret) panic("DRAM init failed: %d\n", ret); #endif - if (IS_ENABLED(CONFIG_SPL_ETH) && IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS) && - spl_boot_device() == BOOT_DEVICE_ETHERNET) { - struct udevice *cpswdev; - - if (uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(am65_cpsw_nuss), &cpswdev)) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } } u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) diff --git a/arch/arm/mach-k3/am64x/boot.c b/arch/arm/mach-k3/am64x/boot.c index ce8ae941be6..bf8e1a5cb44 100644 --- a/arch/arm/mach-k3/am64x/boot.c +++ b/arch/arm/mach-k3/am64x/boot.c @@ -103,3 +103,39 @@ u32 get_boot_device(void) return bootmedia; } + +const char *get_reset_reason(void) +{ + u32 reset_reason = readl(CTRLMMR_MCU_RST_SRC); + + /* After reading reset source register, software must clear it */ + if (reset_reason) + writel(reset_reason, CTRLMMR_MCU_RST_SRC); + + if (reset_reason == 0 || + (reset_reason & (RST_SRC_SW_MAIN_POR_FROM_MAIN | + RST_SRC_SW_MAIN_POR_FROM_MCU))) + return "POR"; + + if (reset_reason & (RST_SRC_SAFETY_ERR | RST_SRC_MAIN_ESM_ERR)) + return "ESM"; + + if (reset_reason & (RST_SRC_SW_MAIN_WARM_FROM_MAIN | + RST_SRC_SW_MAIN_WARM_FROM_MCU | + RST_SRC_SW_MCU_WARM_RST)) + return "RST"; + + if (reset_reason & (RST_SRC_SMS_WARM_RST | RST_SRC_SMS_COLD_RST)) + return "DMSC"; + + if (reset_reason & RST_SRC_DEBUG_RST) + return "JTAG"; + + if (reset_reason & RST_SRC_THERMAL_RST) + return "THERMAL"; + + if (reset_reason & (RST_SRC_MAIN_RESET_PIN | RST_SRC_MCU_RESET_PIN)) + return "PIN"; + + return "UNKNOWN"; +} diff --git a/arch/arm/mach-k3/arm64/arm64-mmu.c b/arch/arm/mach-k3/arm64/arm64-mmu.c index 0e07b1b7ce0..f999af143fb 100644 --- a/arch/arm/mach-k3/arm64/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64/arm64-mmu.c @@ -11,44 +11,38 @@ #include <asm/system.h> #include <asm/armv8/mmu.h> +#include <linux/sizes.h> +#include <mach/k3-ddr.h> -struct mm_region k3_mem_map[] = { - { +struct mm_region k3_mem_map[K3_MEM_MAP_LEN] = { + { /* SoC Peripherals */ .virt = 0x0UL, .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x1e780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x60000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { + }, { /* Flash Peripherals */ .virt = 0x500000000UL, .phys = 0x500000000UL, .size = 0x380000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ + }, [K3_MEM_MAP_FIRST_BANK_IDX] = { /* First DRAM Bank of size 2G */ + .virt = CFG_SYS_SDRAM_BASE, + .phys = CFG_SYS_SDRAM_BASE, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { /* List terminator */ 0, } }; struct mm_region *mem_map = k3_mem_map; + +u64 get_page_table_size(void) +{ + return SZ_128K; +} diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index f8c53b286eb..760aaad0341 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -30,6 +30,9 @@ #include <soc.h> #include <dm/uclass-internal.h> #include <dm/device-internal.h> +#include <asm/armv8/mmu.h> +#include <mach/k3-common-fdt.h> +#include <mach/k3-ddr.h> #define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT 0x00000001 #define PROC_BOOT_STATUS_FLAG_R5_WFI 0x00000002 @@ -258,6 +261,47 @@ void board_prep_linux(struct bootm_headers *images) ROUND(images->os.end, CONFIG_SYS_CACHELINE_SIZE)); } + +void enable_caches(void) +{ + void *fdt = (void *)gd->fdt_blob; + int ret; + + ret = mem_map_from_dram_banks(K3_MEM_MAP_FIRST_BANK_IDX, K3_MEM_MAP_LEN, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE); + if (ret) + debug("%s: Failed to setup dram banks\n", __func__); + + mmu_setup(); + + if (CONFIG_K3_ATF_LOAD_ADDR >= CFG_SYS_SDRAM_BASE) { + ret = fdt_fixup_reserved(fdt, "tfa", CONFIG_K3_ATF_LOAD_ADDR, + 0x80000); + if (ret) + printf("%s: Failed to perform tfa fixups (%s)\n", + __func__, fdt_strerror(ret)); + ret = mmu_unmap_reserved_mem("tfa", true); + if (ret) + printf("%s: Failed to unmap tfa reserved mem (%d)\n", + __func__, ret); + } + + if (CONFIG_K3_OPTEE_LOAD_ADDR >= CFG_SYS_SDRAM_BASE) { + ret = fdt_fixup_reserved(fdt, "optee", + CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); + if (ret) + printf("%s: Failed to perform optee fixups (%s)\n", + __func__, fdt_strerror(ret)); + ret = mmu_unmap_reserved_mem("optee", true); + if (ret) + printf("%s: Failed to unmap optee reserved mem (%d)\n", + __func__, ret); + } + + icache_enable(); + dcache_enable(); +} #endif void spl_enable_cache(void) @@ -267,6 +311,7 @@ void spl_enable_cache(void) int ret = 0; dram_init(); + dram_init_banksize(); /* reserve TLB table */ gd->arch.tlb_size = PGTABLE_SIZE; @@ -303,8 +348,27 @@ static __maybe_unused void k3_dma_remove(void) pr_warn("DMA Device not found (err=%d)\n", rc); } +void spl_perform_arch_fixups(struct spl_image_info *spl_image) +{ + void *fdt = spl_image_fdt_addr(spl_image); + + if (!fdt) + return; + + fdt_fixup_reserved(fdt, "tfa", CONFIG_K3_ATF_LOAD_ADDR, 0x80000); + fdt_fixup_reserved(fdt, "optee", CONFIG_K3_OPTEE_LOAD_ADDR, 0x1800000); +} + void spl_board_prepare_for_boot(void) { +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) + int ret; + + ret = k3_r5_falcon_prep(); + if (ret) + panic("%s: Failed to boot in falcon mode: %d\n", __func__, ret); +#endif /* falcon mode on R5 SPL */ + #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) dcache_disable(); #endif @@ -322,17 +386,6 @@ void spl_board_prepare_for_linux(void) int misc_init_r(void) { - if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) { - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(am65_cpsw_nuss), - &dev); - if (ret) - printf("Failed to probe am65_cpsw_nuss driver\n"); - } - if (IS_ENABLED(CONFIG_TI_ICSSG_PRUETH)) { struct udevice *dev; int ret; @@ -436,3 +489,11 @@ release_proc_ctrl: proc_ops->proc_release(ti_sci, PROC_ID_MCU_R5FSS0_CORE1); return ret; } + +#if IS_ENABLED(CONFIG_ARM64) && IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) +int spl_start_uboot(void) +{ + /* Always boot to linux on Cortex-A SPL with CONFIG_SPL_OS_BOOT set */ + return 0; +} +#endif diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 52d3faaab5c..cd3e19374dc 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -52,6 +52,11 @@ void do_board_detect(void); void ti_secure_image_check_binary(void **p_image, size_t *p_size); int shutdown_mcu_r5_core1(void); +#if IS_ENABLED(CONFIG_SPL_OS_BOOT_SECURE) && !IS_ENABLED(CONFIG_ARM64) +int k3_r5_falcon_bootmode(void); +int k3_r5_falcon_prep(void); +#endif + #if (IS_ENABLED(CONFIG_K3_QOS)) void setup_qos(void); #else diff --git a/arch/arm/mach-k3/common_fdt.c b/arch/arm/mach-k3/common_fdt.c index 2777354c6ab..1e6786f6c20 100644 --- a/arch/arm/mach-k3/common_fdt.c +++ b/arch/arm/mach-k3/common_fdt.c @@ -140,7 +140,9 @@ int fdt_fixup_reserved(void *blob, const char *name, return -EINVAL; if (!strncmp(node_name, name, strlen(name))) { /* Read out old size first */ - addr = fdtdec_get_addr_size(blob, subnode, "reg", &size); + addr = fdtdec_get_addr_size_auto_parent( + blob, nodeoffset, subnode, "reg", 0, &size, + false); if (addr == FDT_ADDR_T_NONE) return -EINVAL; new_size = size; diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 105b42986de..2717da07690 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -46,6 +46,24 @@ /* Use Last 2K as Scratch pad */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800 +/* Reset Reason Detection */ +#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) + +/* Reset causes by bit mapping */ +#define RST_SRC_SAFETY_ERR BIT(31) +#define RST_SRC_MAIN_ESM_ERR BIT(30) +#define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25) +#define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24) +#define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21) +#define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20) +#define RST_SRC_SW_MCU_WARM_RST BIT(16) +#define RST_SRC_SMS_WARM_RST BIT(13) +#define RST_SRC_SMS_COLD_RST BIT(12) +#define RST_SRC_DEBUG_RST BIT(8) +#define RST_SRC_THERMAL_RST BIT(4) +#define RST_SRC_MAIN_RESET_PIN BIT(2) +#define RST_SRC_MCU_RESET_PIN BIT(0) + #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) #define AM64X_DEV_RTI8 127 diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h index d8fae2c8b45..47a61281d94 100644 --- a/arch/arm/mach-k3/include/mach/j721s2_spl.h +++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h @@ -12,6 +12,7 @@ #define BOOT_DEVICE_OSPI 0x01 #define BOOT_DEVICE_QSPI 0x02 #define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_CPGMAC 0x04 #define BOOT_DEVICE_ETHERNET 0x04 #define BOOT_DEVICE_I2C 0x06 #define BOOT_DEVICE_UART 0x07 diff --git a/arch/arm/mach-k3/include/mach/j784s4_spl.h b/arch/arm/mach-k3/include/mach/j784s4_spl.h index d481a46c675..3814dc95d01 100644 --- a/arch/arm/mach-k3/include/mach/j784s4_spl.h +++ b/arch/arm/mach-k3/include/mach/j784s4_spl.h @@ -44,4 +44,6 @@ #define K3_PRIMARY_BOOTMODE 0x0 #define K3_BACKUP_BOOTMODE 0x1 +#define BOOT_DEVICE_CPGMAC 0x04 + #endif diff --git a/arch/arm/mach-k3/include/mach/k3-ddr.h b/arch/arm/mach-k3/include/mach/k3-ddr.h index 39e6725bb9b..207e60b2763 100644 --- a/arch/arm/mach-k3/include/mach/k3-ddr.h +++ b/arch/arm/mach-k3/include/mach/k3-ddr.h @@ -8,6 +8,12 @@ #include <spl.h> +/* We need 3 extra entries for: + * SoC peripherals, flash and the sentinel value. + */ +#define K3_MEM_MAP_LEN ((CONFIG_NR_DRAM_BANKS) + 3) +#define K3_MEM_MAP_FIRST_BANK_IDX 2 + int dram_init(void); int dram_init_banksize(void); diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c b/arch/arm/mach-k3/r5/am62px/clk-data.c index bc62d1d0d08..b552a2be74d 100644 --- a/arch/arm/mach-k3/r5/am62px/clk-data.c +++ b/arch/arm/mach-k3/r5/am62px/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <bb@ti.com>. * - * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include <linux/clk-provider.h> @@ -62,6 +62,17 @@ static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk10", }; +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { "postdiv4_16ff_main_0_hsdivout5_clk", "hsdiv4_16fft_main_2_hsdivout2_clk", @@ -99,8 +110,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = { "board_0_cp_gemac_cpts0_rft_clk_out", "hsdiv4_16fft_main_1_hsdivout3_clk", "postdiv4_16ff_main_2_hsdivout6_clk", - NULL, - NULL, + "cpsw_3guss_am67_main_0_cpts_genf0", + "cpsw_3guss_am67_main_0_cpts_genf1", NULL, NULL, NULL, @@ -148,7 +159,12 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -201,6 +217,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), @@ -216,6 +233,24 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -240,6 +275,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), @@ -286,6 +323,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 40, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 54, "mshsi2c_main_0_porscl"), DEV_CLK(157, 91, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 96, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), DEV_CLK(157, 101, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 103, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 143, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/am62px/dev-data.c b/arch/arm/mach-k3/r5/am62px/dev-data.c index 3cc211ea202..63e6beb4d57 100644 --- a/arch/arm/mach-k3/r5/am62px/dev-data.c +++ b/arch/arm/mach-k3/r5/am62px/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <bb@ti.com>. * - * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -31,11 +31,12 @@ static struct ti_lpsc soc_lpsc_list[] = { [6] = PSC_LPSC(24, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), [7] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), [8] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), - [9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), - [10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]), - [11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), - [12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), - [13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), + [9] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[8]), + [10] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[8]), + [11] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[10]), + [12] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]), + [13] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]), + [14] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[13]), }; static struct ti_dev soc_dev_list[] = { @@ -52,11 +53,12 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(36, &soc_lpsc_list[8]), PSC_DEV(102, &soc_lpsc_list[8]), PSC_DEV(146, &soc_lpsc_list[8]), - PSC_DEV(166, &soc_lpsc_list[9]), - PSC_DEV(135, &soc_lpsc_list[10]), - PSC_DEV(170, &soc_lpsc_list[11]), - PSC_DEV(177, &soc_lpsc_list[12]), - PSC_DEV(55, &soc_lpsc_list[13]), + PSC_DEV(13, &soc_lpsc_list[9]), + PSC_DEV(166, &soc_lpsc_list[10]), + PSC_DEV(135, &soc_lpsc_list[11]), + PSC_DEV(170, &soc_lpsc_list[12]), + PSC_DEV(177, &soc_lpsc_list[13]), + PSC_DEV(55, &soc_lpsc_list[14]), }; const struct ti_k3_pd_platdata am62px_pd_platdata = { diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index 6269b33f66b..03638366046 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -376,3 +376,149 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image, } } #endif + +#ifdef CONFIG_SPL_OS_BOOT_SECURE + +static bool tifalcon_loaded = false; + +int spl_start_uboot(void) +{ + /* If tifalcon.bin is not loaded, proceed to regular boot */ + if (!tifalcon_loaded) + return 1; + + /* Boot to linux on R5 SPL with tifalcon.bin loaded */ + return 0; +} + +int k3_r5_falcon_bootmode(void) +{ + char *mmcdev = env_get("mmcdev"); + + if (!mmcdev) + return BOOT_DEVICE_NOBOOT; + + if (strncmp(mmcdev, "0", sizeof("0")) == 0) + return BOOT_DEVICE_MMC1; + else if (strncmp(mmcdev, "1", sizeof("1")) == 0) + return BOOT_DEVICE_MMC2; + else + return BOOT_DEVICE_NOBOOT; +} + +static int k3_falcon_fdt_add_bootargs(void *fdt) +{ + struct disk_partition info; + struct blk_desc *dev_desc; + char bootmedia[32]; + char bootpart[32]; + char str[256]; + int ret; + + strlcpy(bootmedia, env_get("boot"), sizeof(bootmedia)); + strlcpy(bootpart, env_get("bootpart"), sizeof(bootpart)); + ret = blk_get_device_part_str(bootmedia, bootpart, &dev_desc, &info, 0); + if (ret < 0) { + printf("%s: Failed to get part details for %s %s [%d]\n", + __func__, bootmedia, bootpart, ret); + return ret; + } + + if (!CONFIG_IS_ENABLED(PARTITION_UUIDS)) { + printf("ERROR: Failed to find rootfs PARTUUID\n"); + printf("%s: CONFIG_SPL_PARTITION_UUIDS not enabled\n", + __func__); + return -EOPNOTSUPP; + } + + snprintf(str, sizeof(str), "console=%s root=PARTUUID=%s rootwait", + env_get("console"), disk_partition_uuid(&info)); + + ret = fdt_find_and_setprop(fdt, "/chosen", "bootargs", str, + strlen(str) + 1, 1); + if (ret) { + printf("%s: Could not set bootargs: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + + debug("%s: Set bootargs to: %s\n", __func__, str); + return 0; +} + +static int k3_falcon_fdt_fixup(void *fdt) +{ + int ret; + + if (!fdt) + return -EINVAL; + + fdt_set_totalsize(fdt, fdt_totalsize(fdt) + CONFIG_SYS_FDT_PAD); + + if (fdt_path_offset(fdt, "/chosen/bootargs") < 0) { + ret = k3_falcon_fdt_add_bootargs(fdt); + + if (ret) + return ret; + } + + if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) { + ret = ft_board_setup(fdt, gd->bd); + if (ret) { + printf("%s: Failed in board setup: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + } + + if (IS_ENABLED(CONFIG_OF_SYSTEM_SETUP)) { + ret = ft_system_setup(fdt, gd->bd); + if (ret) { + printf("%s: Failed in system setup: %s\n", __func__, + fdt_strerror(ret)); + return ret; + } + } + + return 0; +} + +int k3_r5_falcon_prep(void) +{ + struct spl_image_loader *loader, *drv; + struct spl_image_info kernel_image; + struct spl_boot_device bootdev; + int ret = -ENXIO, n_ents; + void *fdt; + + tifalcon_loaded = true; + memset(&kernel_image, '\0', sizeof(kernel_image)); + drv = ll_entry_start(struct spl_image_loader, spl_image_loader); + n_ents = ll_entry_count(struct spl_image_loader, spl_image_loader); + bootdev.boot_device = k3_r5_falcon_bootmode(); + + for (loader = drv; loader != drv + n_ents; loader++) { + if (loader && bootdev.boot_device != loader->boot_device) + continue; + + printf("Load falcon from %s\n", spl_loader_name(loader)); + ret = loader->load_image(&kernel_image, &bootdev); + if (ret) + continue; + + fdt = spl_image_fdt_addr(&kernel_image); + ret = k3_falcon_fdt_fixup(fdt); + if (ret) { + printf("Failed to fixup fdt in falcon mode: %d\n", ret); + return ret; + } + + return 0; + } + + printf("%s: ERROR: No supported loader for boot dev '%d'\n", __func__, + bootdev.boot_device); + + return ret; +} +#endif diff --git a/arch/arm/mach-k3/r5/j721s2/clk-data.c b/arch/arm/mach-k3/r5/j721s2/clk-data.c index 0c5c321c1eb..0130c9c4b86 100644 --- a/arch/arm/mach-k3/r5/j721s2/clk-data.c +++ b/arch/arm/mach-k3/r5/j721s2/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Dave Gerlach <d-gerlach@ti.com>. * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include <linux/clk-provider.h> @@ -55,6 +55,32 @@ static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { "hsdiv4_16fft_mcu_2_hsdivout4_clk", }; +static const char * const wkup_gpio0_clksel_out0_parents[] = { + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", + "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", +}; + static const char * const mcu_usart_clksel_out0_parents[] = { "hsdiv4_16fft_mcu_1_hsdivout3_clk", "postdiv3_16fft_main_1_hsdivout5_clk", @@ -174,7 +200,11 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -199,6 +229,8 @@ static const struct clk_data clk_list[] = { CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0), @@ -275,6 +307,24 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(29, 3, "cpsw2g_cpts_rclk_sel_out0"), + DEV_CLK(29, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(29, 5, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(29, 6, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(29, 7, "board_0_cpts0_rft_clk_out"), + DEV_CLK(29, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(29, 9, "board_0_ext_refclk1_out"), + DEV_CLK(29, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(29, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(29, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 22, "board_0_mcu_rgmii1_rxc_out"), + DEV_CLK(29, 26, "board_0_mcu_rmii1_ref_clk_out"), + DEV_CLK(29, 28, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(29, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 30, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 32, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(29, 33, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"), DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"), @@ -367,6 +417,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"), DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"), + DEV_CLK(157, 207, "cpsw_2guss_mcu_0_mdio_mdclk_o"), DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"), DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 221, "mcu_clkout_mux_out0"), @@ -374,6 +425,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"), DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 244, "cpsw_2guss_mcu_0_rgmii1_txc_o"), DEV_CLK(157, 352, "dpi0_ext_clksel_out0"), DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"), DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), @@ -400,7 +452,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j721s2_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 105, + .clk_list_cnt = ARRAY_SIZE(clk_list), .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 124, + .soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data), }; diff --git a/arch/arm/mach-k3/r5/j721s2/dev-data.c b/arch/arm/mach-k3/r5/j721s2/dev-data.c index df70c5e5d7c..b78550707c5 100644 --- a/arch/arm/mach-k3/r5/j721s2/dev-data.c +++ b/arch/arm/mach-k3/r5/j721s2/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Dave Gerlach <d-gerlach@ti.com>. * - * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -47,6 +47,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(29, &soc_lpsc_list[0]), PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(108, &soc_lpsc_list[0]), PSC_DEV(109, &soc_lpsc_list[0]), diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c index b4f27af333d..238d57d0aa0 100644 --- a/arch/arm/mach-k3/r5/j722s/clk-data.c +++ b/arch/arm/mach-k3/r5/j722s/clk-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <bb@ti.com>. * - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include <linux/clk-provider.h> @@ -57,9 +57,15 @@ static const char * const clkout0_ctrl_out0_parents[] = { "hsdiv4_16fft_main_2_hsdivout1_clk", }; -static const char * const main_emmcsd0_refclk_sel_out0_parents[] = { - "postdiv4_16ff_main_0_hsdivout5_clk", - "hsdiv4_16fft_main_2_hsdivout2_clk", +static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = { + "postdiv4_16ff_main_2_hsdivout5_clk", + "postdiv4_16ff_main_0_hsdivout6_clk", + "board_0_cp_gemac_cpts0_rft_clk_out", + NULL, + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", }; static const char * const main_emmcsd1_refclk_sel_out0_parents[] = { @@ -94,8 +100,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = { "board_0_cp_gemac_cpts0_rft_clk_out", "hsdiv4_16fft_main_1_hsdivout3_clk", "postdiv4_16ff_main_2_hsdivout6_clk", - NULL, - NULL, + "cpsw_3guss_am67_main_0_cpts_genf0", + "cpsw_3guss_am67_main_0_cpts_genf1", NULL, NULL, NULL, @@ -143,7 +149,12 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0), + CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_tck_out", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf0", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_cpts_genf1", 0, 0), + CLK_FIXED_RATE("cpsw_3guss_am67_main_0_mdio_mdclk_o", 0, 0), CLK_FIXED_RATE("dmtimer_dmc1ms_main_0_timer_pwm", 0, 0), CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -194,7 +205,7 @@ static const struct clk_data clk_list[] = { CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0), CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0), CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0), - CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0), + CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0), CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0), CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0), CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0), @@ -209,6 +220,24 @@ static const struct clk_data clk_list[] = { }; static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"), + DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"), + DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"), + DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"), + DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(13, 9, "board_0_ext_refclk1_out"), + DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 19, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 20, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"), + DEV_CLK(13, 22, "board_0_rmii1_ref_clk_out"), + DEV_CLK(13, 23, "board_0_rmii2_ref_clk_out"), DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"), DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -233,10 +262,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"), DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"), DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"), - DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), - DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"), - DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"), - DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"), + DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"), DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"), DEV_CLK(58, 1, "board_0_mmc1_clklb_out"), DEV_CLK(58, 2, "board_0_mmc1_clk_out"), @@ -279,6 +306,7 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 62, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(157, 74, "mshsi2c_main_0_porscl"), DEV_CLK(157, 135, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"), + DEV_CLK(157, 140, "cpsw_3guss_am67_main_0_mdio_mdclk_o"), DEV_CLK(157, 143, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 145, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 157, "fss_ul_main_0_ospi_0_ospi_oclk_clk"), diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c index 59176c98999..d6832266884 100644 --- a/arch/arm/mach-k3/r5/j722s/dev-data.c +++ b/arch/arm/mach-k3/r5/j722s/dev-data.c @@ -5,7 +5,7 @@ * This file is auto generated. Please do not hand edit and report any issues * to Bryan Brattlof <bb@ti.com>. * - * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/ */ #include "k3-dev.h" @@ -23,16 +23,16 @@ static struct ti_pd soc_pd_list[] = { static struct ti_lpsc soc_lpsc_list[] = { [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), - [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), - [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]), - [3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]), - [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]), + [1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), + [2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]), + [3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]), + [8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]), [9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]), - [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), + [10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]), [11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]), [12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]), }; @@ -43,13 +43,13 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(61, &soc_lpsc_list[0]), PSC_DEV(178, &soc_lpsc_list[1]), PSC_DEV(179, &soc_lpsc_list[2]), - PSC_DEV(57, &soc_lpsc_list[3]), - PSC_DEV(58, &soc_lpsc_list[4]), - PSC_DEV(161, &soc_lpsc_list[5]), - PSC_DEV(75, &soc_lpsc_list[6]), - PSC_DEV(36, &soc_lpsc_list[7]), - PSC_DEV(102, &soc_lpsc_list[7]), - PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(58, &soc_lpsc_list[3]), + PSC_DEV(161, &soc_lpsc_list[4]), + PSC_DEV(75, &soc_lpsc_list[5]), + PSC_DEV(36, &soc_lpsc_list[6]), + PSC_DEV(102, &soc_lpsc_list[6]), + PSC_DEV(146, &soc_lpsc_list[6]), + PSC_DEV(13, &soc_lpsc_list[7]), PSC_DEV(166, &soc_lpsc_list[8]), PSC_DEV(135, &soc_lpsc_list[9]), PSC_DEV(170, &soc_lpsc_list[10]), diff --git a/arch/arm/mach-k3/r5/j784s4/clk-data.c b/arch/arm/mach-k3/r5/j784s4/clk-data.c index 97d969271ec..24780eb6562 100644 --- a/arch/arm/mach-k3/r5/j784s4/clk-data.c +++ b/arch/arm/mach-k3/r5/j784s4/clk-data.c @@ -57,6 +57,25 @@ static const char * const wkup_gpio0_clksel_out0_parents[] = { "j7am_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", }; +static const char * const cpsw2g_cpts_rclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "board_0_mcu_cpts0_rft_clk_out", + "board_0_cpts0_rft_clk_out", + "board_0_mcu_ext_refclk0_out", + "board_0_ext_refclk1_out", + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", +}; + static const char * const mcu_usart_clksel_out0_parents[] = { "hsdiv4_16fft_mcu_1_hsdivout3_clk", "postdiv3_16fft_main_1_hsdivout5_clk", @@ -132,6 +151,11 @@ static const char * const main_pll_hfosc_sel_out8_parents[] = { "board_0_hfosc1_clk_out", }; +static const char * const mcu_clkout_mux_out0_parents[] = { + "hsdiv4_16fft_mcu_2_hsdivout0_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", +}; + static const char * const usb0_refclk_sel_out0_parents[] = { "gluelogic_hfosc0_clkout", "board_0_hfosc1_clk_out", @@ -142,11 +166,6 @@ static const char * const emmcsd1_lb_clksel_out0_parents[] = { "board_0_mmc1_clk_out", }; -static const char * const mcu_clkout_mux_out0_parents[] = { - "hsdiv4_16fft_mcu_2_hsdivout0_clk", - "hsdiv4_16fft_mcu_2_hsdivout1_clk", -}; - static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { "main_pll_hfosc_sel_out0", "hsdiv4_16fft_main_0_hsdivout0_clk", @@ -201,7 +220,11 @@ static const struct clk_data clk_list[] = { CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0), CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rgmii1_rxc_out", 0, 0), + CLK_FIXED_RATE("board_0_mcu_rmii1_ref_clk_out", 0, 0), CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_mdio_mdclk_o", 0, 0), + CLK_FIXED_RATE("cpsw_2guss_mcu_0_rgmii1_txc_o", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0), CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0), CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), @@ -224,6 +247,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0), + CLK_MUX("cpsw2g_cpts_rclk_sel_out0", cpsw2g_cpts_rclk_sel_out0_parents, 16, 0x40f08050, 8, 4, 0), CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0), CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0), CLK_MUX("wkup_usart_clksel_out0", wkup_usart_clksel_out0_parents, 2, 0x43008064, 0, 1, 0), @@ -317,6 +341,24 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(61, 15, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(61, 16, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(63, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(63, 3, "cpsw2g_cpts_rclk_sel_out0"), + DEV_CLK(63, 4, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(63, 5, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(63, 6, "board_0_mcu_cpts0_rft_clk_out"), + DEV_CLK(63, 7, "board_0_cpts0_rft_clk_out"), + DEV_CLK(63, 8, "board_0_mcu_ext_refclk0_out"), + DEV_CLK(63, 9, "board_0_ext_refclk1_out"), + DEV_CLK(63, 18, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(63, 19, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(63, 20, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 21, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 22, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 24, "board_0_mcu_rgmii1_rxc_out"), + DEV_CLK(63, 27, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 28, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 29, "hsdiv4_16fft_mcu_2_hsdivout0_clk"), + DEV_CLK(63, 30, "board_0_mcu_rmii1_ref_clk_out"), DEV_CLK(78, 0, "postdiv3_16fft_main_0_hsdivout8_clk"), DEV_CLK(78, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), DEV_CLK(78, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), @@ -353,10 +395,12 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), DEV_CLK(157, 179, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"), DEV_CLK(157, 180, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"), + DEV_CLK(157, 190, "cpsw_2guss_mcu_0_mdio_mdclk_o"), DEV_CLK(157, 224, "fss_mcu_0_ospi_0_ospi_oclk_clk"), DEV_CLK(157, 226, "fss_mcu_0_ospi_0_ospi_oclk_clk"), DEV_CLK(157, 228, "fss_mcu_0_ospi_1_ospi_oclk_clk"), DEV_CLK(157, 230, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(157, 233, "cpsw_2guss_mcu_0_rgmii1_txc_o"), DEV_CLK(157, 239, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(157, 243, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), DEV_CLK(157, 245, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), diff --git a/arch/arm/mach-k3/r5/j784s4/dev-data.c b/arch/arm/mach-k3/r5/j784s4/dev-data.c index b32b4ba9588..19901821225 100644 --- a/arch/arm/mach-k3/r5/j784s4/dev-data.c +++ b/arch/arm/mach-k3/r5/j784s4/dev-data.c @@ -54,6 +54,7 @@ static struct ti_lpsc soc_lpsc_list[] = { }; static struct ti_dev soc_dev_list[] = { + PSC_DEV(63, &soc_lpsc_list[0]), PSC_DEV(35, &soc_lpsc_list[0]), PSC_DEV(160, &soc_lpsc_list[0]), PSC_DEV(161, &soc_lpsc_list[0]), diff --git a/arch/arm/mach-k3/schema.yaml b/arch/arm/mach-k3/schema.yaml index c8dd2e79e7d..8c4691f24ed 100644 --- a/arch/arm/mach-k3/schema.yaml +++ b/arch/arm/mach-k3/schema.yaml @@ -344,7 +344,7 @@ properties: resasg_entries: type: array minItems: 0 - maxItems: 468 + maxItems: 586 items: type: object properties: @@ -420,7 +420,7 @@ properties: resasg_entries: type: array minItems: 0 - maxItems: 468 + maxItems: 586 items: type: object properties: diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig index d373ab56ce9..8f4fba4615c 100644 --- a/arch/arm/mach-renesas/Kconfig +++ b/arch/arm/mach-renesas/Kconfig @@ -74,7 +74,6 @@ config RZG2L select RCAR_64 imply CLK_RZG2L imply MULTI_DTB_FIT - imply MULTI_DTB_FIT_USER_DEFINED_AREA imply PINCTRL_RZG2L imply RENESAS_RAVB imply RENESAS_SDHI diff --git a/arch/arm/mach-renesas/Kconfig.rcar3 b/arch/arm/mach-renesas/Kconfig.rcar3 index ad35d1058f2..0d5f7486218 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar3 +++ b/arch/arm/mach-renesas/Kconfig.rcar3 @@ -91,7 +91,6 @@ config TARGET_BEACON_RZG2M imply CLK_CCF imply CLK_VERSACLOCK imply MULTI_DTB_FIT - imply MULTI_DTB_FIT_USER_DEFINED_AREA config TARGET_CONDOR bool "Condor board" @@ -130,7 +129,6 @@ config TARGET_EBISU config TARGET_HIHOPE_RZG2 bool "HiHope RZ/G2 board" imply MULTI_DTB_FIT - imply MULTI_DTB_FIT_USER_DEFINED_AREA imply R8A774A1 imply R8A774B1 imply R8A774E1 @@ -149,7 +147,6 @@ config TARGET_SILINUX_EK874 config TARGET_SALVATOR_X bool "Salvator-X board" imply MULTI_DTB_FIT - imply MULTI_DTB_FIT_USER_DEFINED_AREA imply R8A7795 imply R8A7796 imply R8A77965 @@ -160,7 +157,6 @@ config TARGET_SALVATOR_X config TARGET_ULCB bool "ULCB board" imply MULTI_DTB_FIT - imply MULTI_DTB_FIT_USER_DEFINED_AREA imply R8A7795 imply R8A7796 imply R8A77965 diff --git a/arch/arm/mach-renesas/cpu_info-rzg2l.c b/arch/arm/mach-renesas/cpu_info-rzg2l.c index ab95ce76388..a9cb9f72dd3 100644 --- a/arch/arm/mach-renesas/cpu_info-rzg2l.c +++ b/arch/arm/mach-renesas/cpu_info-rzg2l.c @@ -30,7 +30,7 @@ static const struct tfa_info *get_tfa_info(void) { void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]); - if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) { + if (atf_fdt_blob && fdt_magic(atf_fdt_blob) == FDT_MAGIC) { unsigned int i; for (i = 0; i < ARRAY_SIZE(tfa_info); i++) { if (!fdt_node_check_compatible(atf_fdt_blob, 0, diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h index 7b4f5f0c651..741fb8b7041 100644 --- a/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * ./arch/arm/mach-renesas/include/mach/rcar-gen3-base.h - * * Copyright (C) 2015 Renesas Electronics Corporation */ @@ -73,11 +71,11 @@ #define GICC_BASE 0xF1020000 /* PFC */ -#define PFC_PUEN5 0xE6060414 -#define PUEN_SSI_SDATA4 BIT(17) -#define PFC_PUEN6 0xE6060418 -#define PUEN_USB1_OVC (1 << 2) -#define PUEN_USB1_PWEN (1 << 1) +#define PFC_PUEN5 0xE6060414 +#define PUEN_SSI_SDATA4 BIT(17) +#define PFC_PUEN6 0xE6060418 +#define PUEN_USB1_OVC BIT(2) +#define PUEN_USB1_PWEN BIT(1) #ifndef __ASSEMBLY__ #include <asm/types.h> diff --git a/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h index f34473db35a..d882a9ba4a0 100644 --- a/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * ./arch/arm/mach-renesas/include/mach/rcar-gen4-base.h - * * Copyright (C) 2021 Renesas Electronics Corp. */ @@ -31,6 +29,8 @@ #define RST_BASE 0xE6160000 /* Domain0 */ #define RST_SRESCR0 (RST_BASE + 0x18) #define RST_SPRES 0x5AA58000 +#define RST_WDTRSTCR (RST_BASE + 0x10) +#define RST_RWDT 0xA55A8002 /* Arm Generic Timer */ #define CNTCR_BASE 0xE6080000 diff --git a/arch/arm/mach-renesas/psci-rcar64.c b/arch/arm/mach-renesas/psci-rcar64.c index a230692c9e0..459dd55ff45 100644 --- a/arch/arm/mach-renesas/psci-rcar64.c +++ b/arch/arm/mach-renesas/psci-rcar64.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <asm/psci.h> #include <asm/secure.h> +#include <asm/arch/renesas.h> int __secure psci_features(u32 function_id, u32 psci_fid) { @@ -29,10 +30,6 @@ u32 __secure psci_version(void) return ARM_PSCI_VER_0_2; } -#define RST_BASE 0xE6160000 /* Domain0 */ -#define RST_SRESCR0 (RST_BASE + 0x18) -#define RST_SPRES 0x5AA58000 - void __secure __noreturn psci_system_reset(void) { writel(RST_SPRES, RST_SRESCR0); diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index ae15a9f8a2d..06fb527b21a 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -11,9 +11,9 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o spl_common.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o -obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o spl_common.o -obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o spl_common.o ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),) diff --git a/arch/arm/mach-rockchip/px30-board-tpl.c b/arch/arm/mach-rockchip/px30-board-tpl.c index f0b3c5f83f4..2a3dcdac845 100644 --- a/arch/arm/mach-rockchip/px30-board-tpl.c +++ b/arch/arm/mach-rockchip/px30-board-tpl.c @@ -4,32 +4,9 @@ */ #include <debug_uart.h> -#include <dm.h> -#include <init.h> -#include <ram.h> -#include <spl.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/sdram_px30.h> - -#define TIMER_LOAD_COUNT0 0x00 -#define TIMER_LOAD_COUNT1 0x04 -#define TIMER_CUR_VALUE0 0x08 -#define TIMER_CUR_VALUE1 0x0c -#define TIMER_CONTROL_REG 0x10 - -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void secure_timer_init(void) -{ - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT0); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT1); - writel(TIMER_EN | TIMER_FMODE, - CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); -} +#include <asm/arch-rockchip/timer.h> void board_init_f(ulong dummy) { @@ -50,7 +27,8 @@ void board_init_f(ulong dummy) #endif #endif - secure_timer_init(); + rockchip_stimer_init(); + ret = sdram_init(); if (ret) printascii("sdram_init failed\n"); diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index 8ce9ac561f0..5a5c119328f 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -2,10 +2,14 @@ /* * Copyright (c) 2017 Rockchip Electronics Co., Ltd */ + +#define LOG_CATEGORY LOGC_ARCH + #include <clk.h> #include <dm.h> #include <fdt_support.h> #include <init.h> +#include <misc.h> #include <spl.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> @@ -15,6 +19,7 @@ #include <asm/arch-rockchip/clock.h> #include <asm/arch-rockchip/cru_px30.h> #include <dt-bindings/clock/px30-cru.h> +#include <linux/bitfield.h> const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff390000", @@ -442,3 +447,59 @@ void board_debug_uart_init(void) #endif /* CONFIG_DEBUG_UART_BASE && CONFIG_DEBUG_UART_BASE == ... */ } #endif /* CONFIG_DEBUG_UART_BOARD_INIT */ + +#define PX30_OTP_SPECIFICATION_OFFSET 0x06 + +#define DDR_GRF_BASE_ADDR 0xff630000 +#define DDR_GRF_CON(n) (0 + (n) * 4) + +int checkboard(void) +{ + struct udevice *dev; + u8 specification; + u32 base_soc; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* base SoC: 0x26334b52 for RK3326; 0x30335850 for PX30 */ + ret = misc_read(dev, 0, &base_soc, 4); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (base_soc != 0x26334b52 && base_soc != 0x30335850) { + log_debug("Could not identify SoC, got 0x%04x in OTP\n", base_soc); + return 0; + } + + /* SoC variant: 0x21 for PX30/PX30S/RK3326/RK3326S; 0x2b for PX30K */ + ret = misc_read(dev, PX30_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + + if (specification == 0x2b) { + printf("SoC: PX30K\n"); + return 0; + } + + /* From vendor kernel: drivers/soc/rockchip/rockchip-cpuinfo.c */ + specification = FIELD_GET(GENMASK(15, 14), + readl(DDR_GRF_BASE_ADDR + DDR_GRF_CON(1))); + log_debug("DDR specification is %d\n", specification); + printf("SoC: %s%s\n", base_soc == 0x26334b52 ? "RK3326" : "PX30", + specification == 0x3 ? "S" : ""); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 64e100172fa..d69139278a8 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -5,28 +5,9 @@ #include <debug_uart.h> #include <init.h> -#include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/sdram_rk3036.h> - -#define TIMER_LOAD_COUNT_L 0x00 -#define TIMER_LOAD_COUNT_H 0x04 -#define TIMER_CONTROL_REG 0x10 -#define TIMER_EN 0x1 -#define TIMER_FMODE (0 << 1) -#define TIMER_RMODE (1 << 1) - -void rockchip_stimer_init(void) -{ - asm volatile("mcr p15, 0, %0, c14, c0, 0" - : : "r"(CONFIG_COUNTER_FREQUENCY)); - - writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE); - writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 4); - writel(TIMER_EN | TIMER_FMODE, CONFIG_ROCKCHIP_STIMER_BASE + - TIMER_CONTROL_REG); -} +#include <asm/arch-rockchip/timer.h> void board_init_f(ulong dummy) { diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 43d151708e4..8687a9347ec 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -61,8 +61,8 @@ struct mm_region *mem_map = rk3399_mem_map; #define TIMER_CONTROL_REG 0x1c #define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) void rockchip_stimer_init(void) { diff --git a/arch/arm/mach-rockchip/rk3528/Kconfig b/arch/arm/mach-rockchip/rk3528/Kconfig index 993b2dd274e..480ac2942ff 100644 --- a/arch/arm/mach-rockchip/rk3528/Kconfig +++ b/arch/arm/mach-rockchip/rk3528/Kconfig @@ -1,5 +1,10 @@ if ROCKCHIP_RK3528 +config TARGET_RADXA_ROCK_2_RK3528 + bool "Radxa ROCK 2A/2F" + help + Radxa ROCK 2A/2F single board computers with a RK3528A SoC. + config ROCKCHIP_BOOT_MODE_REG default 0xff370200 @@ -9,6 +14,8 @@ config ROCKCHIP_STIMER_BASE config SYS_SOC default "rk3528" +source "board/radxa/rock-2-rk3528/Kconfig" + config SYS_CONFIG_NAME default "rk3528_common" diff --git a/arch/arm/mach-rockchip/rk3528/MAINTAINERS b/arch/arm/mach-rockchip/rk3528/MAINTAINERS index f343f71cf7f..ee840396e8b 100644 --- a/arch/arm/mach-rockchip/rk3528/MAINTAINERS +++ b/arch/arm/mach-rockchip/rk3528/MAINTAINERS @@ -9,3 +9,9 @@ M: Jonas Karlman <jonas@kwiboo.se> S: Maintained F: arch/arm/dts/rk3528-radxa-e20c* F: configs/radxa-e20c-rk3528_defconfig + +SIGE1-RK3528 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3528-armsom-sige1* +F: configs/sige1-rk3528_defconfig diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index 4892ff6ba9d..57ead0006f1 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -9,6 +9,9 @@ #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> +#define VPU_GRF_BASE 0xff340000 +#define USB3OTG_CON1 0x44 + #define FIREWALL_DDR_BASE 0xff2e0000 #define FW_DDR_MST6_REG 0x58 #define FW_DDR_MST7_REG 0x5c @@ -46,6 +49,21 @@ void board_debug_uart_init(void) { } +u32 read_brom_bootsource_id(void) +{ + u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); + + /* Re-map the raw value read from reg to an existing BROM_BOOTSOURCE + * enum value to avoid having to create a larger boot_devices table. + */ + if (bootsource_id == 0x81) + return BROM_BOOTSOURCE_USB; + else if (bootsource_id > BROM_LAST_BOOTSOURCE) + log_debug("Unknown bootsource %x\n", bootsource_id); + + return bootsource_id; +} + int arch_cpu_init(void) { u32 val; @@ -69,6 +87,9 @@ int arch_cpu_init(void) val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG); writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG); + /* Disable USB3OTG U3 port, later enabled in COMBPHY driver */ + writel(0xffff0181, VPU_GRF_BASE + USB3OTG_CON1); + return 0; } diff --git a/arch/arm/mach-rockchip/rk3576/MAINTAINERS b/arch/arm/mach-rockchip/rk3576/MAINTAINERS new file mode 100644 index 00000000000..393edd3984c --- /dev/null +++ b/arch/arm/mach-rockchip/rk3576/MAINTAINERS @@ -0,0 +1,29 @@ +GENERIC-RK3576 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3576-generic* +F: configs/generic-rk3576_defconfig + +NANOPI-M5-RK3576 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3576-nanopi-m5* +F: configs/nanopi-m5-rk3576_defconfig + +OMNI3576-RK3576 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3576-luckfox-omni3576* +F: configs/omni3576-rk3576_defconfig + +ROCK-4D-RK3576 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3576-rock-4d* +F: configs/rock-4d-rk3576_defconfig + +SIGE5-RK3576 +M: Jonas Karlman <jonas@kwiboo.se> +S: Maintained +F: arch/arm/dts/rk3576-armsom-sige5* +F: configs/sige5-rk3576_defconfig diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index ba5c94b4b3d..a1e8a7572fa 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -3,6 +3,10 @@ * Copyright (c) 2024 Rockchip Electronics Co., Ltd */ +#define LOG_CATEGORY LOGC_ARCH + +#include <dm.h> +#include <misc.h> #include <asm/armv8/mmu.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> @@ -29,8 +33,18 @@ #define SGRF_DOMAIN_CON4 0x10 #define SGRF_DOMAIN_CON5 0x14 +#define USB_GRF_BASE 0x2601E000 +#define USB3OTG0_CON1 0x0030 + +enum { + BROM_BOOTSOURCE_FSPI0 = 3, + BROM_BOOTSOURCE_FSPI1_M1 = 6, +}; + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000", + [BROM_BOOTSOURCE_FSPI0] = "/soc/spi@2a340000/flash@0", + [BROM_BOOTSOURCE_FSPI1_M1] = "/soc/spi@2a300000/flash@0", [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000", }; @@ -78,6 +92,24 @@ void board_debug_uart_init(void) { } +u32 read_brom_bootsource_id(void) +{ + u32 bootsource_id = readl(BROM_BOOTSOURCE_ID_ADDR); + + /* Re-map the raw value read from reg to a redefined or existing + * BROM_BOOTSOURCE enum value to avoid having to create a larger + * boot_devices table. + */ + if (bootsource_id == 0x23) + return BROM_BOOTSOURCE_FSPI1_M1; + else if (bootsource_id == 0x81) + return BROM_BOOTSOURCE_USB; + else if (bootsource_id > BROM_LAST_BOOTSOURCE) + log_debug("Unknown bootsource %x\n", bootsource_id); + + return bootsource_id; +} + #define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE #define HP_CTRL_REG 0x04 #define TIMER_EN BIT(0) @@ -151,5 +183,52 @@ int arch_cpu_init(void) */ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20); + /* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + + return 0; +} + +#define RK3576_OTP_CPU_CODE_OFFSET 0x02 +#define RK3576_OTP_SPECIFICATION_OFFSET 0x08 + +int checkboard(void) +{ + u8 cpu_code[2], specification; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x76 */ + ret = misc_read(dev, RK3576_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3576J */ + ret = misc_read(dev, RK3576_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + specification &= 0x1f; + + /* for RK3576J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + return 0; } diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig b/arch/arm/mach-rockchip/rk3588/Kconfig index 4e7942ada87..9fbe3f225aa 100644 --- a/arch/arm/mach-rockchip/rk3588/Kconfig +++ b/arch/arm/mach-rockchip/rk3588/Kconfig @@ -27,6 +27,23 @@ config TARGET_CM3588_NAS_RK3588 - 3.5mm Headphone out, 2.0mm PH-2A Mic in - 5V Fan connector, PWM beeper, IR receiver, RTC battery connector +config TARGET_GAMEFORCE_ACE_RK3588S + bool "GameForce Ace" + help + The GameForce Ace is a handheld game console from GameForce with + the Rockchip RK3588S SoC. + + Hardware features: + - Rockchip RK3588S SoC + - 12GB LPDDR4x RAM + - 128GB eMMC + - MicroSD card slot + - 1x USB 3.0 Type-C with DP AltMode support + - 1x HDMI 2.1 micro-HDMI out + - 1920x1080 touchscreen MIPI-DSI panel + - Analog joysticks and L/R triggers + - 16 digital buttons + config TARGET_GENBOOK_CM5_RK3588 bool "Cool Pi CM5 GenBook" help @@ -410,6 +427,7 @@ source "board/friendlyelec/cm3588-nas-rk3588/Kconfig" source "board/friendlyelec/nanopc-t6-rk3588/Kconfig" source "board/friendlyelec/nanopi-r6c-rk3588s/Kconfig" source "board/friendlyelec/nanopi-r6s-rk3588s/Kconfig" +source "board/gameforce/ace-rk3588s/Kconfig" source "board/hardkernel/odroid_m2/Kconfig" source "board/indiedroid/nova/Kconfig" source "board/khadas/khadas-edge2-rk3588s/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index e2278ff792b..c01a4002089 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -15,6 +15,10 @@ #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/ioc_rk3588.h> +#define USB_GRF_BASE 0xfd5ac000 +#define USB3OTG0_CON1 0x001c +#define USB3OTG1_CON1 0x0034 + #define FIREWALL_DDR_BASE 0xfe030000 #define FW_DDR_MST5_REG 0x54 #define FW_DDR_MST13_REG 0x74 @@ -184,6 +188,10 @@ int arch_cpu_init(void) /* Disable JTAG exposed on SDMMC */ rk_clrreg(&sys_grf->soc_con[6], SYS_GRF_FORCE_JTAG); #endif + + /* Disable USB3OTG U3 ports, later enabled by USBDP PHY driver */ + writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1); + writel(0xffff0188, USB_GRF_BASE + USB3OTG1_CON1); #endif return 0; diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 3dce9b30898..1ea1033b5ea 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -40,7 +40,7 @@ static int spl_node_to_boot_device(int node) * aware of the block-device layer. Until then (and to avoid unneeded * delays in getting this feature out), it lives at the board-level. */ - if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) { + if (!uclass_find_device_by_of_offset(UCLASS_MMC, node, &parent)) { struct udevice *dev; struct blk_desc *desc = NULL; @@ -72,7 +72,7 @@ static int spl_node_to_boot_device(int node) * extended with awareness of the BLK layer (and matching OF_CONTROL) * soon. */ - if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + if (!uclass_find_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) return BOOT_DEVICE_SPI; return -1; @@ -240,32 +240,40 @@ int spl_decode_boot_device(u32 boot_device, char *buf, size_t buflen) #endif } -void spl_perform_fixups(struct spl_image_info *spl_image) +void spl_perform_arch_fixups(struct spl_image_info *spl_image) { + const char *bootrom_ofpath = board_spl_was_booted_from(); void *blob = spl_image_fdt_addr(spl_image); char boot_ofpath[512]; int chosen, ret; - /* - * Inject the ofpath of the device the full U-Boot (or Linux in - * Falcon-mode) was booted from into the FDT, if a FDT has been - * loaded at the same time. - */ if (!blob) return; - ret = spl_decode_boot_device(spl_image->boot_device, boot_ofpath, sizeof(boot_ofpath)); - if (ret) { - pr_err("%s: could not map boot_device to ofpath: %d\n", __func__, ret); - return; - } - chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); if (chosen < 0) { pr_err("%s: could not find/create '/chosen'\n", __func__); return; } - fdt_setprop_string(blob, chosen, - "u-boot,spl-boot-device", boot_ofpath); + + /* + * Inject the ofpath of the device the full U-Boot (or Linux in + * Falcon-mode) was booted from into the FDT. + */ + ret = spl_decode_boot_device(spl_image->boot_device, boot_ofpath, sizeof(boot_ofpath)); + if (ret) + pr_err("%s: could not map boot_device to ofpath: %d\n", __func__, ret); + else + fdt_setprop_string(blob, chosen, + "u-boot,spl-boot-device", boot_ofpath); + + /* + * Inject the ofpath of the device the BootROM loaded the very first + * stage from into the FDT. + */ + if (!bootrom_ofpath) + pr_err("%s: could not map BootROM boot device to ofpath\n", __func__); + else + fdt_setprop_string(blob, chosen, "bootsource", bootrom_ofpath); } #endif diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index f4d29bbdd17..1ce3a3b0554 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -31,6 +31,11 @@ int board_return_to_bootrom(struct spl_image_info *spl_image, __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { }; +__weak u32 read_brom_bootsource_id(void) +{ + return readl(BROM_BOOTSOURCE_ID_ADDR); +} + const char *board_spl_was_booted_from(void) { static u32 brom_bootsource_id_cache = BROM_BOOTSOURCE_UNKNOWN; @@ -40,7 +45,7 @@ const char *board_spl_was_booted_from(void) if (brom_bootsource_id_cache != BROM_BOOTSOURCE_UNKNOWN) bootdevice_brom_id = brom_bootsource_id_cache; else - bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR); + bootdevice_brom_id = read_brom_bootsource_id(); if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) bootdevice_ofpath = boot_devices[bootdevice_brom_id]; diff --git a/arch/arm/mach-rockchip/spl_common.c b/arch/arm/mach-rockchip/spl_common.c index b29f33448ab..208cd22fcad 100644 --- a/arch/arm/mach-rockchip/spl_common.c +++ b/arch/arm/mach-rockchip/spl_common.c @@ -10,8 +10,8 @@ #define TIMER_LOAD_COUNT_H 0x04 #define TIMER_CONTROL_REG 0x10 #define TIMER_EN 0x1 -#define TIMER_FMODE BIT(0) -#define TIMER_RMODE BIT(1) +#define TIMER_FMODE (0 << 1) +#define TIMER_RMODE (1 << 1) __weak void rockchip_stimer_init(void) { diff --git a/arch/arm/mach-sc5xx/config.mk b/arch/arm/mach-sc5xx/config.mk index e7e4c9a1181..266d2e3a777 100644 --- a/arch/arm/mach-sc5xx/config.mk +++ b/arch/arm/mach-sc5xx/config.mk @@ -12,5 +12,7 @@ ifdef CONFIG_XPL_BUILD INPUTS-y += $(obj)/u-boot-spl.ldr endif +INPUTS-y += u-boot.ldr + LDR_FLAGS += --bcode=$(CONFIG_SC_BOOT_MODE) LDR_FLAGS += --use-vmas diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index fc921a4be26..5fb3240acc5 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -534,8 +534,7 @@ int board_late_init(void) env_set_hex("ramdisk_addr_r", addr) : 1; status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? env_set_hex("kernel_comp_addr_r", addr) : 1; - status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? - env_set_hex("kernel_comp_size", addr) : 1; + status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); status |= !lmb_alloc(SZ_4M, &addr) ? env_set_hex("scriptaddr", addr) : 1; status |= !lmb_alloc(SZ_4M, &addr) ? @@ -544,9 +543,13 @@ int board_late_init(void) if (IS_ENABLED(CONFIG_FASTBOOT)) { status |= !lmb_alloc(FASTBOOT_BUF_SIZE, &addr) ? env_set_hex("fastboot_addr_r", addr) : 1; - /* override loadaddr for memory rich soc */ - status |= !lmb_alloc(SZ_128M, &addr) ? - env_set_hex("loadaddr", addr) : 1; + /* + * Override loadaddr for memory rich soc since ${loadaddr} and + * ${kernel_addr_r} need to be different for the Android boot image + * flow. It's typically safe for ${loadaddr} to be the same address + * as the fastboot buffer. + */ + status |= env_set_hex("loadaddr", addr); } fdt_status |= !lmb_alloc(SZ_2M, &addr) ? diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 156cfbbcf3b..f2e959b5662 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -60,6 +60,18 @@ config TARGET_SOCFPGA_AGILEX select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 +config TARGET_SOCFPGA_AGILEX7M + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV2 + select NCORE_CACHE + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + config TARGET_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF @@ -149,6 +161,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX +config TARGET_SOCFPGA_AGILEX7M_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" + select TARGET_SOCFPGA_AGILEX7M + config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" select TARGET_SOCFPGA_AGILEX5 @@ -226,6 +242,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -248,6 +265,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK @@ -271,6 +289,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index c43fdee4a48..4e85bfb00d4 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -54,6 +54,7 @@ obj-y += timer_s10.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o +obj-y += altera-sysmgr.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 @@ -72,6 +73,22 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o +obj-y += wrap_handoff_soc64.o +obj-y += wrap_pll_config_soc64.o +obj-y += altera-sysmgr.o +endif + ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o @@ -115,6 +132,9 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 obj-y += spl_soc64.o obj-y += spl_agilex5.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +obj-y += spl_agilex7m.o +endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 5ac868a281b..074b9691af8 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016-2024 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ @@ -45,8 +46,10 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 @@ -75,6 +78,7 @@ #define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 #define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300 #define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000 #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 49f3fb2e705..f0431c081d8 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013-2024 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2025 Altera Corporation <www.altera.com> */ #ifndef _CLOCK_MANAGER_H_ @@ -28,7 +28,7 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #include <asm/arch/clock_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/clock_manager_s10.h> -#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #include <asm/arch/clock_manager_agilex.h> #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #include <asm/arch/clock_manager_agilex5.h> diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index 04203cceb8a..b8f2f73e283 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -18,7 +18,7 @@ #define SOC64_HANDOFF_MAGIC_FPGA 0x46504741 #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 -#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d +#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524D #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_MAGIC_PERI 0x50455249 #else @@ -30,9 +30,19 @@ #define SOC64_HANDOFF_SIZE 4096 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_BASE 0xFFE3F000 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x634) +/* DDR handoff */ +#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_DDR_LEN 5 +#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0) +#define SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK BIT(0) +#else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#endif #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_BASE 0x0007F000 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) @@ -88,6 +98,8 @@ #define SOC64_HANDOFF_IOCTL_LEN 96 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_FPGA_LEN 42 +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#define SOC64_HANDOFF_FPGA_LEN 44 #else #define SOC64_HANDOFF_FPGA_LEN 40 #endif diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h index 2099c51b682..1a461de4819 100644 --- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h +++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h @@ -398,10 +398,8 @@ int mbox_rcv_resp(u32 *resp_buf, u32 resp_buf_max_len); int mbox_rcv_resp_psci(u32 *resp_buf, u32 resp_buf_max_len); int mbox_init(void); -#ifdef CONFIG_CADENCE_QSPI int mbox_qspi_close(void); int mbox_qspi_open(void); -#endif int mbox_reset_cold(void); int mbox_hps_stage_notify(u32 execution_stage); diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index ab46415168f..0b80e952131 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -41,7 +41,8 @@ void socfpga_sdram_remap_zero(void); #endif #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) + defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX7M) int is_fpga_config_ready(void); #endif @@ -52,7 +53,7 @@ bool is_periph_program_force(void); void set_regular_boot(unsigned int status); void socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); -void socfpga_get_sys_mgr_addr(const char *compat); +void socfpga_get_sys_mgr_addr(void); int qspi_flash_software_reset(void); #endif /* _SOCFPGA_MISC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index c2ca0a50e35..f768a3a55cb 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -33,6 +33,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_ECC_INTMASK_CLR 0x98 #define SYSMGR_SOC64_ECC_INTMASK_SERR 0x9C #define SYSMGR_SOC64_ECC_INTMASK_DERR 0xA0 +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0 0x1F0 #define SYSMGR_SOC64_MPFE_CONFIG 0x228 #define SYSMGR_SOC64_BOOT_SCRATCH_POR0 0x258 #define SYSMGR_SOC64_BOOT_SCRATCH_POR1 0x25C @@ -47,6 +48,17 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_POR_0_DDR_PROGRESS_MASK BIT(0) #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_USER_MODE_MASK BIT(0) #define ALT_SYSMGR_SCRATCH_REG_POR_1_REVA_WORKAROUND_MASK BIT(1) + +/* + * Bits for SYSMGR_SOC64_USB3_MISC_CTRL_REG0 + * Bits[14:13] Port Overcurrent + * Bit[12] Reset Pulse Override + */ +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR GENMASK(14, 13) +#define SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR BIT(12) +#define SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR 1 +/* BIT 1 actually reflects PIPE power present signal */ +#define SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1 2 #else #define SYSMGR_SOC64_NAND_AXUSER 0x5c #define SYSMGR_SOC64_DMA_L3MASTER 0x74 @@ -141,6 +153,27 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +/* + * Bits for SYSMGR_SOC64_BOOT_SCRATCH_COLD8 + * Bit[31] reserved for FSBL to check DBE is triggered (set by SDM to "1") ? + * + * Bit[30] reserved for FSBL to update the DDR init progress + + * 1 - means in progress, 0 - haven't started / DDR is up running. + * + * Bit[19] store ATF CPU0 ON OFF value. + * + * Bit[18] reserved for SDM to configure ACF + * Bit[17:1] - Setting by Linux EDAC. + * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) + */ +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASK BIT(29) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASK GENMASK(28, 27) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK BIT(18) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT 18 + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 8926c2d1d9c..b39565f591d 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -12,15 +12,110 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ +#ifdef CONFIG_XPL_BUILD + /* Check for L2 reset magic word */ + ldr x4, =L2_RESET_DONE_REG + ldr x5, [x4] + ldr x1, =L2_RESET_DONE_STATUS + cmp x1, x5 + /* No L2 reset, skip warm reset */ + b.ne skipwarmreset + /* Put all slaves CPUs into WFI mode */ + branch_if_slave x0, put_cpu_in_wfi + /* L2 reset completed */ + str xzr, [x4] + /* Clear previous CPU release address */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + /* Master CPU (CPU0) request for warm reset */ + mrs x1, rmr_el3 + orr x1, x1, #0x02 + msr rmr_el3, x1 + isb + dsb sy +put_cpu_in_wfi: + wfi + b put_cpu_in_wfi +skipwarmreset: +#endif + #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) + + /* + * In ATF flow, need to clear the old CPU address when cold reset + * being triggered, but shouldn't clear CPU address if it is reset + * by CPU-ON, so that the core can correctly jump to ATF code after + * reset by CPU-ON. CPU-ON trigger the reset via mpumodrst. + * + * Hardware will set 1 to core*_irq in mpurststat register in + * reset manager if the core is reset by mpumodrst. + * + * The following code will check the mpurststat to identify if the + * core is reset by mpumodrst, and it will skip CPU address clearing + * if the core is reset by mpumodrst. At last, the code need to clear + * the core*_irq by set it to 1. So that it can reflect the correct + * and latest status in next reset. + */ + + /* Check if it is a master core off/on from kernel using boot scratch + * cold register 8 bit 19. This bit is set by ATF. + */ + ldr x4, =BOOT_SCRATCH_COLD8 + ldr x5, [x4] + and x6, x5, #0x80000 + cbnz x6, wait_for_atf_master + + /* Retrieve mpurststat register in reset manager */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + ldr w5, [x4, #0x04] + + /* Set mask based on current core id */ + mrs x0, mpidr_el1 + and x1, x0, #0xF + ldr x2, =0x00000100 + lsl x2, x2, x1 + + /* Skip if core*_irq register is set */ + and x6, x5, x2 + cbnz x6, skip_clear_cpu_address + + /* + * Reach here means core*_irq is 0, means the core is + * reset by cold, warm or watchdog reset. + * Clear previous CPU release address + */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + b skip_clear_core_irq + +skip_clear_cpu_address: + /* Clear core*_irq register by writing 1 */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + str w2, [x4, #0x04] + +skip_clear_core_irq: + /* Master CPU (CPU0) does not need to wait for atf */ + branch_if_master x0, master_cpu + wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] cbz x5, slave_wait_atf br x5 + slave_wait_atf: branch_if_slave x0, wait_for_atf + +wait_for_atf_master: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, master_wait_atf + br x5 +master_wait_atf: + branch_if_master x0, wait_for_atf_master + +master_cpu: #else branch_if_slave x0, 1f #endif diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 97e01140513..76747c2196a 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -11,6 +11,7 @@ #include <hang.h> #include <watchdog.h> #include <fdtdec.h> +#include <dm/ofnode.h> #include <linux/libfdt.h> #include <linux/printk.h> #include <miiphy.h> @@ -222,8 +223,8 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD(bridge, 3, 1, do_bridge, "SoCFPGA HPS FPGA bridge control", - "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n" + "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n" "" ); @@ -260,13 +261,12 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)) - ret = socfpga_get_base_addr("intel,agilex-clkmgr", - &socfpga_clkmgr_base); else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) ret = socfpga_get_base_addr("intel,n5x-clkmgr", &socfpga_clkmgr_base); - else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && + !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); @@ -274,17 +274,24 @@ void socfpga_get_managers_addr(void) hang(); } -void socfpga_get_sys_mgr_addr(const char *compat) +void socfpga_get_sys_mgr_addr(void) { int ret; - struct udevice *sysmgr_dev; + struct udevice *dev; + + ofnode node = ofnode_get_aliases_node("sysmgr"); + + if (!ofnode_valid(node)) { + printf("'sysmgr' alias not found in device tree\n"); + hang(); + } - ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev); + ret = uclass_get_device_by_ofnode(UCLASS_NOP, node, &dev); if (ret) { printf("Altera system manager init failed: %d\n", ret); hang(); } else { - socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev); + socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(dev); } } diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index c442af02888..7e0f3875b7c 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -214,10 +214,7 @@ int qspi_flash_software_reset(void) /* Get the flash info */ ret = spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, CONFIG_SF_DEFAULT_CS, - CONFIG_SF_DEFAULT_SPEED, - CONFIG_SF_DEFAULT_MODE, &flash); - if (ret) { debug("Failed to initialize SPI flash at "); debug("%u:%u (error %d)\n", CONFIG_SF_DEFAULT_BUS, diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c index b212a94b321..a531030f5be 100644 --- a/arch/arm/mach-socfpga/smc_api.c +++ b/arch/arm/mach-socfpga/smc_api.c @@ -57,6 +57,7 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len, resp, ARRAY_SIZE(resp)); if (ret == INTEL_SIP_SMC_STATUS_OK && resp_buf && resp_buf_len) { + invalidate_dcache_range((uintptr_t)resp_buf, (uintptr_t)(resp_buf + *resp_buf_len)); if (!resp[0]) *resp_buf_len = resp[1]; } diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 91c27a5543d..48f258a37b4 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2025 Altera Corporation <www.altera.com> * */ @@ -18,20 +19,42 @@ #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> #include <asm/arch/system_manager.h> -#include <watchdog.h> +#include <wdt.h> #include <dm/uclass.h> DECLARE_GLOBAL_DATA_PTR; +u32 reset_flag(u32 flag) +{ + /* Check rstmgr.stat for warm reset status */ + u32 status = readl(SOCFPGA_RSTMGR_ADDRESS); + + /* Check whether any L4 watchdogs or SDM had triggered warm reset */ + u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK; + + if (status & warm_reset_mask) + return 0; + + return 1; +} + void board_init_f(ulong dummy) { int ret; struct udevice *dev; + /* Enable Async */ + asm volatile("msr daifclr, #4"); + +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION) + spl_save_restore_data(); +#endif + ret = spl_early_init(); if (ret) hang(); + socfpga_get_sys_mgr_addr(); socfpga_get_managers_addr(); /* Ensure watchdog is paused when debugging is happening */ @@ -62,11 +85,30 @@ void board_init_f(ulong dummy) hang(); } + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + preloader_console_init(); print_reset_info(); cm_print_clock_quick_summary(); - firewall_setup(); + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev); + if (ret) { + printf("System manager firewall configuration failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev); + if (ret) { + printf("L3 interconnect firewall configuration failed: %d\n", ret); + hang(); + } + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); if (ret) { debug("CCU init failed: %d\n", ret); diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 2a13301802d..1be347360f5 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; -u32 reset_flag(void) +u32 reset_flag(u32 flag) { /* Check rstmgr.stat for warm reset status */ u32 status = readl(SOCFPGA_RSTMGR_ADDRESS); @@ -51,7 +51,7 @@ void board_init_f(ulong dummy) if (ret) hang(); - socfpga_get_sys_mgr_addr("sysmgr@10d12000"); + socfpga_get_sys_mgr_addr(); socfpga_get_managers_addr(); sysmgr_pinmux_init(); diff --git a/arch/arm/mach-socfpga/spl_agilex7m.c b/arch/arm/mach-socfpga/spl_agilex7m.c new file mode 100644 index 00000000000..90065ccee6f --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex7m.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <spl.h> +#include <wdt.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong dummy) +{ + int ret; + struct udevice *dev; + + /* Enable Async */ + asm volatile("msr daifclr, #4"); + +#ifdef CONFIG_XPL_BUILD + spl_save_restore_data(); +#endif + + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_sys_mgr_addr(); + socfpga_get_managers_addr(); + + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG); + + /* ensure all processors are not released prior Linux boot */ + writeq(0, CPU_RELEASE_ADDR); + + timer_init(); + + mbox_init(); + + mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL); + + sysmgr_pinmux_init(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + hang(); + } + + /* + * Enable watchdog as early as possible before initializing other + * component. Watchdog need to be enabled after clock driver because + * it will retrieve the clock frequency from clock driver. + */ + if (CONFIG_IS_ENABLED(WDT)) + initr_watchdog(); + + preloader_console_init(); + print_reset_info(); + cm_print_clock_quick_summary(); + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev); + if (ret) { + printf("System manager firewall configuration failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev); + if (ret) { + printf("L3 interconnect firewall configuration failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_CACHE, 0, &dev); + if (ret) { + debug("CCU init failed: %d\n", ret); + hang(); + } + + if (IS_ENABLED(CONFIG_SPL_ALTERA_SDRAM)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } + } + + if (IS_ENABLED(CONFIG_CADENCE_QSPI)) + mbox_qspi_open(); +} diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index 651d9fc9cb8..fa7b1506ce6 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -130,7 +130,7 @@ u32 spl_boot_mode(const u32 boot_device) #endif /* board specific function prior loading SSBL / U-Boot */ -void spl_perform_fixups(struct spl_image_info *spl_image) +void spl_perform_arch_fixups(struct spl_image_info *spl_image) { int ret; struct udevice *dev; diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 4b42158be9d..913f93c8f94 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -8,9 +8,29 @@ #include <asm/arch/system_manager.h> #include <asm/global_data.h> #include <asm/io.h> +#include <linux/bitfield.h> DECLARE_GLOBAL_DATA_PTR; +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +/* + * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse + * generation and setting PORT_OVERCURRENT bit so that until we turn on the + * Vbus, it doesn't give false information about Vbus to the HPS controller. + */ +static void sysmgr_config_usb3(void) +{ + u32 reg_val = 0; + + reg_val = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0); + reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR, + SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR); + reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR, + SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1); + writel(reg_val, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0); +} +#endif + /* * Configure all the pin muxes */ @@ -18,6 +38,10 @@ void sysmgr_pinmux_init(void) { populate_sysmgr_pinmux(); populate_sysmgr_fpgaintf_module(); + +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + sysmgr_config_usb3(); +#endif } /* diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 09b7d5123ae..ba4694f2964 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -40,16 +40,19 @@ choice config STM32MP13X bool "Support STMicroelectronics STM32MP13x Soc" select ARCH_EARLY_INIT_R - select ARM_SMCCC + select ARM_SMCCC if TFABOOT + select ARCH_SUPPORT_PSCI if !TFABOOT + select BINMAN if !TFABOOT select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT - select OF_BOARD + select OF_BOARD if TFABOOT select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC select STM32_RESET select STM32_SERIAL + select SUPPORT_SPL if !TFABOOT select SYS_ARCH_TIMER imply CMD_NVEDIT_INFO imply OF_UPSTREAM @@ -81,6 +84,32 @@ config STM32MP15X STMicroelectronics MPU with core ARMv7 dual core A7 for STM32MP157/3, monocore for STM32MP151 +config STM32MP23X + bool "Support STMicroelectronics STM32MP23x Soc" + select ARM64 + select CLK_STM32MP25 + select OF_BOARD + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select STM32MP_TAMP_NVMEM + select SYS_ARCH_TIMER + select TFABOOT + imply CLK_SCMI + imply CMD_NVEDIT_INFO + imply DM_REGULATOR + imply DM_REGULATOR_SCMI + imply OF_UPSTREAM + imply OPTEE + imply RESET_SCMI + imply SYSRESET_PSCI + imply TEE + imply VERSION_VARIABLE + help + Support of STMicroelectronics SOC STM32MP23x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core + config STM32MP25X bool "Support STMicroelectronics STM32MP25x Soc" select ARM64 @@ -165,6 +194,7 @@ config MFD_STM32_TIMERS source "arch/arm/mach-stm32mp/Kconfig.13x" source "arch/arm/mach-stm32mp/Kconfig.15x" +source "arch/arm/mach-stm32mp/Kconfig.23x" source "arch/arm/mach-stm32mp/Kconfig.25x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" diff --git a/arch/arm/mach-stm32mp/Kconfig.13x b/arch/arm/mach-stm32mp/Kconfig.13x index bc8b3f8cf77..6a45c4e4132 100644 --- a/arch/arm/mach-stm32mp/Kconfig.13x +++ b/arch/arm/mach-stm32mp/Kconfig.13x @@ -20,10 +20,11 @@ config TARGET_ST_STM32MP13X endchoice config TEXT_BASE - default 0xC0000000 + default 0xC0000000 if TFABOOT + default 0xC0100000 if !TFABOOT config PRE_CON_BUF_ADDR - default 0xC0800000 + default 0xC2FFF000 config PRE_CON_BUF_SZ default 4096 diff --git a/arch/arm/mach-stm32mp/Kconfig.23x b/arch/arm/mach-stm32mp/Kconfig.23x new file mode 100644 index 00000000000..2859210c77c --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.23x @@ -0,0 +1,37 @@ +if STM32MP23X + +choice + prompt "STM32MP23x board select" + optional + +config TARGET_ST_STM32MP23X + bool "STMicroelectronics STM32MP23x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + help + target the STMicroelectronics board with SOC STM32MP23x + managed by board/st/stm32mp2 + The difference between board are managed with devicetree + +endchoice + +config TEXT_BASE + default 0x84000000 + +config PRE_CON_BUF_ADDR + default 0x84800000 + +config PRE_CON_BUF_SZ + default 4096 + +if DEBUG_UART + +# debug on USART2 by default +config DEBUG_UART_BASE + default 0x400e0000 + +endif + +source "board/st/stm32mp2/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index ecd49fe668d..eeb5fdd7b45 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -10,6 +10,7 @@ obj-y += soc.o obj-$(CONFIG_STM32MP15X) += stm32mp1/ obj-$(CONFIG_STM32MP13X) += stm32mp1/ +obj-$(CONFIG_STM32MP23X) += stm32mp2/ obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_MFD_STM32_TIMERS) += timers.o diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c index 6bfa67859e1..f5def4cd2dc 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32key.c +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -171,7 +171,7 @@ static u8 get_key_nb(void) if (IS_ENABLED(CONFIG_STM32MP15X)) return ARRAY_SIZE(stm32mp15_list); - if (IS_ENABLED(CONFIG_STM32MP25X)) + if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)) return ARRAY_SIZE(stm32mp25_list); } @@ -183,7 +183,7 @@ static const struct stm32key *get_key(u8 index) if (IS_ENABLED(CONFIG_STM32MP15X)) return &stm32mp15_list[index]; - if (IS_ENABLED(CONFIG_STM32MP25X)) + if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)) return &stm32mp25_list[index]; } @@ -195,7 +195,7 @@ static u8 get_otp_close_state_nb(void) if (IS_ENABLED(CONFIG_STM32MP15X)) return ARRAY_SIZE(stm32mp15_close_state_otp); - if (IS_ENABLED(CONFIG_STM32MP25X)) + if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)) return ARRAY_SIZE(stm32mp25_close_state_otp); } @@ -207,7 +207,7 @@ static const struct otp_close *get_otp_close_state(u8 index) if (IS_ENABLED(CONFIG_STM32MP15X)) return &stm32mp15_close_state_otp[index]; - if (IS_ENABLED(CONFIG_STM32MP25X)) + if (IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X)) return &stm32mp25_close_state_otp[index]; } diff --git a/arch/arm/mach-stm32mp/include/mach/rif.h b/arch/arm/mach-stm32mp/include/mach/rif.h index 10b22108120..4f51313980d 100644 --- a/arch/arm/mach-stm32mp/include/mach/rif.h +++ b/arch/arm/mach-stm32mp/include/mach/rif.h @@ -8,19 +8,53 @@ #include <linux/types.h> +#if IS_ENABLED(CONFIG_STM32MP21X) || IS_ENABLED(CONFIG_STM32MP23X) || IS_ENABLED(CONFIG_STM32MP25X) /** - * stm32_rifsc_check_access - Check RIF accesses for given device node + * stm32_rifsc_grant_access_by_id - Grant RIFSC access for a given peripheral using its ID * - * @device_node Node of the device for which the accesses are checked + * @device_node Node of the peripheral + * @id ID of the peripheral of which access should be granted */ -int stm32_rifsc_check_access(ofnode device_node); +int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id); /** - * stm32_rifsc_check_access - Check RIF accesses for given id + * stm32_rifsc_grant_access_by_id - Grant RIFSC access for a given peripheral using its node * - * @device_node Node of the device to get a reference on RIFSC - * @id ID of the resource to check + * @id node of the peripheral of which access should be granted */ -int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id); +int stm32_rifsc_grant_access(ofnode device_node); +/** + * stm32_rifsc_release_access_by_id - Release RIFSC access for a given peripheral using its ID + * + * @device_node Node of the peripheral + * @id ID of the peripheral of which access should be released + */ +void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id); + +/** + * stm32_rifsc_release_access_by_id - Release RIFSC access for a given peripheral using its node + * + * @id node of the peripheral of which access should be released + */ +void stm32_rifsc_release_access(ofnode device_node); +#else +static inline int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id) +{ + return -EACCES; +} + +static inline int stm32_rifsc_grant_access(ofnode device_node) +{ + return -EACCES; +} + +static inline void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id) +{ +} + +static inline void stm32_rifsc_release_access(ofnode device_node) +{ +} +#endif #endif /* MACH_RIF_H*/ diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index dfba57e7dc4..2bf50c755cb 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -156,6 +156,8 @@ enum forced_boot_mode { #endif #ifdef CONFIG_STM32MP13X +#define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4) +#define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5) #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(31) #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif @@ -163,7 +165,7 @@ enum forced_boot_mode { #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ -#ifdef CONFIG_STM32MP25X +#if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) #define STM32_USART2_BASE 0x400E0000 #define STM32_USART3_BASE 0x400F0000 #define STM32_UART4_BASE 0x40100000 @@ -188,7 +190,7 @@ enum forced_boot_mode { /* TAMP registers zone 3 RIF 1 (RW) at 96*/ #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) -#endif /* STM32MP25X */ +#endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */ /* offset used for BSEC driver: misc_read and misc_write */ #define STM32_BSEC_SHADOW_OFFSET 0x0 @@ -212,14 +214,14 @@ enum forced_boot_mode { #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 60 #endif -#ifdef CONFIG_STM32MP25X +#if defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) #define BSEC_OTP_SERIAL 5 #define BSEC_OTP_RPN 9 #define BSEC_OTP_REVID 102 #define BSEC_OTP_PKG 122 #define BSEC_OTP_BOARD 246 #define BSEC_OTP_MAC 247 -#endif +#endif /* defined(CONFIG_STM32MP23X) || defined(CONFIG_STM32MP25X) */ #ifndef __ASSEMBLY__ #include <asm/types.h> diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 19073668497..2a4837184fc 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -30,29 +30,44 @@ #define CPU_STM32MP131Fxx 0x05010EC8 #define CPU_STM32MP131Dxx 0x05010EC9 +/* ID for STM32MP23x = Device Part Number (RPN) (bit31:0) */ +#define CPU_STM32MP235Cxx 0x00082182 +#define CPU_STM32MP233Cxx 0x000B318E +#define CPU_STM32MP231Cxx 0x000B31EF +#define CPU_STM32MP235Axx 0x40082F82 +#define CPU_STM32MP233Axx 0x400B3F8E +#define CPU_STM32MP231Axx 0x400B3FEF +#define CPU_STM32MP235Fxx 0x80082182 +#define CPU_STM32MP233Fxx 0x800B318E +#define CPU_STM32MP231Fxx 0x800B31EF +#define CPU_STM32MP235Dxx 0xC0082F82 +#define CPU_STM32MP233Dxx 0xC00B3F8E +#define CPU_STM32MP231Dxx 0xC00B3FEF + /* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ -#define CPU_STM32MP257Cxx 0x00002000 -#define CPU_STM32MP255Cxx 0x00082000 -#define CPU_STM32MP253Cxx 0x000B2004 -#define CPU_STM32MP251Cxx 0x000B3065 -#define CPU_STM32MP257Axx 0x40002E00 -#define CPU_STM32MP255Axx 0x40082E00 -#define CPU_STM32MP253Axx 0x400B2E04 -#define CPU_STM32MP251Axx 0x400B3E65 -#define CPU_STM32MP257Fxx 0x80002000 -#define CPU_STM32MP255Fxx 0x80082000 -#define CPU_STM32MP253Fxx 0x800B2004 -#define CPU_STM32MP251Fxx 0x800B3065 -#define CPU_STM32MP257Dxx 0xC0002E00 -#define CPU_STM32MP255Dxx 0xC0082E00 -#define CPU_STM32MP253Dxx 0xC00B2E04 -#define CPU_STM32MP251Dxx 0xC00B3E65 +#define CPU_STM32MP257Cxx 0x00002000 +#define CPU_STM32MP255Cxx 0x00082000 +#define CPU_STM32MP253Cxx 0x000B2004 +#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP257Axx 0x40002E00 +#define CPU_STM32MP255Axx 0x40082E00 +#define CPU_STM32MP253Axx 0x400B2E04 +#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP257Fxx 0x80002000 +#define CPU_STM32MP255Fxx 0x80082000 +#define CPU_STM32MP253Fxx 0x800B2004 +#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP257Dxx 0xC0002E00 +#define CPU_STM32MP255Dxx 0xC0082E00 +#define CPU_STM32MP253Dxx 0xC00B2E04 +#define CPU_STM32MP251Dxx 0xC00B3E65 /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 #define CPU_DEV_STM32MP13 0x501 +#define CPU_DEV_STM32MP23 0x505 #define CPU_DEV_STM32MP25 0x505 /* return CPU_DEV constants */ @@ -87,6 +102,12 @@ u32 get_cpu_package(void); #define STM32MP15_PKG_AD_TFBGA257 1 #define STM32MP15_PKG_UNKNOWN 0 +/* package used for STM32MP23x */ +#define STM32MP23_PKG_CUSTOM 0 +#define STM32MP23_PKG_AL_VFBGA361 1 +#define STM32MP23_PKG_AK_VFBGA424 3 +#define STM32MP23_PKG_AJ_TFBGA361 7 + /* package used for STM32MP25x */ #define STM32MP25_PKG_CUSTOM 0 #define STM32MP25_PKG_AL_VFBGA361 1 diff --git a/arch/arm/mach-stm32mp/include/mach/timers.h b/arch/arm/mach-stm32mp/include/mach/timers.h index a84465bb28e..8209dd84911 100644 --- a/arch/arm/mach-stm32mp/include/mach/timers.h +++ b/arch/arm/mach-stm32mp/include/mach/timers.h @@ -29,6 +29,10 @@ #define TIM_DMAR 0x4C /* DMA register for transfer */ #define TIM_TISEL 0x68 /* Input Selection */ +#define TIM_HWCFGR2 0x3EC /* hardware configuration 2 Reg (MP25) */ +#define TIM_HWCFGR1 0x3F0 /* hardware configuration 1 Reg (MP25) */ +#define TIM_IPIDR 0x3F8 /* IP identification Reg (MP25) */ + #define TIM_CR1_CEN BIT(0) /* Counter Enable */ #define TIM_CR1_ARPE BIT(7) #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) @@ -40,11 +44,16 @@ #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ #define TIM_BDTR_MOE BIT(15) /* Main Output Enable */ #define TIM_EGR_UG BIT(0) /* Update Generation */ +#define TIM_HWCFGR2_CNT_WIDTH GENMASK(15, 8) /* Counter width */ +#define TIM_HWCFGR1_NB_OF_DT GENMASK(7, 4) /* Complementary outputs & dead-time generators */ #define MAX_TIM_PSC 0xFFFF +#define STM32MP25_TIM_IPIDR 0x00120002 + struct stm32_timers_plat { void __iomem *base; + u32 ipidr; }; struct stm32_timers_priv { diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 8c09d91de05..e0c6f8ba937 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -28,7 +28,9 @@ * early TLB into the .data section so that it not get cleared * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) */ +#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X)) u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); +#endif u32 get_bootmode(void) { @@ -95,18 +97,19 @@ void dram_bank_mmu_setup(int bank) */ static void early_enable_caches(void) { +#if (!IS_ENABLED(CONFIG_XPL_BUILD) || !IS_ENABLED(CONFIG_STM32MP13X)) /* I-cache is already enabled in start.S: cpu_init_cp15 */ - if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) return; #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - gd->arch.tlb_size = PGTABLE_SIZE; - gd->arch.tlb_addr = (unsigned long)&early_tlb; + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; #endif /* enable MMU (default configuration) */ dcache_enable(); +#endif } /* diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c index 9c4fafbf478..e63bdaaf42f 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/spl.c +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -220,10 +220,11 @@ void board_init_f(ulong dummy) * activate cache on DDR only when DDR is fully initialized * to avoid speculative access and issue in get_ram_size() */ - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !IS_ENABLED(CONFIG_STM32MP13X)) { mmu_set_region_dcache_behaviour(STM32_DDR_BASE, CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); + } } void spl_board_prepare_for_boot(void) diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c index 4a811065fc3..79b2f2d0bba 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c @@ -6,11 +6,59 @@ #define LOG_CATEGORY LOGC_ARCH #include <config.h> +#include <cpu_func.h> #include <log.h> #include <syscon.h> #include <asm/io.h> +#include <asm/system.h> +#include <asm/arch/bsec.h> #include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> +#include <dm/device.h> +#include <dm/uclass.h> +#include <linux/bitfield.h> +#include <malloc.h> + +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_BDCR (STM32_RCC_BASE + 0x400) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x468) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x740) +#define RCC_MP_AHB6ENSETR (STM32_RCC_BASE + 0x780) + +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) + +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* DBGMCU register */ +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2c) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +/* Security register */ +#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) +#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) + +#define TZC_ACTION (STM32_TZC_BASE + 0x004) +#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) +#define TZC_REGION_BASE(n) (STM32_TZC_BASE + 0x100 + (0x20 * (n))) +#define TZC_REGION_TOP(n) (STM32_TZC_BASE + 0x108 + (0x20 * (n))) +#define TZC_REGION_ATTRIBUTE(n) (STM32_TZC_BASE + 0x110 + (0x20 * (n))) +#define TZC_REGION_ID_ACCESS(n) (STM32_TZC_BASE + 0x114 + (0x20 * (n))) + +#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) + +#define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_CR1_DBP BIT(8) + +/* boot interface from Bootrom + * - boot instance = bit 31:16 + * - boot device = bit 15:0 + */ +#define BOOTROM_MODE_MASK GENMASK(15, 0) +#define BOOTROM_MODE_SHIFT 0 +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_SHIFT 16 /* SYSCFG register */ #define SYSCFG_IDC_OFFSET 0x380 @@ -23,6 +71,162 @@ #define RPN_SHIFT 0 #define RPN_MASK GENMASK(11, 0) +static void security_init(void) +{ + /* Disable the backup domain write protection */ + /* the protection is enable at each reset by hardware */ + /* And must be disable by software */ + setbits_le32(PWR_CR1, PWR_CR1_DBP); + + while (!(readl(PWR_CR1) & PWR_CR1_DBP)) + ; + + /* If RTC clock isn't enable so this is a cold boot then we need + * to reset the backup domain + */ + if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { + setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) + ; + clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + } + + /* allow non secure access in Write/Read for all peripheral */ + writel(0, ETZPC_DECPROT0); + + /* Open SYSRAM for no secure access */ + writel(0x0, ETZPC_TZMA1_SIZE); + + /* enable MCE clock */ + writel(BIT(1), RCC_MP_AHB6ENSETR); + + /* enable TZC clock */ + writel(BIT(11), RCC_MP_APB5ENSETR); + + /* Disable Filter 0 */ + writel(0, TZC_GATE_KEEPER); + + /* Region 0 set to no access by default */ + /* bit 0 / 16 => nsaid0 read/write Enable + * bit 1 / 17 => nsaid1 read/write Enable + * ... + * bit 15 / 31 => nsaid15 read/write Enable + */ + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(0)); + + /* bit 30 / 31 => Secure Global Enable : write/read */ + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(0)); + + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(1)); + writel(0xC0000000, TZC_REGION_BASE(1)); + writel(0xDDFFFFFF, TZC_REGION_TOP(1)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(1)); + + writel(0x00000000, TZC_REGION_ID_ACCESS(2)); + writel(0xDE000000, TZC_REGION_BASE(2)); + writel(0xDFFFFFFF, TZC_REGION_TOP(2)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(2)); + + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS(3)); + writel(0x00000000, TZC_REGION_BASE(3)); + writel(0xBFFFFFFF, TZC_REGION_TOP(3)); + writel(BIT(0) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE(3)); + + /* Set Action */ + writel(BIT(0), TZC_ACTION); + + /* Enable Filter 0 */ + writel(BIT(0), TZC_GATE_KEEPER); + + /* RCC trust zone deactivated */ + writel(0x0, RCC_TZCR); + + /* TAMP: deactivate the internal tamper + * Bit 23 ITAMP8E: monotonic counter overflow + * Bit 20 ITAMP5E: RTC calendar overflow + * Bit 19 ITAMP4E: HSE monitoring + * Bit 18 ITAMP3E: LSE monitoring + * Bit 16 ITAMP1E: RTC power domain supply monitoring + */ + writel(0x0, TAMP_CR1); +} + +/* + * Debug init + */ +void dbgmcu_init(void) +{ + /* + * Freeze IWDG2 if Cortex-A7 is in debug mode + * done in TF-A for TRUSTED boot and + * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE + */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + u8 *tlb; + int ret; + + dbgmcu_init(); + + /* force probe of BSEC driver to shadow the upper OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret) + log_warning("BSEC probe failed: %d\n", ret); + + /* Enable Dcache here, now that DRAM is available */ + if (IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_STM32MP13X)) { + tlb = memalign(0x4000, PGTABLE_SIZE); + if (!tlb) + return; + + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)tlb; + dcache_enable(); + } +} + +/* get bootmode from ROM code boot context: saved in TAMP register */ +static void update_bootmode(void) +{ + u32 boot_mode; + u32 bootrom_itf = readl(get_stm32mp_rom_api_table()); + u32 bootrom_device, bootrom_instance; + + /* enable TAMP clock = RTCAPBEN */ + writel(BIT(8), RCC_MP_APB5ENSETR); + + /* read bootrom context */ + bootrom_device = + (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; + bootrom_instance = + (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; + boot_mode = + ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | + ((bootrom_instance << BOOT_INSTANCE_SHIFT) & + BOOT_INSTANCE_MASK); + + /* save the boot mode in TAMP backup register */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); +} + +/* weak function: STM32MP15x mach init for boot without TFA */ +void stm32mp_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_XPL_BUILD)) { + security_init(); + update_bootmode(); + } +} + static u32 read_idc(void) { void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile index 5dbf75daa76..27fbf3ae728 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/Makefile +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -7,4 +7,5 @@ obj-y += cpu.o obj-y += arm64-mmu.o obj-y += rifsc.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_STM32MP23X) += stm32mp23x.o obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c index c3b87d7f981..e081dc605b8 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -92,13 +92,21 @@ uintptr_t get_stm32mp_bl2_dtb(void) } /* - * Save the FDT address provided by TF-A in r2 at boot time + * Save the FDT address provided by TF-A at boot time * This function is called from start.S */ -void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, - unsigned long r3) +void save_boot_params(unsigned long x0, unsigned long x1, unsigned long x2, + unsigned long x3) { - nt_fw_dtb = r2; + /* use the ARM64 kernel booting register settings: + * x0 = physical address of device tree blob (dtb) in system RAM. + * so kernel can replace U-Boot in FIP wihtout BL31 modification + * else falback to x2 used in previous TF-A version + */ + if (x0) + nt_fw_dtb = x0; + else + nt_fw_dtb = x2; save_boot_params_ret(); } diff --git a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c index 50dececf77b..f8f67af4449 100644 --- a/arch/arm/mach-stm32mp/stm32mp2/rifsc.c +++ b/arch/arm/mach-stm32mp/stm32mp2/rifsc.c @@ -61,42 +61,41 @@ struct stm32_rifsc_child_plat { u32 domain_id; }; -static bool stm32_rif_is_semaphore_available(void *base, u32 id) +static bool stm32_rif_is_semaphore_available(void *addr) { - void *addr = base + RIFSC_RISC_PER0_SEMCR(id); - return !(readl(addr) & SEMCR_MUTEX); } -static int stm32_rif_acquire_semaphore(void *base, u32 id) +static int stm32_rifsc_acquire_semaphore(void *base, u32 id) { void *addr = base + RIFSC_RISC_PER0_SEMCR(id); /* Check that the semaphore is available */ - if (!stm32_rif_is_semaphore_available(base, id)) + if (!stm32_rif_is_semaphore_available(addr) && + FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1)) return -EACCES; setbits_le32(addr, SEMCR_MUTEX); /* Check that CID1 has the semaphore */ - if (stm32_rif_is_semaphore_available(base, id) || + if (stm32_rif_is_semaphore_available(addr) || FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) != RIF_CID1)) return -EACCES; return 0; } -static int stm32_rif_release_semaphore(void *base, u32 id) +static int stm32_rifsc_release_semaphore(void *base, u32 id) { void *addr = base + RIFSC_RISC_PER0_SEMCR(id); - if (stm32_rif_is_semaphore_available(base, id)) + if (stm32_rif_is_semaphore_available(addr)) return 0; clrbits_le32(addr, SEMCR_MUTEX); /* Ok if another compartment takes the semaphore before the check */ - if (!stm32_rif_is_semaphore_available(base, id) && + if (!stm32_rif_is_semaphore_available(addr) && FIELD_GET(RIFSC_RISC_SCID_MASK, (readl(addr)) == RIF_CID1)) return -EACCES; @@ -105,11 +104,10 @@ static int stm32_rif_release_semaphore(void *base, u32 id) static int rifsc_parse_access_controller(ofnode node, struct ofnode_phandle_args *args) { - int ret; + int ret = ofnode_parse_phandle_with_args(node, "access-controllers", + "#access-controller-cells", 0, + 0, args); - ret = ofnode_parse_phandle_with_args(node, "access-controllers", - "#access-controller-cells", 0, - 0, args); if (ret) { log_debug("failed to parse access-controller (%d)\n", ret); return ret; @@ -170,8 +168,8 @@ static int rifsc_check_access(void *base, u32 id) log_debug("Not in semaphore whitelist for peripheral %d\n", id); return -EACCES; } - if (!stm32_rif_is_semaphore_available(base, id) && - !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & BIT(RIF_CID1))) { + if (!stm32_rif_is_semaphore_available(base + RIFSC_RISC_PER0_SEMCR(id)) && + !(FIELD_GET(RIFSC_RISC_SCID_MASK, sem_reg_value) & RIF_CID1)) { log_debug("Semaphore unavailable for peripheral %d\n", id); return -EACCES; } @@ -187,22 +185,44 @@ skip_cid_check: return 0; } -int stm32_rifsc_check_access_by_id(ofnode device_node, u32 id) +int stm32_rifsc_grant_access_by_id(ofnode device_node, u32 id) { struct ofnode_phandle_args args; + u32 cid_reg_value; + void *rifsc_base; int err; - if (id >= STM32MP25_RIFSC_ENTRIES) - return -EINVAL; - err = rifsc_parse_access_controller(device_node, &args); if (err) + panic("Failed to parse access-controllers property\n"); + + rifsc_base = (void *)ofnode_get_addr(args.node); + + err = rifsc_check_access(rifsc_base, id); + if (err) return err; - return rifsc_check_access((void *)ofnode_get_addr(args.node), id); + cid_reg_value = readl(rifsc_base + RIFSC_RISC_PER0_CIDCFGR(id)); + + /* + * If the peripheral is in semaphore mode, take the semaphore so that + * the CID1 has the ownership. + */ + if (cid_reg_value & CIDCFGR_SEMEN && + (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { + err = stm32_rifsc_acquire_semaphore(rifsc_base, id); + if (err) { + pr_err("Couldn't acquire RIF semaphore for peripheral %d (%d)\n", + id, err); + return err; + } + pr_debug("Acquiring RIF semaphore for peripheral %d\n", id); + } + + return 0; } -int stm32_rifsc_check_access(ofnode device_node) +int stm32_rifsc_grant_access(ofnode device_node) { struct ofnode_phandle_args args; int err; @@ -211,58 +231,60 @@ int stm32_rifsc_check_access(ofnode device_node) if (err) return err; - return rifsc_check_access((void *)ofnode_get_addr(args.node), args.args[0]); + return stm32_rifsc_grant_access_by_id(device_node, args.args[0]); + } -static int stm32_rifsc_child_pre_probe(struct udevice *dev) +void stm32_rifsc_release_access_by_id(ofnode device_node, u32 id) { - struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent); - struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + struct ofnode_phandle_args args; u32 cid_reg_value; + void *rifsc_base; int err; - u32 id = child_plat->domain_id; - cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id)); + err = rifsc_parse_access_controller(device_node, &args); + if (err) + panic("Failed to parse access-controllers property\n"); - /* - * If the peripheral is in semaphore mode, take the semaphore so that - * the CID1 has the ownership. - */ + rifsc_base = (void *)ofnode_get_addr(args.node); + + cid_reg_value = readl(rifsc_base + RIFSC_RISC_PER0_CIDCFGR(id)); + + /* If the peripheral is in semaphore mode, release it if we have the ownership */ if (cid_reg_value & CIDCFGR_SEMEN && (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { - err = stm32_rif_acquire_semaphore(plat->base, id); + err = stm32_rifsc_release_semaphore(rifsc_base, id); if (err) { - dev_err(dev, "Couldn't acquire RIF semaphore for peripheral %d (%d)\n", - id, err); - return err; + panic("Couldn't release RIF semaphore for peripheral %d (%d)\n", id, err); } - dev_dbg(dev, "Acquiring semaphore for peripheral %d\n", id); + pr_debug("Releasing RIF semaphore for peripheral %d\n", id); } +} - return 0; +void stm32_rifsc_release_access(ofnode device_node) +{ + struct ofnode_phandle_args args; + int err; + + err = rifsc_parse_access_controller(device_node, &args); + if (err) + panic("Failed to parse access-controllers property\n"); + + stm32_rifsc_release_access_by_id(device_node, args.args[0]); } -static int stm32_rifsc_child_post_remove(struct udevice *dev) +static int stm32_rifsc_child_pre_probe(struct udevice *dev) { - struct stm32_rifsc_plat *plat = dev_get_plat(dev->parent); struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); - u32 cid_reg_value; - int err; - u32 id = child_plat->domain_id; - cid_reg_value = readl(plat->base + RIFSC_RISC_PER0_CIDCFGR(id)); + return stm32_rifsc_grant_access_by_id(dev_ofnode(dev), child_plat->domain_id); +} - /* - * If the peripheral is in semaphore mode, release the semaphore so that - * there's no ownership. - */ - if (cid_reg_value & CIDCFGR_SEMEN && - (FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_reg_value) & BIT(RIF_CID1))) { - err = stm32_rif_release_semaphore(plat->base, id); - if (err) - dev_err(dev, "Couldn't release rif semaphore for peripheral %d (%d)\n", - id, err); - } +static int stm32_rifsc_child_post_remove(struct udevice *dev) +{ + struct stm32_rifsc_child_plat *child_plat = dev_get_parent_plat(dev); + + stm32_rifsc_release_access_by_id(dev_ofnode(dev), child_plat->domain_id); return 0; } diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c new file mode 100644 index 00000000000..022db60811a --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp23x.c @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* SYSCFG register */ +#define SYSCFG_DEVICEID_OFFSET 0x6400 +#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 + +/* Revision ID = OTP102[5:0] 6 bits : 3 for Major / 3 for Minor*/ +#define REVID_SHIFT 0 +#define REVID_MASK GENMASK(5, 0) + +/* Device Part Number (RPN) = OTP9 */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(31, 0) + +/* Package = bit 0:2 of OTP122 => STM32MP23_PKG defines + * - 000: Custom package + * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 0 +#define PKG_MASK GENMASK(2, 0) + +static u32 read_deviceid(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return get_otp(BSEC_OTP_REVID, REVID_SHIFT, REVID_MASK); +} + +/* Get Device Part Number (RPN) from OTP */ +u32 get_cpu_type(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +int get_eth_nb(void) +{ + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP235Fxx: + fallthrough; + case CPU_STM32MP235Dxx: + fallthrough; + case CPU_STM32MP235Cxx: + fallthrough; + case CPU_STM32MP235Axx: + fallthrough; + case CPU_STM32MP233Fxx: + fallthrough; + case CPU_STM32MP233Dxx: + fallthrough; + case CPU_STM32MP233Cxx: + fallthrough; + case CPU_STM32MP233Axx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP231Fxx: + fallthrough; + case CPU_STM32MP231Dxx: + fallthrough; + case CPU_STM32MP231Cxx: + fallthrough; + case CPU_STM32MP231Axx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP23) { + switch (get_cpu_type()) { + case CPU_STM32MP235Fxx: + cpu_s = "235F"; + break; + case CPU_STM32MP235Dxx: + cpu_s = "235D"; + break; + case CPU_STM32MP235Cxx: + cpu_s = "235C"; + break; + case CPU_STM32MP235Axx: + cpu_s = "235A"; + break; + case CPU_STM32MP233Fxx: + cpu_s = "233F"; + break; + case CPU_STM32MP233Dxx: + cpu_s = "233D"; + break; + case CPU_STM32MP233Cxx: + cpu_s = "233C"; + break; + case CPU_STM32MP233Axx: + cpu_s = "233A"; + break; + case CPU_STM32MP231Fxx: + cpu_s = "231F"; + break; + case CPU_STM32MP231Dxx: + cpu_s = "231D"; + break; + case CPU_STM32MP231Cxx: + cpu_s = "231C"; + break; + case CPU_STM32MP231Axx: + cpu_s = "231A"; + break; + default: + cpu_s = "23??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case OTP_REVID_1: + cpu_r = "A"; + break; + case OTP_REVID_2: + cpu_r = "B"; + break; + case OTP_REVID_2_1: + cpu_r = "Y"; + break; + case OTP_REVID_2_2: + cpu_r = "X"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP23_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP23_PKG_AL_VFBGA361: + package = "AL"; + break; + case STM32MP23_PKG_AK_VFBGA424: + package = "AK"; + break; + case STM32MP23_PKG_AJ_TFBGA361: + package = "AJ"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/timers.c b/arch/arm/mach-stm32mp/timers.c index a3207895f40..1940ba42f74 100644 --- a/arch/arm/mach-stm32mp/timers.c +++ b/arch/arm/mach-stm32mp/timers.c @@ -10,6 +10,7 @@ #include <asm/io.h> #include <asm/arch/timers.h> #include <dm/device_compat.h> +#include <linux/bitfield.h> static void stm32_timers_get_arr_size(struct udevice *dev) { @@ -29,6 +30,33 @@ static void stm32_timers_get_arr_size(struct udevice *dev) writel(arr, plat->base + TIM_ARR); } +static int stm32_timers_probe_hwcfgr(struct udevice *dev) +{ + struct stm32_timers_plat *plat = dev_get_plat(dev); + struct stm32_timers_priv *priv = dev_get_priv(dev); + u32 val; + + if (!plat->ipidr) { + /* fallback to legacy method for probing counter width */ + stm32_timers_get_arr_size(dev); + return 0; + } + + val = readl(plat->base + TIM_IPIDR); + /* Sanity check on IP identification register */ + if (val != plat->ipidr) { + dev_err(dev, "Unexpected identification: %u\n", val); + return -EINVAL; + } + + val = readl(plat->base + TIM_HWCFGR2); + /* Counter width in bits, max reload value is BIT(width) - 1 */ + priv->max_arr = BIT(FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val)) - 1; + dev_dbg(dev, "TIM width: %ld\n", FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val)); + + return 0; +} + static int stm32_timers_of_to_plat(struct udevice *dev) { struct stm32_timers_plat *plat = dev_get_plat(dev); @@ -38,6 +66,7 @@ static int stm32_timers_of_to_plat(struct udevice *dev) dev_err(dev, "can't get address\n"); return -ENOENT; } + plat->ipidr = (u32)dev_get_driver_data(dev); return 0; } @@ -60,13 +89,16 @@ static int stm32_timers_probe(struct udevice *dev) priv->rate = clk_get_rate(&clk); - stm32_timers_get_arr_size(dev); + ret = stm32_timers_probe_hwcfgr(dev); + if (ret) + clk_disable(&clk); return ret; } static const struct udevice_id stm32_timers_ids[] = { { .compatible = "st,stm32-timers" }, + { .compatible = "st,stm32mp25-timers", .data = STM32MP25_TIM_IPIDR }, {} }; diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 6a511c4fd39..e979ee4a2cc 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -475,6 +475,7 @@ config MACH_SUN8I_R528 select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL select DRAM_SUN20I_D1 + imply OF_UPSTREAM config MACH_SUN8I_V3S bool "sun8i (Allwinner V3/V3s/S3/S3L)" @@ -487,6 +488,7 @@ config MACH_SUN8I_V3S select SUNXI_DRAM_DW_16BIT select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + imply OF_UPSTREAM config MACH_SUN9I bool "sun9i (Allwinner A80)" @@ -497,6 +499,7 @@ config MACH_SUN9I select SUN6I_PRCM select SUNXI_GEN_SUN6I select SUPPORT_SPL + imply OF_UPSTREAM config MACH_SUN50I bool "sun50i (Allwinner A64)" @@ -718,9 +721,9 @@ config DRAM_CLK int "sunxi dram clock speed" default 792 if MACH_SUN9I default 648 if MACH_SUN8I_R40 - default 312 if MACH_SUN6I || MACH_SUN8I default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \ MACH_SUN8I_V3S + default 312 if MACH_SUN6I || MACH_SUN8I default 672 if MACH_SUN50I default 744 if MACH_SUN50I_H6 default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133 diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 579530f27e3..9c79b55abf3 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -47,6 +47,6 @@ obj-$(CONFIG_DRAM_SUN50I_H616) += dram_sun50i_h616.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN50I_H616) += dram_timings/ obj-$(CONFIG_DRAM_SUN50I_A133) += dram_sun50i_a133.o obj-$(CONFIG_DRAM_SUN50I_A133) += dram_timings/ -obj-$(CONFIG_MACH_SUN55I_A523) += dram_sun55i_a523.o +obj-$(CONFIG_MACH_SUN55I_A523) += dram_sun55i_a523.o dram_dw_helpers.o obj-$(CONFIG_DRAM_SUN55I_A523) += dram_timings/ endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index fb4837c2082..432b1c10f92 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -476,8 +476,8 @@ void board_init_f(ulong dummy) /* Enable non-secure access to some peripherals */ tzpc_init(); - clock_init(); timer_init(); + clock_init(); gpio_init(); spl_init(); diff --git a/arch/arm/mach-sunxi/dram_sun50i_a133.c b/arch/arm/mach-sunxi/dram_sun50i_a133.c index 3a231141168..1496f99624d 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_a133.c +++ b/arch/arm/mach-sunxi/dram_sun50i_a133.c @@ -416,7 +416,7 @@ static void mctl_com_init(const struct dram_para *para, static void mctl_drive_odt_config(const struct dram_para *para) { u32 val; - u64 base; + ulong base; u32 i; /* DX drive */ diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 877181016f3..3345c9b8e82 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -1078,18 +1078,18 @@ static bool mctl_phy_init(const struct dram_para *para, mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); break; case SUNXI_DRAM_TYPE_LPDDR3: - writel(mr0, &mctl_ctl->mrctrl1); - writel(0x800000f0, &mctl_ctl->mrctrl0); - mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - - writel(4, &mctl_ctl->mrctrl1); + /* MR0 is read-only */ + /* MR1: nWR=14, BL8 */ + writel(0x183, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); - writel(mr2, &mctl_ctl->mrctrl1); + /* MR2: no WR leveling, WL set A, use nWR>9, nRL=14/nWL=8 */ + writel(0x21c, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); + /* MR3: 34.3 Ohm pull-up/pull-down resistor */ writel(0x301, &mctl_ctl->mrctrl1); writel(0x800000f0, &mctl_ctl->mrctrl0); mctl_await_completion(&mctl_ctl->mrctrl0, BIT(31), 0); diff --git a/arch/arm/mach-sunxi/dram_sun55i_a523.c b/arch/arm/mach-sunxi/dram_sun55i_a523.c index 30bbeb40d0b..1ffb62863e2 100644 --- a/arch/arm/mach-sunxi/dram_sun55i_a523.c +++ b/arch/arm/mach-sunxi/dram_sun55i_a523.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/dram.h> +#include <asm/arch/dram_dw_helpers.h> #include <asm/arch/cpu.h> #include <asm/arch/prcm.h> #include <linux/bitops.h> @@ -1387,91 +1388,14 @@ static bool mctl_ctrl_init(const struct dram_para *para, return true; } -static bool mctl_core_init(const struct dram_para *para, - const struct dram_config *config) +bool mctl_core_init(const struct dram_para *para, + const struct dram_config *config) { mctl_sys_init(config->clk); return mctl_ctrl_init(para, config); } -static void mctl_auto_detect_rank_width(const struct dram_para *para, - struct dram_config *config) -{ - /* this is minimum size that it's supported */ - config->cols = 8; - config->rows = 13; - - /* - * Strategy here is to test most demanding combination first and least - * demanding last, otherwise HW might not be fully utilized. For - * example, half bus width and rank = 1 combination would also work - * on HW with full bus width and rank = 2, but only 1/4 RAM would be - * visible. - */ - - debug("testing 32-bit width, rank = 2\n"); - config->bus_full_width = 1; - config->ranks = 2; - if (mctl_core_init(para, config)) - return; - - debug("testing 32-bit width, rank = 1\n"); - config->bus_full_width = 1; - config->ranks = 1; - if (mctl_core_init(para, config)) - return; - - debug("testing 16-bit width, rank = 2\n"); - config->bus_full_width = 0; - config->ranks = 2; - if (mctl_core_init(para, config)) - return; - - debug("testing 16-bit width, rank = 1\n"); - config->bus_full_width = 0; - config->ranks = 1; - if (mctl_core_init(para, config)) - return; - - panic("This DRAM setup is currently not supported.\n"); -} - -static void mctl_auto_detect_dram_size(const struct dram_para *para, - struct dram_config *config) -{ - /* detect row address bits */ - config->cols = 8; - config->rows = 16; - mctl_core_init(para, config); - - for (config->rows = 13; config->rows < 16; config->rows++) { - /* 8 banks, 8 bit per byte and 16/32 bit width */ - if (mctl_mem_matches((1 << (config->rows + config->cols + - 4 + config->bus_full_width)))) - break; - } - - /* detect column address bits */ - config->cols = 11; - mctl_core_init(para, config); - - for (config->cols = 8; config->cols < 11; config->cols++) { - /* 8 bits per byte and 16/32 bit width */ - if (mctl_mem_matches(1 << (config->cols + 1 + - config->bus_full_width))) - break; - } -} - -static unsigned long long mctl_calc_size(const struct dram_config *config) -{ - u8 width = config->bus_full_width ? 4 : 2; - - /* 8 banks */ - return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; -} - static const struct dram_para para = { #ifdef CONFIG_SUNXI_DRAM_A523_DDR3 .type = SUNXI_DRAM_TYPE_DDR3, diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index c3c352eceb1..32cdfebfc01 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -17,7 +17,9 @@ config TEGRA_CLKRST config TEGRA_CRYPTO bool "Tegra AES128 crypto module" + select DM_AES select AES + select TEGRA_AES config TEGRA_GP_PADCTRL bool diff --git a/arch/arm/mach-tegra/ap.c b/arch/arm/mach-tegra/ap.c index f35bdba4d48..a7938ed7910 100644 --- a/arch/arm/mach-tegra/ap.c +++ b/arch/arm/mach-tegra/ap.c @@ -37,6 +37,14 @@ int tegra_get_chip(void) return rev; } +u32 tegra_get_major_version(void) +{ + struct apb_misc_gp_ctlr *gp = + (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; + + return (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> HIDREV_MAJORPREV_SHIFT; +} + int tegra_get_sku_info(void) { int sku_id; diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 006aae3d070..5477423f4d0 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -71,6 +71,7 @@ void powerup_cpu(void); void reset_A9_cpu(int reset); void start_cpu(u32 reset_vector); int tegra_get_chip(void); +u32 tegra_get_major_version(void); int tegra_get_sku_info(void); int tegra_get_chip_sku(void); void adjust_pllp_out_freqs(void); diff --git a/arch/arm/mach-tegra/crypto.c b/arch/arm/mach-tegra/crypto.c index 49e6a45243a..1005c815b36 100644 --- a/arch/arm/mach-tegra/crypto.c +++ b/arch/arm/mach-tegra/crypto.c @@ -4,164 +4,68 @@ * (C) Copyright 2010 - 2011 NVIDIA Corporation <www.nvidia.com> */ +#include <dm.h> #include <log.h> #include <linux/errno.h> #include <asm/arch-tegra/crypto.h> #include "uboot_aes.h" -static u8 zero_key[16]; - -#define AES_CMAC_CONST_RB 0x87 /* from RFC 4493, Figure 2.2 */ - -enum security_op { - SECURITY_SIGN = 1 << 0, /* Sign the data */ - SECURITY_ENCRYPT = 1 << 1, /* Encrypt the data */ - SECURITY_DECRYPT = 1 << 2, /* Dectypt the data */ -}; - -/** - * Shift a vector left by one bit - * - * \param in Input vector - * \param out Output vector - * \param size Length of vector in bytes - */ -static void left_shift_vector(u8 *in, u8 *out, int size) +int sign_data_block(u8 *source, unsigned int length, u8 *signature) { - int carry = 0; - int i; - - for (i = size - 1; i >= 0; i--) { - out[i] = (in[i] << 1) | carry; - carry = in[i] >> 7; /* get most significant bit */ + struct udevice *dev; + int ret; + + /* Only one AES engine should be present */ + ret = uclass_get_device(UCLASS_AES, 0, &dev); + if (ret) { + log_err("%s: failed to get tegra_aes: %d\n", __func__, ret); + return ret; } -} - -/** - * Sign a block of data, putting the result into dst. - * - * \param key Input AES key, length AES128_KEY_LENGTH - * \param key_schedule Expanded key to use - * \param src Source data of length 'num_aes_blocks' blocks - * \param dst Destination buffer, length AES128_KEY_LENGTH - * \param num_aes_blocks Number of AES blocks to encrypt - */ -static void sign_object(u8 *key, u8 *key_schedule, u8 *src, u8 *dst, - u32 num_aes_blocks) -{ - u8 tmp_data[AES128_KEY_LENGTH]; - u8 iv[AES128_KEY_LENGTH] = {0}; - u8 left[AES128_KEY_LENGTH]; - u8 k1[AES128_KEY_LENGTH]; - u8 *cbc_chain_data; - unsigned int i; - cbc_chain_data = zero_key; /* Convenient array of 0's for IV */ + ret = dm_aes_select_key_slot(dev, 128, TEGRA_AES_SLOT_SBK); + if (ret) + return ret; - /* compute K1 constant needed by AES-CMAC calculation */ - for (i = 0; i < AES128_KEY_LENGTH; i++) - tmp_data[i] = 0; - - aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, - tmp_data, left, 1); - - left_shift_vector(left, k1, sizeof(left)); - - if ((left[0] >> 7) != 0) /* get MSB of L */ - k1[AES128_KEY_LENGTH - 1] ^= AES_CMAC_CONST_RB; - - /* compute the AES-CMAC value */ - for (i = 0; i < num_aes_blocks; i++) { - /* Apply the chain data */ - aes_apply_cbc_chain_data(cbc_chain_data, src, tmp_data); - - /* for the final block, XOR K1 into the IV */ - if (i == num_aes_blocks - 1) - aes_apply_cbc_chain_data(tmp_data, k1, tmp_data); - - /* encrypt the AES block */ - aes_encrypt(AES128_KEY_LENGTH, tmp_data, - key_schedule, dst); - - debug("sign_obj: block %d of %d\n", i, num_aes_blocks); - - /* Update pointers for next loop. */ - cbc_chain_data = dst; - src += AES128_KEY_LENGTH; - } + return dm_aes_cmac(dev, source, signature, + DIV_ROUND_UP(length, AES_BLOCK_LENGTH)); } -/** - * Decrypt, encrypt or sign a block of data (depending on security mode). - * - * \param key Input AES key, length AES128_KEY_LENGTH - * \param oper Security operations mask to perform (enum security_op) - * \param src Source data - * \param length Size of source data - * \param sig_dst Destination address for signature, AES128_KEY_LENGTH bytes - */ -static int tegra_crypto_core(u8 *key, enum security_op oper, u8 *src, - u32 length, u8 *sig_dst) +int encrypt_data_block(u8 *source, u8 *dest, unsigned int length) { - u32 num_aes_blocks; - u8 key_schedule[AES128_EXPAND_KEY_LENGTH]; - u8 iv[AES128_KEY_LENGTH] = {0}; - - debug("%s: length = %d\n", __func__, length); - - aes_expand_key(key, AES128_KEY_LENGTH, key_schedule); - - num_aes_blocks = (length + AES128_KEY_LENGTH - 1) / AES128_KEY_LENGTH; - - if (oper & SECURITY_DECRYPT) { - /* Perform this in place, resulting in src being decrypted. */ - debug("%s: begin decryption\n", __func__); - aes_cbc_decrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, src, - src, num_aes_blocks); - debug("%s: end decryption\n", __func__); - } - - if (oper & SECURITY_ENCRYPT) { - /* Perform this in place, resulting in src being encrypted. */ - debug("%s: begin encryption\n", __func__); - aes_cbc_encrypt_blocks(AES128_KEY_LENGTH, key_schedule, iv, src, - src, num_aes_blocks); - debug("%s: end encryption\n", __func__); - } - - if (oper & SECURITY_SIGN) { - /* encrypt the data, overwriting the result in signature. */ - debug("%s: begin signing\n", __func__); - sign_object(key, key_schedule, src, sig_dst, num_aes_blocks); - debug("%s: end signing\n", __func__); + struct udevice *dev; + int ret; + + /* Only one AES engine should be present */ + ret = uclass_get_device(UCLASS_AES, 0, &dev); + if (ret) { + log_err("%s: failed to get tegra_aes: %d\n", __func__, ret); + return ret; } - return 0; -} + ret = dm_aes_select_key_slot(dev, 128, TEGRA_AES_SLOT_SBK); + if (ret) + return ret; -/** - * Tegra crypto group - */ -int sign_data_block(u8 *source, unsigned int length, u8 *signature) -{ - return tegra_crypto_core(zero_key, SECURITY_SIGN, source, - length, signature); + return dm_aes_cbc_encrypt(dev, (u8 *)AES_ZERO_BLOCK, source, dest, + DIV_ROUND_UP(length, AES_BLOCK_LENGTH)); } -int sign_enc_data_block(u8 *source, unsigned int length, u8 *signature, u8 *key) +int decrypt_data_block(u8 *source, u8 *dest, unsigned int length) { - return tegra_crypto_core(key, SECURITY_SIGN, source, - length, signature); -} + struct udevice *dev; + int ret; + + /* Only one AES engine should be present */ + ret = uclass_get_device(UCLASS_AES, 0, &dev); + if (ret) { + log_err("%s: failed to get tegra_aes: %d\n", __func__, ret); + return ret; + } -int encrypt_data_block(u8 *source, unsigned int length, u8 *key) -{ - return tegra_crypto_core(key, SECURITY_ENCRYPT, source, - length, NULL); -} + ret = dm_aes_select_key_slot(dev, 128, TEGRA_AES_SLOT_SBK); + if (ret) + return ret; -int decrypt_data_block(u8 *source, unsigned int length, u8 *key) -{ - return tegra_crypto_core(key, SECURITY_DECRYPT, source, - length, NULL); + return dm_aes_cbc_decrypt(dev, (u8 *)AES_ZERO_BLOCK, source, dest, + DIV_ROUND_UP(length, AES_BLOCK_LENGTH)); } diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index e9b5259ac70..abdf6504161 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -39,7 +39,7 @@ static u32 tegra_fuse_readl(unsigned long offset) return readl(NV_PA_FUSE_BASE + offset); } -static void tegra_fuse_init(void) +void tegra_fuse_init(void) { u32 reg; @@ -49,8 +49,11 @@ static void tegra_fuse_init(void) * this bit fuse region will not work. */ reg = readl_relaxed(NV_PA_CLK_RST_BASE + 0x48); - reg |= BIT(28); - writel(reg, NV_PA_CLK_RST_BASE + 0x48); + + if (reg & BIT(28)) + return; + + writel(reg | BIT(28), NV_PA_CLK_RST_BASE + 0x48); clock_enable(PERIPH_ID_FUSE); udelay(2); @@ -148,3 +151,57 @@ unsigned long long tegra_chip_uid(void) return uid; } + +static int tegra_is_production_mode_fuse_set(struct fuse_regs *fuse) +{ + return readl(&fuse->production_mode); +} + +static int tegra_is_odm_production_mode_fuse_set(struct fuse_regs *fuse) +{ + return readl(&fuse->security_mode); +} + +static int tegra_is_failure_analysis_mode(struct fuse_regs *fuse) +{ + return readl(&fuse->fa); +} + +static int tegra_is_sbk_zeroes(struct fuse_regs *fuse) +{ + int i; + + for (i = 0; i < 4; i++) + if (readl(&fuse->sbk[i])) + return 0; + + return 1; +} + +static int tegra_is_production_mode(struct fuse_regs *fuse) +{ + if (!tegra_get_major_version()) + return 1; + + return !tegra_is_failure_analysis_mode(fuse) && + tegra_is_production_mode_fuse_set(fuse); +} + +enum fuse_operating_mode tegra_fuse_get_operation_mode(void) +{ + struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; + + tegra_fuse_init(); + + if (tegra_is_production_mode(fuse)) { + if (!tegra_is_odm_production_mode_fuse_set(fuse)) + return MODE_PRODUCTION; + else + if (tegra_is_sbk_zeroes(fuse)) + return MODE_ODM_PRODUCTION_OPEN; + else + return MODE_ODM_PRODUCTION_SECURE; + } + + return MODE_UNDEFINED; +} diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig index 98f1d0e71c1..43dd59fb113 100644 --- a/arch/arm/mach-tegra/tegra114/Kconfig +++ b/arch/arm/mach-tegra/tegra114/Kconfig @@ -8,6 +8,10 @@ config TARGET_DALMORE bool "NVIDIA Tegra114 Dalmore evaluation board" select BOARD_LATE_INIT +config TARGET_SURFACE_2 + bool "Microsoft Surface 2" + select BOARD_LATE_INIT + config TARGET_TEGRATAB bool "NVIDIA Tegra114 TegraTab evaluation board" select BOARD_LATE_INIT @@ -22,6 +26,7 @@ config SYS_SOC default "tegra114" source "board/nvidia/dalmore/Kconfig" +source "board/microsoft/surface-2/Kconfig" source "board/nvidia/tegratab/Kconfig" source "board/asus/transformer-t114/Kconfig" diff --git a/arch/arm/mach-tegra/tegra124/bct.c b/arch/arm/mach-tegra/tegra124/bct.c index 4dc4b7138ab..676b68dc5de 100644 --- a/arch/arm/mach-tegra/tegra124/bct.c +++ b/arch/arm/mach-tegra/tegra124/bct.c @@ -9,12 +9,10 @@ #include <vsprintf.h> #include <linux/string.h> #include <asm/arch-tegra/crypto.h> +#include <asm/arch-tegra/fuse.h> #include "bct.h" #include "uboot_aes.h" -/* Device with "sbk burned: false" will expose zero key */ -const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; - /* * @param bct boot config table start in RAM * @param ect bootloader start in RAM @@ -26,29 +24,25 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) struct nvboot_config_table *bct_tbl = NULL; u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; u8 bct_hash[AES128_KEY_LENGTH] = { 0 }; - u8 sbk[AES128_KEY_LENGTH] = { 0 }; u8 *sbct = bct + UBCT_LENGTH; bool encrypted; int ret; ebt_size = roundup(ebt_size, EBT_ALIGNMENT); - memcpy(sbk, (u8 *)(bct + UBCT_LENGTH + SBCT_LENGTH), - NVBOOT_CMAC_AES_HASH_LENGTH * 4); - - encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); + encrypted = tegra_fuse_get_operation_mode() == MODE_ODM_PRODUCTION_SECURE; if (encrypted) { - ret = decrypt_data_block(sbct, SBCT_LENGTH, sbk); + ret = decrypt_data_block(sbct, sbct, SBCT_LENGTH); if (ret) return 1; - ret = encrypt_data_block(ebt, ebt_size, sbk); + ret = encrypt_data_block(ebt, ebt, ebt_size); if (ret) return 1; } - ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); + ret = sign_data_block(ebt, ebt_size, ebt_hash); if (ret) return 1; @@ -61,12 +55,12 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) bct_tbl->bootloader[0].length = ebt_size; if (encrypted) { - ret = encrypt_data_block(sbct, SBCT_LENGTH, sbk); + ret = encrypt_data_block(sbct, sbct, SBCT_LENGTH); if (ret) return 1; } - ret = sign_enc_data_block(sbct, SBCT_LENGTH, bct_hash, sbk); + ret = sign_data_block(sbct, SBCT_LENGTH, bct_hash); if (ret) return 1; diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig index bedbedade7b..b07b5a15585 100644 --- a/arch/arm/mach-tegra/tegra20/Kconfig +++ b/arch/arm/mach-tegra/tegra20/Kconfig @@ -54,6 +54,10 @@ config TARGET_SEABOARD select TEGRA_LP0 select TEGRA_PMU +config TARGET_SAMSUNG_N1 + bool "Samsung Tegra20 N1 board" + select BOARD_LATE_INIT + config TARGET_STAR bool "LG Tegra20 Star board" select BOARD_LATE_INIT @@ -92,6 +96,7 @@ source "board/compal/paz00/Kconfig" source "board/acer/picasso/Kconfig" source "board/avionic-design/plutux/Kconfig" source "board/nvidia/seaboard/Kconfig" +source "board/samsung/n1/Kconfig" source "board/lg/star/Kconfig" source "board/avionic-design/tec/Kconfig" source "board/asus/transformer-t20/Kconfig" diff --git a/arch/arm/mach-tegra/tegra20/bct.c b/arch/arm/mach-tegra/tegra20/bct.c index 253cb243676..0270cf592c1 100644 --- a/arch/arm/mach-tegra/tegra20/bct.c +++ b/arch/arm/mach-tegra/tegra20/bct.c @@ -9,12 +9,10 @@ #include <vsprintf.h> #include <linux/string.h> #include <asm/arch-tegra/crypto.h> +#include <asm/arch-tegra/fuse.h> #include "bct.h" #include "uboot_aes.h" -/* Device with "sbk burned: false" will expose zero key */ -const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; - /* * @param bct boot config table start in RAM * @param ect bootloader start in RAM @@ -25,7 +23,6 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) { struct nvboot_config_table *bct_tbl = NULL; u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; - u8 sbk[AES128_KEY_LENGTH] = { 0 }; u8 *bct_hash = bct; bool encrypted; int ret; @@ -34,22 +31,19 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) ebt_size = roundup(ebt_size, EBT_ALIGNMENT); - memcpy(sbk, (u8 *)(bct + BCT_LENGTH), - NVBOOT_CMAC_AES_HASH_LENGTH * 4); - - encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); + encrypted = tegra_fuse_get_operation_mode() == MODE_ODM_PRODUCTION_SECURE; if (encrypted) { - ret = decrypt_data_block(bct, BCT_LENGTH, sbk); + ret = decrypt_data_block(bct, bct, BCT_LENGTH); if (ret) return 1; - ret = encrypt_data_block(ebt, ebt_size, sbk); + ret = encrypt_data_block(ebt, ebt, ebt_size); if (ret) return 1; } - ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); + ret = sign_data_block(ebt, ebt_size, ebt_hash); if (ret) return 1; @@ -62,12 +56,12 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) bct_tbl->bootloader[0].length = ebt_size; if (encrypted) { - ret = encrypt_data_block(bct, BCT_LENGTH, sbk); + ret = encrypt_data_block(bct, bct, BCT_LENGTH); if (ret) return 1; } - ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk); + ret = sign_data_block(bct, BCT_LENGTH, bct_hash); if (ret) return 1; diff --git a/arch/arm/mach-tegra/tegra20/warmboot.c b/arch/arm/mach-tegra/tegra20/warmboot.c index 18034c83a1c..3fd39fe3c1a 100644 --- a/arch/arm/mach-tegra/tegra20/warmboot.c +++ b/arch/arm/mach-tegra/tegra20/warmboot.c @@ -19,6 +19,7 @@ #include <asm/arch-tegra/pmc.h> #include <asm/arch-tegra/fuse.h> #include <asm/arch-tegra/warmboot.h> +#include <asm/arch-tegra/crypto.h> DECLARE_GLOBAL_DATA_PTR; @@ -182,98 +183,36 @@ int warmboot_save_sdram_params(void) return 0; } -static u32 get_major_version(void) +static void determine_crypto_options(int *is_encrypted, int *is_signed) { - u32 major_id; - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - - major_id = (readl(&gp->hidrev) & HIDREV_MAJORPREV_MASK) >> - HIDREV_MAJORPREV_SHIFT; - return major_id; -} - -static int is_production_mode_fuse_set(struct fuse_regs *fuse) -{ - return readl(&fuse->production_mode); -} - -static int is_odm_production_mode_fuse_set(struct fuse_regs *fuse) -{ - return readl(&fuse->security_mode); -} - -static int is_failure_analysis_mode(struct fuse_regs *fuse) -{ - return readl(&fuse->fa); -} - -static int ap20_is_odm_production_mode(void) -{ - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - - if (!is_failure_analysis_mode(fuse) && - is_odm_production_mode_fuse_set(fuse)) - return 1; - else - return 0; -} - -static int ap20_is_production_mode(void) -{ - struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; - - if (get_major_version() == 0) - return 1; - - if (!is_failure_analysis_mode(fuse) && - is_production_mode_fuse_set(fuse) && - !is_odm_production_mode_fuse_set(fuse)) - return 1; - else - return 0; -} - -static enum fuse_operating_mode fuse_get_operation_mode(void) -{ - u32 chip_id; - struct apb_misc_gp_ctlr *gp = - (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; - - chip_id = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> - HIDREV_CHIPID_SHIFT; - if (chip_id == CHIPID_TEGRA20) { - if (ap20_is_odm_production_mode()) { - printf("!! odm_production_mode is not supported !!\n"); - return MODE_UNDEFINED; - } else - if (ap20_is_production_mode()) - return MODE_PRODUCTION; - else - return MODE_UNDEFINED; - } - return MODE_UNDEFINED; -} - -static void determine_crypto_options(int *is_encrypted, int *is_signed, - int *use_zero_key) -{ - switch (fuse_get_operation_mode()) { + switch (tegra_fuse_get_operation_mode()) { + case MODE_ODM_PRODUCTION_SECURE: + *is_encrypted = 1; + *is_signed = 1; + break; + case MODE_ODM_PRODUCTION_OPEN: case MODE_PRODUCTION: *is_encrypted = 0; *is_signed = 1; - *use_zero_key = 1; break; case MODE_UNDEFINED: default: *is_encrypted = 0; *is_signed = 0; - *use_zero_key = 0; break; } } -static int sign_wb_code(u32 start, u32 length, int use_zero_key) +static int encrypt_wb_code(u8 *source, u8 *destination, u32 length) +{ + source += offsetof(struct wb_header, random_aes_block); + destination += offsetof(struct wb_header, random_aes_block); + length -= offsetof(struct wb_header, random_aes_block); + + return encrypt_data_block(source, destination, length); +} + +static int sign_wb_code(u32 start, u32 length) { int err; u8 *source; /* Pointer to source */ @@ -295,10 +234,9 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) struct wb_header *dst_header; /* Pointer to dest WB header */ int is_encrypted; /* Segment is encrypted */ int is_signed; /* Segment is signed */ - int use_zero_key; /* Use key of all zeros */ /* Determine crypto options. */ - determine_crypto_options(&is_encrypted, &is_signed, &use_zero_key); + determine_crypto_options(&is_encrypted, &is_signed); /* Get the actual code limits. */ length = roundup(((u32)wb_end - (u32)wb_start), 16); @@ -346,18 +284,15 @@ int warmboot_prepare_code(u32 seg_address, u32 seg_length) dst_header->entry_point = NV_WB_RUN_ADDRESS; dst_header->code_length = length; - if (is_encrypted) { - printf("!!!! Encryption is not supported !!!!\n"); - dst_header->length_insecure = 0; - err = -EACCES; - goto fail; - } else - /* copy the wb code directly following dst_header. */ - memcpy((char *)(dst_header+1), (char *)wb_start, length); + if (is_encrypted) + encrypt_wb_code((u8 *)wb_start, (u8 *)dst_header, + length + sizeof(struct wb_header)); + else + /* copy the wb code directly following dst_header */ + memcpy((char *)(dst_header + 1), (char *)wb_start, length); if (is_signed) - err = sign_wb_code(seg_address, dst_header->length_insecure, - use_zero_key); + err = sign_wb_code(seg_address, dst_header->length_insecure); fail: if (err) diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index b5099ce67fc..4da67b19990 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -16,6 +16,10 @@ config TARGET_CARDHU bool "NVIDIA Tegra30 Cardhu evaluation board" select BOARD_LATE_INIT +config TARGET_CHAGALL + bool "Pegatron Tegra30 Chagall board" + select BOARD_LATE_INIT + config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" select BOARD_LATE_INIT @@ -64,6 +68,7 @@ config SYS_SOC source "board/toradex/apalis_t30/Kconfig" source "board/nvidia/beaver/Kconfig" source "board/nvidia/cardhu/Kconfig" +source "board/pegatron/chagall/Kconfig" source "board/toradex/colibri_t30/Kconfig" source "board/htc/endeavoru/Kconfig" source "board/asus/grouper/Kconfig" diff --git a/arch/arm/mach-tegra/tegra30/bct.c b/arch/arm/mach-tegra/tegra30/bct.c index 398ba1de386..de668214517 100644 --- a/arch/arm/mach-tegra/tegra30/bct.c +++ b/arch/arm/mach-tegra/tegra30/bct.c @@ -9,12 +9,10 @@ #include <vsprintf.h> #include <linux/string.h> #include <asm/arch-tegra/crypto.h> +#include <asm/arch-tegra/fuse.h> #include "bct.h" #include "uboot_aes.h" -/* Device with "sbk burned: false" will expose zero key */ -const u8 nosbk[AES128_KEY_LENGTH] = { 0 }; - /* * @param bct boot config table start in RAM * @param ect bootloader start in RAM @@ -25,7 +23,6 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) { struct nvboot_config_table *bct_tbl = NULL; u8 ebt_hash[AES128_KEY_LENGTH] = { 0 }; - u8 sbk[AES128_KEY_LENGTH] = { 0 }; u8 *bct_hash = bct; bool encrypted; int ret; @@ -34,22 +31,19 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) ebt_size = roundup(ebt_size, EBT_ALIGNMENT); - memcpy(sbk, (u8 *)(bct + BCT_LENGTH), - NVBOOT_CMAC_AES_HASH_LENGTH * 4); - - encrypted = memcmp(&sbk, &nosbk, AES128_KEY_LENGTH); + encrypted = tegra_fuse_get_operation_mode() == MODE_ODM_PRODUCTION_SECURE; if (encrypted) { - ret = decrypt_data_block(bct, BCT_LENGTH, sbk); + ret = decrypt_data_block(bct, bct, BCT_LENGTH); if (ret) return 1; - ret = encrypt_data_block(ebt, ebt_size, sbk); + ret = encrypt_data_block(ebt, ebt, ebt_size); if (ret) return 1; } - ret = sign_enc_data_block(ebt, ebt_size, ebt_hash, sbk); + ret = sign_data_block(ebt, ebt_size, ebt_hash); if (ret) return 1; @@ -62,12 +56,12 @@ static int bct_patch(u8 *bct, u8 *ebt, u32 ebt_size) bct_tbl->bootloader[0].length = ebt_size; if (encrypted) { - ret = encrypt_data_block(bct, BCT_LENGTH, sbk); + ret = encrypt_data_block(bct, bct, BCT_LENGTH); if (ret) return 1; } - ret = sign_enc_data_block(bct, BCT_LENGTH, bct_hash, sbk); + ret = sign_data_block(bct, BCT_LENGTH, bct_hash); if (ret) return 1; diff --git a/arch/arm/mach-zynqmp/aes.c b/arch/arm/mach-zynqmp/aes.c index 9a05fbf9c11..dec428c159e 100644 --- a/arch/arm/mach-zynqmp/aes.c +++ b/arch/arm/mach-zynqmp/aes.c @@ -47,7 +47,8 @@ int zynqmp_aes_operation(struct zynqmp_aes *aes) roundup(sizeof(struct zynqmp_aes), ARCH_DMA_MINALIGN)); ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes), - lower_32_bits((ulong)aes), 0, 0, ret_payload); + lower_32_bits((ulong)aes), 0, 0, 0, 0, + ret_payload); if (ret || ret_payload[1]) { printf("Failed: AES op status:0x%x, errcode:0x%x\n", ret, ret_payload[1]); diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index b7a4142fd54..5f194aaff9a 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -205,7 +205,7 @@ int zynqmp_mmio_write(const u32 address, #if defined(CONFIG_ZYNQMP_FIRMWARE) else return xilinx_pm_request(PM_MMIO_WRITE, address, mask, - value, 0, NULL); + value, 0, 0, 0, NULL); #endif return -EINVAL; @@ -226,7 +226,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value) u32 ret_payload[PAYLOAD_ARG_CNT]; ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, - 0, ret_payload); + 0, 0, 0, ret_payload); *value = ret_payload[1]; } #endif diff --git a/arch/arm/mach-zynqmp/zynqmp.c b/arch/arm/mach-zynqmp/zynqmp.c index 279006b4d13..c0398a466ff 100644 --- a/arch/arm/mach-zynqmp/zynqmp.c +++ b/arch/arm/mach-zynqmp/zynqmp.c @@ -57,7 +57,7 @@ static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc, } ret = xilinx_pm_request(PM_SECURE_IMAGE, src_lo, src_hi, - key_lo, key_hi, ret_payload); + key_lo, key_hi, 0, 0, ret_payload); if (ret) { printf("Failed: secure op status:0x%x\n", ret); } else { @@ -260,7 +260,7 @@ static int do_zynqmp_rsa(struct cmd_tbl *cmdtp, int flag, int argc, ret = xilinx_pm_request(PM_SECURE_RSA, upper_32_bits((ulong)srcaddr), lower_32_bits((ulong)srcaddr), srclen, rsaop, - ret_payload); + 0, 0, ret_payload); if (ret || ret_payload[1]) { printf("Failed: RSA status:0x%x, errcode:0x%x\n", ret, ret_payload[1]); @@ -309,7 +309,7 @@ static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag, srcaddr + roundup(srclen, ARCH_DMA_MINALIGN)); ret = xilinx_pm_request(PM_SECURE_SHA, 0, 0, 0, - ZYNQMP_SHA3_INIT, ret_payload); + ZYNQMP_SHA3_INIT, 0, 0, ret_payload); if (ret || ret_payload[1]) { printf("Failed: SHA INIT status:0x%x, errcode:0x%x\n", ret, ret_payload[1]); @@ -318,7 +318,7 @@ static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag, ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)srcaddr), lower_32_bits((ulong)srcaddr), - srclen, ZYNQMP_SHA3_UPDATE, ret_payload); + srclen, ZYNQMP_SHA3_UPDATE, 0, 0, ret_payload); if (ret || ret_payload[1]) { printf("Failed: SHA UPDATE status:0x%x, errcode:0x%x\n", ret, ret_payload[1]); @@ -328,7 +328,7 @@ static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag, ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)hashaddr), lower_32_bits((ulong)hashaddr), ZYNQMP_SHA3_SIZE, ZYNQMP_SHA3_FINAL, - ret_payload); + 0, 0, ret_payload); if (ret || ret_payload[1]) { printf("Failed: SHA FINAL status:0x%x, errcode:0x%x\n", ret, ret_payload[1]); diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index 3a24cbfff3b..a2bf52c5adc 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -9,8 +9,7 @@ #include <linux/compiler.h> /* - * This function jumps to an image with argument. Normally an FDT or ATAGS - * image. + * This function jumps to an image with argument, usually an FDT. */ #ifdef CONFIG_SPL_OS_BOOT void __noreturn jump_to_image_linux(struct spl_image_info *spl_image) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8c6feae5735..265b5320777 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -11,6 +11,9 @@ choice config TARGET_ANDES_AE350 bool "Support Andes ae350" +config TARGET_ANDES_VOYAGER + bool "Support Andes Voyager Board" + config TARGET_BANANAPI_F3 bool "Support BananaPi F3 Board" @@ -20,8 +23,8 @@ config TARGET_K230_CANMV config TARGET_LICHEERV_NANO bool "Support LicheeRV Nano Board" -config TARGET_MICROCHIP_ICICLE - bool "Support Microchip PolarFire-SoC Icicle Board" +config TARGET_MICROCHIP_GENERIC + bool "Support Microchip PolarFire-SoC Boards" config TARGET_MILKV_DUO bool "Support Milk-v Duo Board" @@ -101,10 +104,11 @@ config SPL_ZERO_MEM_BEFORE_USE # board-specific options below source "board/andestech/ae350/Kconfig" +source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -source "board/microchip/mpfs_icicle/Kconfig" +source "board/microchip/mpfs_generic/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sifive/unleashed/Kconfig" source "board/sifive/unmatched/Kconfig" @@ -339,10 +343,27 @@ endmenu config RISCV_ISA_A bool "Standard extension for Atomic Instructions" + depends on RISCV_ISA_ZAAMO && RISCV_ISA_ZALRSC default y help Adds "A" to the ISA string passed to the compiler. +config RISCV_ISA_ZAAMO + bool "Standard extension for Atomic Memory Operations" + default y + help + Indicates the platform supports Zaamo extension for atomic memory + operations. Hand-written Assembly routines won't use AMO + instructions if set to n. + +config RISCV_ISA_ZALRSC + bool "Standard extension for LR/SC instructions" + default y + help + Indicates the platform supports Zalrsc extension for load-reserved + and store-conditional isntructions. Hand-written assembly routines + won't use LR/SC instructions if set to n. + config RISCV_ISA_ZICBOM bool "Zicbom support" depends on !SYS_DISABLE_DCACHE_OPS diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 6f80f4a7108..fdda6da1df3 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -11,7 +11,12 @@ ifeq ($(CONFIG_ARCH_RV32I),y) ARCH_BASE = rv32im ABI_BASE = ilp32 endif -ifeq ($(CONFIG_RISCV_ISA_A),y) +# GCC starts to recognize "Zaamo" and "Zalrsc" from version 15, which is quite +# recent. We don't bother checking the exact compiler version, but pass "A" +# extension for -march as long as one of "Zaamo" or "Zalrsc" is available. +ifeq ($(findstring y,$(CONFIG_RISCV_ISA_A) \ + $(CONFIG_RISCV_ISA_ZAAMO) \ + $(CONFIG_RISCV_ISA_ZALRSC)),y) ARCH_A = a endif ifeq ($(CONFIG_RISCV_ISA_F),y) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 15c4e14599d..d5123e4b7d9 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -608,14 +608,14 @@ static inline bool supports_extension(char ext) static int riscv_cpu_probe(void) { -#ifdef CONFIG_CPU - int ret; + if (CONFIG_IS_ENABLED(CPU)) { + int ret; - /* probe cpus so that RISC-V timer can be bound */ - ret = cpu_probe_all(); - if (ret) - return log_msg_ret("RISC-V cpus probe failed\n", ret); -#endif + /* probe cpus so that RISC-V timer can be bound */ + ret = cpu_probe_all(); + if (ret) + return log_msg_ret("RISC-V cpus probe failed\n", ret); + } return 0; } diff --git a/arch/riscv/cpu/th1520/Kconfig b/arch/riscv/cpu/th1520/Kconfig index c73462c04b8..a02f5f24906 100644 --- a/arch/riscv/cpu/th1520/Kconfig +++ b/arch/riscv/cpu/th1520/Kconfig @@ -21,3 +21,4 @@ config THEAD_TH1520 imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT + imply OF_UPSTREAM diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 2b10c2d6c01..9b347fc3b50 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb dtb-$(CONFIG_TARGET_K230_CANMV) += k230-canmv.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb @@ -11,9 +12,9 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb +dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb include $(srctree)/scripts/Makefile.dts diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi deleted file mode 100644 index 049b0a7ce28..00000000000 --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -#include "jh7110-u-boot.dtsi" -/ { - aliases { - spi0 = &qspi; - }; - - chosen { - bootph-pre-ram; - }; - - firmware { - spi0 = &qspi; - bootph-pre-ram; - }; - - memory@40000000 { - bootph-pre-ram; - }; -}; - -&uart0 { - bootph-pre-ram; - reg-offset = <0>; - current-speed = <115200>; -}; - -&mmc0 { - bootph-pre-ram; -}; - -&mmc1 { - bootph-pre-ram; -}; - -&qspi { - bootph-pre-ram; - - flash@0 { - bootph-pre-ram; - cdns,read-delay = <2>; - spi-max-frequency = <100000000>; - }; -}; - -&syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, - <&syscrg JH7110_SYSCLK_BUS_ROOT>, - <&syscrg JH7110_SYSCLK_PERH_ROOT>, - <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, - <&pllclk JH7110_PLLCLK_PLL2_OUT>, - <&pllclk JH7110_PLLCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; - assigned-clock-rates = <0>, <0>, <0>, <0>; -}; - -&sysgpio { - bootph-pre-ram; -}; - -&mmc0_pins { - bootph-pre-ram; - rst-pins { - bootph-pre-ram; - }; -}; - -&mmc1_pins { - bootph-pre-ram; - clk-pins { - bootph-pre-ram; - }; - - mmc-pins { - bootph-pre-ram; - }; -}; - -&i2c5_pins { - bootph-pre-ram; - i2c-pins { - bootph-pre-ram; - }; -}; - -&i2c5 { - bootph-pre-ram; - eeprom@50 { - bootph-pre-ram; - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; diff --git a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi b/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi deleted file mode 100644 index ab882d07f6f..00000000000 --- a/arch/riscv/dts/jh7110-deepcomputing-fml13v01-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-common-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi deleted file mode 100644 index ab882d07f6f..00000000000 --- a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-common-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi deleted file mode 100644 index ab882d07f6f..00000000000 --- a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-common-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi deleted file mode 100644 index ab882d07f6f..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2024 StarFive Technology Co., Ltd. - */ - -#include "jh7110-common-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi deleted file mode 100644 index 874074174ff..00000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -#include "jh7110-common-u-boot.dtsi" -#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi deleted file mode 100644 index f8d13277d24..00000000000 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -#include <dt-bindings/reset/starfive,jh7110-crg.h> - -/ { - timer { - compatible = "riscv,timer"; - interrupts-extended = <&cpu0_intc 5>, - <&cpu1_intc 5>, - <&cpu2_intc 5>, - <&cpu3_intc 5>, - <&cpu4_intc 5>; - }; - - soc { - bootph-pre-ram; - - dmc: dmc@15700000 { - bootph-pre-ram; - compatible = "starfive,jh7110-dmc"; - reg = <0x0 0x15700000 0x0 0x10000>, - <0x0 0x13000000 0x0 0x10000>; - resets = <&syscrg JH7110_SYSRST_DDR_AXI>, - <&syscrg JH7110_SYSRST_DDR_OSC>, - <&syscrg JH7110_SYSRST_DDR_APB>; - reset-names = "axi", "osc", "apb"; - clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; - clock-names = "pll1_out"; - clock-frequency = <2133>; - }; - }; -}; - -&clint { - bootph-pre-ram; -}; - -&cpu0_intc { - bootph-pre-ram; -}; - -&cpu1_intc { - bootph-pre-ram; -}; - -&cpu2_intc { - bootph-pre-ram; -}; - -&cpu3_intc { - bootph-pre-ram; -}; - -&cpu4_intc { - bootph-pre-ram; -}; - -&cpus { - bootph-pre-ram; -}; - -&osc { - bootph-pre-ram; -}; - -&gmac0_rgmii_rxin { - bootph-pre-ram; -}; - -&gmac0_rmii_refin { - bootph-pre-ram; -}; - -&gmac1_rgmii_rxin { - bootph-pre-ram; -}; - -&gmac1_rmii_refin { - bootph-pre-ram; -}; - -&aoncrg { - bootph-pre-ram; -}; - -&pllclk { - bootph-pre-ram; -}; - -&syscrg { - assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */ - bootph-pre-ram; -}; - -&stgcrg { - bootph-pre-ram; -}; - -&sys_syscon { - bootph-pre-ram; -}; diff --git a/arch/riscv/dts/qilai-voyager.dts b/arch/riscv/dts/qilai-voyager.dts new file mode 100644 index 00000000000..44933529f89 --- /dev/null +++ b/arch/riscv/dts/qilai-voyager.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "binman.dtsi" +#include "voyager-u-boot.dtsi" + +/ { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "andestech,voyager", "andestech,qilai"; + model = "Voyager"; + + aliases { + uart0 = &serial0; + spi0 = &spi; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlycon=sbi debug loglevel=7"; + stdout-path = "uart0:115200n8"; + }; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + timebase-frequency = <0x3938700>; + + CPU0: cpu@0 { + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU0_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + reg = <0x1>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU1_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + reg = <0x2>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU2_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + reg = <0x3>; + status = "okay"; + compatible = "riscv"; + riscv,isa = "rv64imafdc"; + riscv,priv-major = <0x1>; + riscv,priv-minor = <0xa>; + mmu-type = "riscv,sv39"; + clock-frequency = <0x3938700>; + i-cache-size = <0x8000>; + i-cache-line-size = <0x20>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x20>; + next-level-cache = <&L2>; + + CPU3_intc: interrupt-controller { + #interrupt-cells = <0x1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; + + L2: l2-cache@200000 { + compatible = "cache"; + cache-level = <0x2>; + cache-size = <0x40000>; + reg = <0x0 0x00200000 0x0 0x100000>; + andes,inst-prefetch = <0x3>; + andes,data-prefetch = <0x3>; + andes,tag-ram-ctl = <0x0 0x0>; + andes,data-ram-ctl = <0x0 0x0>; + }; + + memory@400000000 { + device_type = "memory"; + reg = <0x04 0x00000000 0x0 0x40000000>; + }; + + soc { + #address-cells = <0x2>; + #size-cells = <0x2>; + compatible = "simple-bus"; + ranges; + + plic0: interrupt-controller@2000000 { + compatible = "riscv,plic0"; + #address-cells = <0x2>; + #interrupt-cells = <0x2>; + interrupt-controller; + reg = <0x0 0x02000000 0x0 0x2000000>; + riscv,ndev = <0x47>; + interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9 + &CPU1_intc 11 &CPU1_intc 9 + &CPU2_intc 11 &CPU2_intc 9 + &CPU3_intc 11 &CPU3_intc 9>; + }; + + plic1: interrupt-controller@400000 { + compatible = "andestech,plicsw"; + #address-cells = <0x2>; + #interrupt-cells = <0x2>; + interrupt-controller; + reg = <0x0 0x00400000 0x0 0x400000>; + riscv,ndev = <0x1>; + interrupts-extended = <&CPU0_intc 3 + &CPU1_intc 3 + &CPU2_intc 3 + &CPU3_intc 3>; + }; + + plmt0@100000 { + compatible = "andestech,plmt0"; + reg = <0x0 0x00100000 0x0 0x100000>; + interrupts-extended = <&CPU0_intc 7 + &CPU1_intc 7 + &CPU2_intc 7 + &CPU3_intc 7>; + }; + }; + + spiclk: virt_100mhz { + #clock-cells = <0x0>; + compatible = "fixed-clock"; + clock-frequency = <0x5f5e100>; + }; + + serial0: serial@30300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x0 0x30300000 0x0 0x1000>; + interrupts = <0x9 0x4>; + clock-frequency = <0x12c0000>; + reg-shift = <0x2>; + reg-offset = <0x20>; + no-loopback-test = <0x1>; + interrupt-parent = <&plic0>; + }; + + mmc0: mmc@30c00000 { + compatible = "andestech,atfsdc010"; + max-frequency = <0x5f5e100>; + clock-freq-min-max = <0x61a80 0x5f5e100>; + fifo-depth = <0x10>; + reg = <0x0 0x30c00000 0x0 0x1000>; + interrupts = <0x12 0x4>; + cap-sd-highspeed; + interrupt-parent = <&plic0>; + dma-coherent; + }; + + spi: spi@30900000 { + compatible = "andestech,atcspi200"; + reg = <0x0 0x30900000 0x0 0x100000>; + #address-cells = <0x1>; + #size-cells = <0x0>; + num-cs = <0x1>; + clocks = <&spiclk>; + interrupts = <0x4 0x4>; + interrupt-parent = <&plic0>; + + flash@0 { + compatible = "mx25u1635e", "jedec,spi-nor"; + spi-max-frequency = <0x2faf080>; + reg = <0x0>; + spi-cpol; + spi-cpha; + }; + }; +}; diff --git a/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi new file mode 100644 index 00000000000..4c86d285e66 --- /dev/null +++ b/arch/riscv/dts/starfive-visionfive2-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + */ + +/ { + soc { + memory-controller@15700000 { + clock-frequency = <2133>; /* FIXME: delete property and implement CCF */ + }; + }; +}; + +&syscrg { + assigned-clock-rates = <0>; /* FIXME: delete property and implement cpufreq */ +}; + +#include "starfive-visionfive2-binman.dtsi" diff --git a/arch/riscv/dts/sunxi-d1-t113.dtsi b/arch/riscv/dts/sunxi-d1-t113.dtsi deleted file mode 100644 index b7156123df5..00000000000 --- a/arch/riscv/dts/sunxi-d1-t113.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> - -/ { - soc { - dsp_wdt: watchdog@1700400 { - compatible = "allwinner,sun20i-d1-wdt"; - reg = <0x1700400 0x20>; - interrupts = <SOC_PERIPHERAL_IRQ(122) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dcxo>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - status = "reserved"; - }; - }; -}; diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi deleted file mode 100644 index 822f022eec2..00000000000 --- a/arch/riscv/dts/sunxi-d1s-t113.dtsi +++ /dev/null @@ -1,927 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) -// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org> - -#include <dt-bindings/clock/sun6i-rtc.h> -#include <dt-bindings/clock/sun8i-de2.h> -#include <dt-bindings/clock/sun8i-tcon-top.h> -#include <dt-bindings/clock/sun20i-d1-ccu.h> -#include <dt-bindings/clock/sun20i-d1-r-ccu.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/reset/sun8i-de2.h> -#include <dt-bindings/reset/sun20i-d1-ccu.h> -#include <dt-bindings/reset/sun20i-d1-r-ccu.h> - -/ { - #address-cells = <1>; - #size-cells = <1>; - - dcxo: dcxo-clk { - compatible = "fixed-clock"; - clock-output-names = "dcxo"; - #clock-cells = <0>; - }; - - de: display-engine { - compatible = "allwinner,sun20i-d1-display-engine"; - allwinner,pipelines = <&mixer0>, <&mixer1>; - status = "disabled"; - }; - - soc { - compatible = "simple-bus"; - ranges; - dma-noncoherent; - #address-cells = <1>; - #size-cells = <1>; - - pio: pinctrl@2000000 { - compatible = "allwinner,sun20i-d1-pinctrl"; - reg = <0x2000000 0x800>; - interrupts = <SOC_PERIPHERAL_IRQ(69) IRQ_TYPE_LEVEL_HIGH>, - <SOC_PERIPHERAL_IRQ(71) IRQ_TYPE_LEVEL_HIGH>, - <SOC_PERIPHERAL_IRQ(73) IRQ_TYPE_LEVEL_HIGH>, - <SOC_PERIPHERAL_IRQ(75) IRQ_TYPE_LEVEL_HIGH>, - <SOC_PERIPHERAL_IRQ(77) IRQ_TYPE_LEVEL_HIGH>, - <SOC_PERIPHERAL_IRQ(79) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_APB0>, - <&dcxo>, - <&rtc CLK_OSC32K>; - clock-names = "apb", "hosc", "losc"; - gpio-controller; - interrupt-controller; - #gpio-cells = <3>; - #interrupt-cells = <3>; - - /omit-if-no-ref/ - can0_pins: can0-pins { - pins = "PB2", "PB3"; - function = "can0"; - }; - - /omit-if-no-ref/ - can1_pins: can1-pins { - pins = "PB4", "PB5"; - function = "can1"; - }; - - /omit-if-no-ref/ - clk_pg11_pin: clk-pg11-pin { - pins = "PG11"; - function = "clk"; - }; - - /omit-if-no-ref/ - dsi_4lane_pins: dsi-4lane-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", - "PD6", "PD7", "PD8", "PD9"; - drive-strength = <30>; - function = "dsi"; - }; - - /omit-if-no-ref/ - lcd_rgb666_pins: lcd-rgb666-pins { - pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", - "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", - "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", - "PD18", "PD19", "PD20", "PD21"; - function = "lcd0"; - }; - - /omit-if-no-ref/ - mmc0_pins: mmc0-pins { - pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; - function = "mmc0"; - }; - - /omit-if-no-ref/ - mmc1_pins: mmc1-pins { - pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; - function = "mmc1"; - }; - - /omit-if-no-ref/ - mmc2_pins: mmc2-pins { - pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; - function = "mmc2"; - }; - - /omit-if-no-ref/ - rgmii_pe_pins: rgmii-pe-pins { - pins = "PE0", "PE1", "PE2", "PE3", "PE4", - "PE5", "PE6", "PE7", "PE8", "PE9", - "PE11", "PE12", "PE13", "PE14", "PE15"; - function = "emac"; - }; - - /omit-if-no-ref/ - rmii_pe_pins: rmii-pe-pins { - pins = "PE0", "PE1", "PE2", "PE3", "PE4", - "PE5", "PE6", "PE7", "PE8", "PE9"; - function = "emac"; - }; - - /omit-if-no-ref/ - spi0_pins: spi0-pins { - pins = "PC2", "PC3", "PC4", "PC5"; - function = "spi0"; - }; - - /omit-if-no-ref/ - uart1_pg6_pins: uart1-pg6-pins { - pins = "PG6", "PG7"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { - pins = "PG8", "PG9"; - function = "uart1"; - }; - - /omit-if-no-ref/ - uart3_pb_pins: uart3-pb-pins { - pins = "PB6", "PB7"; - function = "uart3"; - }; - }; - - ccu: clock-controller@2001000 { - compatible = "allwinner,sun20i-d1-ccu"; - reg = <0x2001000 0x1000>; - clocks = <&dcxo>, - <&rtc CLK_OSC32K>, - <&rtc CLK_IOSC>; - clock-names = "hosc", "losc", "iosc"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - gpadc: adc@2009000 { - compatible = "allwinner,sun20i-d1-gpadc"; - reg = <0x2009000 0x400>; - clocks = <&ccu CLK_BUS_GPADC>; - resets = <&ccu RST_BUS_GPADC>; - interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - #io-channel-cells = <1>; - }; - - dmic: dmic@2031000 { - compatible = "allwinner,sun20i-d1-dmic", - "allwinner,sun50i-h6-dmic"; - reg = <0x2031000 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(24) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_DMIC>, - <&ccu CLK_DMIC>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_DMIC>; - dmas = <&dma 8>; - dma-names = "rx"; - status = "disabled"; - #sound-dai-cells = <0>; - }; - - i2s1: i2s@2033000 { - compatible = "allwinner,sun20i-d1-i2s", - "allwinner,sun50i-r329-i2s"; - reg = <0x2033000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(27) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2S1>, - <&ccu CLK_I2S1>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S1>; - dmas = <&dma 4>, <&dma 4>; - dma-names = "rx", "tx"; - status = "disabled"; - #sound-dai-cells = <0>; - }; - - i2s2: i2s@2034000 { - compatible = "allwinner,sun20i-d1-i2s", - "allwinner,sun50i-r329-i2s"; - reg = <0x2034000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2S2>, - <&ccu CLK_I2S2>; - clock-names = "apb", "mod"; - resets = <&ccu RST_BUS_I2S2>; - dmas = <&dma 5>, <&dma 5>; - dma-names = "rx", "tx"; - status = "disabled"; - #sound-dai-cells = <0>; - }; - - timer: timer@2050000 { - compatible = "allwinner,sun20i-d1-timer", - "allwinner,sun8i-a23-timer"; - reg = <0x2050000 0xa0>; - interrupts = <SOC_PERIPHERAL_IRQ(59) IRQ_TYPE_LEVEL_HIGH>, - <SOC_PERIPHERAL_IRQ(60) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dcxo>; - }; - - wdt: watchdog@20500a0 { - compatible = "allwinner,sun20i-d1-wdt-reset", - "allwinner,sun20i-d1-wdt"; - reg = <0x20500a0 0x20>; - interrupts = <SOC_PERIPHERAL_IRQ(63) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&dcxo>, <&rtc CLK_OSC32K>; - clock-names = "hosc", "losc"; - status = "reserved"; - }; - - uart0: serial@2500000 { - compatible = "snps,dw-apb-uart"; - reg = <0x2500000 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <SOC_PERIPHERAL_IRQ(2) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_UART0>; - resets = <&ccu RST_BUS_UART0>; - dmas = <&dma 14>, <&dma 14>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart1: serial@2500400 { - compatible = "snps,dw-apb-uart"; - reg = <0x2500400 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <SOC_PERIPHERAL_IRQ(3) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_UART1>; - resets = <&ccu RST_BUS_UART1>; - dmas = <&dma 15>, <&dma 15>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart2: serial@2500800 { - compatible = "snps,dw-apb-uart"; - reg = <0x2500800 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <SOC_PERIPHERAL_IRQ(4) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_UART2>; - resets = <&ccu RST_BUS_UART2>; - dmas = <&dma 16>, <&dma 16>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart3: serial@2500c00 { - compatible = "snps,dw-apb-uart"; - reg = <0x2500c00 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <SOC_PERIPHERAL_IRQ(5) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_UART3>; - resets = <&ccu RST_BUS_UART3>; - dmas = <&dma 17>, <&dma 17>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart4: serial@2501000 { - compatible = "snps,dw-apb-uart"; - reg = <0x2501000 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <SOC_PERIPHERAL_IRQ(6) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_UART4>; - resets = <&ccu RST_BUS_UART4>; - dmas = <&dma 18>, <&dma 18>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - uart5: serial@2501400 { - compatible = "snps,dw-apb-uart"; - reg = <0x2501400 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupts = <SOC_PERIPHERAL_IRQ(7) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_UART5>; - resets = <&ccu RST_BUS_UART5>; - dmas = <&dma 19>, <&dma 19>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - i2c0: i2c@2502000 { - compatible = "allwinner,sun20i-d1-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x2502000 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(9) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C0>; - resets = <&ccu RST_BUS_I2C0>; - dmas = <&dma 43>, <&dma 43>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c1: i2c@2502400 { - compatible = "allwinner,sun20i-d1-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x2502400 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(10) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C1>; - resets = <&ccu RST_BUS_I2C1>; - dmas = <&dma 44>, <&dma 44>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c2: i2c@2502800 { - compatible = "allwinner,sun20i-d1-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x2502800 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(11) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C2>; - resets = <&ccu RST_BUS_I2C2>; - dmas = <&dma 45>, <&dma 45>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c3: i2c@2502c00 { - compatible = "allwinner,sun20i-d1-i2c", - "allwinner,sun8i-v536-i2c", - "allwinner,sun6i-a31-i2c"; - reg = <0x2502c00 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(12) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_I2C3>; - resets = <&ccu RST_BUS_I2C3>; - dmas = <&dma 46>, <&dma 46>; - dma-names = "rx", "tx"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - can0: can@2504000 { - compatible = "allwinner,sun20i-d1-can"; - reg = <0x02504000 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CAN0>; - resets = <&ccu RST_BUS_CAN0>; - pinctrl-names = "default"; - pinctrl-0 = <&can0_pins>; - status = "disabled"; - }; - - can1: can@2504400 { - compatible = "allwinner,sun20i-d1-can"; - reg = <0x02504400 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CAN1>; - resets = <&ccu RST_BUS_CAN1>; - pinctrl-names = "default"; - pinctrl-0 = <&can1_pins>; - status = "disabled"; - }; - - syscon: syscon@3000000 { - compatible = "allwinner,sun20i-d1-system-control"; - reg = <0x3000000 0x1000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - }; - - dma: dma-controller@3002000 { - compatible = "allwinner,sun20i-d1-dma"; - reg = <0x3002000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; - clock-names = "bus", "mbus"; - resets = <&ccu RST_BUS_DMA>; - dma-channels = <16>; - dma-requests = <48>; - #dma-cells = <1>; - }; - - sid: efuse@3006000 { - compatible = "allwinner,sun20i-d1-sid"; - reg = <0x3006000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - crypto: crypto@3040000 { - compatible = "allwinner,sun20i-d1-crypto"; - reg = <0x3040000 0x800>; - interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_CE>, - <&ccu CLK_CE>, - <&ccu CLK_MBUS_CE>, - <&rtc CLK_IOSC>; - clock-names = "bus", "mod", "ram", "trng"; - resets = <&ccu RST_BUS_CE>; - }; - - mbus: dram-controller@3102000 { - compatible = "allwinner,sun20i-d1-mbus"; - reg = <0x3102000 0x1000>, - <0x3103000 0x1000>; - reg-names = "mbus", "dram"; - interrupts = <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_MBUS>, - <&ccu CLK_DRAM>, - <&ccu CLK_BUS_DRAM>; - clock-names = "mbus", "dram", "bus"; - dma-ranges = <0 0x40000000 0x80000000>; - #address-cells = <1>; - #size-cells = <1>; - #interconnect-cells = <1>; - }; - - mmc0: mmc@4020000 { - compatible = "allwinner,sun20i-d1-mmc"; - reg = <0x4020000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC0>; - reset-names = "ahb"; - cap-sd-highspeed; - max-frequency = <150000000>; - no-mmc; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc1: mmc@4021000 { - compatible = "allwinner,sun20i-d1-mmc"; - reg = <0x4021000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC1>; - reset-names = "ahb"; - cap-sd-highspeed; - max-frequency = <150000000>; - no-mmc; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - mmc2: mmc@4022000 { - compatible = "allwinner,sun20i-d1-emmc", - "allwinner,sun50i-a100-emmc"; - reg = <0x4022000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; - clock-names = "ahb", "mmc"; - resets = <&ccu RST_BUS_MMC2>; - reset-names = "ahb"; - cap-mmc-highspeed; - max-frequency = <150000000>; - mmc-ddr-1_8v; - mmc-ddr-3_3v; - no-sd; - no-sdio; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi0: spi@4025000 { - compatible = "allwinner,sun20i-d1-spi", - "allwinner,sun50i-r329-spi"; - reg = <0x04025000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; - clock-names = "ahb", "mod"; - dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI0>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - spi1: spi@4026000 { - compatible = "allwinner,sun20i-d1-spi-dbi", - "allwinner,sun50i-r329-spi-dbi", - "allwinner,sun50i-r329-spi"; - reg = <0x04026000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(16) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; - clock-names = "ahb", "mod"; - dmas = <&dma 23>, <&dma 23>; - dma-names = "rx", "tx"; - resets = <&ccu RST_BUS_SPI1>; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - }; - - usb_otg: usb@4100000 { - compatible = "allwinner,sun20i-d1-musb", - "allwinner,sun8i-a33-musb"; - reg = <0x4100000 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - clocks = <&ccu CLK_BUS_OTG>; - resets = <&ccu RST_BUS_OTG>; - extcon = <&usbphy 0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - usbphy: phy@4100400 { - compatible = "allwinner,sun20i-d1-usb-phy"; - reg = <0x4100400 0x100>, - <0x4101800 0x100>, - <0x4200800 0x100>; - reg-names = "phy_ctrl", - "pmu0", - "pmu1"; - clocks = <&dcxo>, - <&dcxo>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&ccu RST_USB_PHY0>, - <&ccu RST_USB_PHY1>; - reset-names = "usb0_reset", - "usb1_reset"; - status = "disabled"; - #phy-cells = <1>; - }; - - ehci0: usb@4101000 { - compatible = "allwinner,sun20i-d1-ehci", - "generic-ehci"; - reg = <0x4101000 0x100>; - interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_BUS_EHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>, - <&ccu RST_BUS_EHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci0: usb@4101400 { - compatible = "allwinner,sun20i-d1-ohci", - "generic-ohci"; - reg = <0x4101400 0x100>; - interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI0>, - <&ccu CLK_USB_OHCI0>; - resets = <&ccu RST_BUS_OHCI0>; - phys = <&usbphy 0>; - phy-names = "usb"; - status = "disabled"; - }; - - ehci1: usb@4200000 { - compatible = "allwinner,sun20i-d1-ehci", - "generic-ehci"; - reg = <0x4200000 0x100>; - interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_BUS_EHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>, - <&ccu RST_BUS_EHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - ohci1: usb@4200400 { - compatible = "allwinner,sun20i-d1-ohci", - "generic-ohci"; - reg = <0x4200400 0x100>; - interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_OHCI1>, - <&ccu CLK_USB_OHCI1>; - resets = <&ccu RST_BUS_OHCI1>; - phys = <&usbphy 1>; - phy-names = "usb"; - status = "disabled"; - }; - - emac: ethernet@4500000 { - compatible = "allwinner,sun20i-d1-emac", - "allwinner,sun50i-a64-emac"; - reg = <0x4500000 0x10000>; - interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&ccu CLK_BUS_EMAC>; - clock-names = "stmmaceth"; - resets = <&ccu RST_BUS_EMAC>; - reset-names = "stmmaceth"; - syscon = <&syscon>; - status = "disabled"; - - mdio: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - display_clocks: clock-controller@5000000 { - compatible = "allwinner,sun20i-d1-de2-clk", - "allwinner,sun50i-h5-de2-clk"; - reg = <0x5000000 0x10000>; - clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_DE>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - mixer0: mixer@5100000 { - compatible = "allwinner,sun20i-d1-de2-mixer-0"; - reg = <0x5100000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER0>, - <&display_clocks CLK_MIXER0>; - clock-names = "bus", "mod"; - resets = <&display_clocks RST_MIXER0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer0_out: port@1 { - reg = <1>; - - mixer0_out_tcon_top_mixer0: endpoint { - remote-endpoint = <&tcon_top_mixer0_in_mixer0>; - }; - }; - }; - }; - - mixer1: mixer@5200000 { - compatible = "allwinner,sun20i-d1-de2-mixer-1"; - reg = <0x5200000 0x100000>; - clocks = <&display_clocks CLK_BUS_MIXER1>, - <&display_clocks CLK_MIXER1>; - clock-names = "bus", "mod"; - resets = <&display_clocks RST_MIXER1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mixer1_out: port@1 { - reg = <1>; - - mixer1_out_tcon_top_mixer1: endpoint { - remote-endpoint = <&tcon_top_mixer1_in_mixer1>; - }; - }; - }; - }; - - dsi: dsi@5450000 { - compatible = "allwinner,sun20i-d1-mipi-dsi", - "allwinner,sun50i-a100-mipi-dsi"; - reg = <0x5450000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&tcon_top CLK_TCON_TOP_DSI>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - phys = <&dphy>; - phy-names = "dphy"; - status = "disabled"; - - port { - dsi_in_tcon_lcd0: endpoint { - remote-endpoint = <&tcon_lcd0_out_dsi>; - }; - }; - }; - - dphy: phy@5451000 { - compatible = "allwinner,sun20i-d1-mipi-dphy", - "allwinner,sun50i-a100-mipi-dphy"; - reg = <0x5451000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_MIPI_DSI>, - <&ccu CLK_MIPI_DSI>; - clock-names = "bus", "mod"; - resets = <&ccu RST_BUS_MIPI_DSI>; - #phy-cells = <0>; - }; - - tcon_top: tcon-top@5460000 { - compatible = "allwinner,sun20i-d1-tcon-top"; - reg = <0x5460000 0x1000>; - clocks = <&ccu CLK_BUS_DPSS_TOP>, - <&ccu CLK_TCON_TV>, - <&ccu CLK_TVE>, - <&ccu CLK_TCON_LCD0>; - clock-names = "bus", "tcon-tv0", "tve0", "dsi"; - clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; - resets = <&ccu RST_BUS_DPSS_TOP>; - #clock-cells = <1>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_top_mixer0_in: port@0 { - reg = <0>; - - tcon_top_mixer0_in_mixer0: endpoint { - remote-endpoint = <&mixer0_out_tcon_top_mixer0>; - }; - }; - - tcon_top_mixer0_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; - }; - - tcon_top_mixer0_out_tcon_tv0: endpoint@2 { - reg = <2>; - remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; - }; - }; - - tcon_top_mixer1_in: port@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - - tcon_top_mixer1_in_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&mixer1_out_tcon_top_mixer1>; - }; - }; - - tcon_top_mixer1_out: port@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; - }; - - tcon_top_mixer1_out_tcon_tv0: endpoint@2 { - reg = <2>; - remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; - }; - }; - - tcon_top_hdmi_in: port@4 { - reg = <4>; - - tcon_top_hdmi_in_tcon_tv0: endpoint { - remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; - }; - }; - - tcon_top_hdmi_out: port@5 { - reg = <5>; - }; - }; - }; - - tcon_lcd0: lcd-controller@5461000 { - compatible = "allwinner,sun20i-d1-tcon-lcd"; - reg = <0x5461000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(90) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_TCON_LCD0>, - <&ccu CLK_TCON_LCD0>; - clock-names = "ahb", "tcon-ch0"; - clock-output-names = "tcon-pixel-clock"; - resets = <&ccu RST_BUS_TCON_LCD0>, - <&ccu RST_BUS_LVDS0>; - reset-names = "lcd", "lvds"; - #clock-cells = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_lcd0_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; - }; - - tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; - }; - }; - - tcon_lcd0_out: port@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - tcon_lcd0_out_dsi: endpoint@1 { - reg = <1>; - remote-endpoint = <&dsi_in_tcon_lcd0>; - }; - }; - }; - }; - - tcon_tv0: lcd-controller@5470000 { - compatible = "allwinner,sun20i-d1-tcon-tv"; - reg = <0x5470000 0x1000>; - interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_TCON_TV>, - <&tcon_top CLK_TCON_TOP_TV0>; - clock-names = "ahb", "tcon-ch1"; - resets = <&ccu RST_BUS_TCON_TV>; - reset-names = "lcd"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - tcon_tv0_in: port@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - tcon_tv0_in_tcon_top_mixer0: endpoint@0 { - reg = <0>; - remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; - }; - - tcon_tv0_in_tcon_top_mixer1: endpoint@1 { - reg = <1>; - remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; - }; - }; - - tcon_tv0_out: port@1 { - reg = <1>; - - tcon_tv0_out_tcon_top_hdmi: endpoint { - remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; - }; - }; - }; - }; - - ppu: power-controller@7001000 { - compatible = "allwinner,sun20i-d1-ppu"; - reg = <0x7001000 0x1000>; - clocks = <&r_ccu CLK_BUS_R_PPU>; - resets = <&r_ccu RST_BUS_R_PPU>; - #power-domain-cells = <1>; - }; - - r_ccu: clock-controller@7010000 { - compatible = "allwinner,sun20i-d1-r-ccu"; - reg = <0x7010000 0x400>; - clocks = <&dcxo>, - <&rtc CLK_OSC32K>, - <&rtc CLK_IOSC>, - <&ccu CLK_PLL_PERIPH0_DIV3>; - clock-names = "hosc", "losc", "iosc", "pll-periph"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - rtc: rtc@7090000 { - compatible = "allwinner,sun20i-d1-rtc", - "allwinner,sun50i-r329-rtc"; - reg = <0x7090000 0x400>; - interrupts = <SOC_PERIPHERAL_IRQ(144) IRQ_TYPE_LEVEL_HIGH>; - clocks = <&r_ccu CLK_BUS_R_RTC>, - <&dcxo>, - <&r_ccu CLK_R_AHB>; - clock-names = "bus", "hosc", "ahb"; - #clock-cells = <1>; - }; - }; -}; diff --git a/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi b/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi new file mode 100644 index 00000000000..bbfa3c499cf --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-module-4a-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org> + */ + +#include "th1520-u-boot.dtsi" + +&{/memory@0} { + bootph-pre-ram; +}; diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi deleted file mode 100644 index eecd3e9832a..00000000000 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> - */ - -/dts-v1/; - -#include "th1520.dtsi" - -/ { - model = "Sipeed Lichee Module 4A"; - compatible = "sipeed,lichee-module-4a", "thead,th1520"; - - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x00000000 0x2 0x00000000>; - bootph-pre-ram; - }; -}; - -&osc { - clock-frequency = <24000000>; -}; - -&osc_32k { - clock-frequency = <32768>; -}; - -&emmc { - bus-width = <8>; - max-frequency = <198000000>; - mmc-ddr-1_8v; - mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; - non-removable; - no-sdio; - no-sd; - status = "okay"; -}; - -&gmac0 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_pins>, <&mdio0_pins>; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&gmac1 { - pinctrl-names = "default"; - pinctrl-0 = <&gmac1_pins>; - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -&mdio0 { - phy0: ethernet-phy@1 { - reg = <1>; - }; - - phy1: ethernet-phy@2 { - reg = <2>; - }; -}; - -&padctrl0_apsys { - gmac0_pins: gmac0-0 { - tx-pins { - pins = "GMAC0_TX_CLK", - "GMAC0_TXEN", - "GMAC0_TXD0", - "GMAC0_TXD1", - "GMAC0_TXD2", - "GMAC0_TXD3"; - function = "gmac0"; - bias-disable; - drive-strength = <25>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pins = "GMAC0_RX_CLK", - "GMAC0_RXDV", - "GMAC0_RXD0", - "GMAC0_RXD1", - "GMAC0_RXD2", - "GMAC0_RXD3"; - function = "gmac0"; - bias-disable; - drive-strength = <1>; - input-enable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - gmac1_pins: gmac1-0 { - tx-pins { - pins = "GPIO2_18", /* GMAC1_TX_CLK */ - "GPIO2_20", /* GMAC1_TXEN */ - "GPIO2_21", /* GMAC1_TXD0 */ - "GPIO2_22", /* GMAC1_TXD1 */ - "GPIO2_23", /* GMAC1_TXD2 */ - "GPIO2_24"; /* GMAC1_TXD3 */ - function = "gmac1"; - bias-disable; - drive-strength = <25>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pins = "GPIO2_19", /* GMAC1_RX_CLK */ - "GPIO2_25", /* GMAC1_RXDV */ - "GPIO2_30", /* GMAC1_RXD0 */ - "GPIO2_31", /* GMAC1_RXD1 */ - "GPIO3_0", /* GMAC1_RXD2 */ - "GPIO3_1"; /* GMAC1_RXD3 */ - function = "gmac1"; - bias-disable; - drive-strength = <1>; - input-enable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - mdio0_pins: mdio0-0 { - mdc-pins { - pins = "GMAC0_MDC"; - function = "gmac0"; - bias-disable; - drive-strength = <13>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - mdio-pins { - pins = "GMAC0_MDIO"; - function = "gmac0"; - bias-disable; - drive-strength = <13>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; -}; - -&sdio0 { - bus-width = <4>; - max-frequency = <198000000>; - status = "okay"; -}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi b/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi new file mode 100644 index 00000000000..06d4a70d1ea --- /dev/null +++ b/arch/riscv/dts/th1520-lichee-pi-4a-u-boot.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org> + */ + +#include "th1520-lichee-module-4a-u-boot.dtsi" +#include "thead-th1520-binman.dtsi" + +&clk { + bootph-some-ram; +}; + +&padctrl0_apsys { + bootph-some-ram; +}; + +&uart0_pins { + bootph-some-ram; + + tx-pins { + bootph-some-ram; + }; + + rx-pins { + bootph-some-ram; + }; +}; diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts deleted file mode 100644 index 49af88b7adf..00000000000 --- a/arch/riscv/dts/th1520-lichee-pi-4a.dts +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> - */ - -#include "th1520-lichee-module-4a.dtsi" -#include "thead-th1520-binman.dtsi" - -/ { - model = "Sipeed Lichee Pi 4A"; - compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520"; - - aliases { - gpio0 = &gpio0; - gpio1 = &gpio1; - gpio2 = &gpio2; - gpio3 = &gpio3; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/arch/riscv/dts/th1520-u-boot.dtsi b/arch/riscv/dts/th1520-u-boot.dtsi new file mode 100644 index 00000000000..45ffccbb847 --- /dev/null +++ b/arch/riscv/dts/th1520-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org> + */ + +&{/soc} { + ddrc: ddrc@fffd000000 { + compatible = "thead,th1520-ddrc"; + reg = <0xff 0xfd000000 0x0 0x1000000>, + <0xff 0xfe000000 0x0 0x1000000>, + <0xff 0xff000000 0x0 0x4000>, + <0xff 0xff005000 0x0 0x1000>; + reg-names = "phy-0", "phy-1", "ctrl", "sys"; + bootph-pre-ram; + }; +}; + +&cpus { + bootph-pre-ram; +}; + +&c910_0 { + bootph-pre-ram; +}; + +&c910_1 { + bootph-pre-ram; +}; + +&c910_2 { + bootph-pre-ram; +}; + +&c910_3 { + bootph-pre-ram; +}; + +&clint { + bootph-pre-ram; +}; + +&uart0 { + bootph-pre-ram; +}; diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi deleted file mode 100644 index c46925a132a..00000000000 --- a/arch/riscv/dts/th1520.dtsi +++ /dev/null @@ -1,530 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Alibaba Group Holding Limited. - * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> - */ - -#include <dt-bindings/clock/thead,th1520-clk-ap.h> -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - compatible = "thead,th1520"; - #address-cells = <2>; - #size-cells = <2>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - bootph-pre-ram; - timebase-frequency = <3000000>; - - c910_0: cpu@0 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <0>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_1: cpu@1 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <1>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_2: cpu@2 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <2>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - c910_3: cpu@3 { - compatible = "thead,c910", "riscv"; - device_type = "cpu"; - riscv,isa = "rv64imafdc"; - reg = <3>; - bootph-pre-ram; - i-cache-block-size = <64>; - i-cache-size = <65536>; - i-cache-sets = <512>; - d-cache-block-size = <64>; - d-cache-size = <65536>; - d-cache-sets = <512>; - next-level-cache = <&l2_cache>; - mmu-type = "riscv,sv39"; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - l2_cache: l2-cache { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <1048576>; - cache-sets = <1024>; - cache-unified; - }; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_24m"; - #clock-cells = <0>; - }; - - osc_32k: 32k-oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_32k"; - #clock-cells = <0>; - }; - - aonsys_clk: clock-73728000 { - compatible = "fixed-clock"; - clock-frequency = <73728000>; - clock-output-names = "aonsys_clk"; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - plic: interrupt-controller@ffd8000000 { - compatible = "thead,th1520-plic", "thead,c900-plic"; - reg = <0xff 0xd8000000 0x0 0x01000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <240>; - }; - - clint: timer@ffdc000000 { - compatible = "thead,th1520-clint", "thead,c900-clint"; - reg = <0xff 0xdc000000 0x0 0x00010000>; - bootph-pre-ram; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>; - }; - - uart0: serial@ffe7014000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7014000 0x0 0x100>; - bootph-pre-ram; - interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - gmac1: ethernet@ffe7060000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; - reg-names = "dwmac", "apb"; - interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; - clock-names = "stmmaceth", "pclk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <32>; - status = "disabled"; - - mdio1: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - gmac0: ethernet@ffe7070000 { - compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; - reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; - reg-names = "dwmac", "apb"; - interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; - clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; - clock-names = "stmmaceth", "pclk"; - snps,pbl = <32>; - snps,fixed-burst; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <32>; - status = "disabled"; - - mdio0: mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - emmc: mmc@ffe7080000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7080000 0x0 0x10000>; - interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - sdio0: mmc@ffe7090000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe7090000 0x0 0x10000>; - interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - sdio1: mmc@ffe70a0000 { - compatible = "thead,th1520-dwcmshc"; - reg = <0xff 0xe70a0000 0x0 0x10000>; - interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_EMMC_SDIO>; - clock-names = "core"; - status = "disabled"; - }; - - uart1: serial@ffe7f00000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f00000 0x0 0x100>; - interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@ffe7f04000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xe7f04000 0x0 0x100>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - gpio2: gpio@ffe7f34000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f34000 0x0 0x1000>; - clocks = <&clk CLK_GPIO2>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portc: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio3: gpio@ffe7f38000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xe7f38000 0x0 0x1000>; - clocks = <&clk CLK_GPIO3>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portd: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl1_apsys: pinctrl@ffe7f3c000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xe7f3c000 0x0 0x1000>; - clocks = <&clk CLK_PADCTRL1>; - thead,pad-group = <2>; - }; - - gpio0: gpio@ffec005000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec005000 0x0 0x1000>; - clocks = <&clk CLK_GPIO0>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - gpio1: gpio@ffec006000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xec006000 0x0 0x1000>; - clocks = <&clk CLK_GPIO1>; - clock-names = "bus"; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl0_apsys: pinctrl@ffec007000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xec007000 0x0 0x1000>; - clocks = <&clk CLK_PADCTRL0>; - thead,pad-group = <3>; - }; - - uart2: serial@ffec010000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xec010000 0x0 0x4000>; - interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - clk: clock-controller@ffef010000 { - compatible = "thead,th1520-clk-ap"; - reg = <0xff 0xef010000 0x0 0x1000>; - clocks = <&osc>; - #clock-cells = <1>; - }; - - timer0: timer@ffefc32000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32000 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer1: timer@ffefc32014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32014 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer2: timer@ffefc32028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc32028 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer3: timer@ffefc3203c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xefc3203c 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - uart4: serial@fff7f08000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f08000 0x0 0x4000>; - interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart5: serial@fff7f0c000 { - compatible = "snps,dw-apb-uart"; - reg = <0xff 0xf7f0c000 0x0 0x4000>; - interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; - clock-names = "buadclk", "apb_pclk"; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - ddrc: ddrc@fffd000000 { - compatible = "thead,th1520-ddrc"; - reg = <0xff 0xfd000000 0x0 0x1000000>, - <0xff 0xfe000000 0x0 0x1000000>, - <0xff 0xff000000 0x0 0x4000>, - <0xff 0xff005000 0x0 0x1000>; - reg-names = "phy-0", "phy-1", "ctrl", "sys"; - bootph-pre-ram; - }; - - timer4: timer@ffffc33000 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33000 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer5: timer@ffffc33014 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33014 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer6: timer@ffffc33028 { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc33028 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - timer7: timer@ffffc3303c { - compatible = "snps,dw-apb-timer"; - reg = <0xff 0xffc3303c 0x0 0x14>; - clocks = <&clk CLK_PERI_APB_PCLK>; - clock-names = "timer"; - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - ao_gpio0: gpio@fffff41000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff41000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - porte: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - padctrl_aosys: pinctrl@fffff4a000 { - compatible = "thead,th1520-pinctrl"; - reg = <0xff 0xfff4a000 0x0 0x2000>; - clocks = <&aonsys_clk>; - thead,pad-group = <1>; - }; - - ao_gpio1: gpio@fffff52000 { - compatible = "snps,dw-apb-gpio"; - reg = <0xff 0xfff52000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - - portf: gpio-controller@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - }; -}; diff --git a/arch/riscv/dts/voyager-u-boot.dtsi b/arch/riscv/dts/voyager-u-boot.dtsi new file mode 100644 index 00000000000..cef0aa08b37 --- /dev/null +++ b/arch/riscv/dts/voyager-u-boot.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + cpus { + bootph-pre-ram; + CPU0: cpu@0 { + bootph-pre-ram; + CPU0_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU1: cpu@1 { + bootph-pre-ram; + CPU1_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU2: cpu@2 { + bootph-pre-ram; + CPU2_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + CPU3: cpu@3 { + bootph-pre-ram; + CPU3_intc: interrupt-controller { + bootph-pre-ram; + }; + }; + }; + + memory@0 { + bootph-pre-ram; + }; + + soc { + bootph-pre-ram; + + plic1: interrupt-controller@400000 { + bootph-pre-ram; + }; + + plmt0@100000 { + bootph-pre-ram; + }; + }; + + serial0: serial@30300000 { + bootph-pre-ram; + }; + +}; diff --git a/arch/riscv/dts/xilinx-binman.dts b/arch/riscv/dts/xilinx-binman.dts new file mode 100644 index 00000000000..715080ed763 --- /dev/null +++ b/arch/riscv/dts/xilinx-binman.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * binman file for AMD MicroBlaze V + * + * (C) Copyright 2025, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +/dts-v1/; + +#include "binman.dtsi" diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts index 4050ce2f051..f7a3e076fd5 100644 --- a/arch/riscv/dts/xilinx-mbv32.dts +++ b/arch/riscv/dts/xilinx-mbv32.dts @@ -2,15 +2,13 @@ /* * dts file for AMD MicroBlaze V * - * (C) Copyright 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ /dts-v1/; -#include "binman.dtsi" - / { #address-cells = <1>; #size-cells = <1>; @@ -26,6 +24,7 @@ device_type = "cpu"; reg = <0>; riscv,isa = "rv32imafdc"; + mmu-type = "riscv,sv39"; i-cache-size = <32768>; d-cache-size = <32768>; clock-frequency = <100000000>; @@ -70,7 +69,8 @@ interrupt-controller; interrupt-parent = <&cpu0_intc>; #interrupt-cells = <2>; - kind-of-intr = <0>; + xlnx,num-intr-inputs = <2>; + xlnx,kind-of-intr = <0>; }; xlnx_timer0: timer@41c00000 { diff --git a/arch/riscv/dts/xilinx-mbv64.dts b/arch/riscv/dts/xilinx-mbv64.dts index 4d65d338ecb..e6235ed2f52 100644 --- a/arch/riscv/dts/xilinx-mbv64.dts +++ b/arch/riscv/dts/xilinx-mbv64.dts @@ -2,15 +2,13 @@ /* * dts file for AMD MicroBlaze V * - * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <michal.simek@amd.com> */ /dts-v1/; -#include "binman.dtsi" - / { #address-cells = <2>; #size-cells = <2>; @@ -26,6 +24,7 @@ device_type = "cpu"; reg = <0>; riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; i-cache-size = <32768>; d-cache-size = <32768>; clock-frequency = <100000000>; @@ -70,7 +69,8 @@ interrupt-controller; interrupt-parent = <&cpu0_intc>; #interrupt-cells = <2>; - kind-of-intr = <0>; + xlnx,num-intr-inputs = <2>; + xlnx,kind-of-intr = <0>; }; xlnx_timer0: timer@41c00000 { diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 56c5da86e86..ae3e5bce5c1 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -95,7 +95,6 @@ #define DEFAULT_MTVEC 0x00001010 #define CFG_STRING_ADDR 0x0000100C #define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 // page table entry (PTE) fields #define PTE_V 0x001 // Valid diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index db8d235c699..f1f50918eff 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -6,8 +6,8 @@ # Copyright (C) 2017 Andes Technology Corporation # Rick Chen, Andes Technology Corporation <rick@andestech.com> -obj-$(CONFIG_CMD_BOOTM) += bootm.o -obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o +obj-$(CONFIG_$(PHASE_)LIB_BOOTM) += bootm.o +obj-$(CONFIG_$(PHASE_)LIB_BOOTI) += image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S index 9884077c933..e5479bbe84e 100644 --- a/arch/riscv/lib/memcpy.S +++ b/arch/riscv/lib/memcpy.S @@ -125,6 +125,14 @@ WEAK(memcpy) .copy_end: ret +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +#define M_SLL sll +#define M_SRL srl +#else +#define M_SLL srl +#define M_SRL sll +#endif + .Lmisaligned_word_copy: /* * Misaligned word-wise copy. @@ -144,10 +152,10 @@ WEAK(memcpy) addi t0, t0, -(SZREG-1) /* At least one iteration will be executed here, no check */ 1: - srl a4, a5, t3 + M_SRL a4, a5, t3 REG_L a5, SZREG(a1) addi a1, a1, SZREG - sll a2, a5, t4 + M_SLL a2, a5, t4 or a2, a2, a4 REG_S a2, 0(a0) addi a0, a0, SZREG diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S index fbe6701dbe4..b2c1c736713 100644 --- a/arch/riscv/lib/memmove.S +++ b/arch/riscv/lib/memmove.S @@ -91,6 +91,14 @@ WEAK(memmove) mv a0, t0 ret +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +#define M_SLL sll +#define M_SRL srl +#else +#define M_SLL srl +#define M_SRL sll +#endif + .Lmisaligned_word_copy: /* * Misaligned word-wise copy. @@ -110,10 +118,10 @@ WEAK(memmove) addi t0, t0, SZREG-1 /* At least one iteration will be executed here, no check */ 1: - sll a4, a5, t4 + M_SLL a4, a5, t4 addi a1, a1, -SZREG REG_L a5, 0(a1) - srl a2, a5, t3 + M_SRL a2, a5, t3 or a2, a2, a4 addi a0, a0, -SZREG REG_S a2, 0(a0) diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index d61a327f151..e0c70dd3142 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -27,14 +27,17 @@ config SANDBOX_RAM_SIZE_MB config SANDBOX_SPL bool "Enable SPL for sandbox" + depends on !COMPILE_TEST select SUPPORT_SPL config SANDBOX_TPL bool "Enable TPL for sandbox" + depends on !COMPILE_TEST select SUPPORT_TPL config SANDBOX_VPL bool "Enable VPL for sandbox" + depends on !COMPILE_TEST select SUPPORT_VPL config SYS_CONFIG_NAME diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 6db8739e66b..b8fabd07d0b 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -335,6 +335,10 @@ int dcache_status(void) return 1; } +void flush_dcache_all(void) +{ +} + void flush_dcache_range(unsigned long start, unsigned long stop) { } @@ -343,6 +347,19 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) { } +void icache_enable(void) +{ +} + +void icache_disable(void) +{ +} + +int icache_status(void) +{ + return 1; +} + /** * setup_auto_tree() - Set up a basic device tree to allow sandbox to work * diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index f5c9a8aecf2..e48eb23cdc0 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -35,6 +35,7 @@ #include <asm/state.h> #include <os.h> #include <rtc_def.h> +#include <env.h> /* Environment variable for time offset */ #define ENV_TIME_OFFSET "UBOOT_SB_TIME_OFFSET" @@ -1014,7 +1015,7 @@ long os_get_time_offset(void) { const char *offset; - offset = getenv(ENV_TIME_OFFSET); + offset = env_get(ENV_TIME_OFFSET); if (offset) return strtol(offset, NULL, 0); return 0; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index bb696c5ef7f..a2c739a2044 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -936,6 +936,14 @@ }; }; + i3c0 { + compatible = "sandbox,i3c"; + }; + + i3c1 { + compatible = "sandbox,i3c"; + }; + bootcount@0 { compatible = "u-boot,bootcount-rtc"; rtc = <&rtc_1>; diff --git a/arch/sandbox/include/asm/atomic.h b/arch/sandbox/include/asm/atomic.h new file mode 100644 index 00000000000..2fe49f52f34 --- /dev/null +++ b/arch/sandbox/include/asm/atomic.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Based on arch/riscv/include/asm/atomic.h which is: + * Copyright 2023 SiFive, Inc. + */ + +#ifndef __SANDBOX_ATOMIC_H +#define __SANDBOX_ATOMIC_H + +/* use the generic asm/atomic.h until we define a better one */ + +#include <asm/system.h> +#include <asm-generic/atomic.h> + +#endif diff --git a/arch/sandbox/include/asm/dma-mapping.h b/arch/sandbox/include/asm/dma-mapping.h index 853b0877b33..410760c2231 100644 --- a/arch/sandbox/include/asm/dma-mapping.h +++ b/arch/sandbox/include/asm/dma-mapping.h @@ -1 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copied from arch/arm/include/asm/dma-mapping.h which is: + * + * (C) Copyright 2007 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + */ + +#ifndef __ASM_SANDBOX_DMA_MAPPING_H +#define __ASM_SANDBOX_DMA_MAPPING_H + +#include <asm/cache.h> +#include <linux/types.h> +#include <malloc.h> + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, ROUND(len, ARCH_DMA_MINALIGN)); + return (void *)*handle; +} + +static inline void dma_free_coherent(void *addr) +{ + free(addr); +} + +#endif diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 11ed89e0071..e3034b9c703 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -12,6 +12,10 @@ static inline void sync(void) { } +#define mb() sync() +#define dmb() sync() +#define wmb() sync() + enum sandboxio_size_t { SB_SIZE_8, SB_SIZE_16, @@ -40,19 +44,29 @@ phys_addr_t map_to_sysmem(const void *ptr); unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size); void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size); -#define readb(addr) sandbox_read((const void *)addr, SB_SIZE_8) -#define readw(addr) sandbox_read((const void *)addr, SB_SIZE_16) -#define readl(addr) sandbox_read((const void *)addr, SB_SIZE_32) +#define readb(addr) ({ u8 __v = sandbox_read((const void *)addr, SB_SIZE_8); __v; }) +#define readw(addr) ({ u16 __v = sandbox_read((const void *)addr, SB_SIZE_16); __v; }) +#define readl(addr) ({ u32 __v = sandbox_read((const void *)addr, SB_SIZE_32); __v; }) #ifdef CONFIG_64BIT -#define readq(addr) sandbox_read((const void *)addr, SB_SIZE_64) +#define readq(addr) ({ u64 __v = sandbox_read((const void *)addr, SB_SIZE_64); __v; }) #endif -#define writeb(v, addr) sandbox_write((void *)addr, v, SB_SIZE_8) -#define writew(v, addr) sandbox_write((void *)addr, v, SB_SIZE_16) -#define writel(v, addr) sandbox_write((void *)addr, v, SB_SIZE_32) +#define writeb(v, addr) ({ u8 __v = v; sandbox_write((void *)addr, __v, SB_SIZE_8); __v; }) +#define writew(v, addr) ({ u16 __v = v; sandbox_write((void *)addr, __v, SB_SIZE_16); __v; }) +#define writel(v, addr) ({ u32 __v = v; sandbox_write((void *)addr, __v, SB_SIZE_32); __v; }) #ifdef CONFIG_64BIT -#define writeq(v, addr) sandbox_write((void *)addr, v, SB_SIZE_64) +#define writeq(v, addr) ({ u64 __v = v; sandbox_write((void *)addr, __v, SB_SIZE_64); __v; }) #endif +#define readb_relaxed readb +#define readw_relaxed readw +#define readl_relaxed readl +#define readq_relaxed readq + +#define writeb_relaxed writeb +#define writew_relaxed writew +#define writel_relaxed writel +#define writeq_relaxed writeq + /* * Clear and set bits in one shot. These macros can be used to clear and * set multiple bits in a register using a single call. These macros can diff --git a/arch/sandbox/include/asm/processor.h b/arch/sandbox/include/asm/processor.h index 8dced6006bd..6521274efb0 100644 --- a/arch/sandbox/include/asm/processor.h +++ b/arch/sandbox/include/asm/processor.h @@ -6,6 +6,7 @@ #ifndef _ASM_PROCESSOR_H #define _ASM_PROCESSOR_H -/* This file is required for PCI */ +/* Assorted dummy functions */ +#define cpu_relax() #endif diff --git a/arch/sandbox/include/asm/system.h b/arch/sandbox/include/asm/system.h index 7933b6292e2..73f34683b27 100644 --- a/arch/sandbox/include/asm/system.h +++ b/arch/sandbox/include/asm/system.h @@ -7,10 +7,9 @@ #define __ASM_SANDBOX_SYSTEM_H /* Define this as nops for sandbox architecture */ -#define local_irq_save(x) +#define local_irq_save(x) do { (x) = 0; } while (0) #define local_irq_enable() #define local_irq_disable() -#define local_save_flags(x) #define local_irq_restore(x) #endif diff --git a/arch/x86/include/asm/pnp_def.h b/arch/x86/include/asm/pnp_def.h deleted file mode 100644 index 0345d195c69..00000000000 --- a/arch/x86/include/asm/pnp_def.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * Adapted from coreboot src/include/device/pnp_def.h - * and arch/x86/include/arch/io.h - */ - -#ifndef _ASM_PNP_DEF_H_ -#define _ASM_PNP_DEF_H_ - -#include <asm/io.h> - -#define PNP_IDX_EN 0x30 -#define PNP_IDX_IO0 0x60 -#define PNP_IDX_IO1 0x62 -#define PNP_IDX_IO2 0x64 -#define PNP_IDX_IO3 0x66 -#define PNP_IDX_IRQ0 0x70 -#define PNP_IDX_IRQ1 0x72 -#define PNP_IDX_DRQ0 0x74 -#define PNP_IDX_DRQ1 0x75 -#define PNP_IDX_MSC0 0xf0 -#define PNP_IDX_MSC1 0xf1 - -/* Generic functions for pnp devices */ - -/* - * pnp device is a 16-bit integer composed of its i/o port address at high byte - * and logic function number at low byte. - */ -#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) - -static inline void pnp_write_config(uint16_t dev, uint8_t reg, uint8_t value) -{ - uint8_t port = dev >> 8; - - outb(reg, port); - outb(value, port + 1); -} - -static inline uint8_t pnp_read_config(uint16_t dev, uint8_t reg) -{ - uint8_t port = dev >> 8; - - outb(reg, port); - return inb(port + 1); -} - -static inline void pnp_set_logical_device(uint16_t dev) -{ - uint8_t device = dev & 0xff; - - pnp_write_config(dev, 0x07, device); -} - -static inline void pnp_set_enable(uint16_t dev, int enable) -{ - pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0); -} - -static inline int pnp_read_enable(uint16_t dev) -{ - return !!pnp_read_config(dev, PNP_IDX_EN); -} - -static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase) -{ - pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); - pnp_write_config(dev, index + 1, iobase & 0xff); -} - -static inline uint16_t pnp_read_iobase(uint16_t dev, uint8_t index) -{ - return ((uint16_t)(pnp_read_config(dev, index)) << 8) | - pnp_read_config(dev, index + 1); -} - -static inline void pnp_set_irq(uint16_t dev, uint8_t index, unsigned irq) -{ - pnp_write_config(dev, index, irq); -} - -static inline void pnp_set_drq(uint16_t dev, uint8_t index, unsigned drq) -{ - pnp_write_config(dev, index, drq & 0xff); -} - -#endif /* _ASM_PNP_DEF_H_ */ diff --git a/arch/x86/lib/acpi_nhlt.c b/arch/x86/lib/acpi_nhlt.c index 8aae5fa5af7..4ffce589d7a 100644 --- a/arch/x86/lib/acpi_nhlt.c +++ b/arch/x86/lib/acpi_nhlt.c @@ -408,7 +408,7 @@ int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt, memcpy(header->oem_table_id, oem_table_id, oem_table_id_len); } header->oem_revision = oem_revision; - memcpy(header->creator_id, ASLC_ID, 4); + memcpy(header->creator_id, ACPI_CREATOR_ID, 4); cur.buf = (void *)(header + 1); cur.start = (void *)header; diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index b13292c4150..6bd7ad799bf 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -224,7 +224,7 @@ static int acpi_write_tpm2(struct acpi_ctx *ctx, /* Fill out header fields. */ acpi_fill_header(header, "TPM2"); - memcpy(header->creator_id, ASLC_ID, 4); + memcpy(header->creator_id, ACPI_CREATOR_ID, 4); header->length = sizeof(struct acpi_tpm2); header->revision = acpi_get_table_revision(ACPITAB_TPM2); |