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Saved environments cause inconsistencies leading to conflicts
with the default environment that U-boot should update during
development. Remove the previously saved environment so that
the default environment is always loaded.
Signed-off-by: Anurag Dutta <a-dutta@ti.com>
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https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing
boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The
changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
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Automatically start watchdog timer for Agilex5. This
configuration is enabled by default in the Kconfig,
hence removing this configuration from Agilex5 defconfig.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Add the required configuration in the U-Boot env to enable Linux QSPI
boot with UBI / UBIFS.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Add board_boot_order() to retrieve the list of boot devices from
spl-boot-order property in device tree. This board_boot_order()
would be used for all Intel SOC64 devices.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Enable XGMAC for SoCFPGA Agilex5 devkit.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Use default common ARMv8 linker script instead of a separate
SoC64 linker script
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
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Introduce a new symbol in the beginning of .data section in
the common ARMv8 linker script and use that as a reference
for data save and restore.
Previously, the code would rely on calculating the start of
the .data section address via data size, however, we observed
that the data size does not really reflect the SPL mapped
addresses.
In our case, the binman_sym section size was not included in
the data size, which will result in a wrong address for the
.data start section, which prevents us from properly saving
and restoring SPL data.
This approach skips the calculation for the starting address
of the .data section, and instead just defines the beginning
address of the .data section and calling the symbol as needed,
in which we think as a simpler and much more robust method.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Add SPL support for Agilex5 SoCFPGA.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Adding DDR driver support for Agilex5 series.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
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As cache is enabled in U-Boot and disabled in ATF(BL31). We need to
perform cache flush of buffers that are shared between U-Boot and
ATF using secure monitor calls.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Adding configuration for SPL malloc pool.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Board ID is exported as environment variable for use to boot Linux with FIT
configuration.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Update the print info per Agilex5
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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set/way instructions "dc cisw" which is used by the "dcache flush" command
only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in
cache coherency unit, hence this patch enables data flush from system
memory cache of CCU into DDR memory.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Enable PSCI reset driver for Agilex5 cold and warm reset
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Enable XGMAC for SoCFPGA Agilex5 devkit.
Link: https://lore.kernel.org/all/20241204064755.10226-2-mun.yew.tham@intel.com/
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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These firewall configure settings are needed to disable firewall on
respective hardware component so both secure and non-secure transactions
are allowed.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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These configuration settings are required to enable cache maintenance and
access between initiators and targets.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Agilex5 supports both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and Agilex5 device.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Status polling is used instead of using interrupt controller for Agilex5.
Disabling GICV3 in Agilex5 target, as well as disabling GICV2 enabled by
default for all SoCFPGA devices.
All the other SoCFPGA devices uses GICV2, thus enabling GICV2 in each of
the devices.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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There are 5 L4 watchdogs and one SDM triggered warm reset bit
in Agilex5 reset manager "stat" register where bit 16:20 for L4
watchdogs. Assigning value 1 to these bits in the register address
will initiate SDM to trigger warm reset.
Introducing new warm reset mask for Agilex5 to trigger warm reset
to all five L4 watchdogs.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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PLL frequency would overshoot from the original target in
synchronous mode during low VCC voltage condition.
To resolve this issue, PLL is set to run on asynchronous mode
instead of enabling synchronous mode in the clock driver.
Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Replace cm_wait_for_fsm() function with wait_for_bit_le32() function
which supports accurate timeout.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Some customers prefer to minimize the use of external oscillators,
especially when using the FPGA first configuration mode.
By enabling the configuration of the HPS internal oscillator as
the boot_clk source instead of the default external oscillator,
(HPS_OSC_CLK) in non-secure boot scenarios, this allows them
to eliminate the need for an additional oscillator device and
a dedicated HPS pin, simplifying board layout and routing.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
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Agilex5 retrieves its clock manager address via probing its own clock
driver model during SPL initialization.
Therefore, excluding Agilex5 from calling generic clock driver in misc
driver.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
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Initial creation of new system manager driver.
Add supports for the SOCFPGA System Manager Register block which
aggregates different peripheral function into one area.
On 64 bit ARM parts, the system manager only can be accessed during
EL3 mode, this driver model provide user the high level access
to system register and abstract user from low level access.
The base address of system manager can be retrieved
using DT framework through the System Manager driver.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
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Enable i2c3 node in Agilex5 device tree
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
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Prepare v2025.04-rc3
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Signed-off-by: Tom Rini <trini@konsulko.com>
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For eMMC v4 and newer that is smaller than 2 GiB, the JEDEC JESD84-B51
section 6.2.4 Configure partitions indicates that EXT_CSD SEC_COUNT
should not be used to determine device size, and instead device size
should be calculated from C_SIZE and C_SIZE_MULT.
This is not exactly accurate, the 2 GiB limit is not a hard line,
there are eMMC devices which are smaller than 2 GiB and still
require device size to be determined from EXT_CSD SEC_COUNT. The
hard line is instead OCR HCS bit, which indicates whether the device
is byte or sector addressed, the former applies to most devices
below 2 GiB, and the later applies mostly to devices above 2 GiB.
However, there are a couple of devices which are smaller than 2 GiB
and still set the OCR HCS bit to indicate they are sector addressed,
and therefore the size calculation for those devices should also
use EXT_CSD SEC_COUNT . Use mmc->high_capacity flag to discern the
devices instead of arbitrary 2 GiB limit. The mmc->high_capacity flag
reflects the OCR HCS bit state.
Fixes: 639b7827d1ca ("mmc: fix the condition for MMC version 4")
Signed-off-by: Marek Vasut <marex@denx.de>
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This reverts commit c8750efe02c20725388dd4279896aaf306acfad4, reversing
changes made to 8c6cf8aeea7e57ca686de8b765e4baf3a7ef1fa7.
Unfortunately these changes do not build on macOS hosts.
Signed-off-by: Tom Rini <trini@konsulko.com>
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The length of buffers used to read inode tables, directory tables, and
reading a file are calculated as: number of blocks * block size, and
such plain multiplication is prone to overflowing (thus unsafe).
Replace it by __builtin_mul_overflow, i.e. safe math.
Signed-off-by: Joao Marcos Costa <joaomarcos.costa@bootlin.com>
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Branch contains bringup of Acer Iconia Tab A500 (codename picasso), a
Tegra 2 Android device with decent Linux kernel support. Ondevice tests
and U-Boot test suit all passed.
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Recent versions of this module call time.perf_counter() so add a patch
for this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
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Paul HENRYS <paul.henrys_ext@softathome.com> says:
This serie of patches adds a new tool to authenticate files signed
with a preload header.
This tool is also used in the tests to actually verify the
authenticity of the file signed with such a preload header.
Link: https://lore.kernel.org/r/20250212093126.3722186-1-paul.henrys_ext@softathome.com
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This merges a set of patches from myself and Simon Glass to resolve
various problems that the current version of pylint will report with our
codebase. After the problems are fixed, we update to the now current
version which is 3.3.4.
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Memory region used by remote cores was set to non-cached region but
commit 7c9c6e192580 ("arm: mach-k3: Merge initial memory maps") makes
all memory region as cached, unified across K3 devices.
This causes inconsistency while booting remote cores on devices, due to
cache incoherency between remote core and boot code.
So to make this operation coherent, cache the address and len while
loading ELF program headers to memory and flush that region in the next
cycle of load.
Signed-off-by: Udit Kumar <u-kumar1@ti.com>
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
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Defining CONFIG_MT8512 is unnecessary as now board for mediatek
target can be changed in config.
Use CONFIG_TARGET_MT8512 to replace CONFIG_MT8512.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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Not all MediaTek platforms needs u-boot-mtk.bin.
This patch will let u-boot generates u-boot-mtk.bin only if
CONFIG_MTK_BROM_HEADER_INFO is not empty.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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Use preload_check_sign to authenticate the generated image when testing the
preload signature in testPreLoad().
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com>
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pre-load related config options are enabled to have support of it in host
tools.
'CONFIG_FIT_SIGNATURE=y' is being automatically removed since it is
selected by CONFIG_IMAGE_PRE_LOAD_SIG.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com>
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preload_check_sign is added so that it can be used to authenticate images
signed with the pre-load signature supported by binman and U-Boot.
It could also be used to test the signature in binman tests signing
images with the pre-load.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com>
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Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com>
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Add an empty inline declaration when compiling tools for a host where
unmap_sysmem() is not defined.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com>
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rsa_verify_openssl() is used in lib/rsa/rsa-verify.c to authenticate data
when building host tools.
Signed-off-by: Paul HENRYS <paul.henrys_ext@softathome.com>
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With all of the reported warnings now fixed, update to current pylint
version.
Signed-off-by: Tom Rini <trini@konsulko.com>
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This newer pylint produces errors about variables possibly being used
before being set. Adjust the code to pass these checks.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Tom Rini <trini@konsulko.com>
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With a newer pylint we get a warning that gitutil.RunTests does not
exist, so remove the line.
Signed-off-by: Tom Rini <trini@konsulko.com>
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