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path: root/arch/arm/include/asm/arch-imx9/ddr.h
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13 daysimx93_frdm: Add initial board supportFabio Estevam
Add the initial board support for the NXP i.MX93 FRDM board: https://www.nxp.com/design/design-center/development-boards-and-designs/frdm-i-mx-93-development-board:FRDM-IMX93 Based on the NXP U-Boot code. There were attempts to upstream the board devicetree, but it has not been accepted upstream yet: https://lore.kernel.org/linux-arm-kernel/20250526-fpg-nxp-imx93-frdm-v2-2-e5ad0efaec33@pengutronix.de/ Once it reaches upstream, we can switch to OF_UPSTREAM. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-12-23imx: Use per board ddrphy_trained_csrPeng Fan
Drop global ddrphy_trained_csr which maybe different with per board ddrphy_trained_csr. DDR TOOL generates ddrphy_trained_csr for each board, using the global ddrphy_trained_csr has risk that values may be not up to date. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx93: update the ddr init to support mult setpointsJacky Bai
Update the DDR init flow for multi-setpoint support on i.MX93. A new fsp_cfg struct need to be added in the timing file to store the diff part of the DDRC and DRAM MR register for each setpoint. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-05-21ddr: imx9: Add workaround for DDRPHY rank-to-rank errataYe Li
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap specification does not include the Critical Delay Difference (CDD) to properly define the required rank-to-rank read command spacing after executing PHY training firmware. Following the errata workaround, at the end of data training, we get all CDD values through the MessageBlock, then re-configure the DDRC timing of WWT/WRT/RRT/RWT with comparing MAX CDD values. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2022-07-26ddr: imx: Add i.MX9 DDR controller driverYe Li
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common directory under imx, then use dedicated ddr controller driver for each iMX9 and iMX8M. The DDRPHY registers are space compressed, so it needs conversion to access the DDRPHY address. Introduce a common PHY address remap function for both iMX8M and iMX9 for all PHY registers accessing. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>