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2025-06-20env: Rename SYS_RELOC_GD_ENV_ADDR to ENV_RELOC_GD_ENV_ADDRMarek Vasut
Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-04-23arm: add initjmp()Jerome Forissier
Implement initjmp() for Arm. a non-standard extension to setjmp()/ longjmp() allowing to initialize a jump buffer with a function pointer and a stack pointer. This will be useful to later introduce threads. With this new function it becomes possible to longjmp() to a particular function pointer (rather than to a point previously reached during program execution as is the case with setjmp()), and with a custom stack. Both things are needed to spin off a new thread. Then the usual setjmp()/longjmp() pair is enough to save and restore a context, i.e., switch thread. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-04-14Merge patch series "Static initcalls"Tom Rini
Jerome Forissier <jerome.forissier@linaro.org> says: This series replaces the dynamic initcalls (with function pointers) with static calls, and gets rid of initcall_run_list(), init_sequence_f, init_sequence_f_r and init_sequence_r. This makes the code simpler and the binary slighlty smaller: -2281 bytes/-0.21 % with LTO enabled and -510 bytes/-0.05 % with LTO disabled (xilinx_zynqmp_kria_defconfig). Execution time doesn't seem to change noticeably. There is no impact on the SPL. The inline assembly fixes, although they look unrelated, are triggered on some platforms with LTO enabled. For example: kirkwood_defconfig. CI: https://source.denx.de/u-boot/custodians/u-boot-net/-/pipelines/25514 Link: https://lore.kernel.org/r/20250404135038.2134570-1-jerome.forissier@linaro.org
2025-04-14arm: asm/system.h: mrc and mcr need .arm if __thumb2__ is not setJerome Forissier
The mcr and msr instructions are available in Thumb mode only if Thumb2 is supported. Therefore, if __thumb2__ is not set, make sure we switch to ARM mode by inserting a .arm directive in the inline assembly. Fixes LTO link errors with kirkwood platforms, triggered by a later commit: tools/buildman/buildman -o /tmp/build -eP sheevaplug [...] {standard input}:24085: Error: selected processor does not support `mrc p15,0,r3,c1,c0,0' in Thumb mode Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
2025-04-11Merge patch series "Switch to using $(PHASE_) in Makefiles"Tom Rini
Tom Rini <trini@konsulko.com> says: This series switches to always using $(PHASE_) in Makefiles when building rather than $(PHASE_) or $(XPL_). It also starts on documenting this part of the build, but as a follow-up we need to rename doc/develop/spl.rst and expand on explaining things a bit. Link: https://lore.kernel.org/r/20250401225851.1125678-1-trini@konsulko.com
2025-04-11Kbuild: Always use $(PHASE_)Tom Rini
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our Makefiles as part of the macros to determine when to do something in our Makefiles based on what phase of the build we are in. For consistency, bring this down to a single macro and use "$(PHASE_)" only. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-04-08arm: gic-v3: Scan for subnodesPatrick Rudolph
According to the binding [1] the ITS node should be a subnode of the GICv3 node. Since the ITS node has it's own driver, manually probe for possible subnodes after binding since dm_scan_fdt() is not recursive. 1: https://www.kernel.org/doc/Documentation/devicetree/bindings/interrupt-controller/arm%2Cgic-v3.txt Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2025-04-07Revert "Merge patch series "pxe: Precursor series for supporting read_all() ↵Tom Rini
in extlinux / PXE"" This reverts commit 8bc3542384e3a1219e5ffb62b79d16dddc1b1fb9, reversing changes made to 698edd63eca090a2e299cd3facf90a0b97bed677. There are still problems with this series to work out. Link: https://lore.kernel.org/u-boot/CAFLszTjw_MJbK9tpzVYi3XKGazcv55auBAdgVzcAVUta7dRqcg@mail.gmail.com/ Signed-off-by: Tom Rini <trini@konsulko.com>
2025-04-02Merge patch series "Various toolchain compatibility fixes/improvements"Tom Rini
Sam Edwards <cfsworks@gmail.com> says: This is v2 of my "misc. fixes" series, sent to prepare the codebase for more direct LLVM support in the near future. This series contains several fixes that I found in the process of preparing that support and which address issues independent of any future feature or enhancement. I am sending these now, both so that their inclusion is not delayed by discussion on my upcoming series and to make the latter more manageable. Link: https://lore.kernel.org/r/20250315221813.1265193-1-CFSworks@gmail.com
2025-04-02arm: riscv: efi: Export _start symbol from crt0_*_efi stubsSam Edwards
While the _start label is only intended for use locally to populate the (hand-written) PE header, the linker script includes ENTRY(_start) which designates it as the entry point in the output ELF, resulting in linker warnings under some linkers (e.g. LLVM's lld) due to _start not being a globally-visible symbol. Since ELF is only an intermediary build format, and the aforementioned PE header correctly points to _start, the ENTRY(_start) directive could easily be removed to silence this warning. However, since some developers who are debugging EFI by analyzing the intermediary ELF may appreciate having correct entry-point information, this patch instead promotes the _start labels to global symbols, silencing the linker warning and making the intermediary ELF reflect the true entry point. This patch doesn't affect the final output binaries in any way. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2025-04-02arm: Replace 'adrl' in EFI crt0Sam Edwards
LLVM's IAS does not (and cannot easily) support the 'adrl' pseudoinstruction, and ARM developers generally do not consider it portable across assembler implementations either. Instead, expand it into the two subtract instructions it would emit anyway. An explanation of the math follows: The .+8 and .+4 refer to the same memory location; this is because the .+4 expression occurs in a subsequent instruction, 4 bytes after the first. This memory location is the value of the PC register when it is read by the first sub instruction. Thus, both inner parenthesized expressions evaluate to the same result: PC's offset relative to image_base. The subtract instructions then remove one byte each (low, then high) of the total offset, thereby getting the absolute address of image_base loaded in r0. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-04-02arm: Add aligned-memory aliases to eabi_compatSam Edwards
These are sometimes used by LLVM's code-generator, when it can guarantee that the memory buffer being passed is aligned on a (4- or 8-byte) boundary. They can safely be aliased to the unaligned versions. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-04-02arm: Add __aeabi_memclr in eabi_compatSam Edwards
LLVM's code generator will sometimes emit calls to __aeabi_memclr. Add an implementation of this for LLVM compatibility. Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-04-02arm: Exclude eabi_compat from LTOSam Edwards
These symbols need to survive the IR-level dead function elimination pass, since nothing at the IR level is referencing them (calls to these are inserted later, at codegen time). Signed-off-by: Sam Edwards <CFSworks@gmail.com> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-03-24Merge tag 'v2025.04-rc5' into nextTom Rini
Prepare v2025.04-rc5
2025-03-18Merge patch series "pxe: Precursor series for supporting read_all() in ↵Tom Rini
extlinux / PXE" Simon Glass <sjg@chromium.org> says: This series includes some patches related to allowing read_all() to be used with the extlinux / PXE bootmeths. These patches were split out from the stb4 series, since it will need to have additional patches for LWIP, to avoid breaking PXE booting when LWIP is used. Link: https://lore.kernel.org/r/20250306002533.2380866-1-sjg@chromium.org
2025-03-18boot: arm: riscv: sandbox: Add a format for the booti fileSimon Glass
Arm invented a new format for arm64 and something similar is also used with RISC-V. Add this to the list of supported formats and provide a way for the format to be detected on both architectures. Update the genimg_get_format() function to support this. Fix up switch() statements which don't currently mention this format. Booti does not support a ramdisk, so this can be ignored. Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-17arm: riscv: efi: Export _start symbol from crt0_*_efi stubsSam Edwards
While the _start label is only intended for use locally to populate the (hand-written) PE header, the linker script includes ENTRY(_start) which designates it as the entry point in the output ELF, resulting in linker warnings under some linkers (e.g. LLVM's lld) due to _start not being a globally-visible symbol. Since ELF is only an intermediary build format, and the aforementioned PE header correctly points to _start, the ENTRY(_start) directive could easily be removed to silence this warning. However, since some developers who are debugging EFI by analyzing the intermediary ELF may appreciate having correct entry-point information, this patch instead promotes the _start labels to global symbols, silencing the linker warning and making the intermediary ELF reflect the true entry point. This patch doesn't affect the final output binaries in any way. Signed-off-by: Sam Edwards <CFSworks@gmail.com>
2025-03-14treewide: Add a function to change page permissionsIlias Apalodimas
For armv8 we are adding proper page permissions for the relocated U-Boot binary. Add a weak function that can be used across architectures to change the page permissions Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905X-CC Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-03-13Merge patch series "xPL-stack cleanup"Tom Rini
Simon Glass <sjg@chromium.org> says: This series was split from the VBE part H series. It adjusts the logic for selecting the top of the stack so that it is more consistent across xPL phases. Link: https://lore.kernel.org/r/20250228122042.1277079-1-sjg@chromium.org
2025-03-13spl: Use CONFIG_VAL() to obtain the SPL stackSimon Glass
Now that we have the same option for SPL and TPL, simplify the logic for determining the initial stack. Note that this changes behaviour as current SPL_STACK is a fallback for TPL. However, that was likely unintended and can be handled with Kconfig defaults if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Suggested-by: Tom Rini <trini@konsulko.com>
2025-03-13spl: Add an SPL_HAVE_INIT_STACK optionSimon Glass
At present there is a hex value SPL_STACK which both determines whether SPL has its own initial stack and the hex value of that stack. Split off the former into SPL_HAVE_INIT_STACK with SPL_STACK depending on that and only providing the latter. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Resync defconfig files]
2025-03-13tpl: Rename TPL_NEEDS_SEPARATE_STACK to TPL_HAVE_INIT_STACKSimon Glass
The most common word for features that make a platform work is to use 'HAVE_xxx'. Rename this option to match. Update the help to use the word 'phase' rather than 'stage', since that is the current terminology. Also clarify that, absent this setting, the stack pointer generally comes from the value used by U-Boot proper, rather than SPL. Move the option just above TPL_STACK which depends on it. Signed-off-by: Simon Glass <sjg@chromium.org>
2025-03-10usb: gadget: Remove final remnants of CONFIG_USB_DEVICETom Rini
The lone user of the legacy USB device framework have been removed for some time. Remove the final parts of the code that were missed. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20250227205101.4127604-1-trini@konsulko.com Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
2025-02-19Merge patch series "bloblist: refactor xferlist and bloblist"Tom Rini
Tom Rini <trini@konsulko.com> says: This small series separates "bloblist" and "standard passage" to allow for these similar concepts to explore solutions to problems without introduces breaking changes to the other. Link: https://lore.kernel.org/r/20250220000223.1044376-1-raymond.mao@linaro.org
2025-02-19bloblist: refactor xferlist and bloblistRaymond Mao
Refactor the xferlist to remove the relocating when bloblist passed from the boot args. Refactor bloblist init to use incoming standard passage by default if a valid transfer list exists in the boot args. For bloblist relocation, use the actual total size if it has a smaller BLOBLIST_SIZE_RELOC. Signed-off-by: Raymond Mao <raymond.mao@linaro.org> Suggested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2025-02-10arm: Remove redundant loading of image copy start offseLiya Huang
Because the beginning is already computed Signed-off-by: Liya Huang <1425075683@qq.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2025-01-17efi_loader: use include in ARM EFI linker scriptHeinrich Schuchardt
Use the same include as arm64 for the linker script. Adjust the 32-bit ARM PE-COFF header accordingly and harmonize it with the 64-bit ARM header. Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-01-17efi_loader: correct SizeOfCode, SizeOfInitializedDataHeinrich Schuchardt
The fields SizeOfCode, SizeOfInitializedData, and SizeOfUninitializedData are define in the PE-COFF specification [1]. * SizeOfCode must match the size of all .text sections. * SizeOfInitializedData must match the size of all .data sections. * SizeOfUninitializedData must match the size of all .bss sections. We only have one .text and one .data section. SizeOfCode and SizeOfInitializedData have to be calculated as the difference between the end and the start of the respective section. As we don't have any .bss sections in the generated EFI binaries. SizeOfUninitializedData must remain 0. [1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-01-17efi_loader: use INCLUDE in EFI linker scriptsHeinrich Schuchardt
Except for the architecture specific lines ARM and RISC-V can use the same linker script. Move the common lines to an include. Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2025-01-17efi_loader: Fix section alignment on EFI binariesIlias Apalodimas
When creating EFI binaries, the alignment of the text section isn't correctly factored in. As a result trying to load signed EFI binaries throws an error with: efi_image_region_add() efi_image_region_add: new region already part of another Image not authenticated Running the binary through sbverify has a similar warning sbverify ./lib/efi_loader/helloworld.efi warning: gap in section table: .text : 0x00001000 - 0x00001c00, .data : 0x00002000 - 0x00002200, gaps in the section table may result in different checksums warning: data remaining[7680 vs 12720]: gaps between PE/COFF sections? ..... If we include the alignment in the text section, the signed binary boots fine, and the relevant sbverify warning goes away sbverify ./lib/efi_loader/helloworld.efi warning: data remaining[8704 vs 12720]: gaps between PE/COFF sections? ..... We should look into the remaining warning at some point as well regarding the gaps between PE/COFF sections. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2024-11-24dm: Add dm_remove_devices_active() for ordered device removalJanne Grunau
This replaces dm_remove_devices_flags() calls in all boot implementations to ensure non vital devices are consistently removed first. All boot implementation except arch/arm/lib/bootm.c currently just call dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL). This can result in crashes when dependencies between devices exists. The driver model's design document describes DM_FLAG_VITAL as "indicates that the device is 'vital' to the operation of other devices". Device removal at boot should follow this. Instead of adding dm_remove_devices_flags() with (DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL) everywhere add dm_remove_devices_active() which does this. Fixes a NULL pointer deref in the apple dart IOMMU driver during EFI boot. The xhci-pci (driver which depends on the IOMMU to work) removes its mapping on removal. This explodes when the IOMMU device was removed first. dm_remove_devices_flags() is kept since it is used for testing of device_remove() calls in dm. Signed-off-by: Janne Grunau <j@jannau.net>
2024-10-27Merge patch series "Implement ACPI on aarch64"Tom Rini
Patrick Rudolph <patrick.rudolph@9elements.com> says: Based on the existing work done by Simon Glass this series adds support for booting aarch64 devices using ACPI only. As first target QEMU SBSA support is added, which relies on ACPI only to boot an OS. As secondary target the Raspberry Pi4 was used, which is broadly available and allows easy testing of the proposed solution. The series is split into ACPI cleanups and code movements, adding Arm specific ACPI tables and finally SoC and mainboard related changes to boot a Linux on the QEMU SBSA and RPi4. Currently only the mandatory ACPI tables are supported, allowing to boot into Linux without errors. The QEMU SBSA support is feature complete and provides the same functionality as the EDK2 implementation. The changes were tested on real hardware as well on QEMU v9.0: qemu-system-aarch64 -machine sbsa-ref -nographic -cpu cortex-a57 \ -pflash secure-world.rom \ -pflash unsecure-world.rom qemu-system-aarch64 -machine raspi4b -kernel u-boot.bin -cpu cortex-a72 \ -smp 4 -m 2G -drive file=raspbian.img,format=raw,index=0 \ -dtb bcm2711-rpi-4-b.dtb -nographic Tested against FWTS V24.03.00. Known issues: - The QEMU rpi4 support is currently limited as it doesn't emulate PCI, USB or ethernet devices! - The SMP bringup doesn't work on RPi4, but works in QEMU (Possibly cache related). - PCI on RPI4 isn't working on real hardware since the pcie_brcmstb Linux kernel module doesn't support ACPI yet. Link: https://lore.kernel.org/r/20241023132116.970117-1-patrick.rudolph@9elements.com
2024-10-27arm: cpu: Add ACPI parking protocol supportPatrick Rudolph
On Arm platforms that use ACPI they cannot rely on the "spin-table" CPU bringup usually defined in the FDT. Thus implement the 'ACPI Multi-processor Startup for ARM Platforms', also referred to as 'ACPI parking protocol'. The ACPI parking protocol works similar to the spin-table mechanism, but the specification also covers lots of shortcomings of the spin-table implementations. Every CPU defined in the ACPI MADT table has it's own 4K page where the spinloop code and the OS mailbox resides. When selected the U-Boot board code must make sure that the secondary CPUs enter u-boot after relocation as well, so that they can enter the spinloop code residing in the ACPI parking protocol pages. The OS will then write to the mailbox and generate an IPI to release the CPUs from the spinloop code. For now it's only implemented on ARMv8, but can easily be extended to other platforms, like ARMv7. TEST: Boots all CPUs on qemu-system-aarch64 -machine raspi4b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2024-10-27drivers/arm: Implement acpi_fill_madtPatrick Rudolph
Fill the MADT table in the GIC driver and armv8 CPU driver to drop SoC specific code. While the GIC only needs devicetree data, the CPU driver needs additional information stored in the cpu_plat struct. While on it update the only board making use of the existing drivers and writing ACPI MADT in mainboard code. TEST: Booted on QEMU sbsa-ref using GICV3 driver model generated MADT. Booted on QEMU raspb4 using GICV2 driver model generated MADT. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org>
2024-10-27arm: lib: Add GICV2 driverPatrick Rudolph
Add a generic GICV2 driver that: - parses the DT and generates the ACPI MADT subtables - implement of_xlate() and allows irq_get_by_index() to return the correct interrupt mappings Map DT interrupts to ARM GIC interrupts as follows: - Interrupt numbers ID32-ID1019 are used for SPIs - ID0-ID15 are used for SGIs - ID16-ID31 are used for PPIs TEST: Booted on QEMU raspb4 using GICV2 driver model generated MADT. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-10-27arm: gic-v3-its: Implement of_xlatePatrick Rudolph
Translate IRQs by implementing of_xlate() as required by irq_get_by_index() to parse interrupt properties. Map DT interrupts to ARM GIC interrupts as follows: - Interrupt numbers ID32-ID1019 are used for SPIs - ID0-ID15 are used for SGIs - ID16-ID31 are used for PPIs TEST: Booted on qemu sbsa-ref that has a GICV3. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Moritz Fischer <moritzf@google.com>
2024-10-27arm: gic-v3-its: Rename objectsPatrick Rudolph
The code accesses the gic-v3 node, but not the gic-v3-its node, thus rename the objects to clarify which node it operates on. The following commit will make use of the gic-v3-its node for real. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2024-10-27acpi: Add fill_madt to acpi_opsPatrick Rudolph
Add a new method to acpi_ops to let drivers fill out ACPI MADT. The code is unused for now until drivers implement the new ops. TEST: Booted on QEMU sbsa using driver model generated MADT. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org>
2024-10-27arm: acpi: Add generic ACPI methodsPatrick Rudolph
Add generic ACPI code to generate - MADT GICC - MADT GICD - MADT GICR - MADT GIC ITS - PPTT processor - PPTT cache as commonly used on arm platforms. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org>
2024-10-11Merge patch series "Tidy up use of 'SPL' and CONFIG_SPL_BUILD"Tom Rini
Simon Glass <sjg@chromium.org> says: When the SPL build-phase was first created it was designed to solve a particular problem (the need to init SDRAM so that U-Boot proper could be loaded). It has since expanded to become an important part of U-Boot, with three phases now present: TPL, VPL and SPL Due to this history, the term 'SPL' is used to mean both a particular phase (the one before U-Boot proper) and all the non-proper phases. This has become confusing. For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL' phases, not just SPL. So code which can only be compiled for actual SPL, for example, must use something like this: #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) In Makefiles we have similar issues. SPL_ has been used as a variable which expands to either SPL_ or nothing, to chose between options like CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was updated to support 'VPL_' as well. This series starts a change in terminology and usage to resolve the above issues: - The word 'xPL' is used instead of 'SPL' to mean a non-proper build - A new CONFIG_XPL_BUILD define indicates that the current build is an 'xPL' build - The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now defined for TPL and VPL phases - The existing SPL_ Makefile variable is renamed to SPL_ - The existing SPL_TPL Makefile variable is renamed to PHASE_ It should be noted that xpl_phase() can generally be used instead of the above CONFIGs without a code-space or run-time penalty. This series does not attempt to convert all of U-Boot to use this new terminology but it makes a start. In particular, renaming spl.h and common/spl seems like a bridge too far at this point. The series is fully bisectable. It has also been checked to ensure there are no code-size changes on any commit.
2024-10-11global: Rename SPL_TPL_ to PHASE_Simon Glass
Use PHASE_ as the symbol to select a particular XPL build. This means that SPL_TPL_ is no-longer set. Update the comment in bootstage to refer to this symbol, instead of SPL_ Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11global: Rename SPL_ to XPL_Simon Glass
Use XPL_ as the symbol to indicate an SPL build. This means that SPL_ is no-longer set. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-11log: global: Rename warn_non_spl()Simon Glass
This should now refer to xPL rather than SPL, so update it throughout the tree. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-10-09efi: arm: x86: riscv: Drop crt0/relocal extra- rulesSimon Glass
The link rule (for $(obj)/%_efi.so) in scripts/Makefile.lib handles pulling in efi_crt0.o and efi_reloc.o so drop the 'extra' rules. Signed-off-by: Simon Glass <sjg@chromium.org> Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2024-10-09efi_loader: Rename and move CMD_BOOTEFI_HELLO_COMPILESimon Glass
This is not actually a command so the name is confusing. Use BOOTEFI_HELLO_COMPILE instead. Put it in the efi_loader directory with the other such config options. The link rule (for $(obj)/%_efi.so) in scripts/Makefile.lib handles pulling in efi_crt0.o and efi_reloc.o so drop the 'extra' rules. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-10-03arm: Fix up a stale comment in sections.cSimon Glass
There are currently four symbols here, so drop the word 'two'. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2024-10-03arm: cache: Drop a stale commentSimon Glass
This header includes more than just dummy functions, so drop this comment. Signed-off-by: Simon Glass <sjg@chromium.org>
2024-09-03Merge patch series "Make LMB memory map global and persistent"Tom Rini
Sughosh Ganu <sughosh.ganu@linaro.org> says: This is a follow-up from an earlier RFC series [1] for making the LMB and EFI memory allocations work together. This is a non-rfc version with only the LMB part of the patches, for making the LMB memory map global and persistent. This is part one of a set of patches which aim to have the LMB and EFI memory allocations work together. This requires making the LMB memory map global and persistent, instead of having local, caller specific maps. This is being done keeping in mind the usage of LMB memory by platforms where the same memory region can be used to load multiple different images. What is not allowed is to overwrite memory that has been allocated by the other module, currently the EFI memory module. This is being achieved by introducing a new flag, LMB_NOOVERWRITE, which represents memory which cannot be re-requested once allocated. The data structures (alloced lists) required for maintaining the LMB map are initialised during board init. The LMB module is enabled by default for the main U-Boot image, while it needs to be enabled for SPL. This version also uses a stack implementation, as suggested by Simon Glass to temporarily store the lmb structure instance which is used during normal operation when running lmb tests. This does away with the need to run the lmb tests separately. The tests have been tweaked where needed because of these changes. The second part of the patches, to be sent subsequently, would work on having the EFI allocations work with the LMB API's. [1] - https://lore.kernel.org/u-boot/20240704073544.670249-1-sughosh.ganu@linaro.org/T/#t Notes: 1) These patches are on next, as the alist patches have been applied to that branch. 2) I have tested the boot on the ST DK2 board, but it would be good to get a T-b/R-b from the ST maintainers. 3) It will be good to test these changes on a PowerPC platform (ideally an 85xx, as I do not have one).