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path: root/arch/arm/mach-snapdragon/qcom-priv.h
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2025-06-24mach-snapdragon: track boot sourceCaleb Connolly
Keep track of whether we were loaded via ABL or if U-Boot is running as a first-stage bootloader. For now we set this based on if we have a valid external FDT or not, since it isn't possible to chainload U-Boot from ABL without there being an external FDT. This will be used to inform the capsule update logic which partition U-Boot is flashed to. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org> Link: https://lore.kernel.org/r/20250411-b4-qcom-capsule-update-improvements-v2-1-27f6b2fcc4a9@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
2025-05-02mach-snapdragon: use EVT_OF_LIVE_INIT to apply DT fixupsCaleb Connolly
This will now apply fixups prior to devices being bound, which makes it possible to enable/disable devices and adjust more properties that might be read before devices probe. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-11-20mach-snapdragon: implement capsule update supportCaleb Connolly
Qualcomm boards flash U-Boot a variety of partitions, implement support for determining which slot U-Boot is running from, finding the correct partition for that slot and configuring the appropriate DFU string. Initially, we only support the RB3 Gen 2 where U-Boot is flashed to the UEFI partition, and ignore handling of slots. In the future we will additionally support booting U-Boot from other partitions (e.g. boot) and correct handling for A/B. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
2024-04-04mach-snapdragon: fixup USB nodesCaleb Connolly
We don't support USB super-speed in U-Boot yet, we lack the SS PHY drivers, however from my testing even with a PHY driver there seem to be other issues when talking to super-speed peripherals. In pursuit of maintaining upstream DT compatibility, and simplifying porting for new devices, let's implement the DT fixups necessary to configure USB in high-speed only mode at runtime. The pattern is identical for all Qualcomm boards that use the Synaptics DWC3 controller: * Add an additional property on the Qualcomm wrapper node * Remove the super-speed phy phandle and phy-name entries. Acked-by: Sumit Garg <sumit.garg@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>