| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-02-25 | arm: socfpga: agilex5: Enable cache flush for system memory cache in CCU | Tien Fong Chee | |
| set/way instructions "dc cisw" which is used by the "dcache flush" command only flushing CPU data caches from L1 -> L2 -> L3 to system memory cache in cache coherency unit, hence this patch enables data flush from system memory cache of CCU into DDR memory. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> | |||
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index : u-boot-toradex.git | |
| U-Boot bootloader for Apalis and Colibri modules | Toradex |
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