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path: root/arch/arm/mach-socfpga/include
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2025-06-14arch: use lowercase hex prefix styleE Shattow
Use consistent lowercase hex prefix style in arch/* Signed-off-by: E Shattow <e@freeshell.de>
2025-04-22arm: socfpga: soc64: Enable F2S bridge reset supportAlif Zakuan Yuslaimi
Enable reset support for FPGA2SDRAM bridge for Stratix10, as well as FPGA2SoC and SoC2FPGA bridges for all SoC64 families. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-04-22arm: socfpga: soc64: Update reset manager registers for F2S bridgeAlif Zakuan Yuslaimi
Add reset manager registers in preparation for F2S bridge reset support as well as the mask support to enable/disable the bridges. Mask value: BIT0: soc2fpga BIT1: lwhps2fpga BIT2: fpga2soc These bridges are available only in Stratix10: BIT3: f2sdram0 BIT4: f2sdram1 BIT5: f2sdram2 Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-04-22arm: socfpga: mailbox: Notify SDM on HPS code execution stagesAlif Zakuan Yuslaimi
Introducing a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device Manager (SDM) on the stage of HPS code execution. Generally, there are three main code execution stages: First Stage Boot Loader (FSBL) which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot, and the Operating System (OS) which is Linux. This enables the user to query the SDM for HPS error details. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25ddr: altera: Add DDR driver for Agilex5 seriesTingting Meng
Adding DDR driver support for Agilex5 series. Signed-off-by: Tingting Meng <tingting.meng@altera.com>
2025-02-25arm: socfpga: Export board ID as U-Boot environmentAlif Zakuan Yuslaimi
Board ID is exported as environment variable for use to boot Linux with FIT configuration. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25arm: socfpga: Add handoff data support for SoCFPGA Agilex5 deviceTien Fong Chee
Agilex5 supports both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and Agilex5 device. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25arm: socfpga: agilex5: Add warm reset mask for Agilex5Alif Zakuan Yuslaimi
There are 5 L4 watchdogs and one SDM triggered warm reset bit in Agilex5 reset manager "stat" register where bit 16:20 for L4 watchdogs. Assigning value 1 to these bits in the register address will initiate SDM to trigger warm reset. Introducing new warm reset mask for Agilex5 to trigger warm reset to all five L4 watchdogs. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-02-25arm: socfpga: agilex5: Add new driver model for system manager in Agilex5Tien Fong Chee
Initial creation of new system manager driver. Add supports for the SOCFPGA System Manager Register block which aggregates different peripheral function into one area. On 64 bit ARM parts, the system manager only can be accessed during EL3 mode, this driver model provide user the high level access to system register and abstract user from low level access. The base address of system manager can be retrieved using DT framework through the System Manager driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
2025-01-24fpga: intel_sdm_mb: add support for query SDM config error and statusBoon Khai Ng
Currently the FPGA reconfig status only return a single error status which make the debugging of FPGA reconfiguration hard. This patch is to expose the error status, major error code and minor error code, for the FPGA reconfig to upper layer app. Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2025-01-24arm: socfpga:agilex5: Fix system manager watchdog mode settingMuhammad Hazim Izzat Zamri
This commit is to fix the system manager watchdog mode setting to support until mode_4 for Agilex5. This changes can refer to system manager register map on wddbg fields. In Agilex7 it is not detected as an issue because Agilex7 only have 4 watchdog until mode_3 and it is already been set correctly for it to halt on any CPU in debug mode. However, in Agilex5 this fix is needed in order to enable the watchdog pause feature for mode_4 when entering debug mode. If 0xF is not been set on mode_4, the Watchdog Timers will not halt on any CPU. As by default value, the pause signal does not assert when any CPU is in debug mode and the watchdog continue to count. Signed-off-by: Muhammad Hazim Izzat Zamri <muhammad.hazim.izzat.zamri@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2024-10-11arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILDSimon Glass
Use the new symbol to refer to any 'SPL' build, including TPL and VPL Signed-off-by: Simon Glass <sjg@chromium.org>
2024-07-15arm: mach: socfpga: Remove duplicate newlinesMarek Vasut
Drop all duplicate newlines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07arm: socfpga: Add missing <linux/types.h>Tom Rini
This file has many "Linux" style types in it, add <linux/types.h> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-06arm: socfpga: Remove <common.h> and add needed includesTom Rini
Remove <common.h> from all mach-socfpga files and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
2024-03-18arch: arm: Agilex5 enablementJit Loon Lim
This patch is to enable Agilex5 platform for Intel product. Changes, modification and new files are created for board, dts, configs and makefile to create the base for Agilex5. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2024-01-11mach-socfpga: do not overlap defines with lwipMaxim Uvarov
Fix compilation issue with overlapping lwip and march defines. Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-17arm: socfpga: arria10: Enable double peripheral RBF configurationTien Fong Chee
Double peripheral RBF configuration are needed on some devices or boards to stabilize the IO configuration system. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBFTien Fong Chee
This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17arm: socfpga: arria10: Setting image magic value to romcode initswstate regTien Fong Chee
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID value if the current FSBL image is found valid, otherwise BootROM will look for next subsequent valid FSBL image when warm reset is triggered. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-30WS cleanup: remove SPACE(s) followed by TABWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-08-25ddr: altera: Add SDRAM driver for Intel N5X deviceTien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY, memory reset manager and memory clock manager. Configuration settings of controller, PHY and memory reset manager is come from DDR handoff data in bitstream, which contain the register base addresses and user settings from tool. Configuration settings of memory clock manager is come from the HPS handoff data in bitstream, however the register base address is defined in device tree. The calibration is fully done in HPS, which requires IMEM and DMEM binaries loading to PHY SRAM for running this calibration, both IMEM and DMEM binaries are also part of bitstream, this bitstream would be loaded to OCRAM by SDM, and configured by DDR driver. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25arm: socfpga: Add clock manager for Intel N5X deviceSiew Chin Lim
Add clock manager for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.hSiew Chin Lim
Move cm_get_mpu_clk_hz function declaration from individual device's clock manager header file to common clock_manager.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Add handoff data support for Intel N5X deviceTien Fong Chee
N5X support both HPS handoff data and DDR handoff data. Existing HPS handoff functions are restructured to support both existing devices and N5X device. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-24arm: socfpga: Add base address for Intel N5X deviceSiew Chin Lim
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.hSiew Chin Lim
Rename to common file name to used by all SOC64 devices and change "_S10_" to "_SOC64_" in base_addr_soc64.h. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: smc: Add function to get usercodeSiew Chin Lim
Add function to send mailbox command via SMC to get usercode from SDM. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Changed to store QSPI reference clock in kHzSiew Chin Lim
Changed to store QSPI reference clock in kHz instead of Hz in boot scratch cold0 register for Stratix10 and Agilex. This patch is in preparation for Intel N5X SDRAM driver support. Reserved 4 bits for Intel N5X SDRAM driver, and there will be 28 bits to store QSPI reference clock. Due to limited bits, QSPI reference clock frequency is converted to kHz from Hz. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-04-08arm: socfpga: Move Stratix10 and Agilex clock manager common codeSiew Chin Lim
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Restructure Stratix10 and Agilex handoff codeSiew Chin Lim
Restructure Stratix10 and Agilex handoff code to used by all SOC64 devices, in preparation to support handoff for Diamond Mesa. Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c which contains the generic function to parse the handoff data. Update system_manager_soc64.c to use generic handoff function in wrap_handoff_soc64.c. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08arm: socfpga: Rearrange sequence of macros in handoff_soc64.hSiew Chin Lim
Rearrange sequence of macros in handoff_soc64.h without any functionality change. In preparation for Stratix10 and Agilex handoff function restructuring. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08arm: socfpga: Rename Stratix10 and Agilex handoff common macrosSiew Chin Lim
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from S10_HANDOFF to SOC64_HANDOFF. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-15Merge tag 'v2021.04-rc4' into nextTom Rini
Prepare v2021.04-rc4
2021-03-08arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)Siew Chin Lim
Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-03-08arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-03-02reset: Remove addr parameter from reset_cpu()Harald Seiler
Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-15arm: socfpga: Add secure register access helper functions for SoC 64bitsSiew Chin Lim
These secure register access functions allow U-Boot proper running at EL2 (non-secure) to access System Manager's secure registers by calling the ATF's PSCI runtime services (EL3/secure). Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-01-15arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits)Chee Hong Ang
invoke_smc() allow U-Boot proper running in non-secure mode (EL2) to invoke SMC call to ATF's PSCI runtime services such as System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. smc_send_mailbox() is a send mailbox command helper function which invokes the ATF's PSCI runtime service (function ID: INTEL_SIP_SMC_MBOX_SEND_CMD) to send mailbox messages to Secure Device Manager (SDM). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-21arm: socfpga: fix Gen5 enable of EMAC via FPGARalph Siemsen
An earlier conversion from struct to defines introduced two errors, both related to setup of EMAC routed via the FPGA. One of the offsets was incorrect, and the EMAC0/EMAC1 were swapped. The effect of this was rather odd: both ports could operate at gigabit, but one of them would fail to transmit when operating at 100Mbit. Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines") Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: mailbox: Update mailbox response codesLey Foon Tan
Sync latest mailbox response codes from SDM firmware. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2020-10-09arm: socfpga: soc64: Document down boot_scratch_cold register usageChin Liang See
Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Show reset state in SPLChee Hong Ang
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-09arm: socfpga: soc64: Add SDM triggered warm reset bit maskChee Hong Ang
Include SDM triggered warm reset bit (BIT1) in Reset Manager's stat register when checking for HPS warm reset status. Refactor the warm reset mask macro for clarity purpose. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-09-03arm: socfpga: soc64: Check FPGA Config status register before bridge resetChee Hong Ang
Instead of querying SDM for FPGA configuration status through mailbox messages, U-Boot now checks System Manager's FPGA Config status register for FPGA configuration status before resetting bridge. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-07-01socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA caseTom Rini
Unless we mark the function as 'static inline' it may end up being non-inlined by the compiled and result in duplicate functions. Cc: Marek Vasut <marex@denx.de> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Vasut <marex@denx.de>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18Use __ASSEMBLY__ as the assembly macrosSimon Glass
Some places use __ASSEMBLER__ instead which does not work since the Makefile does not define it. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.2.3 (git 2.0.4) at 2025-07-26 08:10:57 +0000