| Age | Commit message (Expand) | Author |
|---|---|---|
| 2025-08-08 | ddr: altera: soc64: Fix dram size calculation in clamshell mode | Tingting Meng |
| 2025-08-08 | ddr: altera: soc64: Clean up bit-shift by zero bit | Tingting Meng |
| 2025-08-08 | ddr: altera: Add DDR driver for Agilex7 M-series | Tingting Meng |
| 2025-08-08 | ddr: altera: agilex: Get ACF from boot scratch register | Alif Zakuan Yuslaimi |
| 2025-02-25 | ddr: altera: Add DDR driver for Agilex5 series | Tingting Meng |
| 2023-12-21 | global: Drop common.h inclusion | Tom Rini |
| 2022-06-16 | ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS | Tien Fong Chee |
| 2021-08-25 | ddr: altera: Add SDRAM driver for Intel N5X device | Tien Fong Chee |
| 2020-12-13 | dm: treewide: Rename ..._platdata variables to just ..._plat | Simon Glass |
| 2020-07-17 | treewide: convert bd_t to struct bd_info by coccinelle | Masahiro Yamada |
| 2020-01-07 | ddr: altera: agilex: Add SDRAM driver for Agilex | Ley Foon Tan |
| 2020-01-07 | ddr: altera: Restructure Stratix 10 SDRAM driver | Ley Foon Tan |
