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path: root/drivers/mmc/fsl_esdhc_imx.c
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2025-03-13mmc: fsl_esdhc: Migrate ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE to KconfigTom Rini
The flag for enabling the ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE quirk can be handled easily enough in Kconfig. This lets us remove a function but not obviously correct usage of the IS_ENABLED() macro. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2024-10-25mmc: fsl_esdhc: Convert to use livetree API for fdt accessTim Harvey
Convert to using livetree API functions. Without this if livetree is enabled (OF_LIVE) the fsl_esdhc_imx driver will fail to read vendor-specific properties from the dt. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2024-10-04mmc: fsl_esdhc_imx: Reset tuning logicPeng Fan
When supporting partition reset for SoC such as i.MX95 , the Linux Kernel may have configured the tuning, while after force reset by wdog or else, uboot CMD0 will never pass unless config RSTT to reset tuning logic. Since RSTA and RSTT are independent, so need both to be reseted in the controller. Acked-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-10-04mmc: fsl_esdhc_imx: Avoid resource leakYe Li
The memory of priv and plat are leaked if max_bus_width is wrong. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-10-04mmc: fsl_esdhc_imx: Fix host_caps issue for non-DM driverYe Li
The plat->cfg is wrongly memset to 0, so the host_caps value configured in fsl_esdhc_initialize is reset. Remove the unnecessary memset since plat is allocated via calloc. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-10-04mmc: fsl_esdhc_imx: Send 80 clocks before IDLE commandYe Li
According to SD and MMC spec, 74 clocks must be sent to device after power stable. This is need in reinit ops for DM MMC or init ops for non-DM MMC after power cycle. So set the INTIA to send 80 clocks in esdhc_init_common and move its calling from probe to reinit. However, on 8MQ EVK and 8QXP MEK with some brands of SD cards, sending 80 clocks may not work well. The root cause is related with power up time. According to spec, after power stable, host shall supply at least 74 SD clocks to the SD card with the maximum of 1ms. However, the power ram up time is related with the characteristic of SD card. At the moment of sending 74 SD clocks, the power probably not ram up to the operating level on the problematic cards. Then cause the cards not ready. This patch changes to send SD clock with 1ms duration to replace 80 SD clocks (0.2ms at 400Khz clock). This way meets the spec requirement as well, and adds the margin for power ram up time to be compatible with the problematic SD cards. This is also aligned with implementation which has FORCE clock always on. Reviewed-and-tested-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-10-04mmc: fsl_esdhc_imx: Enable AHB/IPG clk with clk bulk APIPeng Fan
With partition reset supported for i.MX8QM/QXP/95 and etc, when linux mmc runtime suspended, the mmc clks are gated off. While at same time system controller reset Cortex-A cores because of various reasons( WDOG timeout and etc), with SPL run again, only enable PER clk is not enough, also need to enable AHB/IPG clk, here use clk bulk API to enable all the clocks. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2024-07-06mmc: fsl_esdhc_imx: Fix error messageAlexander Stein
Add missing newline character and also add the return code of regulator_set_value() to the output. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07mmc: Remove <common.h> and add needed includesTom Rini
Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07mmc: Migrate MMC_SUPPORTS_TUNING to KconfigTom Rini
The constraints on the MMC_SUPPORTS_TUNING symbol can easily be expressed in Kconfig (with the addition of SPL_MMC_SUPPORTS_TUNING). Furthermore, in order to remove <common.h> from the MMC subsystem, the way this symbol is used today needs to be changed in order to continue functioning. Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-04-15mmc: Drop unused mmc_send_tuning() cmd_error parameterMarek Vasut
The cmd_error parameter is not used, remove it. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2023-09-24common: Drop linux/printk.h from common headerSimon Glass
This old patch was marked as deferred. Bring it back to life, to continue towards the removal of common.h Move this out of the common header and include it only where needed. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-12-22Convert CONFIG_FSL_ESDHC_PIN_MUX to KconfigTom Rini
This converts the following to Kconfig: CONFIG_FSL_ESDHC_PIN_MUX Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-10global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespaceTom Rini
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-21mmc: fsl_esdhc: fix problem when using clk driverYe Li
Move init_clk_usdhc to non-clk driver case, since assigned-clocks properties will initialize the clocks by clk driver. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-06-15mmc: fsl_esdhc_imx: Implement wait_dat0 mmc opsLoic Poulain
Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time. Before (using grabserial): [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.028257 0.028257] DDRINFO: start DRAM init [0.028500 0.000243] DDRINFO: DRAM rate 3000MTS [0.304627 0.276127] DDRINFO:ddrphy calibration done [0.305647 0.001020] DDRINFO: ddrmix config done [0.352584 0.046937] SEC0: RNG instantiated [0.374299 0.021715] Normal Boot [0.374675 0.000376] Trying to boot from MMC2 [1.250580 0.875905] NOTICE: BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9 [1.251985 0.001405] NOTICE: BL31: Built : 08:02:40, Apr 12 2022 [1.522560 0.270575] [1.522734 0.000174] [1.522788 0.000054] U-Boot 2021.04-xxxx After: [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.001614 0.001614] DDRINFO: start DRAM init [0.002377 0.000763] DDRINFO: DRAM rate 3000MTS [0.278494 0.276117] DDRINFO:ddrphy calibration done [0.279266 0.000772] DDRINFO: ddrmix config done [0.338432 0.059166] SEC0: RNG instantiated [0.339051 0.000619] Normal Boot [0.339431 0.000380] Trying to boot from MMC2 [0.412587 0.073156] NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b [0.414191 0.001604] NOTICE: BL31: Built : 10:35:26, Apr 6 2022 [0.700685 0.286494] [0.700793 0.000108] [0.700845 0.000052] U-Boot 2021.04-xxxx Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-04-12mmc: fsl_esdhc_imx: Add i.MX8MP compatible stringMarek Vasut
Add compatible string for i.MX8MP, which permits i.MX8MP to use HS400ES mode, just like all the other i.MX8M. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@denx.de> Cc: Haibo Chen <haibo.chen@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-03-16mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessaryHaibo Chen
After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it involve issue in mmc_switch_voltage(), because of the special design of usdhc. For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits(Though RM contain the definition of these bits, but actually internal IC logic do not implement, already confirm with IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. Here is the definition of this bit in RM: [8] FRC_SDCLK_ON Force CLK output active Do not set this bit to 1 unless it is necessary. Also, make sure that this bit is cleared when uSDHC’s clock is about to be changed (frequency change, clock source change, or delay chain tuning). 0b - CLK active or inactive is fully controlled by the hardware. 1b - Force CLK active In default, the FRC_SDCLK_ON is 0. This means, when there is no command or data transfer on bus, hardware will gate off the card clock. But in some case, we need the card clock keep on. Take IO voltage 1.8v switch as example, after IO voltage change to 1.8v, spec require gate off the card clock for 5ms, and gate on the clock back, once detect the card clock on, then the card will draw the dat0 to high immediately. If there is not clock gate off/on behavior, some card will keep the dat0 to low level. This is the reason we fail in mmc_switch_voltage(). To fix this issue, and concern that this is only the fsl usdhc hardware design limitation, set the bit FRC_SDCLK_ON in the beginning of the wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage switch process align with SD specification. For standard tuning process, usdhc specification also require the card clock keep on, so also add these behavior in fsl_esdhc_execute_tuning(). Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-19mmc: fsl_esdhc_imx: correct the actual card clockHaibo Chen
The original code logic can not show the correct card clock, and also has one risk when the div is 0. Because there is div -=1 before. So move the operation before div -=1, and also involve ddr_pre_div to get the correct value. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Marek Vasut <marex@denx.de>
2022-02-19mmc: fsl_esdhc_imx: remove redundant ARCH_MXCHaibo Chen
Now original fsl_esdhc.c are split as fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c only cover i.MX SoC. So ARCH_MXC is redundant. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Marek Vasut <marex@denx.de>
2022-02-19mmc: fsl_esdhc_imx: Use esdhc_soc_data flags to set host capsAdam Ford
The Linux driver automatically can detect and enable UHS, HS200, HS400 and HS400_ES automatically without extra flags being placed into the device tree. Right now, for U-Boot to use UHS, HS200 or HS400, the extra flags are needed in the device tree. Instead, go through the esdhc_soc_data flags and enable the host caps where applicable to automatically enable higher speeds. Suggested-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Adam Ford <aford173@gmail.com>
2022-02-09Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- Fix an issue with fsl_esdhc_imx - Consider GP partitions in "mmc hwpartition user enh start -"
2022-02-08mmc: fsl: Use brackets around if()Simon Glass
At present the IS_ENABLED() macro has extra brackets, making it possible to write: if IS_ENABLED(CONFIG_XXX) but it is a bit confusing. Add the missing brackets. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-02-09mmc: fsl_esdhc_imx: fix watermark level in dmaMarcel Ziswiler
Seems that we need the waterlevel setting not only for PIO mode as without this at least the i.MX 8M Mini won't boot anymore when being written by such a U-Boot. Corruption has also been observed both on the i.MX 6 as well as i.MX 8M Mini when using ums on the eMMC. Fix this by setting the watermark level again regardless of whether in DMA or PIO mode. Fixes: 41c6a22fc296 ("mmc: fsl_esdhc_imx: simplify esdhc_setup_data()") Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Tested-by: Fabio Estevam <festevam@gmail.com>
2022-01-12mmc: fsl_esdhc_imx: set sysctl register for clock initializationSean Anderson
[ fsl_esdhc commit 263ddfc3454ead3a988adef39b962479adce2b28 ] The initial clock setting should be through sysctl register only, while the mmc_set_clock() will call mmc_set_ios() introduce other configurations like bus width, mode, and so on. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-01-12mmc: fsl_esdhc_imx: Replace more #ifdefs by ifSean Anderson
This builds on the previous patch by converting yet more preprocessor macros to C ifs. This is split off so that the changes adapted from Micheal's patch may be clearly distinguished from the ones I have authored myself. MMC_SUPPORTS_TUNING should really get a Kconfig conversion. And DM_GPIO needs some -ENOSYS stubs when it isn't defined. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-01-12mmc: fsl_esdhc_imx: replace most #ifdefs by IS_ENABLED()Sean Anderson
[ fsl_esdhc commit 52faec31827ec1a1837977e29c067424426634c5 ] Make the code cleaner and drop the old-style #ifdef constructs where it is possible. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-01-12mmc: fsl_esdhc_imx: simplify esdhc_setup_data()Sean Anderson
[ fsl_esdhc commit 7e48a028a42c111ba38a90b86e5f57dace980fa0 ] First, we need the waterlevel setting for PIO mode only. Secondy, both DMA setup code is identical for both directions, except for the data pointer. Thus, unify them. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12mmc: fsl_esdhc_imx: use dma-mapping APISean Anderson
[ fsl_esdhc commit b1ba1460a445bcc67972a617625d0349e4f22b31 ] Use the dma_{map,unmap}_single() calls. These will take care of the flushing and invalidation of caches. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12mmc: fsl_esdhc_imx: simplify 64bit check for SDMA transfersSean Anderson
[ fsl_esdhc commit da86e8cfcb03ed5c1d8e0718bc8bc8583e60ced8 ] SDMA can only do DMA with 32 bit addresses. This is true for all architectures (just doesn't apply to 32 bit ones). Simplify the code and remove unnecessary CONFIG_FSL_LAYERSCAPE. Also make the error message more concise. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12mmc: fsl_esdhc_imx: fix mmc->clock with actual clockSean Anderson
[ fsl_esdhc commit 30f6444d024a74ee48aa6969c1531aecd3c59deb ] Fix mmc->clock with actual clock which is divided by the controller, and record it with priv->clock. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12mmc: fsl_esdhc_imx: drop redundant code for non-removable featureSean Anderson
[ fsl_esdhc commit commit 08197cb8dff7cd097ab07a325093043c39d19bbd ] Drop redundant code for non-removable feature. "non-removable" property has been read in mmc_of_parse(). Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> [ set MMC_CAP_NONREMOVABLE in plat->cfg.host_caps ] Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-01-12mmc: fsl_esdhc_imx: clean up bus width configuration codeSean Anderson
[ fsl_esdhc commit 07bae1de382723b94244096953b05225572728cd ] This patch is to clean up bus width setting code. - For DM_MMC, remove getting "bus-width" from device tree. This has been done in mmc_of_parse(). - For non-DM_MMC, move bus width configuration from fsl_esdhc_init() to fsl_esdhc_initialize() which is non-DM_MMC specific. And fix up bus width configuration to support only 1-bit, 4-bit, or 8-bit. Keep using 8-bit if it's not set because many platforms use driver without providing max bus width. - Remove bus_width member from fsl_esdhc_priv structure. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> [ converted if statement to switch ] Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12mmc: fsl_esdhc_imx: fix voltage validationSean Anderson
[ fsl_esdhc commit 5b05fc0310cd933acf76ee661577c6b07a95e684 ] Voltage validation should be done by CMD8. Current comparison between mmc_cfg voltages and host voltage capabilities is meaningless. So drop current comparison and let voltage validation is through CMD8. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12mmc: fsl_esdhc_imx: remove redundant DM_MMC checkingSean Anderson
[ fsl_esdhc commit 2913926f3b3dec282f8773e3c02377c9600d8267 ] Remove redundant DM_MMC checking which is already in DM_MMC conditional compile block. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2022-01-12mmc: fsl_esdhc_imx: make BLK as hard requirement of DM_MMCSean Anderson
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already support it, so let's force to use it. - Drop non-BLK support for DM_MMC introduced by below patch. 66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled - Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC). - Use DM_MMC instead of BLK for conditional compile. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Sean Anderson <sean.anderson@seco.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-10-07mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULPOleksandr Suvorov
Import HS400 support for iMX7ULP B0 from the Linux kernel: 2eaf5a533afd ("mmc: sdhci-esdhc-imx: Add HS400 support for iMX7ULP") According to IC suggest, need to clear the STROBE_DLL_CTRL_RESET before any setting of STROBE_DLL_CTRL register. USDHC has register bits(bit[27~20] of register STROBE_DLL_CTRL) for slave sel value. If this register bits value is 0, it needs 256 ref_clk cycles to update slave sel value. IC suggest to set bit[27~20] to 0x4, it only need 4 ref_clk cycle to update slave sel value. This will short the lock time of slave. i.MX7ULP B0 will need more time to lock the REF and SLV, so change to add 5us delay. Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-10-07mmc: fsl_esdhc_imx: initialize data for imx7ulpJorge Ramirez-Ortiz
Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel. Set supported by u-boot flags only. Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io> Signed-off-by: Ricardo Salveti <ricardo@foundries.io> Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2021-10-07mmc: fsl_esdhc_imx: Fix clock disable issueYe Li
The SD clock disable is wrapped by MMC_SUPPORTS_TUNING. So it only works when UHS is enabled. However, in SD initialization the power cycle does not depends on UHS. But the power cycle needs disable the SD clock before power down. So this causes a problem when UHS is not enabled. Some cards can't become ready (ACMD14 timeout) due to the clock is enabled during power cycle. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-09-25treewide: Try to avoid the preprocessor with OF_REALSimon Glass
Convert some of these occurences to C code, where it is easy to do. This should help encourage this approach to be used in new code. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25treewide: Use OF_REAL instead of !OF_PLATDATASimon Glass
Now that we have a 'positive' Kconfig option, use this instead of the negative one, which is harder to understand. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-09drivers: mmc: fsl_esdhc_imx: support i.MX8ULPPeng Fan
i.MX8ULP reuse same SDHC IP as i.MX8M, so follow i.MX8M code logic. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-06-22Revert "mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card ↵Fabio Estevam
clock output" This reverts commit 63756575b42b8b4fb3f59cbbf0cedf03331bc2d2. Since this commit a imx6qdl-pico board boots extremely slowly in both SPL as well as U-Boot proper. Fix this regression by reverting the offending commit for now. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Pierre-Jean Texier <texier.pj2@gmail.com>
2021-06-22mmc: fsl_esdhc_imx: use mmc_send_cmd instead of dm_mmc_send_cmdJaehoon Chung
Use mmc_send_cmd instead of dm_mmc_send_cmd. It doesn't need to distinguish this function. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-06-17mmc: fsl_esdhc_imx: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33Yangbo Lu
There is no i.MX board using such option. Drop it. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-04-08mmc: fsl_esdhc_imx: add extra delay for IO voltage switch if necessaryHaibo Chen
Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need around 18ms, common code only delay 10ms, so need to delay extra 8ms. Otherwise voltage switch will timeout when wait for data0 line. This IO voltage switch time depends on board design, depend on the PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF capacitance. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2021-04-08mmc: fsl_esdhc_imx: remove redundant cmd11 related code.Haibo Chen
Common code already handle the voltage switch sequence based on spec, so remove the redundant voltage switch code. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2021-04-08mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock outputHaibo Chen
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"), we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON, after CMD11, hardware will gate off the card clock automatically, so card do not detect the clock off/on behavior, so will draw the data0 line low until next command. Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support") Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
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