summaryrefslogtreecommitdiff
path: root/drivers/mmc
AgeCommit message (Collapse)Author
9 dayssunxi: mmc: add support for Allwinner A523 MMC mod clockAndre Przywara
The Allwinner A523 SoC has a slightly changed mod clock, where the P factor, formerly a shift value, is now a second divider value. Also the input clock is not PLL_PERIPH0 (600MHz) anymore, but PLL_PERIPH0_400M (for MMC0/1), so adjust the input rate calculation accordingly. MMC2 has a different set of parents, so the input clock is 800 MHz there. Adjust for all of this. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
12 daysFix emmc error state after mmc write timeoutIulian Banaga
This is a fix for the sporadic mmc write failure: mmc write failed 0 blocks written: ERROR After this happens the emmc will remain in an error state where subsequent read/writes fail with a timeout. The mmc driver sends CMD25 - WRITE_MULTIPLE_BLOCK which can sporadically timeout. When this happens, the mmc driver aborts the transfer and returns the above error messages. But the emmc still remains in data transfer mode, since the timeout was decided by uboot, not by the emmc. Fix this by sending the STOP_TRANSMISSION command (CMD12) and waiting for the emmc to be in ready state again (CMD13). Transferring data blocks after a CMD25 can take anywhere between 5 and +15s on Samsung EMMCs and the current timeout is not enough. Increase the timeout by 2x to accommodate the long transfer times observed. Signed-off-by: Iulian Banaga <iulianeugen.banaga@mobileye.com> Acked-by: Jimmy Durand Wesolowski <jimmy.wesolowski@mobileye.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
12 daysmmc: exynos_dw_mmc: add exynos5420 compatiblesJaehoon Chung
The exynos5420 DTSes in linux kernel uses the compatibles samsung,exynos5420-dw-mshc{,-smu} instead of just samsung,exynos-dwmmc. Match the additional compatibles in the driver to make it possible to use it with DTSes from Linux kernel. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> [ grimler: rebase after clksel reg abstraction and re-write commit message ] Signed-off-by: Henrik Grimler <henrik@grimler.se> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
12 daysmmc: s5p_sdhci: add samsung,exynos4210-sdhci compatibleHenrik Grimler
the Exynos4210 devices in u-boot uses samsung,exynos4412-sdhci as sdhci compatible in their DTSes, while the upstream DTSes uses samsung,exynos4210-sdhci. Add samsung,exynos4210-sdhci compatible string for s5p_sdhci driver as well so that it can be used with upstream DTSes. Signed-off-by: Henrik Grimler <henrik@grimler.se> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
12 daysmmc: s5p_sdhci: remove duplicated card detect codeHenrik Grimler
The common sdhci infrastructure is already parsing the cd-gpios property, since commit 451931ea7002 ("mmc: sdhci: Read cd-gpio from devicetree"). The s5p code is therefore duplicated, and also broken since it assumes that the GPIO value is inverted, while the sdhci code correctly follows the ACTIVE_LOW/ACTIVE_HIGH flag specified in the device tree. This fix was originally authored by Simon Shields: https://github.com/fourkbomb/u-boot/commit/2eac9dea7903 The change has been tested on exynos4210-i9100, a device similar to exynos4210-trats. Signed-off-by: Henrik Grimler <henrik@grimler.se> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17Merge tag 'u-boot-imx-master-20250717' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27088 - Add support for the i.MX95 B0 version. - Enable standard boot for phycore-imx8mp. - Kconfig fixes for i.MX MMC and FSL_SEC_MON. - Support 4Gb single die variant of the i.MX8MM Venice board.
2025-07-17mmc: Remove unused kona_sdhci driverTom Rini
As no platforms use this driver anymore, remove it. Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17mmc: Tighten some mmc driver dependenciesTom Rini
A large number of mmc drivers cannot build without access to some platform specific header files. Express those requirements in Kconfig as well. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17mmc: Take cleanup path to free memory on error exitAndrew Goodbody
Instead of returning -EINVAL directly which will not call the cleanup path to free memory, fix the code to set the error and then goto the cleanup code. This issue found by Smatch. Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-17arm: imx: Remove unused mxcmmc driverTom Rini
As no platforms use this driver anymore, remove it. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-07-08mmc: zynq_sdhci: Reset the host controllerVenkatesh Yadav Abbarapu
Reset the host controller at the early stage of probe so that the configuration will be done properly for reboot cases. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20250626062440.295301-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
2025-07-02mmc: socfpga_dw_mmc: Retrieve clock manager address via DTAlif Zakuan Yuslaimi
Update the MMC driver to retrieve the clock manager base address via probing the clock manager node in the device tree. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-07-02Revert "drivers: mmc: rpmb: Use R1 response"Jan Kiszka
This reverts commit ae93d8106bdb5926efef9222d553adb295ebce96. It is no longer needed since 24b1e0c7e2e3. Since the obsolete include pulled in byteorder.h which is needed by now, include this one directly. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-06-20Merge patch series "Consistent Kconfig environment options CONFIG_ENV_ prefix"Tom Rini
Marek Vasut <marek.vasut+renesas@mailbox.org> says: Rename the environment related variables and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Link: https://lore.kernel.org/r/20250609192701.20260-1-marek.vasut+renesas@mailbox.org
2025-06-20env: Rename SYS_MMC_ENV_DEV to ENV_MMC_DEVICE_INDEXMarek Vasut
Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Use ENV_MMC_DEVICE_INDEX to clarify this is the SD/MMC device index, a number, as enumerated by U-Boot. Update the help text accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2025-06-16Merge tag 'u-boot-dfu-next-20250616' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-dfu into next u-boot-dfu-next-20250616 CI: https://source.denx.de/u-boot/custodians/u-boot-dfu/-/pipelines/26704 Usb gadget: - Fix ti_musb driver in gadget mode (with DM_USB_GADGET) DFU: - mmc/scsi backends when using 10 or more partitions
2025-06-14Merge patch series "Hex value prefix case cleanup"Tom Rini
E Shattow <e@freeshell.de> says: Make consistent use of lowercase hexadecimal prefix '0x' throughout U-Boot. There are a few remaining uses of uppercase 'X' to denote hexadecimal prefix or placeholder in documentation and error messages. External devicetree-rebasing dts/upstream and the generated code of xilinx/zynq are ignored for the series. Link: https://lore.kernel.org/r/20250606224558.1117422-1-e@freeshell.de
2025-06-14drivers: use lowercase hex prefix styleE Shattow
Use consistent lowercase hex prefix style in drivers/* Does not change hex prefix case in allcaps uppercase style error messages Signed-off-by: E Shattow <e@freeshell.de>
2025-06-11mmc: Kconfig: Really correct dependencies SDHCI ADMA optionsTom Rini
When doing the investigation for commit 53bb8fdea12a ("mmc: Kconfig: Correct dependencies SDHCI ADMA options") I missed the implications of MMC_SDHCI_ADMA_HELPERS. The problem is that FSL_ESDHC via the FSL_ESDHC_SUPPORT_ADMA2 option will also enable these helper functions. This in turn means the correct dependency here is MMC_SDHCI_ADMA_HELPERS and not *MMC_SDHCI_ADMA. Reported-by: Heiko Thiery <heiko.thiery@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2025-06-09Merge tag 'v2025.07-rc4' into nextTom Rini
Prepare v2025.07-rc4
2025-06-04mmc: am654_sdhci: Clear UHS_MODE_SELECT when <= MMC_HS_52Judith Mendez
This clears UHS_MODE_SELECT for timing modes <= MMC_HS_52. When initializing to HS400 mode, the host controller downgrades to non-uhs modes so clear UHS_MODE_SELECT at modes <= MMC_HS_52. This fixes eMMC writes on j7200 EVM. Fixes: 6067aa66b3bb ("mmc: am654_sdhci: Add am654_sdhci_set_control_reg") Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2025-06-02Merge patch series "Audit include list for include/[a-m]*.h"Tom Rini
Tom Rini <trini@konsulko.com> says: Hey all, Related to my other series I've posted recently on cleaning up some headers, this series here is the result of at least lightly auditing the #includes used in include/[a-m]*.h. This ignores subdirectories, as at least in part I think the top-level includes we've constructed are the most likely places to have some extra transitive include paths. I'm sure there's exceptions and I'll likely audit deeper once this first pass is done. This only gets as far as "include/m*.h" because I didn't want this to get too big. This also sets aside <miiphy.h> and <phy.h>. While miiphy.h does not directly need <phy.h> there are *so* many users and I think I had half of the tree just about not building when I first tried. It might be worth further investigation, but it might just be OK as-is. Link: https://lore.kernel.org/r/20250521230119.2084088-1-trini@konsulko.com
2025-06-02include/mmc.h: Audit include listTom Rini
This file does not need <linux/sizes.h> nor <linux/compiler.h> so remove them. This exposes however that a number of other files had been relying on this implicit include for <linux/sizes.h> so add that where needed. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-05-20mmc: cv1800b: Fix build without MMC_SUPPORTS_TUNINGAlexander Sverdlin
That's how it looks like without CONFIG_MMC_SUPPORTS_TUNING before the patch: aarch64-buildroot-linux-gnu-ld.bfd: drivers/mmc/cv1800b_sdhci.o: in function `cv1800b_execute_tuning': drivers/mmc/cv1800b_sdhci.c:47:(.text.cv1800b_execute_tuning+0x50): undefined reference to `mmc_send_tuning' Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-28sunxi: mmc: remove usage of struct sunxi_ccm_regAndre Przywara
The Allwinner MMC code uses a complex C struct, modelling the clock device's register frame. We rely on sharing the member names across all Allwinner SoCs, which is fragile. Drop the usage of the struct in the MMC code, by using #define'd register names and their offset, and then adding those names to the base pointer. This requires to define those offsets for all SoCs, but since we only use between four and six clock registers in the MMC code, this is easily done. This removes one common user of the clock register struct. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-04-24Merge patch series "More MMC fixes"Tom Rini
Judith Mendez <jm@ti.com> says: This patch series fixes MMC_HS_52 mode in am654_sdhci driver, as well as HIGH_SPEED_ENA and UHS_MODE_SELECT for HS modes. Also add TI_COMMON_CMD_OPTIONS to K3 Sitara board a53 defconfigs. Link: https://www.ti.com/lit/er/sprz574a/sprz574a.pdf Link: https://lore.kernel.org/r/20250417234334.3661321-1-jm@ti.com
2025-04-24mmc: am654_sdhci: Add am654_sdhci_set_control_regJudith Mendez
This patch adds am654_sdhci_set_control_reg to am654_sdhci. This is required to fix UHS_MODE_SELECT for TI K3 boards. If any of HIGH_SPEED_ENA, V1P8_SIGNAL_ENA, UHS_MODE_SELECT are set, then data will be launched on the pos-edge of the clock. Since K3 SoCs did not meet timing requirements for High Speed SDR mode at rising clock edge, none of these three should be set, therefore limit UHS_MODE_SELECT to only be set for modes above MMC_HS_52. This fixes MMC write issue on am64x evm at mode High Speed SDR. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-04-24mmc: am654_sdhci: Fix HIGH_SPEED_ENAJudith Mendez
High Speed enable bit switches data launch from the falling clock edge (half cycle timing) to the rising clock edge (full cycle timing). For all SD UHS modes, data launch must happen at the rising clock edge, so set HIGH_SPEED_ENA for SDR12 and SDR25 modes. For all HS modes, data launch must happen at the falling clock edge, so do not set HIGH_SPEED_ENA for MMC_HS_52. Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-04-24mmc: am654_sdhci: Add MMC_HS_52 to timing dataJudith Mendez
This patch adds MMC_HS_52 to the timing data structure. Previously, this bus mode tap settings were not populated and were instead populated for MMC_HS which is a different bus mode up to 26MHz. Since we intended these settings according to the device data sheet[0] for MMC_HS_52 up to 52MHz, populate MMC_HS tap settings for MMC_HS_52. While we are here, fix typo in ti,itap-del-sel-mms-hs. [0] https://www.ti.com/lit/ds/symlink/am625.pdf Table 7-79 Signed-off-by: Judith Mendez <jm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com>
2025-04-23Merge tag 'u-boot-rockchip-20250423' of ↵Tom Rini
https://source.denx.de/u-boot/custodians/u-boot-rockchip CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/25909 Please pull the updates for rockchip platform: - New SoC support: RK3528, RK3576 - New Board support: rk3528 Radxa E20C, rk3576 Firefly ROC-RK3576-PC; - Add generic board for rk3288 and rk3399; - rng driver binding update; - misc updates on board level or header files;
2025-04-23mmc: rockchip_dw_mmc: Add support for rk3576Heiko Stuebner
The rk3576 uses a different base-compatible, as starting with this generation, the clock phase tuning is done via registers inside the mmc controller and not from inside the CRU. In U-Boot we do not tune at all, so no other code changes are necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23mmc: rockchip_sdhci: Add support for RK3576Heiko Stuebner
Add support for RK3576 to the rockchip sdhci driver. It's pretty similar to its cousins found in the RK3568 and RK3588 and the specific hs400-tx-tap number was taken from the vendor-u-boot. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23mmc: rockchip_sdhci: Gate clock for glitch free phase switchingJonas Karlman
Enable clock stopping to gate clock during phase code change to ensure glitch free phase switching in auto-tuning circuit. Fixes HS200 mode on RK3528. POST_CHANGE_DLY Time taken for phase switching and stable clock output. - Less than 4-cycle latency PRE_CHANGE_DLY Maximum Latency specification between transmit clock and receive clock. - Less than 4-cycle latency TUNE_CLK_STOP_EN Clock stopping control for Tuning and auto-tuning circuit. When enabled, clock gate control output is pulled low before changing phase select codes. This effectively stops the receive clock. Changing phase code when clocks are stopped ensures glitch free phase switching. - Clocks stopped during phase code change Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23mmc: rockchip_sdhci: Add initial support for RK3528Jonas Karlman
Add initial support for SDHCI controller in RK3528. Only MMC Legacy and MMC High Speed (52MHz) mode is supported after this, more work is needed to get the faster HS200/HS400/HS400ES modes working. Variant tap and delay num is copied from vendor Linux tag linux-6.1-stan-rkr5. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23mmc: rockchip_sdhci: Extend variant configurationJonas Karlman
RK3528 and RK3576 use different tap and delay num for cmdout and strbin. Move tap and delay num for cmdout and strbin to driver data to prepare for adding new SoCs. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2025-04-23mmc: omap_hsmmc: implement send_init_stream callbackMathieu Othacehe
This callback is used to send the 74 clock cycles after power up. Signed-off-by: Mathieu Othacehe <othacehe@gnu.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-23mmc: Add a new callback function to perform the 74 clocks cycle sequenceJean-Jacques Hiblot
Add a new callback function *send_init_stream* which start a sequence of at least 74 clock cycles. The mmc core uses *mmc_send_init_stream* in order to invoke the callback function. This will be used during power cycle where the specification requires such a sequence after power up. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-23mmc: type 'Relatvie'Heinrich Schuchardt
%s/Relatvie/Relative' Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-16mmc: mediatek: permit to also build for Airoha archChristian Marangi
Airoha new SoC implement the same Mediatek driver for MMC. Permit to also build for Airoha arch. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2025-04-11Merge patch series "Switch to using $(PHASE_) in Makefiles"Tom Rini
Tom Rini <trini@konsulko.com> says: This series switches to always using $(PHASE_) in Makefiles when building rather than $(PHASE_) or $(XPL_). It also starts on documenting this part of the build, but as a follow-up we need to rename doc/develop/spl.rst and expand on explaining things a bit. Link: https://lore.kernel.org/r/20250401225851.1125678-1-trini@konsulko.com
2025-04-11Kbuild: Always use $(PHASE_)Tom Rini
It is confusing to have both "$(PHASE_)" and "$(XPL_)" be used in our Makefiles as part of the macros to determine when to do something in our Makefiles based on what phase of the build we are in. For consistency, bring this down to a single macro and use "$(PHASE_)" only. Signed-off-by: Tom Rini <trini@konsulko.com>
2025-04-11mmc: mmc_boot: Support Sandisk and Micron eMMC BOOT/RPMB hardware partition ↵Luke Wang
resizing Current mmc bootpart-resize command only support Samsung eMMC BOOT/RPMB hardware partition resizing. Add Sandisk and Micron eMMC BOOT/RPMB hardware partition resizing support. The commands and parameters for resizing partitions are different for each manufacturer. Select the corresponding function according to CID. Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-11mmc: Avoid uniniting twiceSimon Glass
Each MMC device has a child which ihs a block device. At present we call mmc_deinit() when the block device is removed. But the MMC struct (i.e. struct mmc) is attached to the MMC's device, not its child. So at present, when an MMC device is removed, mmc_deinit() is called twice, once for the MMC device and once for its block device. This results in a double call to cyclic_unregister(). Fix this by adding a 'remove' method to the uclass and calling mmc_deinit() from there. Also drop the call to device_probe() within the block-device's probe() method. The device is already in the process of being probed, so this call does nothing. Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: c822c1a50bd ("mmc: call device_probe() after scanning") Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-11mmc: sdhci: Fix possible Synchronous Abort using PIO modeJonas Karlman
When MMC_SDHCI_SDMA=y or MMC_SDHCI_ADMA=y and PIO mode is used dma_unmap_single() is called on an unmapped address, 0x0. This may result in a Synchronous Abort: ## Checking hash(es) for Image atf-1 ... sha256+ OK CMD_SEND:16 ARG 0x00000200 MMC_RSP_R1,5,6,7 0x00000900 CMD_SEND:18 ARG 0x00004005 "Synchronous Abort" handler, esr 0x96000147 elr: 00000000400015bc lr : 0000000040012b4c x 0: 0000000000008000 x 1: 0000000000092600 x 2: 0000000000000040 x 3: 000000000000003f x 4: 0000000000000030 x 5: 0000000000000001 x 6: 0000000000000001 x 7: 0000000000000000 x 8: 000000000000000a x 9: 0000000000000090 x10: 0000000043dffc68 x11: 0000000043c00440 x12: 0000000043c00440 x13: ffffffffbfe00000 x14: 000000000000031c x15: 0000000240000000 x16: 000000004001145c x17: 0000000000000032 x18: 0000000043dffef0 x19: 0000000043c00000 x20: 0000000043dffbc8 x21: 0000000000000000 x22: 00000000000f3d95 x23: 0000000000000002 x24: 0000000000000493 x25: 0000000000092600 x26: 0000000000000001 x27: 0000000000000001 x28: 0000000000000008 x29: 0000000043dffab0 Code: d2800082 9ac32042 d1000443 8a230000 (d5087620) Resetting CPU ... resetting ... Fix this by only dma_unmap_single() when DMA mode is used and sdhci_prepare_dma() has been called to map host->start_addr. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-11mmc: Optimize eMMC erase speedPeng Fan
Per JESD84-B51 6.6.9 Erase: The host can erase a contiguous range of Erase Groups. Starting the erase process is a three steps sequence. First the host defines the start address of the range using the ERASE_GROUP_START (CMD35) command, next it defines the last address of the range using the ERASE_GROUP_END (CMD36) command and finally it starts the erase process by issuing the ERASE (CMD38) command with argument bits set to zero. See Table 11 for the arguments supported by CMD38. The address field in the erase commands is an Erase Group address, in byte units for densities up to 2GB, and in sector units for densities greater than 2GB. The Device will ignore all LSB's below the Erase Group size, effectively rounding the address down to the Erase Group boundary. So choose 2GB bytes as check condition. If the erase size is larger that 2GB, use 2GB to avoid breaking non high capacity cards. If erase size is less than 2GB and larger than a grp, use 'grpcnt * mmc->erase_grp_size' to cover all the sectors, else use the number of sectors. With test erasing 20GB eMMC board: Evk_8ulp Evk_8mm Evk_8mn Evk_8mp Mek_8qxpc0 Mek_8qm kingston sandisk before: 37.683s 112.738s 129.365s 28.238s 112.605s 500.470s 490.708s after: 0.093s 0.111s 0.951s 0.080s 0.121s 6.960s 6.915s Tested-by: Faqiang Zhu <faqiang.zhu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-11mmc: Exit from mmc_init() if mmc_complete_init() failsMarek Vasut
In case mmc_complete_init() returns error, exit from mmc_init() without possibly calling cyclic_register(), which at that point would be undesired. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-11mmc: Simplify poll CD logic in case cyclic framework is enabledMarek Vasut
Simplify 90cc07fd786d ("mmc: Poll CD in case cyclic framework is enabled") according to suggestions by Rasmus. The struct cyclic_info is zero-size in case CONFIG_CYCLIC is not enabled and does not add any size to struct mmc, so it can unconditionally be part of that structure. This allows clean up of all the other conditionals in mmc.c which can now be unconditionally present, as they also add no extra space. Suggested-by: Rasmus Villemoes <ravi@prevas.dk> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2025-04-11mmc: Kconfig: Correct dependencies SDHCI ADMA optionsTom Rini
The option MMC_SDHCI_ADMA_FORCE_32BIT is only tested or used when MMC_SDHCI_ADMA or SPL_MMC_SDHCI_ADMA is enabled. And for MMC_SDHCI_ADMA_64BIT the same is true except we also require MMC_SDHCI_ADMA_FORCE_32BIT to be disabled. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Peng Fan <peng.fan@nxp.com>
2025-03-27sunxi: mmc: Improve reset procedureJernej Skrabec
Cards should always be reset and threshold set. This fixes eMMC on H616. Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> [Andre: use macro-defined offsets to fix build on older SoCs] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2025-03-27sunxi: mmc: Fix T113-s3 MMC clock dividerAndre Przywara
On the Allwinner D1/R528/T113-s3 SoCs the MMC clock source selected by mux value 1 is PLL_PERIPH0(1x), not (2x), as in the other SoCs. But we have still the hidden divisor of 2 in the MMC mod clock, so need to explicitly compensate for that on those SoCs. This leads to the actually programmed clock rate to be double compared to before, which increases the MMC performance on those SoCs. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reported-by: Kuba Szczodrzyński <kuba@szczodrzynski.pl> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.2.3 (git 2.0.4) at 2025-08-05 14:16:23 +0000