| Age | Commit message (Collapse) | Author |
|---|
|
Transmission of short packets does not work good for XFI (GDM2) and
HSGMII (GDM3) interfaces. The issue can be solved with:
- padding of short packets to 60 bytes
- setting of PAD_EN bit in the corresponding REG_GDM_FWD_CFG(n)
register.
The issue should present for the lan switch (GDM1) as well, but it does
does not appear due to unknown reason.
This patch set PAD_EN bit for the used GDM.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
|
|
ARCH_DMA_MINALIGN is 64 for ARMv7a/ARMv8a architectures, but RX/TX
descriptors are 32 bytes long. So they may not be aligned on an
ARCH_DMA_MINALIGN boundary. In case of RX path, this may cause the
following problem
1) Assume that a packet has arrived and the EVEN rx descriptor has been
updated with the incoming data. The driver will invalidate and check
the corresponding rx descriptor.
2) Now suppose the next descriptor (ODD) has not yet completed.
Please note that all even descriptors starts on 64-byte boundary,
and the odd ones are NOT aligned on 64-byte boundary.
Inspecting even descriptor, we will read the entire CPU cache line
(64 bytes). So we read and sore in CPU cache also the next (odd)
descriptor.
3) Now suppose the next packet (for the odd rx descriptor) arrived
while the first packet was being processed. So we have new data
in memory but old data in cache.
4) After packet processing (in arht_eth_free_pkt() function) we will
cleanup the descriptor and put it back to rx queue.
This will call flush_dcache_range() function for the even descriptor,
so the odd one will be flushed as well (it is in the same cache line).
So the old data will be written to the next rx descriptor.
5) We get a freeze. The next descriptor is empty (so the driver is
waiting for packets), but the hardware will continue to receive
packets on other available descriptors. This will continue until
the last available rx descriptor is full. Then the hardware will
also freeze.
The problem will be solved if the previous descriptor will be put back
to the queue instead of the current one.
If the current descriptor is even (starts on a 64-byte boundary),
then putting the previous descriptor to the rx queue will affect
the previous cache line. To be 100% ok, we must make sure that the
previous and the one before the previous descriptor cannot be used
for receiving at this moment.
If the current descriptor is odd, then the previous descriptor is on
the same cache line. Both (current and previous) descriptors are not
currently in use, so issue will not arrise.
WARNING: The following restrictions on PKTBUFSRX must be held:
* PKTBUFSRX is even,
* PKTBUFSRX >= 4.
The bug appears on 32-bit airoha platform, but should be present on
64-bit as well.
The code was tested both on 32-bit and 64-bit airoha boards.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
|
|
The dma_map_single() function calls one of the functions
* invalidate_dcache_range(),
* flush_dcache_range().
Both of them expect that 'vaddr' is aligned to the ARCH_DMA_MINALIGN
boundary. Unfortunately, RX/TX descriptors are 32-byte long. Thus they
might not be aligned to the ARCH_DMA_MINALIGN boundary. Data flushing
(or invalidating) might do nothing in this case.
The same applies to dma_unmap_single() function.
In the TX path case the issue might prevent package transmission (filled
TX descriptor was not flushed).
To fix an issue a special wrappers for
* dma_map_single(),
* dma_unmap_single()
functions were created. The patch fix flushing/invalidatiog for the
RX path as well.
The bug appears on 32-bit airoha platform, but should be present on
64-bit as well.
The code was tested both on 32-bit and 64-bit airoha boards.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
|
|
Compatible device list must have a terminator. If terminator is missed
the u-boot driver subsystem will access random data placed after the
list in the memory.
The issue can be observed with the "dm compat" command.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
|
|
Add airoha Ethernet driver for Airoha AN7581 SoC. This is a majorly
rewritten and simplified version of the Linux airoha_eth.c driver.
It's has been modified to support a single RX/TX ring to reflect U-Boot
implementation with recv and send API.
The struct and the define are kept as similar as possible to upstream
one to not diverge too much.
The AN7581 SoC include an Ethernet Switch based on the Mediatek MT753x
but doesn't require any modification aside from setting the CPU port and
applying the Flood configuration hence it can be handled entirely in the
Ethernet driver.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
|
