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path: root/drivers/net/phy/marvell.c
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2025-01-01Revert "net: phy: marvell 88e151x: Fix handling of bare RGMII interface type"Rufus Segar
This reverts commit 431be621c6cbc72efd1d45fa36686a682cbb470a. Section 3.3 of Reduced Gigabit Media Independent Interface (RGMII) Version 2.0 (4/1/2002) details that a PHYs using a ~2ns internal delay are referred to as RGMII-ID. This internal delay is optional. Page 147-148 of the Marvell Doc. No. MV-S107146-U0 Rev. F details timings of the RX/TX delays. We see that with the TX/RX_CLK delay enabled, our RX/TX_CTL signal is shifted w.r.t CLK to reflect the delay added. In 431be62 there is no timing difference between RGMII and RGMII-ID, and so programmers wanting to explicitly set their PHY to RGMII will find that delay added anyway. This could throw off timing if that internal delay is undesired. We should be handling all 4 possible RGMII cases of PHY_INTERFACE_MODE: RGMII, RGMII_ID, RGMII_TXID, and RGMII_RXID. Reverting 431be62 implements this. See also m88e1111_config_init_rgmii_delays in the equivalent driver in Linux (drivers/net/phy/marvell.c), which does not set these delays in RGMII mode. 68e6eca was tested out on an 88E1512 PHY in RGMII-ID mode. This reversion has been tested by myself on an 88E1518 in RGMII-ID mode. This patch affects boards using this driver in "rgmii" mode, as the internal delay will no longer be enabled. Namely kikwood-nsa310s. Signed-off-by: Rufus Segar <rhs@riseup.net>
2024-05-20Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"Tom Rini
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-19Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""Tom Rini
When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
2024-05-07net: Remove <common.h> and add needed includesTom Rini
Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
2023-04-07net: phy: marvell: Import and use marvell_phy.h from LinuxMarek Vasut
Import marvell_phy.h from Linux 5.14.y as of commit a5de4be0aaaa6 ("net: phy: marvell10g: fix differentiation of 88X3310 from 88X3340") and use it in marvell PHY driver instead of current ad-hoc macros. Two of the PHY IDs are unknown to Linux, 88E1149S and 88E1680, for those two, only sync the length of the hexadecimal number to 8 digits. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2023-04-07net: phy: marvell: Convert to U_BOOT_PHY_DRIVER()Marek Vasut
Convert PHY driver to U_BOOT_PHY_DRIVER() macro and drop phy_register() init call. Converted using sed "s@^static struct phy_driver \(.*\)_driver = \+{@U_BOOT_PHY_DRIVER(\L\1) = {" Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Michal Simek <michal.simek@amd.com> Tested-by: Michal Simek <michal.simek@amd.com> #microblaze (MANUAL_RELOC)
2022-12-07net: phy: Remove non-DM_ETH codeTom Rini
As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-08net: phy: marvell: Add support for 88E1240 PHYStefan Roese
This patch adds basic support for the Marvell 88E1240 PHY. This will be used by the upcoming ethernet support addition for the Marvell MIPS Octeon EBB7304 platform. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2022-08-08net: phy: marvell: Support reg config via "marvell, reg-init" DT propertyStefan Roese
This patch adds support for the "marvell,reg-init" DT property, which is used to describe board specific Marvell PHY register configurations in the board dts file. This DT property is supported in the Linux Kernel since a longer time. Adding it to U-Boot now, enables the boards which describe the register settings in their DT files here as well. I've included calling this marvell_of_reg_init() to all foo_config() functions in this patch as well. If CONFIG_DM_ETH is not set, there is no ofnode, or no "marvell,reg-init" property, the PHY initialization is unchanged. The function marvell_of_reg_init() is a port of the Linux version. Please note that I explicitly did not add error checking and handling to the U-Boot version, as this is basically not done for phy_read/write in this Marvell PHY code. This will be used by the upcoming ethernet support on the MIPS Octeon EBB 7304 board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Marek Behún <marek.behun@nic.cz> Reviewed-by: Marek Behún <marek.behun@nic.cz>
2020-05-18common: Drop linux/bitops.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18common: Drop linux/delay.h from common headerSimon Glass
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-03-09net: phy: marvell: Unify 88E151x series phy_driverClemens Gruber
The PHY models of the Marvell 88E151x series are not reliably distinguishable by their uid / PHY identifiers. The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are described as HW revision number, but both 88E1510 and 88E1518 PHYs were observed with the same HW rev number (1). Before commit 83cfbeb0df9f ("net: phy: Fix mask so that we can identify Marvell 88E1518"), the 88E151x were detected because the HW revision bits were masked from the uid. After that change, 88E1510/12/18 were all detected as 88E1518 and the 88E1510 specific code was no longer run. I modified the mask to again ignore all four HW revision bits, removed the 88E1510 specific code (board-specific LED/INTn setup), which was not called since late 2016 anyway and renamed the config function and phy_driver struct to the better fitting 88e151x. The uid and mask bits 3:0 are now again the same as in the Linux kernel. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
2018-07-26net: phy: Clean up includes of common.hJoe Hershberger
We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-02-26net: phy: marvell 88e151x: Fix handling of bare RGMII interface typeMario Six
Commit 68e6ecadc551 ("net: phy: marvell 88e151x: Fix handling of RGMII interface types") fixed the initialization of 88e151x phys, but made it so that interfaces of type PHY_INTERFACE_MODE_RGMII had both RX and TX delay bits cleared. The default (like in m88e1111s_config) is to have both bits set. Hence, this patch changes the behavior in the PHY_INTERFACE_MODE_RGMII case so that both bits are set. Signed-off-by: Mario Six <mario.six@gdsys.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-02-26net: phy: marvell: Fix style violationsMario Six
Fix some style violations (mostly wrong indentions) in the Marvell PHY driver. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-15net: phy: marvell: Add functions to read PHY's extended registersLukasz Majewski
This commit allows extended Marvell registers to be read with: foo > mdio rx FEC 3.10 Reading from bus FEC PHY at address 0: 3.16 - 0x1063 foo > mdio wx FEC 3.10 0x1011 The above code changes the way ETH connector LEDs blink. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: York Sun <york.sun@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-12net: phy: marvell: Fix init function for m88e1145York Sun
Commit a058052c changed the generic phy_reset() to clear all bits in BMCR. This inevitably clears the ANEG bit. m88e1145 requires any change to ANEG bit to be followed by a software reset. This seems to be different from other PHYs. Implement read-modify-write procedure for this PHY init. Signed-off-by: York Sun <york.sun@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-06-02net: phy: marvell 88e151x: Fix handling of RGMII interface typesPhil Edworthy
The 88E1518 code is programming the wrong registers for rgmii-id, rgmii-txid and rgmii-rxid interfaces. Since the PHY defaults to rgmii-id, it would appear that the code was previously only used with sgmii and rgmii-id interfaces. Tested on 88E1512 PHY in rgmii-id mode which is from the same family as 88E1518. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07net: phy: Improve the Marvell 151x constantsJoe Hershberger
Use some constants for the phy configuration instead of so many magic numbers. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07net: phy: Marvell: Use phy_interface_is_rgmii helper functionPhil Edworthy
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07net: phy: Add support for Marvell M88E1512Phil Edworthy
This device also works with the 88E1518 code, so we just adjust the UID mask accordingly. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-07net: phy: Fix mask so that we can identify Marvell 88E1518Phil Edworthy
The mask for the 88E1510 meant that the 88E1518 code would never be used. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2017-02-01net: phy: Support Marvell 88E1680Dirk Eibach
Add support for Marvell 88E1680 Integrated Octal 10/100/1000 Mbps Energy Efficient Ethernet Transceiver. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Stefan Roese <sr@denx.de>
2016-07-27net: phy: marvell: Add a missing errno.h headerSimon Glass
This corrects a build error on zynqmp. Signed-off-by: Simon Glass <sjg@chromium.org>
2016-06-21net: phy: marvell: Do not reset 88e1310 after autonegNathan Rossi
Commit a058052c "net: phy: do not read configuration register on reset", changes the behaviour of the phy_reset function such that the state of the BMCR register is not preserved during reset. Change the config function for the m88e1310 so that it does not do a reset after configuring auto-negotiation. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Stefan Roese <sr@denx.de> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Stefan Roese <sr@denx.de>
2016-05-24phy: marvell: Do not reset phy after negotiationMichal Simek
The patch "net: phy: do not read configuration register on reset" (sha1: a058052c358c3ecf5f394ff37def6a45eb26768c) was causing regression on zynq zc702 board where Marwell 88e1118 phy was resetted after negotiation was setup. Phy reset is done pretty early in phy_connect_dev() and doens't need to be called again in phy code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-05-24net: phy: Handle phy_startup() error codes properlyMichal Simek
Propagate error code from genphy_update_link() to phy startup(). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-05-24phy: Return correct error code when timeout happensMichal Simek
Return -ETIMEDOUT if timeout happens. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-02-18net: phy: marvell: Fix problem with phy_reset() clearing BMCRStefan Roese
With commit a058052c [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Resulting in bit 12 being cleared (A/N enable). This leads to autonegotiation link problems, at least on the Marvell Armada ClearFog board. I suspect that other boards using this driver will be affected as well. At the of m88e1111s_config(), phy_reset() is called. This is not needed for the PHY to load the changed configuration, as phy_reset() is called a few lines before already. So lets call genphy_restart_aneg() here instead to start the AN correctly. Tested on clearfog. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-18net: phy: marvell: Call phy_reset() where possibleStefan Roese
Instead of coding the soft PHY reset function multiple times in marvell.c, lets call the common phy_reset() function from phy.c. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-11net: Add support for Marvell 88E1510 PHYClemens Gruber
Support the 88E1510 PHY which is very similar to the 88E1518. I also set the INTn output and configured the LEDs. Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-11net: Improve 88E151x PHY initializationClemens Gruber
- The EEE fixup magic should also be enabled for RGMII - Improved comments Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2014-11-06net: phy: marvell: add errata w/a for 88E151* chipsHao Zhang
As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512/88E1514 Rev A0, Errata Section 3.1 Marvell PHY has an errata which requires that certain registers get written in order to restart autonegotiation. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Reviewed-by: Stefan Roese <sr@denx.de>
2013-07-24Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
2013-06-24NET: phy: add 88E1310 PHY initializationSebastian Hesselbarth
This adds PHY initialization for Marvell Alaska 88E1310 PHY. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
2013-04-30net: phy: Define Marvell 88e1518 phyMichal Simek
This phy is used on zedboard (xilinx zynq platform). Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
2012-12-15phy: Add support for Marvell 88E1118RMichal Simek
Marvell 88E1118R has different uid then 88E1118. Signed-off-by: Michal Simek <monstr@monstr.eu> CC: Andy Fleming <afleming@freescale.com> CC: Zang Roy-R61911 <tie-fei.zang@freescale.com> CC: Kumar Gala <galak@kernel.crashing.org>
2011-12-05Phy/Marvell: Rewrite the MV88E1111 phy config function based on kernel codeZang Roy-R61911
The original m88e1111s_config() does not do the SGMII mode initialization and is buggy. Rewrite the function according to 3.0.6 kernel function m88e1111_config_init() in drivers/net/phy/marvell.c Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org>
2011-04-20phylib: Add a bunch of PHY drivers from tsecAndy Fleming
The tsec driver had a bunch of PHY drivers already written. This converts them all into PHY Lib drivers, and serves as the first set of PHY drivers for PHY Lib. While doing that, cleaned up a number of magic numbers (though not all of them, as PHY vendors like to keep their numbers as magical as possible). Also, noticed that almost all of the vitesse/cicada PHYs had the same config/parse/startup functions, so those have been collapsed into one. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
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