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path: root/drivers/phy/Kconfig
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2026-03-02phy: Add MediaTek UFS PHY DriverIgor Belwon
This UFS M-PHY driver can be used on recent MediaTek SoCs as the primary PHY for the UFS controller. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://patch.msgid.link/20251011-mtk-ufs-uboot-v1-1-a05f991ee150@mentallysanemainliners.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2026-01-09dm: core: Default to using DEVRES outside of xPLTom Rini
The devm alloc functions that we have may follow the Linux kernel model where allocations are (almost always) automatically free()'d. However, quite often we don't enable, in full U-Boot, the tracking and free()'ing functionality. This in turn leads to memory leaks because the driver author expects that since the functions have the same name as in the Linux Kernel they have the same behavior. In turn we then get functionally correct commits such as commit 00e1fed93c8c ("firmware: ti_sci: Fix memory leaks in devm_ti_sci_get_of_resource") that manually add these calls. Rather than manually tracking allocations and implementing free()s, rework things so that we follow expectations by enabling the DEVRES functionality (outside of xPL phases). This turns DEVRES from a prompted symbol to a symbol that must be select'd, and we now remove our non-managed alloc/free functions from outside of xPL builds. Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2025-11-04phy: imx8mq-usb: Add SPL support for i.MX8MQ, i.MX8MP, i.MX95, and i.MX94 ↵Alice Guo
USB3.0 PHY This patch adds SPL Kconfig option (SPL_PHY_IMX8MQ_USB) for the i.MX8MQ, i.MX8MP, i.MX95, and i.MX94 USB3.0 PHY driver, allowing the driver to be compiled and probed in SPL stage. Signed-off-by: Alice Guo <alice.guo@nxp.com>
2025-08-23phy: phy-imx8mq-usb: Add support for i.MX95 USB3 PHYTim Harvey
Add initial support for i.MX95 USB.30 PHY, which is similar to the i.MX8MQ and i.MX8MP USB PHY. The i.MX95 USB3 PHY has a Type-C Assist block (TCA) consisting of two functional blocks (XBar assist and VBus assist) and is documented in the i.MX95 RM Chapter 163.3.8 Type-C assist (TCA) block. Instead of relying on an external MUX for Type-C plug orientation the XBar can handle the flip internally. Add initial support for i.MX95 by: - allowing the driver to be enabled i.MX95 - resetting the XBar - configuring the TCA in System Configuration mode (which was determined to be necessary to enable the PHY in device-mode) Follow-on support will need to be added to steer the XBar based on either board design (if only one pair is brought out) or if used with a Type-C controller. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Alice Guo <alice.guo@nxp.com>
2025-07-25phy: samsung: Add Exynos USB DRD PHY driverSam Protsenko
Add DM driver for Exynos USB PHY controllers. For now it only supports Exynos850 SoC. Only UTMI+ (USB 2.0) PHY interface is implemented, as Exynos850 doesn't support USB 3.0. Only two clocks are used for this controller: - phy: bus clock, used for PHY registers access - ref: PHY reference clock (OSCCLK) Ported from Linux kernel: drivers/phy/samsung/phy-exynos5-usbdrd.c Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2025-03-19phy: rcar: Support RZ/G2L USB PHYPaul Barker
Extend the existing Renesas R-Car Gen3 USB 2.0 PHY driver to support the RZ/G2L and related SoCs. Also enable this driver by default for the RZ/G2L SoC family. Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
2025-03-17phy: starfive: Add Starfive JH7110 USB 2.0 PHY driverMinda Chen
Add Starfive JH7110 USB 2.0 PHY driver, which is generic PHY driver. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: E Shattow <lucent@gmail.com>
2024-07-08phy: phy-mtk-tphy: add support for phy type switchChristian Marangi
Add support for PHY type switch via the mediatek topmisc syscon. This is needed on mt7981 to make the PCIe correctly work and display LinkUp. Follow the same implementation done on Linux kernel with the usage of the mediatek,syscon-type property. Example: u3port0: usb-phy@11e10700 { reg = <0x11e10700 0x900>; clocks = <&topckgen CK_TOP_USB3_PHY_SEL>; clock-names = "ref"; #phy-cells = <1>; mediatek,syscon-type = <&topmisc 0x218 0>; status = "okay"; }; Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-03-24phy: phy-imx8m-pcie: Add support for i.MX8M{M/P} PCIe PHYSumit Garg
Add initial support for i.MX8M{M/P} PCIe PHY. On i.MX8M{M/P} SoCs PCIe PHY initialization moved to this standalone PHY driver. Inspired from counterpart Linux kernel v6.8-rc3 driver: drivers/phy/freescale/phy-fsl-imx8m-pcie.c. Use last Linux kernel driver reference commit 7559e7572c03 ("phy: Explicitly include correct DT includes"). Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice* Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2023-10-12phy: support Amlogic A1 familyAlexey Romanov
Setting G12A and A1 is similar, so we can use G12A phy driver with little changes. Signed-off-by: Alexey Romanov <avromanov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231005085434.74755-6-avromanov@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-08-14phy: Add support for the Apple Type-C PHYMark Kettenis
This is merely a dummy driver that makes sure the DWC3 XHCI driver finds its reset and PHY controllers. We rely on iBoot to set up the PHY for us. Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2023-04-16phy: renesas: Add Renesas Ethernet SERDES driver for R-Car S4-8Marek Vasut
Add Renesas Ethernet SERDES driver for R-Car S4-8 (r8a779f0). The datasheet describes initialization procedure without any information about registers' name/bits. So, this is all black magic to initialize the hardware. Especially, all channels should be initialized at once. This driver is imported and adjusted from Linux 6.3-rc1 commit: 50133cd3e8dd1 ("phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()") Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
2022-08-26phy: Move qcom SoCs specific phy drivers to qcom folderSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2022-07-13phy: mtk-tphy: add support for MediaTek MT7621 SoCWeijie Gao
This patch makes mtk-tphy driver available for MediaTek MT7621 SoC Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2022-07-06phy: nuvoton: add NPCM7xx phy control driverJim Liu
add BMC NPCM750 phy control driver Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2022-04-12phy: phy-imx8mq-usb: Add support for i.MX8MP USB PHYMarek Vasut
Add initial support for i.MX8MP USB PHY, i.MX8MP USB is similar to the i.MX8MQ, except for clock and power domain design customization. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8mp-venice-gw74xx
2022-01-12phy: zynqmp: Add serdes/psgtr driverMichal Simek
Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/36e6e9d3baf8511af1916e91e4887032ca2b6c20.1641458978.git.michal.simek@xilinx.com
2021-07-27phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCJean-Jacques Hiblot
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
2021-07-27phy: cadence: Add driver for Sierra PHYAlan Douglas
Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com
2021-07-17Merge tag 'u-boot-imx-20210717' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX ---- - mx7ulp : fix WDOG - imx8 : Phytec - USB3 support for i.MX8 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQYe Li
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Patrick Wildt <patrick@blueri.se> Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-14phy: Add driver for ST-Ericsson AB8500 USB PHYStephan Gerhold
The AB8500 PMIC contains an USB PHY that needs to be set up in device or host mode to make USB work properly. Add a simple driver for the generic PHY uclass that allows enabling it. The if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) might be a bit strange. The USB PHY must be configured in either host or device mode and somehow the USB PHY driver must be made aware of the mode. Actually, the MUSB driver used together with this PHY does not support dynamic selection of host/device mode in U-Boot at the moment. Therefore, one very simple approach that works fine is to select the mode to configure at compile time. When the MUSB driver is configured in host mode the PHY is configured in host mode, and similarly when the MUSB driver is configured in device/gadget mode. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-02-10phy: Add Amlogic AXG MIPI PCIe Analog PHY driverNeil Armstrong
The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and MIPI DSI at the same time, and provides the Analog part of MIPI DSI transmission and Analog part of the PCIe lines. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10phy: Add Amlogic AXG MIPI D-PHY driverNeil Armstrong
The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. This D-PHY depends on a separate analog PHY. Signed-off-by:Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10phy: dphy: Add configuration helpersNeil Armstrong
The MIPI D-PHY spec defines default values and boundaries for most of the parameters it defines. Introduce helpers to help drivers get meaningful values based on their current parameters, and validate the boundaries of these parameters if needed. These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux 5.9-rc1"). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-01-24phy: add USB PHY driver for MediaTek MT7620 SoCWeijie Gao
This patch adds USB PHY driver for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-10-06Merge tag 'u-boot-amlogic-20201005' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - generate unique mac address from SoC serial on S400 board - Add USB support for GXL and AXG SoCs - Update Gadget code to use the new GXL and AXG USB glue driver - Add a VIM3 board support to add dynamic PCIe enable in OS DT - Fix AXG pinmux with requesting GPIOs - Add missing GPIOA_18 for AXG pinctrl - Add Amlogic PWM driver
2020-10-05phy: meson-gxl-usb: depend on Meson AXG aswellNeil Armstrong
Enable build of meson-gxl-usb PHY for the AXG architecture aswell. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-09-30phy: add support for stingray PAXB PHY controllerSrinath Mannam
Add support for stingray PAXB PHY controller driver. This driver supports maximum 8 PAXB phys using pipemux data. Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Stefan Roese <sr@denx.de>
2020-09-18phy: add driver for Qualcomm IPQ40xx USB PHYRobert Marko
Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
2020-05-29phy: rockchip: Add Rockchip USB2PHY driverJagan Teki
Add Rockchip USB2PHY driver with initial support. This will help to use it for EHCI controller in host mode, and USB 3.0 controller in otg mode. More functionality like charge, vbus detection will add it in future changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-28phy: meson: add GXBB PHY driverBeniamino Galvani
This adds support for the USB PHY found on Amlogic GXBB SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-25phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 partWeijie Gao
This patch adds slew rate calibration for mt76x8-usb-phy, removes code which belongs to mt7620, and gets rid of using syscon and regmap by using clock driver and reset controller. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-11phy: mediatek: add MediaTek T-PHY support for PCIeRyder Lee
The driver provides PHY for USB2, USB3.0, PCIe and SATA, and now we just enable PCIe. As for the other functionalities will be added gradually in upcoming days. This is adapted from the Linux version. Tested-by: Frank Wunderlich <frank-w@public-files.de> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
2019-08-26Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford
Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-08-12phy: add support for AM654x SERDESSekhar Nori
Add a new SERDES driver for TI's AM654x SoC which configures the SERDES only for PCIe. Support fo USB3 can be added later. SERDES in am654x has three input clocks (left input, external reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The driver has support to select PLL mux and left/right output mux as specified in device tree. Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2019-08-08phy: Add support for phy-da8xx-usbAdam Ford
In preparation for supporting the musb driver, this patch adds support for the usb phy associated with the musb driver. Signed-off-by: Adam Ford <aford173@gmail.com>
2019-05-09phy: meson: add Amlogic G12A USB2 and USB3+PCIE PHY driversNeil Armstrong
This adds support for the USB PHYs found in the Amlogic G12A SoC Family. The USB2 PHY supports Host and/or Peripheral mode, depending on it's position. The first PHY is only used as Host, but the second supports Dual modes defined by the USB Control Glue HW in front of the USB Controllers. The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on the layout of the board. Selection is done by the #phy-cells, making the mode static and exclusive. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-12phy: Add USB PHY driver for the MT76x8 (7628/7688) SoCStefan Roese
This driver is derived from this Linux driver: linux/drivers/phy/ralink/phy-ralink-usb.c The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. I removed the reset controller handling for the USB host and device, as it does not seem to be necessary right now. The soft reset bits for both devices are enabled by default and testing has shown (with hackish reset handling added), that USB related commands work identical with or without the reset handling. Please note that the resulting USB support is tested only very minimal. I was able to detect one of my 3 currently available USB sticks. Perhaps some further work is needed to fully support the EHCI controller integrated in the MT76x8 SoC. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-04-03phy: Also allow MESON_GXM for MESON_GXL_USB_PHYNeil Armstrong
The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs. Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-12-14PHY: Add phy driver for the keystone USB PHYJean-Jacques Hiblot
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-12-07phy: Add a new driver for OMAP's USB2 PHYsJean-Jacques Hiblot
This drivers supports the USB2 PHY found on omap5 and dra7 SOCs. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-10-03phy: rcar: Add R-Car Gen3 PHY driverMarek Vasut
Add a PHY driver for the R-Car Gen3 which allows configuring USB OTG PHY on Gen3 into host mode and toggles VBUS in case a dedicated regulator is present. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-09-30phy: db410c: Add MSM USB PHY driverRamon Fried
Add a PHY driver for the Qualcomm dragonboard 410c which allows switching on/off and resetting the phy connected to the EHCI controllers and USBHS controller. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-08-14phy: rcar: Add R-Car Gen2 PHY driverMarek Vasut
Add a PHY driver for the R-Car Gen2 which allows configuring the mux connected to the EHCI controllers and USBHS controller. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-18phy: add support for STM32 usb phy controllerPatrice Chotard
This patch adds phy tranceiver driver for STM32 USB PHY Controller (usbphyc) that provides dual port High-Speed phy for OTG (single port) and EHCI/OHCI host controller (two ports). One port of the phy is shared between the two USB controllers through a UTMI+ switch. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-04-11phy: Add Amlogic Meson USB2 & USB3 Generic PHY driversNeil Armstrong
The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs and an USB3 PHY. This patch adds drivers for these for the standard generic PHY interface and supports the power-on/off calls and set the Host mode by default. They are based on the excellent work from Martin Blumenstingl merged in linux. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-21phy: add support for bcm6318 usbh phyÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-03-21phy: add support for bcm6368 usbh phyÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-03-21phy: add support for bcm6358 usbh phyÁlvaro Fernández Rojas
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
generated by cgit v1.2.3 (git 2.0.4) at 2026-03-18 11:39:24 +0000