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Enable QMP phy for QCS615, referenced from Linux.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250521035324.1182833-3-aswin.murugan@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Enable QMP phy for QCS8300, referenced from Linux.
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250529154931.1879976-5-quic_bselvana@quicinc.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
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Recent addition of support for SDM660 inadvertently broke USB PHY power
on sequence on RB1/RB2 and others with following error:
starting USB...
Bus usb@4e00000: QUSB2PHY pll lock failed: status reg = 0
qcom-qusb2-phy phy@1613000: PHY: Failed to power on phy@1613000: -16.
Can't power on PHY0
probe failed, error -16
No USB controllers found
The root cause was the addition of flag se_clk_scheme_default which was
configured correctly for SDM660 but incorrect for all other supported
SoC. Fix that by properly assignment as per upstream Linux driver.
Fixes: 475497dc3c15 ("phy: Add SDM660 support to Qualcomm QUSB2 phy")
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by:
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250410080027.208674-3-sumit.garg@kernel.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Imported from Linux driver.
Note that already existing but previously unused member of
struct qusb2_phy::has_se_clk_scheme is now utilized for it's
purpose.
Signed-off-by: Alexey Minnekhanov <alexeymin@postmarketos.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250325083713.2425430-1-alexeymin@postmarketos.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add support for the PCIe QMP PHY on the SM8550,
SM8650 and x1e80100 SoCs.
The driver is based on the Linux phy/qualcomm/phy-qcom-qmp-pcie.c
driver and adapted to U-Boot.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241125-topic-pcie-phy-v1-1-bf08811d0a07@linaro.org
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Copy PHY tables over from Linux to support SA8775.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tag/?h=v6.13-rc6
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250110050817.3819282-5-quic_varada@quicinc.com
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Copy PHY tables over from Linux to support SM8150
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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Add configuration for the SC7280, copied from Linux 6.11
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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The ufsphy_v2_regs_layout is not used, drop it and fix:
phy-qcom-qmp-ufs.c:87:27: warning: ‘ufsphy_v2_regs_layout’ defined but not used [-Wunused-const-variable=]
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add Qualcomm QMP UFS PHY driver which is available on the following
Snapdragon SoCs - SDM845, SM8250, SM8550 and SM8650 SoCs.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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Import Qualcomm QMP phy related header files from Linux v6.11-rc7,
limit to headers needed to setup QMP v2 to v6 UFS PHYs.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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As part of bringing the master branch back in to next, we need to allow
for all of these changes to exist here.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
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When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay
Ethernet"' I failed to notice that b4 noticed it was based on next and
so took that as the base commit and merged that part of next to master.
This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing
changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35.
Reported-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
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Remove <common.h> from this driver directory and when needed
add missing include files directly.
Signed-off-by: Tom Rini <trini@konsulko.com>
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There is a clock associated with this phy, but it's always from the
rpmhcc and isn't actually needed for the hardware to work.
Drop all the clock handling from the driver.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Add a driver for the new Synopsys eUSB2 PHY found in the SM8550
and SM8650 SoCs.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
driver, notable the SM8250 SoC which will gain U-Boot support in
upcoming patches.
Introduce a driver based on the Linux driver.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[code cleanup, align symbol names with Linux, switch to clk/reset_bulk APIs]
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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The Snapdragon 845 and several other Qualcomm SoCs feature this
USB high-speed phy. Add a driver for it based on the Linux driver, with
support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain
support in U-Boot in future patches.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[code cleanup, switch to clk_bulk]
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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Use the root compatible strings from upstream Linux, add missing
'#clock-cells' property to the gcc node.
Adjust some of the msm8916/apq8016 drivers to use the correct upstream
compatible properties and DT bindings.
This prepares us to switch to upstream DT in a future patch.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Sumit Garg <sumit.garg@linaro.org> #qcs404
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
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The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU
can expect 64-bit data from the device tree parser, so use
dev_read_addr_ptr instead of the dev_read_addr function in the
various files in the drivers directory that cast to a pointer.
As we are there also streamline the error response to -EINVAL on return.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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QCS404 SoC supports two types of PHY, one supports high speed mode or
USB2 PHY and the other supports super speed mode or USB3 PHY. So add
corresponding PHY drivers.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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